@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_ccc_0\PF_ccc_0_0\PF_ccc_0_PF_ccc_0_0_PF_CCC.v":39:12:39:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1340 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CL190 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":501:0:501:5|Sharing sequential element clear_framing_error_en. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":136:8:136:17|Object data_ready is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":376:0:376:5|Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":326:0:326:5|Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":293:0:293:5|Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":159:0:159:5|Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\fir_rtl.v":88:0:88:5|Pruning unused register sample_data[127][15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\fir_rtl.v":70:0:70:5|Pruning unused register coeffreg[0][15:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":502:7:502:15|Removing wire load_over, as there is no assignment to it.
@W: CL265 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":675:2:675:7|Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":412:13:412:17|Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":234:61:234:72|Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":118:38:118:50|Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":267:19:267:27|Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":268:19:268:27|Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:6:270:15|Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:18:270:26|Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:29:270:38|Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:22:590:32|Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:35:590:49|Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":86:20:86:24|Removing wire outPQ, as there is no assignment to it.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":87:16:87:24|Removing wire ctrl_outp, as there is no assignment to it.
@W: CL318 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:34:86:36|*Output RFS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:39:86:49|*Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG296 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":135:8:135:13|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":142:10:142:22|Referenced variable FIR_OUT_RDATA is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":149:10:149:21|Referenced variable FFT_RE_RDATA is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":156:10:156:21|Referenced variable FFT_IM_RDATA is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":139:16:139:22|Referenced variable RAM_REN is not in sensitivity list.
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":50:12:50:18|Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":52:8:52:15|Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":51:8:51:15|Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL246 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":369:22:369:24|Input port bits 46 to 32 of inp[47:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL279 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\mult18X18.v":53:0:53:5|Pruning register bits 47 to 35 of out1[47:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.

