@N|Running in 64-bit mode
@N|Running in 64-bit mode
@N: CG1349 :	| Running Verilog Compiler in System Verilog mode
@N: CG347 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\twiddle32.v":35:25:35:37|Read a parallel_case directive.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":489:7:489:12|Synthesizing module CLKINT in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\polarfire_syn_comps.v":8364:7:8364:9|Synthesizing module PLL in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":504:7:504:9|Synthesizing module VCC in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":500:7:500:9|Synthesizing module GND in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_ccc_0\PF_ccc_0_0\PF_ccc_0_PF_ccc_0_0_PF_CCC.v":5:7:5:32|Synthesizing module PF_ccc_0_PF_ccc_0_0_PF_CCC in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_ccc_0\PF_ccc_0.v":263:7:263:14|Synthesizing module PF_ccc_0 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":38:7:38:45|Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Clock_gen in library work.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":128:51:128:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":149:51:149:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":169:51:169:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":189:51:189:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":209:51:209:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":229:51:229:59|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v":249:51:249:59|Removing redundant assignment.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":31:7:31:44|Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Tx_async in library work.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":356:21:356:29|Removing redundant assignment.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":30:7:30:44|Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Rx_async in library work.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":254:23:254:35|Removing redundant assignment.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":280:18:280:25|Removing redundant assignment.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":31:7:31:44|Synthesizing module PF_COREUART_0_PF_COREUART_0_0_COREUART in library work.
@N: CG179 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":390:22:390:33|Removing redundant assignment.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0.v":26:7:26:19|Synthesizing module PF_COREUART_0 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\FILTER_CONTROL_FSM.v":35:7:35:23|Synthesizing module FILTERCONTROL_FSM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\fir_rtl.v":35:7:35:13|Synthesizing module FIR_RTL in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\mult18X18.v":35:7:35:15|Synthesizing module mult18x18 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\MultADD.v":36:7:36:13|Synthesizing module MultADD in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":578:7:578:13|Synthesizing module RAM1K20 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0_0\PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM.v":5:7:5:41|Synthesizing module PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0.v":59:7:59:17|Synthesizing module PF_TPSRAM_0 in library work.
@N: CG775 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":28:7:28:37|Component PF_COREFFT_PF_COREFFT_0_COREFFT not found in library "work" or "__hyper__lib__", but found in library COREFFT_LIB
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":28:7:28:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_COREFFT in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":445:7:445:24|Synthesizing module fft_inpl_slowClock in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":186:7:186:31|Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":29:7:29:22|Synthesizing module fft_inpl_kitEdge in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":126:7:126:24|Synthesizing module fft_inpl_counter_w in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":70:7:70:22|Synthesizing module fft_inpl_counter in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":186:7:186:31|Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":361:7:361:25|Synthesizing module fft_inpl_rdFFTtimer in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":186:7:186:31|Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":99:7:99:24|Synthesizing module fft_inpl_kitCountS in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":70:7:70:22|Synthesizing module fft_inpl_counter in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":481:7:481:24|Synthesizing module fft_inpl_inBuf_ldA in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":623:7:623:30|Synthesizing module fft_inpl_inBuf_fftA_pipe in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":695:7:695:22|Synthesizing module fft_inpl_twid_rA in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":186:7:186:31|Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":405:7:405:28|Synthesizing module fft_inpl_kitSync_ngrst in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":161:7:161:23|Synthesizing module fft_inpl_bcounter in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":739:7:739:26|Synthesizing module fft_inpl_twid_wA_gen in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":532:7:532:22|Synthesizing module fft_inpl_outBufA in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":29:7:29:21|Synthesizing module fft_inpl_sm_top in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":249:7:249:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_inPlace in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":163:7:163:38|Synthesizing module PF_COREFFT_PF_COREFFT_0_inBuffer in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":36:7:36:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_wrapRam in library COREFFT_LIB.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":133:7:133:9|Synthesizing module OR2 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":102:7:102:10|Synthesizing module CFG2 in library work.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":508:7:508:14|Synthesizing module RAM64x12 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\PF_COREFFT_PF_COREFFT_0_uram_g5.v":5:7:5:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_uram_g5 in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":460:7:460:21|Synthesizing module fft_inpl_switch in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":326:7:326:23|Synthesizing module fft_inpl_kitRndUp in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v":442:7:442:24|Synthesizing module fft_inpl_cmplx_rnd in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":364:7:364:22|Synthesizing module fft_inpl_signExt in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\mac_lib.v":36:7:36:25|Synthesizing module fft_inpl_mac18x18mx in library COREFFT_LIB.
@N: CG364 :"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v":674:7:674:13|Synthesizing module MACC_PA in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":364:7:364:22|Synthesizing module fft_inpl_signExt in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v":354:7:354:28|Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v":354:7:354:28|Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v":414:7:414:23|Synthesizing module fft_inpl_cmplx_18 in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":226:7:226:27|Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":499:7:499:20|Synthesizing module fft_inpl_bfly2 in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\twiddle32.v":27:7:27:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_twiddle in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":369:7:369:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_twidLUT in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":570:7:570:24|Synthesizing module fft_inpl_autoScale in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":28:7:28:43|Synthesizing module PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":329:7:329:37|Synthesizing module PF_COREFFT_PF_COREFFT_0_outBuff in library COREFFT_LIB.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT.v":46:7:46:16|Synthesizing module PF_COREFFT in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3_0\PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM.v":5:7:5:41|Synthesizing module PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3.v":59:7:59:17|Synthesizing module PF_TPSRAM_3 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4_0\PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM.v":5:7:5:41|Synthesizing module PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4.v":59:7:59:17|Synthesizing module PF_TPSRAM_4 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1_0\PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM.v":5:7:5:41|Synthesizing module PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1.v":59:7:59:17|Synthesizing module PF_TPSRAM_1 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2_0\PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM.v":5:7:5:41|Synthesizing module PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2.v":59:7:59:17|Synthesizing module PF_TPSRAM_2 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":35:7:35:13|Synthesizing module UART_IF in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_DSP_FLOW_DEMO_TOP\PF_DSP_FLOW_DEMO_TOP.v":9:7:9:26|Synthesizing module PF_DSP_FLOW_DEMO_TOP in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\polarfire_syn_comps.v":1714:7:1714:10|Synthesizing module INIT in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\polarfire_syn_comps.v":216:7:216:12|Synthesizing module BANKEN in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":5:7:5:59|Synthesizing module PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0.v":82:7:82:23|Synthesizing module PF_init_monitor_0 in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v":21:7:21:42|Synthesizing module reset_sync_reset_sync_0_CORERESET_PF in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\reset_sync\reset_sync.v":21:7:21:16|Synthesizing module reset_sync in library work.
@N: CG364 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\top\top.v":9:7:9:9|Synthesizing module top in library work.
@N: CL135 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v":58:0:58:5|Found sequential shift dff with address depth of 16 words and data bit width of 1.
@N: CL201 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\UART_IF.v":186:0:186:5|Trying to extract state machine for register rfsm.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":584:8:584:22|Input fftRd_done_tick is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":258:20:258:23|Input load is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":549:8:549:20|Input rTimerTC_tick is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":493:20:493:24|Input clkEn is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":85:32:85:36|Input CLKEN is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":85:20:85:22|Input RST is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":85:25:85:29|Input START is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":85:39:85:50|Input INVERSE_STRM is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":85:53:85:59|Input REFRESH is unused.
@N: CL201 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\hdl\FILTER_CONTROL_FSM.v":98:0:98:5|Trying to extract state machine for register fsm.
@N: CL201 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":286:0:286:5|Trying to extract state machine for register rx_state.
@N: CL201 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Trying to extract state machine for register xmit_state.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":44:11:44:21|Input tx_dout_reg is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":45:6:45:15|Input fifo_empty is unused.
@N: CL159 :"C:\PF_task_jan_2021\test\DG0762\DG0762_FIR_RTL\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":46:6:46:14|Input fifo_full is unused.
@N|Running in 64-bit mode

