Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Wed Jan 13 11:23:51 2021

Design top
Family PolarFire
Die MPF300TS
Package FCG1152
Temperature Range -40 - 100 C
Voltage Range 1.0185 - 1.0815 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions slow_lv_ht, slow_lv_lt, fast_hv_lt
Scenario for Timing Analysis timing_analysis

*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/A N/A
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 5.000 200.000 1.461 slow_lv_ht
REF_CLK_0 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] 4.633 8.015 0.063 4.587 slow_lv_ht
Path 2 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] 4.613 7.995 0.063 4.572 slow_lv_ht
Path 3 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] 4.582 7.964 0.063 4.536 slow_lv_ht
Path 4 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] 4.562 7.944 0.063 4.521 slow_lv_ht
Path 5 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[4] 4.509 7.891 0.064 4.469 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK
To: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9]
data required time N/C
data arrival time - 8.015
slack N/C
Data arrival time calculation
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q 0.000 0.000
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 0.000 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_Z[2] + 0.164 0.164 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y cell ADLIB:CFG1 + 0.045 0.209 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2] + 2.102 2.311 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:Y cell ADLIB:GB + 0.113 2.424 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y + 0.361 2.785 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1:Y cell ADLIB:RGB + 0.052 2.837 22 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:CLK net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/divider_i_0[2] + 0.545 3.382 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1]:Q cell ADLIB:SLE + 0.175 3.557 76 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m6:B net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[1] + 0.992 4.549 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m6:Y cell ADLIB:CFG2 + 0.061 4.610 21 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m8_i:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m6 + 1.079 5.689 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m8_i:Y cell ADLIB:CFG3 + 0.061 5.750 2 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_1:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/N_9_i + 0.139 5.889 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_1:Y cell ADLIB:CFG4 + 0.066 5.955 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_2:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m65_1 + 0.407 6.362 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_2:Y cell ADLIB:CFG4 + 0.081 6.443 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m71:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m65_2 + 0.438 6.881 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m71:Y cell ADLIB:CFG3 + 0.086 6.967 2 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_20:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Data1_4 + 0.228 7.195 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_20:Y cell ADLIB:CFG3 + 0.078 7.273 2 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/CFG_7:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidData_w[20] + 0.609 7.882 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/CFG_7:IPC cell ADLIB:CFG4_IP_ABCD + 0.022 7.904 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/W_DATA_net[9] + 0.111 8.015 f
data arrival time 8.015
Data required time calculation
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/C N/C
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 N/C f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_Z[2] + 0.133 N/C f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y cell ADLIB:CFG1 + 0.037 N/C 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2] + 1.699 N/C r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:Y cell ADLIB:GB + 0.103 N/C 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y + 0.326 N/C r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1:Y cell ADLIB:RGB + 0.047 N/C 22 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_CLK net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/divider_i_0[2] + 0.654 N/C r
clock reconvergence pessimism + 0.492 N/C
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[9] Library setup time ADLIB:RAM64x12_IP - 0.063 N/C
Operating Conditions slow_lv_ht

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 to PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

No Path

Clock Domain PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 reset_sync_0/reset_sync_0/dff_15:CLK PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][9]:EN 3.266 1.461 6.464 7.925 0.112 3.539 slow_lv_ht
Path 2 reset_sync_0/reset_sync_0/dff_15:CLK PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][7]:EN 3.266 1.461 6.464 7.925 0.112 3.539 slow_lv_ht
Path 3 reset_sync_0/reset_sync_0/dff_15:CLK PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[60][9]:EN 3.266 1.461 6.464 7.925 0.112 3.539 slow_lv_ht
Path 4 reset_sync_0/reset_sync_0/dff_15:CLK PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[60][15]:EN 3.266 1.461 6.464 7.925 0.112 3.539 slow_lv_ht
Path 5 reset_sync_0/reset_sync_0/dff_15:CLK PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[60][12]:EN 3.266 1.461 6.464 7.925 0.112 3.539 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: reset_sync_0/reset_sync_0/dff_15:CLK
To: PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][9]:EN
data required time 7.925
data arrival time - 6.464
slack 1.461
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.151 2.223 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.372 2.595 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 2.647 1133 f
reset_sync_0/reset_sync_0/dff_15:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.551 3.198 r
reset_sync_0/reset_sync_0/dff_15:Q cell ADLIB:SLE + 0.166 3.364 2906 f
PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[1]_1_sqmuxa_0_a4_i:A net reset_sync_0.reset_sync_0.dff + 0.704 4.068 f
PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[1]_1_sqmuxa_0_a4_i:Y cell ADLIB:CFG2 + 0.045 4.113 257 r
PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][9]:EN net PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[1]_1_sqmuxa_0_a4_i_Z + 2.351 6.464 r
data arrival time 6.464
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 Clock Constraint 5.000 5.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 5.000 r
Clock generation + 1.254 6.254
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 6.398 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 6.529 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 6.874 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:Y cell ADLIB:GB + 0.132 7.006 3 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB2:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y + 0.326 7.332 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB2:Y cell ADLIB:RGB + 0.047 7.379 523 f
PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][9]:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB2_rgb_net_1 + 0.460 7.839 r
clock reconvergence pessimism + 0.198 8.037
PF_DSP_FLOW_DEMO_TOP_0/FIR_RTL_0/coeffreg[61][9]:EN Library setup time ADLIB:SLE - 0.112 7.925
data required time 7.925
Operating Conditions slow_lv_ht

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D 1.509 1.509 0.000 -0.246 fast_hv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX
To: PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D
data required time N/C
data arrival time - 1.509
slack N/C
Data arrival time calculation
RX 0.000 0.000 f
RX_ibuf/U_IOPAD:PAD net RX + 0.000 0.000 f
RX_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.619 0.619 1 f
RX_ibuf/U_IOIN:YIN net RX_ibuf/YIN + 0.000 0.619 f
RX_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.131 0.750 1 f
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D net RX_c + 0.759 1.509 f
data arrival time 1.509
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 0.699 N/C
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.093 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.089 N/C 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.225 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.100 N/C 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.227 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.034 N/C 1133 f
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.288 N/C r
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D Library setup time ADLIB:SLE - 0.000 N/C
Operating Conditions fast_hv_lt

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK TX 4.362 7.540 7.540 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK
To: TX
data required time N/C
data arrival time - 7.540
slack N/C
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.151 2.223 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.372 2.595 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 2.647 1133 f
PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.531 3.178 r
PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:Q cell ADLIB:SLE + 0.166 3.344 1 f
TX_obuf/U_IOTRI:D net TX_c + 1.245 4.589 f
TX_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.918 5.507 1 f
TX_obuf/U_IOPAD:D net TX_obuf/DOUT + 0.000 5.507 f
TX_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.033 7.540 0 f
TX net TX + 0.000 7.540 f
data arrival time 7.540
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
TX N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 reset_sync_0/reset_sync_0/dff_15:CLK PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3]:ALn 1.316 3.433 4.514 7.947 0.170 1.567 0.081 slow_lv_ht
Path 2 reset_sync_0/reset_sync_0/dff_15:CLK PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[2]:ALn 1.317 3.433 4.515 7.948 0.170 1.567 0.080 slow_lv_ht
Path 3 reset_sync_0/reset_sync_0/dff_15:CLK PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_full_int:ALn 1.317 3.433 4.515 7.948 0.170 1.567 0.080 slow_lv_ht
Path 4 reset_sync_0/reset_sync_0/dff_15:CLK PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[0]:ALn 1.316 3.434 4.514 7.948 0.170 1.566 0.080 slow_lv_ht
Path 5 reset_sync_0/reset_sync_0/dff_15:CLK PF_COREUART_0_0/PF_COREUART_0_0/make_RX/last_bit[0]:ALn 1.316 3.434 4.514 7.948 0.170 1.566 0.080 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: reset_sync_0/reset_sync_0/dff_15:CLK
To: PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3]:ALn
data required time 7.947
data arrival time - 4.514
slack 3.433
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.151 2.223 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.372 2.595 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 2.647 1133 f
reset_sync_0/reset_sync_0/dff_15:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.551 3.198 r
reset_sync_0/reset_sync_0/dff_15:Q cell ADLIB:SLE + 0.175 3.373 2906 r
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3]:ALn net reset_sync_0.reset_sync_0.dff + 1.141 4.514 r
data arrival time 4.514
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 Clock Constraint 5.000 5.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 5.000 r
Clock generation + 1.254 6.254
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 6.398 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 6.529 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 6.874 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.137 7.011 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.333 7.344 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.047 7.391 1133 f
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3]:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.470 7.861 r
clock reconvergence pessimism + 0.256 8.117
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3]:ALn Library recovery time ADLIB:SLE - 0.170 7.947
data required time 7.947
Operating Conditions slow_lv_ht

SET External Recovery

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) External Recovery (ns) Operating Conditions
Path 1 RESET_N reset_sync_0/reset_sync_0/dff_15:ALn 4.343 4.343 0.170 1.635 slow_lv_ht
Path 2 RESET_N reset_sync_0/reset_sync_0/dff_14:ALn 3.592 3.592 0.170 0.911 slow_lv_ht
Path 3 RESET_N reset_sync_0/reset_sync_0/dff_12:ALn 3.160 3.160 0.170 0.509 slow_lv_ht
Path 4 RESET_N reset_sync_0/reset_sync_0/dff_13:ALn 3.159 3.159 0.170 0.508 slow_lv_ht
Path 5 RESET_N reset_sync_0/reset_sync_0/dff_11:ALn 3.078 3.078 0.170 0.420 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RESET_N
To: reset_sync_0/reset_sync_0/dff_15:ALn
data required time N/C
data arrival time - 4.343
slack N/C
Data arrival time calculation
RESET_N 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:PAD net RESET_N + 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.599 0.599 1 r
RESET_N_ibuf/U_IOIN:YIN net RESET_N_ibuf/YIN + 0.000 0.599 r
RESET_N_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.336 0.935 1 r
reset_sync_0/reset_sync_0/un1_D:A net RESET_N_c + 1.386 2.321 r
reset_sync_0/reset_sync_0/un1_D:Y cell ADLIB:CFG4 + 0.145 2.466 16 r
reset_sync_0/reset_sync_0/dff_15:ALn net reset_sync_0/reset_sync_0/un1_INTERNAL_RST_i + 1.877 4.343 r
data arrival time 4.343
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 N/C 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.137 N/C 4 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.333 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.047 N/C 1133 f
reset_sync_0/reset_sync_0/dff_15:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.487 N/C r
reset_sync_0/reset_sync_0/dff_15:ALn Library recovery time ADLIB:SLE - 0.170 N/C
Operating Conditions slow_lv_ht

SET Asynchronous to Register

No Path

SET PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0

No Path

Clock Domain REF_CLK_0

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin REF_CLK_0_ibuf/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets