Global Net Report

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Wed Jan 13 11:20:31 2021

Global Nets Information

	From	GB Location	Net Name	Fanout
1	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0	(1164, 163)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1	3650
2	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0	(1152, 162)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y	1475
3	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0	(1164, 162)	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y	22

I/O to GB Connections

(none)

Fabric to GB Connections

	From	From Location	To	Net Name	Net Type	Fanout
1	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y	(1249, 45)	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2]	ROUTED	1

CCC to GB Connections

	From	From Location	To	Net Name	Net Type	Fanout
1	PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0	(2460, 5)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0	PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0	HARDWIRED	1
2	PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0	(2460, 5)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0	PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0	HARDWIRED	1

CCC Input Connections

	Port Name	Pin Number	I/O Function	From	From Location	To	CCC Location	Net Name	Net Type	Fanout
1	REF_CLK_0	E25	HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0	REF_CLK_0_ibuf/U_IOPAD:Y	(2256, 1)	PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:REF_CLK_0	(2460, 5)	REF_CLK_0_c	HARDWIRED	2

Local Nets to RGB Connections

(none)

Global Nets to RGB Connections

	From	From Location	Net Name	Fanout		RGB Location	Local Fanout
1	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0	(1164, 163)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1	3650	1	(1741, 12)	1133
					2	(1741, 39)	1644
					3	(1747, 12)	865
					4	(1747, 39)	8
2	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0	(1152, 162)	PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y	1475	1	(576, 12)	523
					2	(576, 39)	24
					3	(582, 12)	928
3	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0	(1164, 162)	PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y	22		(1740, 39)	22

Clock Signals Summary

The number of clock signals through H-Chip Global resources	3
The number of clock signals through Row Global resources	8
The number of clock signals through Sector Global resources	47
The number of clock signals through Cluster Global resources	627