logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COEF_BUF/PF_TPSRAM_0_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COEF_BUF/PF_TPSRAM_0_0/PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-16 Port_B_Depth-128 Port_B_Width-16 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-128 Port_A_Width-32 Port_B_Depth-128 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_IM_BUF/PF_TPSRAM_3_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_IM_BUF/PF_TPSRAM_3_0/PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-256 Port_A_Width-16 Port_B_Depth-256 Port_B_Width-16 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_RE_BUF/PF_TPSRAM_4_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_RE_BUF/PF_TPSRAM_4_0/PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-256 Port_A_Width-16 Port_B_Depth-256 Port_B_Width-16 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-16 Port_B_Depth-1024 Port_B_Width-16 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_OUT_BUF/PF_TPSRAM_2_0 Physical_names-[PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_OUT_BUF/PF_TPSRAM_2_0/PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-1024 Port_A_Width-16 Port_B_Depth-1024 Port_B_Width-16 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
