///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title        : led_block.v
// Author       : <Application Team>
// Description  : Shows the status of JESD signals on LEDs. 
// Hierarchy    :
//               hdl           
//					led_block.v   <-- This module
//					prbs_checker.v
//					prbs_generator.v
//					prbs_wav_sel.v
//					reset_synchronizer.v
//					uart_if.v
//					wav_gen_16bit.v
//					err_gen.v      
//  Target device: <Family:PolarFire> <Die:MPF300T> <Pkg:FCG484>  
//
//-------------------------------------------------------------------------





module LED_DEBUG_BLK(SYNC_N,
                     CLK_IN,
                     RESET_N,
                     ALIGNED,
                     CGS_ERR,
                     NIT_ERR,
                     DISP_ERR,
                     LINK_CD_ERR,
                     UCC_ERR,
                     EPCS_0_READY,
                     EPCS_0_RX_VAL,
                     EPCS_0_RX_IDLE,
                     EPCS_0_RX_RESET_N,
                     SEL_IN,
                     LED_OUT,
                     INIT_DONE);
  //----------------------------------------------------------------------
  // Inputs
  //-----------------------------------------------------------------------
  input CLK_IN; // Clock input, 156.25 MHz
  input RESET_N; // Sync reset, active low  
  input SYNC_N; // Status of  JESD204BRX :SYNC_N  signal
  input ALIGNED; // Status of  JESD204BRX :ALIGNED signal
  input CGS_ERR; // Status of  JESD204BRX :CGS Error signal
  input LINK_CD_ERR; // Status of  JESD204BRX :LINK_CD Error signal
  input UCC_ERR; // Status of  JESD204BRX :UCC Error signal
  input[3 : 0] NIT_ERR; // Status of  XCVR : LANE0_RX_CODE_VIOLATION  signal
  input[3 : 0] DISP_ERR; // Status of  XCVR : LANE0_RX_DISPARITY_ERROR signal
  input EPCS_0_READY; // Status of  XCVR : LANE0_RX_READY signal         
  input EPCS_0_RX_VAL; // Status of  XCVR : LANE0_RX_VAL signal         
  input EPCS_0_RX_IDLE; // Status of  XCVR : LANE0_RX_IDLE signal    
  input EPCS_0_RX_RESET_N; // Status of  XCVR : LANE0_PCS_ARST_N signal     
  input INIT_DONE; // Status of  XCVR : LANE0_TX_CLK_STABLE  
  input[3 : 0] SEL_IN; // Debugging selection using DIP switch
  //-----------------------------------------------------------------------
  // Outputs
  //-----------------------------------------------------------------------
  output[7 : 0] LED_OUT; // LED status output  
  //-----------------------------------------------------------------------
  // Internal signals
  //-----------------------------------------------------------------------
  reg[7 : 0] LED_OUT;
  //This block is used to debug the JESD and XCVR  status
  //   
  always
    @(posedge CLK_IN or
      negedge RESET_N)
    begin
      if (!RESET_N)
        begin
          LED_OUT <= 8'hF0;
        end
      else
        begin
          case (SEL_IN[3 : 0])
            //EPCS clocks, Rx valid, Sync, aligned
            4'b0000:
              LED_OUT <= { 1'b0, EPCS_0_RX_IDLE,EPCS_0_READY, 
			              EPCS_0_RX_VAL, EPCS_0_RX_RESET_N,
			              SYNC_N, ALIGNED, INIT_DONE };
            // Error monitoring
            4'b0001:
              LED_OUT <= { 5'b0, CGS_ERR, UCC_ERR, LINK_CD_ERR };
            // Error and EPCS outputs monitoring  
            4'b0010:
              LED_OUT <= { 4'b0, NIT_ERR };
            // Error and EPCS outputs monitoring  
            4'b0011:
              LED_OUT <= { 4'b0, DISP_ERR };
            default:
              LED_OUT <= 8'b01010101;
          endcase
        end
    end
endmodule
