# Import source files
import_files -hdl_source {./src/hdl/err_gen.v}
import_files -hdl_source {./src/hdl/led_block.v}
import_files -hdl_source {./src/hdl/prbs_checker.v}
import_files -hdl_source {./src/hdl/prbs_generator.v}
import_files -hdl_source {./src/hdl/prbs_wav_sel.v}
import_files -hdl_source {./src/hdl/uart_if.v}
import_files -hdl_source {./src/hdl/wav_gen_16bit.v}
import_files -hdl_source {./src/hdl/reset_synchronizer.v}


build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CORE_JESD_RX.tcl
source ./src/components/Core_JESD_TX.tcl
source ./src/components/CORE_UART_0.tcl
source ./src/components/Init_Monitor_0.tcl
source ./src/components/PF_CLK_DIV_C0.tcl
source ./src/components/PF_OSC_0.tcl
source ./src/components/PF_TPSRAM_C0.tcl
source ./src/components/PF_TPSRAM_C1.tcl
source ./src/components/PF_TX_PLL_0.tcl
source ./src/components/PF_XCVR_0.tcl
source ./src/components/PF_XCVR_REF_CLK_0.tcl
source ./src/components/reset_syn.tcl






# Generate SmartDesign Components
build_design_hierarchy 
source ./src/components/DATA_GENERATOR.tcl
build_design_hierarchy 
source ./src/components/DATA_HANDLE.tcl
build_design_hierarchy 
source ./src/components/top.tcl
# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
