library IEEE;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity summer is
generic (g_a_width: INTEGER := 16;
g_B_WIDTH: INTEGER := 16;
G_ADD_width: INteger := 17); port (clock_i: in STD_LOGIC;
nreset_i: in std_logic;
DATA_VLD_I: in STD_LOGIC;
a_I: in STD_LOGIC_vector(G_A_WIDTH-1 downto 0);
b_i: in std_logic_veCTOR(g_b_width-1 downto 0);
p_o: out std_logic_vecTOR(g_add_width-2 downto 0);
data_vld_o: out STD_logic);
end summer;

architecture O of SUMMER is

signal iol: STD_LOGIC_VECTOR(g_a_width-1 downto 0);

signal i00: STD_LOGIC_VECTOR(g_B_WIDTH-1 downto 0);

signal O10: std_logic_VECTOR(g_add_width-1 downto 0);

signal L10: std_logic_vector(G_ADD_WIDTH-2 downto 0);

signal I10: STD_LOGic;

signal oo1: std_logic;

signal lo1: std_logic;

signal io1: std_logic;

signal ol1: std_logic;

signal LL1: std_logic_vectOR(1 downto 0);

begin
iol <= a_I;
i00 <= b_i;
I10 <= DATA_VLD_I;
IL1:
process (NRESET_I,clock_i)
begin
if (NRESET_I = '0') then
O10 <= ( others => '0');
elsif (rising_edge(CLOCK_I)) then
if (i10 = '1') then
o10 <= STD_LOGIC_VECTOR(RESIZE(signed(IOL),
g_add_width)+(REsize(signed(I00),
G_ADD_WIDTH)));
end if;
end if;
end process IL1;
oi1:
process (nRESET_I,clock_i)
begin
if (nreset_i = '0') then
OO1 <= '0';
lo1 <= '0';
elsif (RISING_EDGE(CLOCK_I)) then
OO1 <= I10;
LO1 <= oo1;
end if;
end process oi1;
IO1 <= O10(g_add_WIDTH-1);
OL1 <= o10(g_add_width-2);
LL1 <= IO1&ol1;
li1:
process (NRESET_I,CLOCK_I)
begin
if (NRESEt_i = '0') then
l10 <= ( others => '0');
elsif (rising_EDGE(clock_i)) then
case (LL1) is
when "01" =>
l10 <= X"7fff";
when "10" =>
l10 <= X"8000";
when others =>
l10 <= IO1&o10(G_ADD_WIDTH-3 downto 0);
end case;
end if;
end process;
p_o <= l10;
DATA_VLD_O <= lo1;
end;
