# Creating SmartDesign "DUC_Antenna"
set sd_name {DUC_Antenna}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {clock_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {data_vld_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {nreset_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {data_vld_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {chan_in_i} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {chan_i} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {cos_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {data_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {sin_i} -port_direction {IN} -port_range {[15:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {I0_data_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {I1_data_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Q0_data_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Q1_data_o} -port_direction {OUT} -port_range {[15:0]}


# Add CF_Demux_Mux_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_0}
# Exporting Parameters of instance CF_Demux_Mux_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0}



# Add CF_Demux_Mux_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_1}
# Exporting Parameters of instance CF_Demux_Mux_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1} -params {\
"g_CHAN_WIDTH:2" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_1:chan_out_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_1:chan_out_o} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_1:chan_out_o[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_1:data_vld_o}



# Add CF_Demux_Mux_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_2}
# Exporting Parameters of instance CF_Demux_Mux_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2} -params {\
"g_CHAN_WIDTH:2" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_2:chan_out_o} -pin_slices {[0:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_2:chan_out_o[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_2:chan_out_o} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_2:chan_out_o[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_2:data_vld_o}



# Add CF_Demux_Mux_3 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_3}
# Exporting Parameters of instance CF_Demux_Mux_3
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3} -params {\
"g_CHAN_WIDTH:2" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_3:chan_in_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_3:chan_in_i} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_3:data2_o}



# Add CF_Demux_Mux_6 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_6}
# Exporting Parameters of instance CF_Demux_Mux_6
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6} -params {\
"g_CHAN_WIDTH:2" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_6:chan_in_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CF_Demux_Mux_6:chan_in_i} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_6:data2_o}



# Add Channel_Delay_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Channel_Delay} -instance_name {Channel_Delay_0}
# Exporting Parameters of instance Channel_Delay_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Channel_Delay_0} -params {\
"g_DATA_WIDTH:1" \
"g_DELAYS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Channel_Delay_0}
sd_update_instance -sd_name ${sd_name} -instance_name {Channel_Delay_0}



# Add complex_mult_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {complex_MULT} -instance_name {complex_mult_0}
# Exporting Parameters of instance complex_mult_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {complex_mult_0} -params {\
"g_awidth:16" \
"G_BWIDTH:16" \
"g_cwidth:16" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {complex_mult_0}
sd_update_instance -sd_name ${sd_name} -instance_name {complex_mult_0}



# Add dds_demux_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {dds_demux} -hdl_file {hdl\dds_demux.vhd} -instance_name {dds_demux_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {dds_demux_0:cos1_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {dds_demux_0:sin1_o}



# Add DUC_hb2_int_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUC_HB2_INT} -hdl_file {hdl\DUC_hb2_int.vhd} -instance_name {DUC_hb2_int_0}



# Add DUC_hb2_int_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUC_HB2_INT} -hdl_file {hdl\DUC_hb2_int.vhd} -instance_name {DUC_hb2_int_1}



# Add DUC_hb3_int_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUC_HB3_INT} -hdl_file {hdl\DUC_hb3_int.vhd} -instance_name {DUC_hb3_int_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_0:chan_out_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_0:chan_out_o} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_0:chan_out_o} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DUC_hb3_int_0:chan_out_o[2:2]}



# Add DUC_hb3_int_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUC_HB3_INT} -hdl_file {hdl\DUC_hb3_int.vhd} -instance_name {DUC_hb3_int_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_1:chan_out_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_1:chan_out_o} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DUC_hb3_int_1:chan_out_o} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DUC_hb3_int_1:chan_out_o[2:2]}



# Add DUC_Multi_channel_FIR_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUC_Multi_channel_fir} -hdl_file {hdl\DUC_Multi_channel_FIR.vhd} -instance_name {DUC_Multi_channel_FIR_0}



# Add Mix_Chan_Delay_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Channel_Delay} -instance_name {Mix_Chan_Delay_0}
# Exporting Parameters of instance Mix_Chan_Delay_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_0} -params {\
"g_DATA_WIDTH:2" \
"g_DELAYS:7" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_0}
sd_update_instance -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_0}



# Add Mix_Chan_Delay_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Channel_Delay} -instance_name {Mix_Chan_Delay_1}
# Exporting Parameters of instance Mix_Chan_Delay_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_1} -params {\
"g_DATA_WIDTH:2" \
"g_DELAYS:7" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_1}
sd_update_instance -sd_name ${sd_name} -instance_name {Mix_Chan_Delay_1}



# Add Mix_Valid_Delay_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Channel_Delay} -instance_name {Mix_Valid_Delay_0}
# Exporting Parameters of instance Mix_Valid_Delay_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_0} -params {\
"g_DATA_WIDTH:1" \
"g_DELAYS:5" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_0}
sd_update_instance -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_0}



# Add Mix_Valid_Delay_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Channel_Delay} -instance_name {Mix_Valid_Delay_2}
# Exporting Parameters of instance Mix_Valid_Delay_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_2} -params {\
"g_DATA_WIDTH:1" \
"g_DELAYS:5" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_2}
sd_update_instance -sd_name ${sd_name} -instance_name {Mix_Valid_Delay_2}



# Add Summer_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {summer} -instance_name {Summer_0}
# Exporting Parameters of instance Summer_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Summer_0} -params {\
"g_a_width:16" \
"G_ADD_width:17" \
"g_B_WIDTH:16" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Summer_0}
sd_update_instance -sd_name ${sd_name} -instance_name {Summer_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Summer_0:b_i} -value {GND}



# Add Summer_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {summer} -instance_name {Summer_2}
# Exporting Parameters of instance Summer_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Summer_2} -params {\
"g_a_width:16" \
"G_ADD_width:17" \
"g_B_WIDTH:16" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Summer_2}
sd_update_instance -sd_name ${sd_name} -instance_name {Summer_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Summer_2:b_i} -value {GND}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:clock_i" "CF_Demux_Mux_1:clock_i" "CF_Demux_Mux_2:clock_i" "CF_Demux_Mux_3:clock_i" "CF_Demux_Mux_6:clock_i" "Channel_Delay_0:clock_i" "DUC_Multi_channel_FIR_0:CLOCK_I" "DUC_hb2_int_0:clock_i" "DUC_hb2_int_1:clock_i" "DUC_hb3_int_0:clock_i" "DUC_hb3_int_1:clock_i" "Mix_Chan_Delay_0:clock_i" "Mix_Chan_Delay_1:clock_i" "Mix_Valid_Delay_0:clock_i" "Mix_Valid_Delay_2:clock_i" "Summer_0:clock_i" "Summer_2:clock_i" "clock_i" "complex_mult_0:clock_i" "dds_demux_0:clock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_vld_i" "DUC_Multi_channel_FIR_0:data_VLD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_vld_o" "DUC_hb3_int_0:data_vld_i" "DUC_hb3_int_1:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:nreset_i" "CF_Demux_Mux_1:nreset_i" "CF_Demux_Mux_2:nreset_i" "CF_Demux_Mux_3:nreset_i" "CF_Demux_Mux_6:nreset_i" "Channel_Delay_0:nreset_i" "DUC_Multi_channel_FIR_0:NRESET_I" "DUC_hb2_int_0:nrESET_I" "DUC_hb2_int_1:nrESET_I" "DUC_hb3_int_0:NRESET_i" "DUC_hb3_int_1:NRESET_i" "Mix_Chan_Delay_0:nreset_i" "Mix_Chan_Delay_1:nreset_i" "Mix_Valid_Delay_0:nreset_i" "Mix_Valid_Delay_2:nreset_i" "Summer_0:nreset_i" "Summer_2:nreset_i" "complex_mult_0:nreset_i" "dds_demux_0:nreset_i" "nreset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:chan_out_o[0:0]" "Channel_Delay_0:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data_vld_i" "DUC_hb2_int_0:DATA_VLD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data_vld_i" "DUC_hb2_int_1:DATA_VLD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:chan_in_i[0:0]" "DUC_hb3_int_0:chan_out_o[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:chan_in_i[1:1]" "DUC_hb3_int_0:chan_out_o[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data_vld_i" "DUC_hb3_int_0:data_vlD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data_vld_o" "Mix_Valid_Delay_0:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:chan_in_i[0:0]" "DUC_hb3_int_1:chan_out_o[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:chan_in_i[1:1]" "DUC_hb3_int_1:chan_out_o[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data_vld_i" "DUC_hb3_int_1:data_vlD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data_vld_o" "Mix_Valid_Delay_2:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Channel_Delay_0:data_o" "data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_Multi_channel_FIR_0:DATA_VLD_I" "data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_0:DATA_VLd_i" "Summer_0:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_1:DATA_VLd_i" "Summer_2:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Mix_Valid_Delay_0:data_o" "Summer_0:DATA_VLD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Mix_Valid_Delay_2:data_o" "Summer_2:DATA_VLD_I" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:chan_in_i" "DUC_Multi_channel_FIR_0:chAN_OUT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:chan_out_o" "DUC_hb3_int_0:chan_in_i" "DUC_hb3_int_1:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data1_o" "DUC_hb3_int_0:Data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data2_o" "DUC_hb3_int_1:Data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_i" "DUC_Multi_channel_FIR_0:DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:chan_in_i" "DUC_hb2_int_0:chan_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data1_o" "I0_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data2_o" "I1_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data_i" "DUC_hb2_int_0:data_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:chan_in_i" "DUC_hb2_int_1:chan_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data1_o" "Q0_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data2_o" "Q1_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data_i" "DUC_hb2_int_1:data_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:chan_out_o" "Mix_Chan_Delay_0:data_i" "dds_demux_0:data_chan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data1_o" "complex_mult_0:areal_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data_i" "DUC_hb3_int_0:DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:chan_out_o" "Mix_Chan_Delay_1:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data1_o" "complex_mult_0:AIMAG_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data_i" "DUC_hb3_int_1:DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_Multi_channel_FIR_0:CHAN_IN_I" "chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_Multi_channel_FIR_0:DATA_I" "data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_0:DATA_I" "Summer_0:p_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_0:chan_in_i" "Mix_Chan_Delay_0:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_1:DATA_I" "Summer_2:p_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUC_hb2_int_1:chan_in_i" "Mix_Chan_Delay_1:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Summer_0:a_I" "complex_mult_0:creal_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Summer_2:a_I" "complex_mult_0:CIMAG_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"chan_i" "dds_demux_0:chan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"complex_mult_0:BREal_i" "dds_demux_0:cos0_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"complex_mult_0:bimag_i" "dds_demux_0:sin0_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cos_i" "dds_demux_0:cos_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"dds_demux_0:sin_i" "sin_i" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "DUC_Antenna"
generate_component -component_name ${sd_name}
