--/******************************************************************************
--    Company      		: MICROSEMI

--    File Name    		: DUCDDC_Top.vhd 
                   		
--    Description  		: This module instantiates DUC and DDC Top modules

--    Targeted device 	: Family           Die          Package
--                   	  PolarFire     MPF300T_ES      MPF300T_ES

--    Author          	: India Solutions Team

--
-- SVN Revision Information:
-- SVN $Revision: 
-- SVN $Date:  $  
-- COPYRIGHT 2018 BY MICROSEMI 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM MICROSEMI CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
-- 

--******************************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
use work.System_pack.all;

entity DUCDDC_Top is        
  port( 		
    clock_i        			              : in     std_logic;                           -- Clock signal
			 nreset_i       			              : in     std_logic;                           -- Asynchronous reset signal
    -- DUC Inputs			    
    duc_data_vld_i_0                : in  std_logic;                              -- Input duc data valid signals  
    duc_chan_i_0                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals          
			 duc_data_i_0				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals
    duc_data_vld_i_1                : in  std_logic;                              -- Input duc data valid signals 
    duc_chan_i_1                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals     
			 duc_data_i_1				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals   
    duc_freqvalue_i                 : in  std_logic_vector(31 downto 0);          -- Input duc dds frequency value signal
    duc_freqword_ch_i               : in  std_logic_vector(1 downto 0);           -- Input duc dds frequency channel signal
    duc_freqword_en_i               : in  std_logic;                              -- Input duc dds frequency enable signal
    -- DDC Inputs                  
    ddc_freqvalue_i                 : in  std_logic_vector(31 downto 0);          -- Input ddc dds frequency value signal
    ddc_freqword_ch_i               : in  std_logic_vector(1 downto 0);           -- Input ddc dds frequency channel signal
    ddc_freqword_en_i               : in  std_logic;                              -- Input ddc dds frequency enable signal
    -- DUC Outputs                 
    duc_I0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Inphase data signals
    duc_Q0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Quadrature data signals
    duc_I1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Inphase data signals
    duc_Q1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Quadrature data signals
    duc_data_vld_o_0                : out  std_logic;                             --- Output duc data valid signals
    duc_I0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Inphase data signals
    duc_Q0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Quadrature data signals
    duc_I1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Inphase data signals
    duc_Q1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Quadrature data signals
    duc_data_vld_o_1                : out  std_logic;                             -- Output duc data valid signals
    -- DDC Inputs                  
    ddc_I0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Inphase data signals    
    ddc_Q0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Quadrature data signals     
    ddc_I1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Inphase data signals
    ddc_Q1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Quadrature data signals      
    ddc_data_vld_i_0                : in  std_logic;                              -- Input ddc data valid signals  
    ddc_I0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Inphase data signals      
    ddc_Q0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Quadrature data signals        
    ddc_I1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Inphase data signals
    ddc_Q1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Quadrature data signals     
    ddc_data_vld_i_1                : in  std_logic;                              -- Input ddc data valid signals  
    -- DDC Outputs
			 ddc_data_vld_o_0                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_0                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_0				                : out  std_logic_vector (15   downto 0);      -- Output ddc data  signals
    ddc_data_vld_o_1                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_1                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_1				                : out  std_logic_vector (15   downto 0)       -- Output ddc data  signals

);
end DUCDDC_Top;
architecture architecture_DUCDDC_Top of DUCDDC_Top is
-----------------------------------------------------------------------------------------------------------------------
-- component declarations 
-----------------------------------------------------------------------------------------------------------------------
-- DUC_Top
component DUC_Top
  port( 
			 clock_i        			              : in     std_logic;
			 nreset_i       			              : in     std_logic;
    -- DUC Inputs
    duc_data_vld_i_0                : in  std_logic;                              -- Input duc data valid signals  
    duc_chan_i_0                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals          
    duc_data_i_0				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals
    duc_data_vld_i_1                : in  std_logic;                              -- Input duc data valid signals 
    duc_chan_i_1                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals     
    duc_data_i_1				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals 
    duc_freqvalue_i                 : in  std_logic_vector(31 downto 0);
    duc_freqword_ch_i               : in  std_logic_vector(1 downto 0);
    duc_freqword_en_i               : in  std_logic;      
    -- DUC Outputs   
    duc_I0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Inphase data signals
    duc_Q0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Quadrature data signals
    duc_I1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Inphase data signals
    duc_Q1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Quadrature data signals
    duc_data_vld_o_0                : out  std_logic;                             --- Output duc data valid signals
    duc_I0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Inphase data signals
    duc_Q0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Quadrature data signals
    duc_I1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Inphase data signals
    duc_Q1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Quadrature data signals
    duc_data_vld_o_1                : out  std_logic
  );
end component;

-- DDC_Top
component DDC_Top
  port( 
			 clock_i        			              : in     std_logic;
			 nreset_i       			              : in     std_logic;
    -- DDC Inputs
    ddc_I0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Inphase data signals    
    ddc_Q0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Quadrature data signals     
    ddc_I1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Inphase data signals
    ddc_Q1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Quadrature data signals      
    ddc_data_vld_i_0                : in  std_logic;                              -- Input ddc data valid signals  
    ddc_I0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Inphase data signals      
    ddc_Q0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Quadrature data signals        
    ddc_I1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Inphase data signals
    ddc_Q1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Quadrature data signals     
    ddc_data_vld_i_1                : in  std_logic;
    ddc_freqvalue_i                 : in  std_logic_vector(31 downto 0);
    ddc_freqword_ch_i               : in  std_logic_vector(1 downto 0);
    ddc_freqword_en_i               : in  std_logic;
    -- DDC Outputs
    ddc_data_vld_o_0                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_0                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_0				                : out  std_logic_vector (15   downto 0);      -- Output ddc data  signals
    ddc_data_vld_o_1                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_1                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_1				                : out  std_logic_vector (15   downto 0) 
  );
end component;
--------------------------------------------------------------------------------------------------------------------------
-- signal declaration
-------------------------------------------------------------------------------------------------------------------------- 
signal  ddc_I0_data_i               :   T_Antenna_dataout;
signal  ddc_Q0_data_i               :   T_Antenna_dataout;
signal  ddc_I1_data_i               :   T_Antenna_dataout;
signal  ddc_Q1_data_i               :   T_Antenna_dataout; 
signal  ddc_data_vld_i              :   T_Antenna_Rxvalid; 
signal  ddc_data_vld_o              :   T_Antenna_Rxvalid;
signal  ddc_chan_o                  :   T_Antenna_chanout;
signal	 ddc_data_o				              :   T_Antenna_dataout;
signal  duc_data_vld_i              :   T_Antenna_Txvalid;
signal  duc_chan_i                  :   T_Antenna_chanin;
signal	 duc_data_i				              :   T_Antenna_datain;
signal  duc_I0_data_o               :   T_Antenna_datain;
signal  duc_Q0_data_o               :   T_Antenna_datain;
signal  duc_I1_data_o               :   T_Antenna_datain;
signal  duc_Q1_data_o               :   T_Antenna_datain; 
signal  duc_data_vld_o              :   T_Antenna_Txvalid;


begin

-- DUC_Top_0
DUC_Top_0 : DUC_Top    
  port map( 
    -- Inputs
    clock_i            => clock_i,
    nreset_i           => nreset_i,
    duc_data_vld_i_0   => duc_data_vld_i_0,
    duc_chan_i_0       => duc_chan_i_0,
    duc_data_i_0       => duc_data_i_0, 
    duc_data_vld_i_1   => duc_data_vld_i_1,
    duc_chan_i_1       => duc_chan_i_1,
    duc_data_i_1       => duc_data_i_1, 
    duc_freqvalue_i    => duc_freqvalue_i,
    duc_freqword_ch_i  => duc_freqword_ch_i,
    duc_freqword_en_i  => duc_freqword_en_i,
    -- Outputs
    duc_I0_data_o_0    => duc_I0_data_o_0,  
    duc_Q0_data_o_0    => duc_Q0_data_o_0,  
    duc_I1_data_o_0    => duc_I1_data_o_0,  
    duc_Q1_data_o_0    => duc_Q1_data_o_0,  
    duc_data_vld_o_0   => duc_data_vld_o_0, 
    duc_I0_data_o_1    => duc_I0_data_o_1,  
    duc_Q0_data_o_1    => duc_Q0_data_o_1,  
    duc_I1_data_o_1    => duc_I1_data_o_1,  
    duc_Q1_data_o_1    => duc_Q1_data_o_1, 
    duc_data_vld_o_1   => duc_data_vld_o_1              
  );

-- DDC_Top_0
DDC_Top_0 : DDC_Top
  port map( 
    -- Inputs
    clock_i           => clock_i,
    nreset_i          => nreset_i,
    ddc_I0_data_i_0   =>  ddc_I0_data_i_0, 
    ddc_Q0_data_i_0   =>  ddc_Q0_data_i_0,     
    ddc_I1_data_i_0   =>  ddc_I1_data_i_0, 
    ddc_Q1_data_i_0   =>  ddc_Q1_data_i_0,      
    ddc_data_vld_i_0  =>  ddc_data_vld_i_0,
    ddc_I0_data_i_1   =>  ddc_I0_data_i_1,   
    ddc_Q0_data_i_1   =>  ddc_Q0_data_i_1,        
    ddc_I1_data_i_1   =>  ddc_I1_data_i_1, 
    ddc_Q1_data_i_1   =>  ddc_Q1_data_i_1,     
    ddc_data_vld_i_1  =>  ddc_data_vld_i_1,
    ddc_freqvalue_i   => ddc_freqvalue_i,
    ddc_freqword_ch_i => ddc_freqword_ch_i,
    ddc_freqword_en_i => ddc_freqword_en_i,
    -- Outputs
    ddc_data_vld_o_0  => ddc_data_vld_o_0,
    ddc_chan_o_0      => ddc_chan_o_0,    
		  ddc_data_o_0		    => ddc_data_o_0,	
    ddc_data_vld_o_1  => ddc_data_vld_o_1,
    ddc_chan_o_1      => ddc_chan_o_1,    
		  ddc_data_o_1		    => ddc_data_o_1	
  );
    
end architecture_DUCDDC_Top;
