# Import source files
file copy -force "./src/cfg/sincos.hex" "./$Prjname/sincos.hex"

import_files -hdl_source {./src/hdl/CF_Demux_Mux.vhd}
import_files -hdl_source {./src/hdl/CNTRL_LPBCK.v}
import_files -hdl_source {./src/hdl/Data_Shifter.vhd}
import_files -hdl_source {./src/hdl/Macc_ROM.vhd}
import_files -hdl_source {./src/hdl/round_sat.vhd}
import_files -hdl_source {./src/hdl/mult_addsub.vhd}
import_files -hdl_source {./src/hdl/System_pack.vhd}
import_files -hdl_source {./src/hdl/ddc_hb3_dec_coeffpack.vhd}
import_files -hdl_source {./src/hdl/DDC_hb3_dec.vhd}
import_files -hdl_source {./src/hdl/ddc_cf_coeffpack .vhd}
import_files -hdl_source {./src/hdl/DDC_Multi_channel_FIR.vhd}
import_files -hdl_source {./src/hdl/complex_mult.vhd}
import_files -hdl_source {./src/hdl/ddc_hb2_dec_coeffpack.vhd}
import_files -hdl_source {./src/hdl/DDC_hb2_dec.vhd}
import_files -hdl_source {./src/hdl/dds_pack.vhd}
import_files -hdl_source {./src/hdl/dds_demux.vhd}
import_files -hdl_source {./src/hdl/Channel_Mux.vhd}
import_files -hdl_source {./src/hdl/Channel_Delay.vhd}
import_files -hdl_source {./src/hdl/dds_top.vhd}
import_files -hdl_source {./src/hdl/DDC_Top.vhd}
import_files -hdl_source {./src/hdl/duc_hb2_int_coeffpack.vhd}
import_files -hdl_source {./src/hdl/DUC_hb2_int.vhd}
import_files -hdl_source {./src/hdl/duc_hb3_int_coeffpack.vhd}
import_files -hdl_source {./src/hdl/DUC_hb3_int.vhd}
import_files -hdl_source {./src/hdl/duc_cf_coeffpack.vhd}
import_files -hdl_source {./src/hdl/DUC_Multi_channel_FIR.vhd}
import_files -hdl_source {./src/hdl/Summer.vhd}
import_files -hdl_source {./src/hdl/DUC_Top.vhd}
import_files -hdl_source {./src/hdl/DUCDDC_Top.vhd}
import_files -hdl_source {./src/hdl/IQ_packer.v}
import_files -hdl_source {./src/hdl/IQ_unpacker.v}
import_files -hdl_source {./src/hdl/LED_STATUS.v}
import_files -hdl_source {./src/hdl/cdc_data_ram.vhd}
import_files -hdl_source {./src/hdl/ddc_axc_tdm_data.vhd}
import_files -hdl_source {./src/hdl/duc_axc_tdm_data.vhd}
import_files -hdl_source {./src/hdl/heart_beat.vhd}
build_design_hierarchy

# Create, configure and generate core components
#Sourcing the Tcl files in which HDL+ core definitions are created for HDL modules
source ./src/components/CF_Demux_Mux.tcl 
source ./src/components/complex_MULT.tcl 
source ./src/components/Channel_Mux.tcl 
source ./src/components/Channel_Delay.tcl 
source ./src/components/DDC_Top.tcl 
source ./src/components/summer.tcl 
source ./src/components/DUC_Top.tcl 
source ./src/components/cdc_data_ram.tcl 
source ./src/components/ddc_axc_tdm_data.tcl 
source ./src/components/duc_axc_tdm_data.tcl 
source ./src/components/heart_beat.tcl 
build_design_hierarchy

#Sourcing the Tcl files for creating individual components under the top level
source ./src/components/BUFFER_LPBCK.tcl 
source ./src/components/CPRI_IP0.tcl 
source ./src/components/PF_TX_PLL_C1.tcl 
source ./src/components/PF_XCVR_ERM_C1.tcl 
source ./src/components/CPRI_TOP.tcl 
source ./src/components/DDC_Antenna.tcl 
source ./src/components/sincos_ram.tcl 
source ./src/components/DUC_Antenna.tcl 
source ./src/components/PF_TX_PLL_C0.tcl 
source ./src/components/PF_XCVR_ERM_C0.tcl 
source ./src/components/JESD204B_IF.tcl 
source ./src/components/CCC_0.tcl 
source ./src/components/COREAHBTOAPB30.tcl 
source ./src/components/COREAXI4_INTERCONNECT.tcl 
source ./src/components/CORERESET_PF_C0.tcl 
source ./src/components/CORERESET_PF_C1.tcl 
source ./src/components/CoreAHBLite0.tcl 
source ./src/components/CoreAPB3_0.tcl 
source ./src/components/CoreJTAGDebug_0.tcl 
source ./src/components/CoreUARTapb0.tcl 
source ./src/components/MIV_RV32_C0.tcl 
source ./src/components/PF_DDR3_C0.tcl 
source ./src/components/PF_Init.tcl 
source ./src/components/SPI_Controller.tcl 
source ./src/components/coregpio_inout.tcl 
source ./src/components/MiV_SUBSYSTEM.tcl 
source ./src/components/RISCV_TOP.tcl 
source ./src/components/cdcram.tcl 
source ./src/components/top.tcl 

#Downgrade the DRC check
smartdesign -memory_map_drc_change_error_to_warning true \

# Generate SmartDesign Components

build_design_hierarchy 
# source ./src/components/Radio4x4_20BW.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
