library ieee;
use Ieee.std_logIC_1164.all;
use ieee.numeric_std.all;
use IEee.Std_logic_unsigned.all;
use ieee.MATH_REAL.all;
use work.SYSTEM_pack.all;
use work.Duc_hb2_int_coeffpack.all;
entity DUC_HB2_INT is
port (clock_i: in std_LOGIC;
nrESET_I: in STD_LOGIC;
DATA_VLd_i: in STD_LOGIC;
DATA_I: in std_logic_vector(g_daTAIN_WIDTH-1 downto 0);
data_O: out std_logic_vector(g_dataout_width-1 downto 0);
chan_in_i: in STD_LOGIC_vector(g_chan_wIDTH-1 downto 0);
chan_out_o: out STD_LOGIC_VECTOR(g_chan_width-1 downto 0);
DATA_VLD_O: out STD_LOGIC);
end duc_hb2_int;

architecture O of duc_HB2_INT is

attribute SYN_preserve: BOOLEAN;

attribute syN_PRESERVE of O: architecture is TRUE;

signal L: STD_LOGIC;

signal I: std_logic_vector(g_datain_width-1 downto 0);

signal ol: STD_logic_vector(g_datain_width-1 downto 0);

type ll is array (0 to G_DSPCOUNT-1) of STd_logic_vector(0 downto 0);

type IL is array (1 to g_dspcount-1) of STD_LOGIC_VECTOR(0 downto 0);

signal oi: IL;

signal li: ll;

type II is array (0 to g_dspcount-1) of STD_LOGIC_VECTOR((G_DATAIN_Width-1) downto 0);

type O0 is array (1 to G_DSPCOUNT-1) of STD_LOGIc_vector((G_DATAIN_width-1) downto 0);

signal L0: O0;

signal i0: II;

signal O1: II;

signal L1: ii;

signal i1: STD_LOGIc;

signal OOL: STD_LOGIC_VECTOR(0 downto 0);

signal lol: STD_logic_vector(0 downto 0);

signal iol: STD_LOGIc_vector(G_COEFF_WIDTH-1 downto 0);

type OLL is array (0 to G_DSPCOUNT-1) of STD_LOGIC_VECTOR((g_accwidth-1) downto 0);

signal LLL: OLL;

signal ILL: oll;

type OIL is array (0 to G_DSPCOUNT-1) of std_logic_vector((G_FINALADDWidth-1) downto 0);

signal LIL: OLL;

signal IIL: sTD_LOGIC_VECTOR(G_ACCWIDTH-1 downto 0);

signal o0l: STd_logic_vector(g_datain_width-1 downto 0);

signal l0l: STD_LOGIc_vector(G_FINALADDWIDth-1 downto 0);

signal i0l: STD_LOGIC_VECTOR(G_FINALADDWIDTH-1 downto 0);

signal o1l: std_logic_vector((g_chan_width-1) downto 0);

signal l1l: STD_LOgic_vector((G_CHAN_WIDTh-1) downto 0);

signal i1l: STD_LOGIC_VEctor((g_cHAN_WIDTH-1) downto 0);

signal ooi: std_logic_vector(G_DATAOUT_WIDth-1 downto 0);

signal LOI: std_logiC_VECTOR(g_datain_width-1 downto 0);

signal ioi: STD_logic_vector(G_DATAIN_width-1 downto 0);

signal oLI: STD_logic_vector(G_ACCWIdth-1 downto 0);

signal lli: std_logic;

component datA_SHIFTER
generic (g_data_width: integer := 16;
G_SHIFT_DELAY: INTEGER := 3);
port (CLOCK_I: in std_logic;
nresET_I: in std_logic;
SHIFT_EN_I: in std_logic;
data_i: in std_logic_VECTOR((g_daTA_WIDTH-1) downto 0);
data_o: out std_logic_veCTOR((g_DATA_WIDTH-1) downto 0));
end component;

component mult_addsub is
generic (G_A_WIDTh: integer := 16;
g_b_width: integer := 16;
G_d_width: integer := 16;
G_C_WIDTH: INTEGER := 37;
g_cin_width: integer := 37;
G_P_WIdth: integer := 37);
port (clock_i: in std_logic;
nreseT_I: in std_logic;
a_i: in std_logic_VECTOR(g_a_width-1 downto 0);
B_I: in std_logic_vector(g_b_width-1 downto 0);
D_I: in std_logic_vector(G_D_WIDTH-1 downto 0);
c_i: in std_logic_vecTOR(g_c_width-1 downto 0);
CIN_i: in std_logic_vecTOR(G_CIN_WIDTH-1 downto 0);
cdin_fdbk_sel_i: in STD_LOGIC_vector(1 downto 0);
cdout_o: out STD_LOGIC_VECTOR(G_P_WIDTH-1 downto 0);
p_o: out STD_LOGIC_VECTOR(G_P_WIDTH-1 downto 0));
end component;

component macc_rom
generic (G_A_WIDTh: INTeger := 16;
G_B_WIDTH: INTEGER := 16;
G_D_WIDTH: INTEGER := 16;
g_c_width: integer := 37;
G_Cin_width: integer := 37;
G_p_width: integer := 37;
G_INIT: STD_LOGIC_VECTOR(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000");
port (clock_i: in std_logic;
NRESET_I: in std_logIC;
a_i: in STD_LOGIC_VECTOR(G_A_WIDTH-1 downto 0);
b_i: in STD_LOGIC_VECTOR(g_b_width-1 downto 0);
a_rom_addr_i: in STD_LOGIC_VECTOR(3 downto 0);
d_i: in STD_LOGIC_VECTOR(g_d_width-1 downto 0);
c_i: in stD_LOGIC_VECTOR(G_C_WIDTH-1 downto 0);
cin_i: in std_logIC_VECTOR(G_CIN_Width-1 downto 0);
CDIN_FDBK_SEL_I: in std_logic_vECTOR(1 downto 0);
CDOUT_O: out std_loGIC_VECTOR(47 downto 0);
p_o: out std_logic_vector(g_p_width-1 downto 0));
end component;

component ROUND_SAT is
generic (G_UNRND_DATA_WIDTH: positive := 33;
g_rnd_DATA_WIDTH: POSITIVE := 16;
g_unrnd_fract_bits: pOSITIVE := 30;
G_RND_FRACT_BITS: POSITIVE := 15);
port (CLOck_i: in STD_LOGIC;
NRESET_I: in std_logic;
DATA_I: in STD_Logic_vector(G_UNRND_DATA_WIDTH-1 downto 0);
data_o: out STD_LOGIc_vector(g_rnd_data_width-1 downto 0));
end component;

begin
ILI:
process (NRESET_I,clock_i)
begin
if (NRESET_I = '0') then
L <= '0';
elsif (RISING_EDGE(CLOCK_I)) then
L <= DATa_vld_i;
end if;
end process ili;
oii:
process (nreset_i,CLOCK_I)
begin
if (nreset_I = '0') then
i <= ( others => '0');
OL <= ( others => '0');
elsif (RISING_EDGE(clock_i)) then
I <= ol;
OL <= DATA_I;
end if;
end process OII;
LII:
for III in 1 to (g_dspcouNT-1)
generate
begin
p_fwd_delay_sHIFT: data_shiFTER
generic map (G_DATA_WIDth => 1,
g_shift_delay => 1)
port map (CLOCK_I => clock_i,
nreset_i => nRESET_I,
shift_en_i => '1',
DATA_I => oi(iii),
data_o => li(III));
end generate LII;
li(0)(0) <= L;
o0i:
for III in 0 to (g_dspcount-2)
generate
begin
OI(iii+1) <= LI(iii);
end generate O0I;
L0I:
for iii in 1 to (G_DSPCOUNT-1)
generate
begin
P_fwd_delay_ram: DATA_SHIFter
generic map (g_data_width => G_DATAIN_WIDTH,
G_SHIFt_delay => G_Chancount+1)
port map (cloCK_I => CLock_i,
nreset_i => NRESEt_i,
SHIFT_EN_I => LI(III)(0),
DATA_I => L0(III),
DATA_O => I0(III));
end generate l0i;
i0(0) <= I;
I0I:
for iii in 0 to (G_DSPCOUNT-2)
generate
begin
L0(iii+1) <= I0(iii);
end generate I0I;
o1(0) <= I0(g_dspcount-1);
I1 <= LI(G_Dspcount-1)(0);
o1i:
if (g_has_sYMM = 1)
generate
L1I:
if (G_SYMM = 0)
generate
P_REV_DELAY_RAM_0: DATA_SHIfter
generic map (G_data_width => g_datain_width,
g_shift_delAY => 0)
port map (clock_i => CLOCK_I,
NRESET_I => NRESET_I,
shift_en_i => I1,
DAta_i => o1(0),
data_o => L1(0));
end generate l1i;
I1I:
if (G_SYMM = 1)
generate
P_REV_DELAY_RAM_0: DATA_SHIFTER
generic map (g_dATA_WIDTH => G_DAtain_width,
g_shift_delay => g_chanCOUNT)
port map (clock_I => CLOCK_I,
NRESET_I => nreset_i,
shiFT_EN_I => i1,
data_i => o1(0),
daTA_O => l1(0));
end generate i1i;
P_FINAl_delay_shift: data_shifter
generic map (G_DATA_WIDTH => 1,
G_SHIFT_delay => (G_DSPCOUNT+4))
port map (CLOCK_I => CLOCK_I,
NRESET_I => nreset_i,
shift_en_i => '1',
data_i => ool,
data_o => lol);
ool(0) <= L;
OO0:
for iii in 1 to (G_DSPCOUNT-1)
generate
begin
p_rev_delay_ram: data_shifter
generic map (g_data_width => G_DATAIN_WIDTH,
g_shift_delay => G_CHANCOUNT-1)
port map (clock_i => clock_i,
nreset_I => NRESET_I,
SHIFT_en_i => '1',
data_i => o1(III),
DATA_O => L1(III));
end generate OO0;
lo0:
for iii in 0 to (g_dspcount-2)
generate
begin
O1(iii+1) <= l1(iii);
end generate LO0;
end generate o1i;
iil <= ( others => '0');
IOL <= ( others => '0');
P_mult_acc0: Macc_rom
generic map (g_a_width => g_coeff_wIDTH,
G_B_WIDTH => g_datain_width,
g_d_wiDTH => G_DATAIN_WIdth,
g_c_width => G_ACCWIDTH,
g_cin_width => G_ACCWIDTH,
G_P_WIDTH => g_accwidth,
g_init => G_INIT)
port map (clock_i => clock_i,
nreset_i => nreset_i,
a_i => Iol,
B_I => I0(0),
A_rom_addr_i => "0000",
d_I => l1(G_DSPCOUNT-1),
c_i => IIL,
cin_i => ill(0),
cdin_fdbk_sEL_I => "00",
CDOut_o => lll(0),
P_O => lil(0));
io0:
for III in 1 to (G_dspcount-1)
generate
begin
P_MULT_ACC: macc_rom
generic map (G_A_WIDTH => g_coeff_widTH,
G_B_WIDTH => G_DATAIN_width,
g_d_width => G_datain_width,
g_c_width => g_accwidth,
g_CIN_WIDTH => g_accwidth,
G_P_WIDTH => G_ACCWIDTH,
g_init => g_init)
port map (clOCK_I => CLOCK_I,
NRESET_I => NRESEt_i,
a_i => IOl,
b_i => i0(iii),
A_ROM_ADDR_I => std_logic_VECTOR(TO_UNSIGNED(iii,
4)),
D_i => l1(G_DSPCOUNT-1-iii),
c_i => iil,
cIN_I => ILL(III),
CDIN_FDBK_SEL_I => "11",
cdout_o => lll(III),
P_O => lil(Iii));
end generate io0;
ol0:
for III in 0 to (G_DSPCOUNT-2)
generate
begin
ILL(III+1) <= LLL(III);
end generate OL0;
ill(0) <= ( others => '0');
ll0:
process (NRESET_I,CLOCK_I)
begin
if (nreset_i = '0') then
L0L <= ( others => '0');
elsif (rising_edge(CLOCK_I)) then
L0L <= std_logic_vector(resize(signed(lil(G_DSPCOUNT-1)),
G_FINALADDWIDTH));
end if;
end process ll0;
loi <= i0(G_DSPCOUNT-1);
P_CENTER_delay_ram: data_shifter
generic map (G_DATA_WIDTH => g_datain_width,
g_shift_delaY => G_NUMCHANNELS+1)
port map (CLOCK_I => clock_i,
nreset_i => nreset_i,
shift_en_i => '1',
data_i => LOI,
data_o => IOI);
p_mult_center: mult_addsub
generic map (g_a_width => G_COEFF_WIDTH,
G_B_WIDTH => g_datain_width,
g_d_WIDTH => G_datain_width,
g_c_width => g_accwidth,
g_cin_width => g_accwidtH,
g_p_width => g_accwiDTH)
port map (CLOCK_I => CLOCK_I,
NRESET_I => nreset_i,
a_i => G_CENTER_TAP,
B_I => IOI,
D_I => O0L,
c_I => IIL,
CIN_I => IIL,
CDIN_FDBK_SEL_i => "00",
cdout_o => open ,
P_O => OLI);
O0L <= ( others => '0');
il0:
process (NRESET_I,clock_I)
begin
if (NRESET_I = '0') then
o1l <= ( others => '0');
elsif (rising_edge(clock_i)) then
if (lol(0) = '1') then
if (i1l = sTD_LOGIC_VECTOR(to_unsigned((G_NUMCHANNels),
g_chan_width)) or I1L = std_logic_vector(to_unsigned((0),
g_chan_width))) then
o1l <= ( others => '0');
else
o1l <= o1l+'1';
end if;
end if;
end if;
end process il0;
oi0: data_shifter
generic map (G_DATA_WIdth => g_chan_width,
G_SHIFT_DELAY => (g_dspcount+3))
port map (CLock_i => clock_i,
nreset_i => nreset_i,
shift_en_i => '1',
data_i => chan_in_i,
data_o => i1l);
li0:
process (nreset_i,CLOCK_i)
begin
if (nreset_i = '0') then
LLi <= '0';
elsif (rising_edgE(clock_i)) then
if (I1L > std_logic_vector(TO_UNSIGNED(G_NUMCHANNELS-1,
g_chan_width)) and lol(0) = '1') then
lli <= '1';
else
lli <= '0';
end if;
end if;
end process li0;
ii0:
process (nresET_I,clock_i)
begin
if (NRESET_I = '0') then
I0L <= ( others => '0');
elsif (rising_edge(CLOck_i)) then
if (llI = '0') then
i0l <= l0l;
else
i0l <= std_logic_vector(resize(signed(OLi),
g_finaLADDWIDTH));
end if;
end if;
end process II0;
U_ROUND_SAT: ROUND_SAT
generic map (G_UNRND_data_width => G_finaladdwidth,
G_RND_DATA_WIDTH => g_dataoUT_WIDTH,
g_unrnd_fract_BITS => G_UNRND_FRACWIDTh,
G_RND_FRACT_BITS => G_DATAOUT_FRACWIDTH)
port map (clock_i => clock_i,
nreset_i => NRESET_I,
data_i => I0L,
data_o => OOI);
DATA_O <= OOI;
o00:
process (nreset_i,CLOCK_I)
begin
if (nreset_i = '0') then
l1l <= ( others => '0');
chan_out_o <= ( others => '0');
elsif (rising_EDGE(CLOCK_I)) then
if (lol(0) = '1') then
l1L <= o1l;
end if;
CHAN_out_o <= L1L;
end if;
end process O00;
L00:
process (nreset_I,CLOck_i)
begin
if (nreset_i = '0') then
DATA_VLD_O <= '0';
elsif (rising_edge(CLOCK_I)) then
dATA_VLD_O <= LOL(0);
end if;
end process l00;
end;
