# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_1} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_1} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PADN} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PADP} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N_1} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P_1} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {clk} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_REF_CLK2} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_REF_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_REFCLKOUT_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_REFCLKOUT_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS1_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {test} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[14:4]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LED_OUT} -port_direction {OUT} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[15:0]} -port_is_pad {1}

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add AND2_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_3}



# Add AND3_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_1}



# Add AND3_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_2}



# Add cdc_data_cpri_ddc_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_data_cpri_ddc_0}
# Exporting Parameters of instance cdc_data_cpri_ddc_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_0} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_0}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rdata_o} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rdata_o} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rdata_o} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_0:rdata_o} -pin_slices {[63:48]}



# Add cdc_data_cpri_ddc_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_data_cpri_ddc_1}
# Exporting Parameters of instance cdc_data_cpri_ddc_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_1} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_1}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_ddc_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rdata_o} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rdata_o} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rdata_o} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_ddc_1:rdata_o} -pin_slices {[63:48]}



# Add cdc_data_cpri_duc_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_data_cpri_duc_0}
# Exporting Parameters of instance cdc_data_cpri_duc_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_0} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_0}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wen_i} -pin_slices {[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wdata_i} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wdata_i} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wdata_i} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:wdata_i} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rdata_vld_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_0:rdata_vld_o} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {cdc_data_cpri_duc_0:rdata_vld_o[1:1]}



# Add cdc_data_cpri_duc_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_data_cpri_duc_1}
# Exporting Parameters of instance cdc_data_cpri_duc_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_1} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_1}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_data_cpri_duc_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wdata_i} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wdata_i} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wdata_i} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:wdata_i} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rdata_vld_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_cpri_duc_1:rdata_vld_o} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {cdc_data_cpri_duc_1:rdata_vld_o[1:1]}



# Add cdc_data_ddc_jesd_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_data_ddc_jesd_0}
# Exporting Parameters of instance cdc_data_ddc_jesd_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_data_ddc_jesd_0} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_data_ddc_jesd_0}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_data_ddc_jesd_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wrstn_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wrstn_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rrstn_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rrstn_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rclk_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rclk_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wclk_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wclk_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wen_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wen_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wen_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wen_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:ren_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:ren_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:ren_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:ren_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wdata_i} -pin_slices {[127:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wdata_i} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wdata_i} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:wdata_i} -pin_slices {[95:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[111:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[127:112]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[79:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_o} -pin_slices {[95:80]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_vld_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_vld_o} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {cdc_data_ddc_jesd_0:rdata_vld_o[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_vld_o} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_data_ddc_jesd_0:rdata_vld_o} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {cdc_data_ddc_jesd_0:rdata_vld_o[3:3]}



# Add cdc_ram_duc_jesd_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {cdc_data_ram} -instance_name {cdc_ram_duc_jesd_0}
# Exporting Parameters of instance cdc_ram_duc_jesd_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {cdc_ram_duc_jesd_0} -params {\
"g_DATAWIDTH:32" \
"g_NUM_AXC:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {cdc_ram_duc_jesd_0}
sd_update_instance -sd_name ${sd_name} -instance_name {cdc_ram_duc_jesd_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wrstn_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wrstn_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rrstn_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rrstn_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rrstn_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rrstn_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rclk_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rclk_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wclk_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wclk_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wclk_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wclk_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wen_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wen_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wen_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wen_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:ren_i} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:ren_i} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:ren_i} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:ren_i} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[111:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[127:112]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[79:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:wdata_i} -pin_slices {[95:80]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_o} -pin_slices {[127:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_o} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_o} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_o} -pin_slices {[95:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_vld_o} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_vld_o} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_vld_o} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {cdc_ram_duc_jesd_0:rdata_vld_o} -pin_slices {[3:3]}



# Add CF_Demux_Mux_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_0}
# Exporting Parameters of instance CF_Demux_Mux_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_0}



# Add CF_Demux_Mux_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_1}
# Exporting Parameters of instance CF_Demux_Mux_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:4" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_1}



# Add CF_Demux_Mux_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_2}
# Exporting Parameters of instance CF_Demux_Mux_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_2:data2_o}



# Add CF_Demux_Mux_3 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_3}
# Exporting Parameters of instance CF_Demux_Mux_3
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_3:data2_o}



# Add CF_Demux_Mux_4 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_4}
# Exporting Parameters of instance CF_Demux_Mux_4
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_4} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_4}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_4}



# Add CF_Demux_Mux_5 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_5}
# Exporting Parameters of instance CF_Demux_Mux_5
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_5} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_5}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_5:data_vld_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_5:chan_out_o}



# Add CF_Demux_Mux_6 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_6}
# Exporting Parameters of instance CF_Demux_Mux_6
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_6:data2_o}



# Add CF_Demux_Mux_7 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_7}
# Exporting Parameters of instance CF_Demux_Mux_7
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_7} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_7}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_7:data2_o}



# Add CF_Demux_Mux_8 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_8}
# Exporting Parameters of instance CF_Demux_Mux_8
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_8} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_8}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_8}



# Add CF_Demux_Mux_9 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {CF_Demux_Mux} -instance_name {CF_Demux_Mux_9}
# Exporting Parameters of instance CF_Demux_Mux_9
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_9} -params {\
"g_CHAN_WIDTH:3" \
"g_DATA_WIDTH:16" \
"g_NUMCHANNELS:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CF_Demux_Mux_9}
sd_update_instance -sd_name ${sd_name} -instance_name {CF_Demux_Mux_9}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_9:data_vld_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CF_Demux_Mux_9:chan_out_o}



# Add CPRI_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CPRI_TOP} -instance_name {CPRI_TOP_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_clk} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_clk} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_clk} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_clk} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_resetn} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_resetn} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_resetn} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_resetn} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_req} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_req} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_req} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_req} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_valid} -pin_slices {[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_valid} -pin_slices {[3:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_data} -pin_slices {[127:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_data} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_data} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_rx_data} -pin_slices {[95:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_valid} -pin_slices {[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_valid} -pin_slices {[3:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_clk} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_clk} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_clk} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_clk} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_resetn} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_resetn} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_resetn} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_resetn} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_data} -pin_slices {[127:96]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_data} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_data} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_data} -pin_slices {[95:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_req} -pin_slices {[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CPRI_TOP_0:axc_tx_req} -pin_slices {[3:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CPRI_TOP_0:LANE0_TX_CLK_STABLE}



# Add ddc_axc_tdm_data_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {ddc_axc_tdm_data} -instance_name {ddc_axc_tdm_data_0}
# Exporting Parameters of instance ddc_axc_tdm_data_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_0} -params {\
"g_AXC_RATE:8" \
"g_DATAWIDTH:32" \
"g_NUM_ANTENNA:4" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_0}
sd_update_instance -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_i} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_i} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_i} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_i} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_chan_i} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_0:data_chan_i} -pin_slices {[3:3]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {ddc_axc_tdm_data_0:data_chan_i[3:3]} -value {GND}



# Add ddc_axc_tdm_data_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {ddc_axc_tdm_data} -instance_name {ddc_axc_tdm_data_1}
# Exporting Parameters of instance ddc_axc_tdm_data_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_1} -params {\
"g_AXC_RATE:8" \
"g_DATAWIDTH:32" \
"g_NUM_ANTENNA:4" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_1}
sd_update_instance -sd_name ${sd_name} -instance_name {ddc_axc_tdm_data_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_i} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_i} -pin_slices {[31:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_i} -pin_slices {[47:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_i} -pin_slices {[63:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_chan_i} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {ddc_axc_tdm_data_1:data_chan_i} -pin_slices {[3:3]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {ddc_axc_tdm_data_1:data_chan_i[3:3]} -value {GND}



# Add DFN1_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_0}



# Add DFN1_9 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_9}



# Add duc_axc_tdm_data_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {duc_axc_tdm_data} -instance_name {duc_axc_tdm_data_0}
# Exporting Parameters of instance duc_axc_tdm_data_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_0} -params {\
"g_AXC_RATE:8" \
"g_DATAWIDTH:32" \
"g_NUM_ANTENNA:4" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_0}
sd_update_instance -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {duc_axc_tdm_data_0:data_o} -pin_slices {[15:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {duc_axc_tdm_data_0:data_chan_0} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {duc_axc_tdm_data_0:data_chan_0} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {duc_axc_tdm_data_0:data_chan_0[3:3]}



# Add duc_axc_tdm_data_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {duc_axc_tdm_data} -instance_name {duc_axc_tdm_data_1}
# Exporting Parameters of instance duc_axc_tdm_data_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_1} -params {\
"g_AXC_RATE:8" \
"g_DATAWIDTH:32" \
"g_NUM_ANTENNA:4" \
"g_NUM_AXC:2" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_1}
sd_update_instance -sd_name ${sd_name} -instance_name {duc_axc_tdm_data_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {duc_axc_tdm_data_1:data_chan_0} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {duc_axc_tdm_data_1:data_chan_0} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {duc_axc_tdm_data_1:data_chan_0[3:3]}



# Add DUCDDC_Top_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DUCDDC_Top} -hdl_file {hdl\DUCDDC_Top.vhd} -instance_name {DUCDDC_Top_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:duc_freqword_en_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:ddc_freqword_en_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:duc_freqvalue_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:duc_freqword_ch_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:ddc_freqvalue_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DUCDDC_Top_0:ddc_freqword_ch_i} -value {GND}



# Add heart_beat_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {heart_beat} -instance_name {heart_beat_0}
# Exporting Parameters of instance heart_beat_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {heart_beat_0} -params {\
"g_BEAT:23" \
"g_TOP:25" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {heart_beat_0}
sd_update_instance -sd_name ${sd_name} -instance_name {heart_beat_0}



# Add INBUF_DIFF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INBUF_DIFF} -instance_name {INBUF_DIFF_0}



# Add INV_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_0}



# Add INV_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_1}



# Add IQ_packer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_packer} -hdl_file {hdl\IQ_packer.v} -instance_name {IQ_packer_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_packer_0:iq_swap} -value {VCC}



# Add IQ_packer_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_packer} -hdl_file {hdl\IQ_packer.v} -instance_name {IQ_packer_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_packer_1:iq_swap} -value {VCC}



# Add IQ_packer_2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_packer} -hdl_file {hdl\IQ_packer.v} -instance_name {IQ_packer_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_packer_2:iq_swap} -value {VCC}



# Add IQ_packer_3 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_packer} -hdl_file {hdl\IQ_packer.v} -instance_name {IQ_packer_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_packer_3:iq_swap} -value {VCC}



# Add IQ_unpacker_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_unpacker} -hdl_file {hdl\IQ_unpacker.v} -instance_name {IQ_unpacker_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_unpacker_0:iq_swap} -value {VCC}



# Add IQ_unpacker_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_unpacker} -hdl_file {hdl\IQ_unpacker.v} -instance_name {IQ_unpacker_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_unpacker_1:iq_swap} -value {VCC}



# Add IQ_unpacker_2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_unpacker} -hdl_file {hdl\IQ_unpacker.v} -instance_name {IQ_unpacker_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_unpacker_2:iq_swap} -value {VCC}



# Add IQ_unpacker_3 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {IQ_unpacker} -hdl_file {hdl\IQ_unpacker.v} -instance_name {IQ_unpacker_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IQ_unpacker_3:iq_swap} -value {VCC}



# Add JESD204B_IF_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {JESD204B_IF} -instance_name {JESD204B_IF_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {JESD204B_IF_0:REF_CLK}



# Add JESD204B_IF_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {JESD204B_IF} -instance_name {JESD204B_IF_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {JESD204B_IF_1:REF_CLK}



# Add LED_STATUS_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {LED_STATUS} -hdl_file {hdl\LED_STATUS.v} -instance_name {LED_STATUS_0}



# Add OUTBUF_DIFF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {OUTBUF_DIFF} -instance_name {OUTBUF_DIFF_0}



# Add PF_CCC_0 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:SgCore:PF_CCC:$PF_CCCver -instance_name {PF_CCC_0}
# Exporting Parameters of instance PF_CCC_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {PF_CCC_0} -params {\
"DLL_CLK_0_BANKCLK_EN:false" \
"DLL_CLK_0_DEDICATED_EN:false" \
"DLL_CLK_0_FABCLK_EN:false" \
"DLL_CLK_1_BANKCLK_EN:false" \
"DLL_CLK_1_DEDICATED_EN:false" \
"DLL_CLK_1_FABCLK_EN:false" \
"DLL_CLK_P_EN:false" \
"DLL_CLK_P_OPTIONS_EN:false" \
"DLL_CLK_REF_OPTION:DIVIDE_BY_1" \
"DLL_CLK_REF_OPTIONS_EN:false" \
"DLL_CLK_S_EN:false" \
"DLL_CLK_S_OPTION:DIVIDE_BY_1" \
"DLL_CLK_S_OPTIONS_EN:false" \
"DLL_DELAY4:0" \
"DLL_DYNAMIC_CODE_EN:false" \
"DLL_DYNAMIC_RECONFIG_INTERFACE_EN:false" \
"DLL_EXPORT_PWRDWN:false" \
"DLL_FB_CLK:Primary" \
"DLL_FB_EN:false" \
"DLL_FINE_PHASE_CODE:0" \
"DLL_IN:1" \
"DLL_JITTER:0" \
"DLL_MODE:PHASE_REF_MODE" \
"DLL_ONLY_EN:false" \
"DLL_OUT_0:1" \
"DLL_OUT_1:1" \
"DLL_PRIM_PHASE:90" \
"DLL_PRIM_PHASE_CODE:0" \
"DLL_SEC_PHASE:90" \
"DLL_SEC_PHASE_CODE:0" \
"DLL_SELECTED_IN:Output2" \
"FAMILY:26" \
"FF_REQUIRES_LOCK_EN_0:0" \
"GL0_0_BANKCLK_USED:false" \
"GL0_0_BYPASS:0" \
"GL0_0_BYPASS_EN:false" \
"GL0_0_DEDICATED_USED:false" \
"GL0_0_DIV:40" \
"GL0_0_DIVSTART:0" \
"GL0_0_DYNAMIC_PH:false" \
"GL0_0_EXPOSE_EN:false" \
"GL0_0_FABCLK_GATED_USED:false" \
"GL0_0_FABCLK_USED:true" \
"GL0_0_FREQ_SEL:false" \
"GL0_0_IS_USED:true" \
"GL0_0_OUT_FREQ:30.72" \
"GL0_0_PHASE_INDEX:0" \
"GL0_0_PHASE_SEL:false" \
"GL0_0_PLL_PHASE:0" \
"GL0_1_BANKCLK_USED:false" \
"GL0_1_BYPASS:0" \
"GL0_1_BYPASS_EN:false" \
"GL0_1_DEDICATED_USED:false" \
"GL0_1_DIV:1" \
"GL0_1_DIVSTART:0" \
"GL0_1_DYNAMIC_PH:false" \
"GL0_1_EXPOSE_EN:false" \
"GL0_1_FABCLK_USED:false" \
"GL0_1_FREQ_SEL:false" \
"GL0_1_IS_USED:true" \
"GL0_1_OUT_FREQ:100" \
"GL0_1_PHASE_INDEX:0" \
"GL0_1_PHASE_SEL:false" \
"GL0_1_PLL_PHASE:0" \
"GL1_0_BANKCLK_USED:false" \
"GL1_0_BYPASS:0" \
"GL1_0_BYPASS_EN:false" \
"GL1_0_DEDICATED_USED:false" \
"GL1_0_DIV:5" \
"GL1_0_DIVSTART:0" \
"GL1_0_DYNAMIC_PH:false" \
"GL1_0_EXPOSE_EN:false" \
"GL1_0_FABCLK_GATED_USED:false" \
"GL1_0_FABCLK_USED:true" \
"GL1_0_FREQ_SEL:false" \
"GL1_0_IS_USED:true" \
"GL1_0_OUT_FREQ:245.76" \
"GL1_0_PHASE_INDEX:0" \
"GL1_0_PHASE_SEL:false" \
"GL1_0_PLL_PHASE:0" \
"GL1_1_BANKCLK_USED:false" \
"GL1_1_BYPASS:0" \
"GL1_1_BYPASS_EN:false" \
"GL1_1_DEDICATED_USED:false" \
"GL1_1_DIV:1" \
"GL1_1_DIVSTART:0" \
"GL1_1_DYNAMIC_PH:false" \
"GL1_1_EXPOSE_EN:false" \
"GL1_1_FABCLK_USED:false" \
"GL1_1_FREQ_SEL:false" \
"GL1_1_IS_USED:false" \
"GL1_1_OUT_FREQ:0" \
"GL1_1_PHASE_INDEX:0" \
"GL1_1_PHASE_SEL:false" \
"GL1_1_PLL_PHASE:0" \
"GL2_0_BANKCLK_USED:false" \
"GL2_0_BYPASS:0" \
"GL2_0_BYPASS_EN:false" \
"GL2_0_DEDICATED_USED:false" \
"GL2_0_DIV:1" \
"GL2_0_DIVSTART:0" \
"GL2_0_DYNAMIC_PH:false" \
"GL2_0_EXPOSE_EN:false" \
"GL2_0_FABCLK_GATED_USED:false" \
"GL2_0_FABCLK_USED:true" \
"GL2_0_FREQ_SEL:false" \
"GL2_0_IS_USED:false" \
"GL2_0_OUT_FREQ:100" \
"GL2_0_PHASE_INDEX:0" \
"GL2_0_PHASE_SEL:false" \
"GL2_0_PLL_PHASE:0" \
"GL2_1_BANKCLK_USED:false" \
"GL2_1_BYPASS:0" \
"GL2_1_BYPASS_EN:false" \
"GL2_1_DEDICATED_USED:false" \
"GL2_1_DIV:1" \
"GL2_1_DIVSTART:0" \
"GL2_1_DYNAMIC_PH:false" \
"GL2_1_EXPOSE_EN:false" \
"GL2_1_FABCLK_USED:false" \
"GL2_1_FREQ_SEL:false" \
"GL2_1_IS_USED:false" \
"GL2_1_OUT_FREQ:0" \
"GL2_1_PHASE_INDEX:0" \
"GL2_1_PHASE_SEL:false" \
"GL2_1_PLL_PHASE:0" \
"GL3_0_BANKCLK_USED:false" \
"GL3_0_BYPASS:0" \
"GL3_0_BYPASS_EN:false" \
"GL3_0_DEDICATED_USED:false" \
"GL3_0_DIV:1" \
"GL3_0_DIVSTART:0" \
"GL3_0_DYNAMIC_PH:false" \
"GL3_0_EXPOSE_EN:false" \
"GL3_0_FABCLK_GATED_USED:false" \
"GL3_0_FABCLK_USED:true" \
"GL3_0_FREQ_SEL:false" \
"GL3_0_IS_USED:false" \
"GL3_0_OUT_FREQ:100" \
"GL3_0_PHASE_INDEX:0" \
"GL3_0_PHASE_SEL:false" \
"GL3_0_PLL_PHASE:0" \
"GL3_1_BANKCLK_USED:false" \
"GL3_1_BYPASS:0" \
"GL3_1_BYPASS_EN:false" \
"GL3_1_DEDICATED_USED:false" \
"GL3_1_DIV:1" \
"GL3_1_DIVSTART:0" \
"GL3_1_DYNAMIC_PH:false" \
"GL3_1_EXPOSE_EN:false" \
"GL3_1_FABCLK_USED:false" \
"GL3_1_FREQ_SEL:false" \
"GL3_1_IS_USED:false" \
"GL3_1_OUT_FREQ:0" \
"GL3_1_PHASE_INDEX:0" \
"GL3_1_PHASE_SEL:false" \
"GL3_1_PLL_PHASE:0" \
"PARAM_IS_FALSE:false" \
"PLL_ALLOW_CCC_EXT_FB:false" \
"PLL_BANDWIDTH_0:0" \
"PLL_BANDWIDTH_1:1" \
"PLL_BYPASS_GO_B_0:false" \
"PLL_BYPASS_GO_B_1:false" \
"PLL_BYPASS_POST_0:0" \
"PLL_BYPASS_POST_0_0:false" \
"PLL_BYPASS_POST_0_1:false" \
"PLL_BYPASS_POST_0_2:false" \
"PLL_BYPASS_POST_0_3:false" \
"PLL_BYPASS_POST_1:0" \
"PLL_BYPASS_POST_1_0:false" \
"PLL_BYPASS_POST_1_1:false" \
"PLL_BYPASS_POST_1_2:false" \
"PLL_BYPASS_POST_1_3:false" \
"PLL_BYPASS_PRE_0:0" \
"PLL_BYPASS_PRE_0_0:false" \
"PLL_BYPASS_PRE_0_1:false" \
"PLL_BYPASS_PRE_0_2:false" \
"PLL_BYPASS_PRE_0_3:false" \
"PLL_BYPASS_PRE_1:0" \
"PLL_BYPASS_PRE_1_0:false" \
"PLL_BYPASS_PRE_1_1:false" \
"PLL_BYPASS_PRE_1_2:false" \
"PLL_BYPASS_PRE_1_3:false" \
"PLL_BYPASS_SEL_0:0" \
"PLL_BYPASS_SEL_0_0:false" \
"PLL_BYPASS_SEL_0_1:false" \
"PLL_BYPASS_SEL_0_2:false" \
"PLL_BYPASS_SEL_0_3:false" \
"PLL_BYPASS_SEL_1:0" \
"PLL_BYPASS_SEL_1_0:false" \
"PLL_BYPASS_SEL_1_1:false" \
"PLL_BYPASS_SEL_1_2:false" \
"PLL_BYPASS_SEL_1_3:false" \
"PLL_DELAY_LINE_REF_FB_0:false" \
"PLL_DELAY_LINE_REF_FB_1:false" \
"PLL_DELAY_LINE_USED_0:false" \
"PLL_DELAY_LINE_USED_1:false" \
"PLL_DELAY_STEPS_0:1" \
"PLL_DELAY_STEPS_1:1" \
"PLL_DLL_CASCADED_EN:false" \
"PLL_DYNAMIC_CONTROL_EN_0:true" \
"PLL_DYNAMIC_CONTROL_EN_1:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_0:false" \
"PLL_DYNAMIC_RECONFIG_INTERFACE_EN_1:false" \
"PLL_EXPORT_PWRDWN:false" \
"PLL_EXT_MAX_ADDR_0:128" \
"PLL_EXT_MAX_ADDR_1:128" \
"PLL_EXT_WAVE_SEL_0:0" \
"PLL_EXT_WAVE_SEL_1:0" \
"PLL_FB_CLK_0:GL0_0" \
"PLL_FB_CLK_1:GL0_1" \
"PLL_FEEDBACK_MODE_0:Post-VCO" \
"PLL_FEEDBACK_MODE_1:Post-VCO" \
"PLL_IN_FREQ_0:122.88" \
"PLL_IN_FREQ_1:100" \
"PLL_INT_MODE_EN_0:false" \
"PLL_INT_MODE_EN_1:false" \
"PLL_LOCK_COUNT_0:0" \
"PLL_LOCK_COUNT_1:0" \
"PLL_LP_REQUIRES_LOCK_EN_0:false" \
"PLL_LP_REQUIRES_LOCK_EN_1:false" \
"PLL_PLL_CASCADED_EN:false" \
"PLL_PLL_CASCADED_SELECTED_CLK:Output2" \
"PLL_POSTDIVIDERADDSOFTLOGIC_0:true" \
"PLL_REF_CLK_SEL_0:false" \
"PLL_REF_CLK_SEL_1:false" \
"PLL_REFDIV_0:1" \
"PLL_REFDIV_1:1" \
"PLL_RESET_ON_LOCK_0:true" \
"PLL_SPREAD_MODE_0:false" \
"PLL_SPREAD_MODE_1:false" \
"PLL_SSM_DEPTH_0:5" \
"PLL_SSM_DEPTH_1:5" \
"PLL_SSM_DIVVAL_0:1" \
"PLL_SSM_DIVVAL_1:1" \
"PLL_SSM_FREQ_0:32" \
"PLL_SSM_FREQ_1:32" \
"PLL_SSM_RAND_PATTERN_0:2" \
"PLL_SSM_RAND_PATTERN_1:2" \
"PLL_SSMD_EN_0:false" \
"PLL_SSMD_EN_1:false" \
"PLL_SYNC_CORNER_PLL:false" \
"PLL_SYNC_EN:false" \
"PLL_VCO_MODE_0:MIN_JITTER" \
"PLL_VCO_MODE_1:MIN_JITTER" \
"SD_EXPORT_HIDDEN_PORTS:false" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {PF_CCC_0}



# Add PF_XCVR_REF_CLK_0 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:$PF_XCVR_REF_CLKver -instance_name {PF_XCVR_REF_CLK_0}
# Exporting Parameters of instance PF_XCVR_REF_CLK_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
"ENABLE_REF_CLK_1:false" \
"FAMILY:26" \
"PARAM_IS_FALSE:false" \
"REF_CLK_MODE_0:DIFFERENTIAL" \
"REF_CLK_MODE_1:LVCMOS" \
"SD_EXPORT_HIDDEN_PORTS:false" \
"TGIGEN_DISPLAY_LOG_WINDOW:false" \
"TGIGEN_DISPLAY_SYMBOL:true" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {PF_XCVR_REF_CLK_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_REF_CLK_0:FAB_REF_CLK}



# Add RISCV_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RISCV_TOP} -instance_name {RISCV_TOP_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RISCV_TOP_0:GPIO_OUT} -pin_slices {[14:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RISCV_TOP_0:GPIO_OUT} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RISCV_TOP_0:GPIO_OUT[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RISCV_TOP_0:GPIO_OUT} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {RISCV_TOP_0:GPIO_OUT} -pin_slices {[3:3]}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_N" "JESD204B_IF_0:ADC_SYNC_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_N_0" "JESD204B_IF_1:ADC_SYNC_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_P" "JESD204B_IF_0:ADC_SYNC_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_P_0" "JESD204B_IF_1:ADC_SYNC_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CPRI_TOP_0:cpri_ready" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "AND2_1:B" "AND2_3:B" "AND3_1:B" "AND3_2:B" "PF_CCC_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CF_Demux_Mux_0:nreset_i" "CF_Demux_Mux_1:nreset_i" "CF_Demux_Mux_2:nreset_i" "CF_Demux_Mux_3:nreset_i" "CF_Demux_Mux_4:nreset_i" "CF_Demux_Mux_5:nreset_i" "CF_Demux_Mux_6:nreset_i" "CF_Demux_Mux_7:nreset_i" "CF_Demux_Mux_8:nreset_i" "CF_Demux_Mux_9:nreset_i" "DUCDDC_Top_0:nreset_i" "cdc_data_cpri_ddc_0:wrstn_i[0:0]" "cdc_data_cpri_ddc_0:wrstn_i[1:1]" "cdc_data_cpri_ddc_1:wrstn_i[0:0]" "cdc_data_cpri_ddc_1:wrstn_i[1:1]" "cdc_data_cpri_duc_0:rrstn_i[0:0]" "cdc_data_cpri_duc_0:rrstn_i[1:1]" "cdc_data_cpri_duc_1:rrstn_i[0:0]" "cdc_data_cpri_duc_1:rrstn_i[1:1]" "ddc_axc_tdm_data_0:nreset_i" "ddc_axc_tdm_data_1:nreset_i" "duc_axc_tdm_data_0:nreset_i" "duc_axc_tdm_data_1:nreset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "JESD204B_IF_0:rx_ready_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "cdc_data_ddc_jesd_0:rrstn_i[0:0]" "cdc_data_ddc_jesd_0:rrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:A" "JESD204B_IF_1:rx_ready_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_3:Y" "cdc_data_ddc_jesd_0:rrstn_i[2:2]" "cdc_data_ddc_jesd_0:rrstn_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_1:A" "RISCV_TOP_0:GPIO_OUT[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_1:C" "AND3_2:C" "CPRI_TOP_0:CPRI_RESETN" "RISCV_TOP_0:PRESETN" "heart_beat_0:nreset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_1:Y" "JESD204B_IF_0:CTRL_ARST_N" "JESD204B_IF_0:HRESETN" "cdc_ram_duc_jesd_0:wrstn_i[0:0]" "cdc_ram_duc_jesd_0:wrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_2:A" "RISCV_TOP_0:GPIO_OUT[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_2:Y" "JESD204B_IF_1:CTRL_ARST_N" "JESD204B_IF_1:HRESETN" "cdc_ram_duc_jesd_0:wrstn_i[2:2]" "cdc_ram_duc_jesd_0:wrstn_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "RISCV_TOP_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:clock_i" "CF_Demux_Mux_1:clock_i" "CF_Demux_Mux_2:clock_i" "CF_Demux_Mux_3:clock_i" "CF_Demux_Mux_4:clock_i" "CF_Demux_Mux_5:clock_i" "CF_Demux_Mux_6:clock_i" "CF_Demux_Mux_7:clock_i" "CF_Demux_Mux_8:clock_i" "CF_Demux_Mux_9:clock_i" "DFN1_9:CLK" "DUCDDC_Top_0:clock_i" "PF_CCC_0:OUT1_FABCLK_0" "cdc_data_cpri_ddc_0:wclk_i[0:0]" "cdc_data_cpri_ddc_0:wclk_i[1:1]" "cdc_data_cpri_ddc_1:wclk_i[0:0]" "cdc_data_cpri_ddc_1:wclk_i[1:1]" "cdc_data_cpri_duc_0:rclk_i[0:0]" "cdc_data_cpri_duc_0:rclk_i[1:1]" "cdc_data_cpri_duc_1:rclk_i[0:0]" "cdc_data_cpri_duc_1:rclk_i[1:1]" "cdc_data_ddc_jesd_0:rclk_i[0:0]" "cdc_data_ddc_jesd_0:rclk_i[1:1]" "cdc_data_ddc_jesd_0:rclk_i[2:2]" "cdc_data_ddc_jesd_0:rclk_i[3:3]" "cdc_ram_duc_jesd_0:wclk_i[0:0]" "cdc_ram_duc_jesd_0:wclk_i[1:1]" "cdc_ram_duc_jesd_0:wclk_i[2:2]" "cdc_ram_duc_jesd_0:wclk_i[3:3]" "ddc_axc_tdm_data_0:clock_i" "ddc_axc_tdm_data_1:clock_i" "duc_axc_tdm_data_0:clock_i" "duc_axc_tdm_data_1:clock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_vld_i" "DUCDDC_Top_0:ddc_data_vld_o_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_vld_o" "CF_Demux_Mux_2:data_vld_i" "CF_Demux_Mux_3:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data_vld_i" "DUCDDC_Top_0:ddc_data_vld_o_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data_vld_o" "CF_Demux_Mux_6:data_vld_i" "CF_Demux_Mux_7:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data_vld_o" "CF_Demux_Mux_4:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data_vld_o" "CF_Demux_Mux_5:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_4:data_vld_o" "ddc_axc_tdm_data_0:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data_vld_o" "CF_Demux_Mux_8:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_7:data_vld_o" "CF_Demux_Mux_9:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_8:data_vld_o" "ddc_axc_tdm_data_1:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "RISCV_TOP_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "RISCV_TOP_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "RISCV_TOP_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:CTRL_ARST_N" "CPRI_TOP_0:HRESETN" "HRESETN" "RISCV_TOP_0:HRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:CTRL_CLK" "JESD204B_IF_1:CTRL_CLK" "JESD204B_IF_1:CTRL_CLK_0" "RISCV_TOP_0:clk" "clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:CTRL_CLK_0" "CPRI_TOP_0:HCLK" "JESD204B_IF_0:CTRL_CLK" "JESD204B_IF_0:CTRL_CLK_0" "RISCV_TOP_0:HCLK" "heart_beat_0:clock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_RXD_N_0" "LANE0_RXD_N_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_RXD_P_0" "LANE0_RXD_P_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_RX_CLK_G" "PF_CCC_0:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_RX_CLK_R" "CPRI_TOP_0:axc_rx_clk[0:0]" "CPRI_TOP_0:axc_rx_clk[1:1]" "CPRI_TOP_0:axc_rx_clk[2:2]" "CPRI_TOP_0:axc_rx_clk[3:3]" "cdc_data_cpri_duc_0:wclk_i[0:0]" "cdc_data_cpri_duc_0:wclk_i[1:1]" "cdc_data_cpri_duc_1:wclk_i[0:0]" "cdc_data_cpri_duc_1:wclk_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_RX_VAL" "LED_STATUS_0:CPRI_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_TXD_N_0" "LANE0_TXD_N_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_TXD_P_0" "LANE0_TXD_P_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:LANE0_TX_CLK_R" "CPRI_TOP_0:axc_tx_clk[0:0]" "CPRI_TOP_0:axc_tx_clk[1:1]" "CPRI_TOP_0:axc_tx_clk[2:2]" "CPRI_TOP_0:axc_tx_clk[3:3]" "cdc_data_cpri_ddc_0:rclk_i[0:0]" "cdc_data_cpri_ddc_0:rclk_i[1:1]" "cdc_data_cpri_ddc_1:rclk_i[0:0]" "cdc_data_cpri_ddc_1:rclk_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:REF_CLK" "PF_XCVR_REF_CLK_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_req[0:0]" "CPRI_TOP_0:axc_rx_req[1:1]" "CPRI_TOP_0:axc_rx_req[2:2]" "CPRI_TOP_0:axc_rx_req[3:3]" "CPRI_TOP_0:axc_rx_resetn[0:0]" "CPRI_TOP_0:axc_rx_resetn[1:1]" "CPRI_TOP_0:axc_rx_resetn[2:2]" "CPRI_TOP_0:axc_rx_resetn[3:3]" "CPRI_TOP_0:axc_rxdata_resetn" "cdc_data_cpri_duc_0:wrstn_i[0:0]" "cdc_data_cpri_duc_0:wrstn_i[1:1]" "cdc_data_cpri_duc_1:wrstn_i[0:0]" "cdc_data_cpri_duc_1:wrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_resetn[0:0]" "CPRI_TOP_0:axc_tx_resetn[1:1]" "CPRI_TOP_0:axc_tx_resetn[2:2]" "CPRI_TOP_0:axc_tx_resetn[3:3]" "CPRI_TOP_0:axc_txdata_resetn" "cdc_data_cpri_ddc_0:rrstn_i[0:0]" "cdc_data_cpri_ddc_0:rrstn_i[1:1]" "cdc_data_cpri_ddc_1:rrstn_i[0:0]" "cdc_data_cpri_ddc_1:rrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "RISCV_TOP_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_N" "JESD204B_IF_0:DAC_SYNC_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_N_0" "JESD204B_IF_1:DAC_SYNC_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_P" "JESD204B_IF_0:DAC_SYNC_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_P_0" "JESD204B_IF_1:DAC_SYNC_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:CLK" "OUTBUF_DIFF_0:D" "PF_CCC_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:D" "INV_0:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:Q" "INV_0:A" "test" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_9:D" "INV_1:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_9:Q" "INV_1:A" "cdc_data_ddc_jesd_0:ren_i[0:0]" "cdc_data_ddc_jesd_0:ren_i[1:1]" "cdc_data_ddc_jesd_0:ren_i[2:2]" "cdc_data_ddc_jesd_0:ren_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_data_vld_i_0" "cdc_data_ddc_jesd_0:rdata_vld_o[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_data_vld_i_1" "cdc_data_ddc_jesd_0:rdata_vld_o[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_vld_i_0" "duc_axc_tdm_data_0:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_vld_i_1" "duc_axc_tdm_data_1:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_vld_o_0" "cdc_ram_duc_jesd_0:wen_i[0:0]" "cdc_ram_duc_jesd_0:wen_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_vld_o_1" "cdc_ram_duc_jesd_0:wen_i[2:2]" "cdc_ram_duc_jesd_0:wen_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FAB_REF_CLK" "JESD204B_IF_0:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FAB_REF_CLK2" "JESD204B_IF_1:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FPGA_REFCLKOUT_N" "OUTBUF_DIFF_0:PADN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FPGA_REFCLKOUT_P" "OUTBUF_DIFF_0:PADP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:PADN" "PADN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:PADP" "PADP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:Y" "JESD204B_IF_0:SYSREF_IN" "JESD204B_IF_1:SYSREF_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:ALIGNED" "LED_STATUS_0:ALIGNED_JESD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_RXD_N_0" "LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_RXD_P_0" "LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_RX_CLK_R" "cdc_data_ddc_jesd_0:wclk_i[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_RX_VAL" "LED_STATUS_0:RX_VAL_JESD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_TXD_N_0" "LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_TXD_P_0" "LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE0_TX_CLK_R" "cdc_ram_duc_jesd_0:rclk_i[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_RXD_N_0" "LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_RXD_P_0" "LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_RX_CLK_R" "cdc_data_ddc_jesd_0:wclk_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_TXD_N_0" "LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_TXD_P_0" "LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:LANE1_TX_CLK_R" "cdc_ram_duc_jesd_0:rclk_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:REF_CLK_PAD_N" "REF_CLK_PAD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:REF_CLK_PAD_P" "REF_CLK_PAD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:SYNC_N" "LED_STATUS_0:SYNC_N_JESD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:rx_resetn" "cdc_data_ddc_jesd_0:wen_i[0:0]" "cdc_data_ddc_jesd_0:wen_i[1:1]" "cdc_data_ddc_jesd_0:wrstn_i[0:0]" "cdc_data_ddc_jesd_0:wrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:tx_resetn" "cdc_ram_duc_jesd_0:ren_i[0:0]" "cdc_ram_duc_jesd_0:ren_i[1:1]" "cdc_ram_duc_jesd_0:rrstn_i[0:0]" "cdc_ram_duc_jesd_0:rrstn_i[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:ALIGNED" "LED_STATUS_0:ALIGNED_JESD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_RXD_N_0" "LANE0_RXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_RXD_P_0" "LANE0_RXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_RX_CLK_R" "cdc_data_ddc_jesd_0:wclk_i[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_TXD_N_0" "LANE0_TXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_TXD_P_0" "LANE0_TXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE0_TX_CLK_R" "cdc_ram_duc_jesd_0:rclk_i[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_RXD_N_0" "LANE1_RXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_RXD_P_0" "LANE1_RXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_RX_CLK_R" "cdc_data_ddc_jesd_0:wclk_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_TXD_N_0" "LANE1_TXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_TXD_P_0" "LANE1_TXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:LANE1_TX_CLK_R" "cdc_ram_duc_jesd_0:rclk_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:REF_CLK_PAD_N" "REF_CLK_PAD_N_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:REF_CLK_PAD_P" "REF_CLK_PAD_P_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:SYNC_N" "LED_STATUS_0:SYNC_N_JESD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:rx_resetn" "cdc_data_ddc_jesd_0:wen_i[2:2]" "cdc_data_ddc_jesd_0:wen_i[3:3]" "cdc_data_ddc_jesd_0:wrstn_i[2:2]" "cdc_data_ddc_jesd_0:wrstn_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:tx_resetn" "cdc_ram_duc_jesd_0:ren_i[2:2]" "cdc_ram_duc_jesd_0:ren_i[3:3]" "cdc_ram_duc_jesd_0:rrstn_i[2:2]" "cdc_ram_duc_jesd_0:rrstn_i[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LED_STATUS_0:HB" "heart_beat_0:HB_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LED_STATUS_0:RX_VAL_JESD1" "RISCV_TOP_0:CTRLR_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "RISCV_TOP_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RAS_N" "RISCV_TOP_0:RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RESET_N" "RISCV_TOP_0:RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:RX" "RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISCLKO0" "SPISCLKO0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISCLKO1" "SPISCLKO1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISDI0" "SPISDI0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISDI1" "SPISDI1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISDO0" "SPISDO0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISDO1" "SPISDO1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISS0_0" "SPISS0_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISS0_1" "SPISS0_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:SPISS1_0" "SPISS1_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:TX" "TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RISCV_TOP_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_0:rdata_vld_o[0:0]" "duc_axc_tdm_data_0:data_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_1:rdata_vld_o[0:0]" "duc_axc_tdm_data_1:data_vld_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "RISCV_TOP_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "RISCV_TOP_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:chan_in_i" "DUCDDC_Top_0:ddc_chan_o_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:chan_out_o" "CF_Demux_Mux_2:chan_in_i" "CF_Demux_Mux_3:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data1_o" "CF_Demux_Mux_2:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data2_o" "CF_Demux_Mux_3:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_0:data_i" "DUCDDC_Top_0:ddc_data_o_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:chan_in_i" "DUCDDC_Top_0:ddc_chan_o_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:chan_out_o" "CF_Demux_Mux_6:chan_in_i" "CF_Demux_Mux_7:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data1_o" "CF_Demux_Mux_6:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data2_o" "CF_Demux_Mux_7:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_1:data_i" "DUCDDC_Top_0:ddc_data_o_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:chan_out_o" "CF_Demux_Mux_4:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_2:data1_o" "CF_Demux_Mux_4:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:chan_out_o" "CF_Demux_Mux_5:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_3:data1_o" "CF_Demux_Mux_5:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_4:chan_out_o" "ddc_axc_tdm_data_0:data_chan_i[2:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_4:data1_o" "ddc_axc_tdm_data_0:data_i[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_4:data2_o" "ddc_axc_tdm_data_0:data_i[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_5:data1_o" "ddc_axc_tdm_data_0:data_i[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_5:data2_o" "ddc_axc_tdm_data_0:data_i[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:chan_out_o" "CF_Demux_Mux_8:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_6:data1_o" "CF_Demux_Mux_8:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_7:chan_out_o" "CF_Demux_Mux_9:chan_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_7:data1_o" "CF_Demux_Mux_9:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_8:chan_out_o" "ddc_axc_tdm_data_1:data_chan_i[2:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_8:data1_o" "ddc_axc_tdm_data_1:data_i[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_8:data2_o" "ddc_axc_tdm_data_1:data_i[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_9:data1_o" "ddc_axc_tdm_data_1:data_i[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CF_Demux_Mux_9:data2_o" "ddc_axc_tdm_data_1:data_i[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_data[127:96]" "IQ_unpacker_3:iq_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_data[31:0]" "IQ_unpacker_0:iq_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_data[63:32]" "IQ_unpacker_1:iq_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_data[95:64]" "IQ_unpacker_2:iq_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_valid[1:0]" "cdc_data_cpri_duc_0:wen_i[1:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_rx_valid[3:2]" "cdc_data_cpri_duc_1:wen_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_data[127:96]" "IQ_packer_1:iq_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_data[31:0]" "IQ_packer_2:iq_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_data[63:32]" "IQ_packer_3:iq_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_data[95:64]" "IQ_packer_0:iq_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_req[1:0]" "cdc_data_cpri_ddc_1:ren_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_req[3:2]" "cdc_data_cpri_ddc_0:ren_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_valid[1:0]" "cdc_data_cpri_ddc_1:rdata_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:axc_tx_valid[3:2]" "cdc_data_cpri_ddc_0:rdata_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM" "RISCV_TOP_0:DM" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "RISCV_TOP_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "RISCV_TOP_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "RISCV_TOP_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_I0_data_i_0" "cdc_data_ddc_jesd_0:rdata_o[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_I0_data_i_1" "cdc_data_ddc_jesd_0:rdata_o[79:64]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_I1_data_i_0" "cdc_data_ddc_jesd_0:rdata_o[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_I1_data_i_1" "cdc_data_ddc_jesd_0:rdata_o[111:96]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_Q0_data_i_0" "cdc_data_ddc_jesd_0:rdata_o[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_Q0_data_i_1" "cdc_data_ddc_jesd_0:rdata_o[95:80]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_Q1_data_i_0" "cdc_data_ddc_jesd_0:rdata_o[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:ddc_Q1_data_i_1" "cdc_data_ddc_jesd_0:rdata_o[127:112]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_I0_data_o_0" "cdc_ram_duc_jesd_0:wdata_i[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_I0_data_o_1" "cdc_ram_duc_jesd_0:wdata_i[79:64]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_I1_data_o_0" "cdc_ram_duc_jesd_0:wdata_i[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_I1_data_o_1" "cdc_ram_duc_jesd_0:wdata_i[111:96]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_Q0_data_o_0" "cdc_ram_duc_jesd_0:wdata_i[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_Q0_data_o_1" "cdc_ram_duc_jesd_0:wdata_i[95:80]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_Q1_data_o_0" "cdc_ram_duc_jesd_0:wdata_i[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_Q1_data_o_1" "cdc_ram_duc_jesd_0:wdata_i[127:112]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_chan_i_0" "duc_axc_tdm_data_0:data_chan_0[2:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_chan_i_1" "duc_axc_tdm_data_1:data_chan_0[2:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_i_0" "duc_axc_tdm_data_0:data_o[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DUCDDC_Top_0:duc_data_i_1" "duc_axc_tdm_data_1:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "RISCV_TOP_0:GPIO_OUT[14:4]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_0:I_data_i" "cdc_data_cpri_ddc_0:rdata_o[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_0:Q_data_i" "cdc_data_cpri_ddc_0:rdata_o[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_1:I_data_i" "cdc_data_cpri_ddc_0:rdata_o[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_1:Q_data_i" "cdc_data_cpri_ddc_0:rdata_o[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_2:I_data_i" "cdc_data_cpri_ddc_1:rdata_o[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_2:Q_data_i" "cdc_data_cpri_ddc_1:rdata_o[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_3:I_data_i" "cdc_data_cpri_ddc_1:rdata_o[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_packer_3:Q_data_i" "cdc_data_cpri_ddc_1:rdata_o[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_0:I_data_o" "cdc_data_cpri_duc_0:wdata_i[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_0:Q_data_o" "cdc_data_cpri_duc_0:wdata_i[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_1:I_data_o" "cdc_data_cpri_duc_0:wdata_i[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_1:Q_data_o" "cdc_data_cpri_duc_0:wdata_i[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_2:I_data_o" "cdc_data_cpri_duc_1:wdata_i[15:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_2:Q_data_o" "cdc_data_cpri_duc_1:wdata_i[31:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_3:I_data_o" "cdc_data_cpri_duc_1:wdata_i[47:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IQ_unpacker_3:Q_data_o" "cdc_data_cpri_duc_1:wdata_i[63:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:DATA_IN1" "cdc_ram_duc_jesd_0:rdata_o[31:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:DATA_IN2" "cdc_ram_duc_jesd_0:rdata_o[63:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:DATA_OUT_0" "cdc_data_ddc_jesd_0:wdata_i[31:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_0:DATA_OUT_1" "cdc_data_ddc_jesd_0:wdata_i[63:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:DATA_IN1" "cdc_ram_duc_jesd_0:rdata_o[95:64]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:DATA_IN2" "cdc_ram_duc_jesd_0:rdata_o[127:96]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:DATA_OUT_0" "cdc_data_ddc_jesd_0:wdata_i[95:64]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"JESD204B_IF_1:DATA_OUT_1" "cdc_data_ddc_jesd_0:wdata_i[127:96]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LED_OUT" "LED_STATUS_0:LED_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_ddc_0:wdata_i" "ddc_axc_tdm_data_0:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_ddc_0:wen_i" "ddc_axc_tdm_data_0:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_ddc_1:wdata_i" "ddc_axc_tdm_data_1:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_ddc_1:wen_i" "ddc_axc_tdm_data_1:data_vld_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_0:rdata_o" "duc_axc_tdm_data_0:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_0:ren_i" "duc_axc_tdm_data_0:rd_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_1:rdata_o" "duc_axc_tdm_data_1:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"cdc_data_cpri_duc_1:ren_i" "duc_axc_tdm_data_1:rd_req_o" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_TOP_0:AHB_SLV" "RISCV_TOP_0:AHBmslave7" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Radio4x4_20BW"
generate_component -component_name ${sd_name}
