--/******************************************************************************
--    Company      		: MICROSEMI

--    File Name    		: DDC_Top.vhd 
                   		
--    Description  		: This module instantiates the DDC modules for defined antennas

--    Targeted device 	: Family           Die          Package
--                   	  PolarFire     MPF300T_ES      MPF300T_ES

--    Author          	: India Solutions Team

--
-- SVN Revision Information:
-- SVN $Revision: 
-- SVN $Date:  $  
-- COPYRIGHT 2018 BY MICROSEMI 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM MICROSEMI CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
-- 

--******************************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.System_pack.all;
use work.dds_pack.all;

entity DDC_Top is       
  port( 
		  clock_i        			              : in     std_logic;                           -- Clock signal
		  nreset_i       			              : in     std_logic;                           -- Asynchronous reset signal
    -- DDC Inputs                                                                   
    ddc_I0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Inphase data signals    
    ddc_Q0_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant0 Quadrature data signals     
    ddc_I1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Inphase data signals
    ddc_Q1_data_i_0                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant1 Quadrature data signals      
    ddc_data_vld_i_0                : in  std_logic;                              -- Input ddc data valid signals  
    ddc_I0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Inphase data signals      
    ddc_Q0_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant2 Quadrature data signals        
    ddc_I1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Inphase data signals
    ddc_Q1_data_i_1                 : in  std_logic_vector (15   downto 0);       -- Input ddc Ant3 Quadrature data signals     
    ddc_data_vld_i_1                : in  std_logic;                              -- Input ddc data valid signals 
    ddc_freqvalue_i                 : in  std_logic_vector(31 downto 0);          -- Input dds frequency value signal
    ddc_freqword_ch_i               : in  std_logic_vector(1 downto 0);           -- Input dds frequency channel signal
    ddc_freqword_en_i               : in  std_logic;                              -- Input dds frequency enable signal
    -- DDC Outputs
    ddc_data_vld_o_0                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_0                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_0				                : out  std_logic_vector (15   downto 0);      -- Output ddc data  signals
    ddc_data_vld_o_1                : out  std_logic;                             -- Output ddc data valid signals
    ddc_chan_o_1                    : out  std_logic_vector (2   downto 0);       -- Output ddc channel count signals
			 ddc_data_o_1				                : out  std_logic_vector (15   downto 0)       -- Output ddc data  signals    
  );
end DDC_Top;
architecture architecture_DDC_Top of DDC_Top is
-----------------------------------------------------------------------------------------------------------------------
-- component declarations 
-----------------------------------------------------------------------------------------------------------------------
-- DDC_Antenna
component DDC_Antenna
  -- Port list
  port(
    -- Inputs
    I0_data_i                       : in  std_logic_vector(15 downto 0);
    I1_data_i                       : in  std_logic_vector(15 downto 0);
    Q0_data_i                       : in  std_logic_vector(15 downto 0);
    Q1_data_i                       : in  std_logic_vector(15 downto 0);       
    clock_i                         : in  std_logic;
    data_vld_i                      : in  std_logic;        
    cos_i                           : in std_logic_vector (g_DATAWIDTH-1 downto 0);
    sin_i                           : in std_logic_vector (g_DATAWIDTH-1 downto 0);
    chan_i                          : in std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
    nreset_i                        : in  std_logic;
    -- Outputs                      
    chan_out_o                      : out std_logic_vector(2 downto 0);
    data_o                          : out std_logic_vector(15 downto 0);
    data_vld_o                      : out std_logic
  );
end component;

component dds_top
  port (
    clock_i                         : in STD_LOGIC;
    nreset_i                        : in STD_LOGIC;
    -- Phase word inputs            
    freqvalue_i                     : in std_logic_vector (g_PHASE_WIDTH-1 downto 0);
    freqword_en_i                   : in std_logic;
    freqword_ch_i                   : in std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
    -- Output sin cos               
    cos_o                           : out std_logic_vector (g_DATAWIDTH-1 downto 0);
    sin_o                           : out std_logic_vector (g_DATAWIDTH-1 downto 0);
    chan_o                          : out std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0)
    );
end component;
--------------------------------------------------------------------------------------------------------------------------
-- signal declaration
-------------------------------------------------------------------------------------------------------------------------- 
 signal s_cos                      : std_logic_vector (g_DATAWIDTH-1 downto 0);
 signal s_sin                      : std_logic_vector (g_DATAWIDTH-1 downto 0);
 signal s_chan                     : std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
 signal ddc_I0_data_i              :   T_Antenna_dataout;
 signal ddc_Q0_data_i              :   T_Antenna_dataout;
 signal ddc_I1_data_i              :   T_Antenna_dataout;
 signal ddc_Q1_data_i              :   T_Antenna_dataout; 
 signal ddc_data_vld_i             :   T_Antenna_Rxvalid; 
 signal ddc_data_vld_o             :   T_Antenna_Rxvalid;
 signal ddc_chan_o                 :   T_Antenna_chanout;
 signal	ddc_data_o				             :   T_Antenna_dataout;
begin

ddc_I0_data_i(0)    <= ddc_I0_data_i_0;    
ddc_Q0_data_i(0)    <= ddc_Q0_data_i_0;        
ddc_I1_data_i(0)    <= ddc_I1_data_i_0;        
ddc_Q1_data_i(0)    <= ddc_Q1_data_i_0;        
ddc_data_vld_i(0)   <= ddc_data_vld_i_0;       
ddc_data_vld_o_0    <= ddc_data_vld_o(0);    
ddc_chan_o_0        <= ddc_chan_o(0);
ddc_data_o_0        <= ddc_data_o(0);

ddc_I0_data_i(1)    <= ddc_I0_data_i_1;    
ddc_Q0_data_i(1)    <= ddc_Q0_data_i_1;        
ddc_I1_data_i(1)    <= ddc_I1_data_i_1;        
ddc_Q1_data_i(1)    <= ddc_Q1_data_i_1;        
ddc_data_vld_i(1)   <= ddc_data_vld_i_1;       
ddc_data_vld_o_1    <= ddc_data_vld_o(1);    
ddc_chan_o_1        <= ddc_chan_o(1);
ddc_data_o_1        <= ddc_data_o(1);


DDC_Gen : for i in 0 to (g_NUM_Rx_DATAPATHS-1) generate
          begin
            p_antennadual :  DDC_Antenna                                            
            port map( 
              -- Inputs
              nreset_i      => nreset_i,                                                   
              clock_i       => clock_i, 
              data_vld_i    => ddc_data_vld_i(i),                                                                                                   
              I0_data_i     => ddc_I0_data_i(i),
              Q0_data_i     => ddc_Q0_data_i(i),
              I1_data_i     => ddc_I1_data_i(i),
              Q1_data_i     => ddc_Q1_data_i(i),                                                    
              cos_i         => s_cos,
              sin_i         => s_sin,
              chan_i        => s_chan,
              -- Outputs
              data_vld_o    => ddc_data_vld_o(i),
              data_o        => ddc_data_o(i),
              chan_out_o    => ddc_chan_o(i)
            );
          end generate DDC_Gen;

U_dds_top: dds_top
  port map(
    clock_i                 => clock_i,
    nreset_i                => nreset_i,                      
    freqvalue_i             => ddc_freqvalue_i,
    freqword_en_i           => ddc_freqword_en_i,
    freqword_ch_i           => ddc_freqword_ch_i,                      
    cos_o                   => s_cos,
    sin_o                   => s_sin,
    chan_o                  => s_chan
  );
  

end architecture_DDC_Top;
