# Creating SmartDesign "JESD204B_IF"
set sd_name {JESD204B_IF}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DAC_SYNC_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYSREF_IN} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ADC_SYNC_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ALIGNED} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_REF_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYNC_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_ready_resetn} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_resetn} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {tx_resetn} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_IN1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_IN2} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_OUT_1} -port_direction {OUT} -port_range {[31:0]}


# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add CoreJESD204BRX_0 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:DirectCore:CoreJESD204BRX:$CoreJESD204BRXver -instance_name {CoreJESD204BRX_0}
# Exporting Parameters of instance CoreJESD204BRX_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CoreJESD204BRX_0} -params {\
"CF:0" \
"CS:0" \
"D_WIDTH:32" \
"DECODER_EN:0" \
"ECC_ENABLE:false" \
"F:4" \
"FAC_EN:1" \
"FAMILY:26" \
"FIELD_OCTET:0" \
"HD:0" \
"HDL_license:U" \
"ILA_MFS:4" \
"JESDV:1" \
"K:32" \
"L:1" \
"LCD_EN:0" \
"M:4" \
"N:16" \
"Na:16" \
"RAM_SEL:1" \
"S:1" \
"SCR:0" \
"SERDES_MODE:1" \
"SUBCLASSV:1" \
"testbench:User" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CoreJESD204BRX_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:SYSREF_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:CGS_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:UCC_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:SOF_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:SOF_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:SOMF_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:SOMF_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:RX_STATE_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BRX_0:RX_STATE_1}



# Add CoreJESD204BTX_1 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:DirectCore:CoreJESD204BTX:$CoreJESD204BTXver -instance_name {CoreJESD204BTX_1}
# Exporting Parameters of instance CoreJESD204BTX_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {CoreJESD204BTX_1} -params {\
"CF:0" \
"CS:0" \
"D_WIDTH:32" \
"ENCODER_EN:0" \
"F:4" \
"FAMILY:26" \
"FIELD_OCTET:0" \
"HD:0" \
"HDL_license:U" \
"ILA_MFS:4" \
"JESDV:1" \
"K:32" \
"L:1" \
"M:4" \
"N:16" \
"Na:16" \
"S:1" \
"SCR:0" \
"SERDES_MODE:1" \
"SUBCLASSV:1" \
"testbench:User" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {CoreJESD204BTX_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BTX_1:SYSREF_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BTX_1:TX_STATE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BTX_1:SOF}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreJESD204BTX_1:SOMF}



# Add INBUF_DIFF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INBUF_DIFF} -instance_name {INBUF_DIFF_0}



# Add OUTBUF_DIFF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {OUTBUF_DIFF} -instance_name {OUTBUF_DIFF_0}



# Add PF_TX_PLL_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C0} -instance_name {PF_TX_PLL_C0_0}



# Add PF_XCVR_ERM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0} -instance_name {PF_XCVR_ERM_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_TX_DISPFNC} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_TX_DISPFNC} -value {GND}



# Add PF_XCVR_REF_CLK_0 instance
sd_instantiate_core -sd_name ${sd_name} -core_vlnv Actel:SgCore:PF_XCVR_REF_CLK:$PF_XCVR_REF_CLKver -instance_name {PF_XCVR_REF_CLK_0}
# Exporting Parameters of instance PF_XCVR_REF_CLK_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {PF_XCVR_REF_CLK_0} -params {\
"ENABLE_FAB_CLK_0:true" \
"ENABLE_FAB_CLK_1:false" \
"ENABLE_REF_CLK_0:true" \
"ENABLE_REF_CLK_1:false" \
"FAMILY:26" \
"PARAM_IS_FALSE:false" \
"REF_CLK_MODE_0:DIFFERENTIAL" \
"REF_CLK_MODE_1:LVCMOS" \
"SD_EXPORT_HIDDEN_PORTS:false" \
"TGIGEN_DISPLAY_LOG_WINDOW:false" \
"TGIGEN_DISPLAY_SYMBOL:true" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {PF_XCVR_REF_CLK_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_N" "OUTBUF_DIFF_0:PADN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ADC_SYNC_P" "OUTBUF_DIFF_0:PADP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ALIGNED" "CoreJESD204BRX_0:ALIGNED" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CoreJESD204BTX_1:RESET_N" "HRESETN" "PF_XCVR_ERM_C0_0:LANE0_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PMA_ARST_N" "tx_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "PF_XCVR_ERM_C0_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CoreJESD204BRX_0:RESET_N" "rx_ready_resetn" "rx_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRL_ARST_N" "PF_XCVR_ERM_C0_0:CTRL_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRL_CLK_0" "PF_XCVR_ERM_C0_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:EPCS_0_RX_CLK" "CoreJESD204BRX_0:LANE_CLK" "LANE0_RX_CLK_R" "PF_XCVR_ERM_C0_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:EPCS_0_RX_VAL" "LANE0_RX_VAL" "PF_XCVR_ERM_C0_0:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:EPCS_1_RX_CLK" "LANE1_RX_CLK_R" "PF_XCVR_ERM_C0_0:LANE1_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:EPCS_1_RX_VAL" "PF_XCVR_ERM_C0_0:LANE1_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_RESET_N" "PF_XCVR_ERM_C0_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PCS_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:SYNC_N" "OUTBUF_DIFF_0:D" "SYNC_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:SYSREF_IN" "CoreJESD204BTX_1:SYSREF_IN" "SYSREF_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:EPCS_0_TX_CLK" "CoreJESD204BTX_1:LANE_CLK" "LANE0_TX_CLK_R" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:EPCS_0_TX_STABLE" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:EPCS_1_TX_CLK" "LANE1_TX_CLK_R" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:EPCS_1_TX_STABLE" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:SYNC_N" "INBUF_DIFF_0:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_N" "INBUF_DIFF_0:PADN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DAC_SYNC_P" "INBUF_DIFF_0:PADP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FAB_REF_CLK" "PF_XCVR_REF_CLK_0:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N_0" "PF_XCVR_ERM_C0_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P_0" "PF_XCVR_ERM_C0_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N_0" "PF_XCVR_ERM_C0_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P_0" "PF_XCVR_ERM_C0_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N_0" "PF_XCVR_ERM_C0_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P_0" "PF_XCVR_ERM_C0_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_N_0" "PF_XCVR_ERM_C0_0:LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_P_0" "PF_XCVR_ERM_C0_0:LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C0_0:REF_CLK" "PF_XCVR_ERM_C0_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_ERM_C0_0:LANE1_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_0:REF_CLK" "REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:DATA_OUT_0" "DATA_OUT_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:DATA_OUT_1" "DATA_OUT_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_CODE_VIOLATION_0" "PF_XCVR_ERM_C0_0:LANE0_RX_CODE_VIOLATION" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_CODE_VIOLATION_1" "PF_XCVR_ERM_C0_0:LANE1_RX_CODE_VIOLATION" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_DATA_0" "PF_XCVR_ERM_C0_0:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_DATA_1" "PF_XCVR_ERM_C0_0:LANE1_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_DISP_ERR_0" "PF_XCVR_ERM_C0_0:LANE0_RX_DISPARITY_ERROR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_DISP_ERR_1" "PF_XCVR_ERM_C0_0:LANE1_RX_DISPARITY_ERROR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_K_0" "PF_XCVR_ERM_C0_0:LANE0_8B10B_RX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BRX_0:RX_K_1" "PF_XCVR_ERM_C0_0:LANE1_8B10B_RX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:DATA_IN_0" "DATA_IN1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:DATA_IN_1" "DATA_IN2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:TX_DATA_0" "PF_XCVR_ERM_C0_0:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:TX_DATA_1" "PF_XCVR_ERM_C0_0:LANE1_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:TX_K_0" "PF_XCVR_ERM_C0_0:LANE0_8B10B_TX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJESD204BTX_1:TX_K_1" "PF_XCVR_ERM_C0_0:LANE1_8B10B_TX_K" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C0_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C0_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "JESD204B_IF"
generate_component -component_name ${sd_name}
