--/******************************************************************************
--    Company      		: MICROSEMI

--    File Name    		: Channel_Delay.vhd 
                   		
--    Description  		: This module implements programmable delay to the input signal

--    Targeted device 	: Family           Die          Package
--                   	  PolarFire     MPF300T_ES      MPF300T_ES

--    Author          	: India Solutions Team

--
-- SVN Revision Information:
-- SVN $Revision: 
-- SVN $Date:  $  
-- COPYRIGHT 2018 BY MICROSEMI 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM MICROSEMI CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
-- 

--******************************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;

entity Channel_Delay is
            generic(                   
                    g_DATA_WIDTH     : integer := 2;										-- Data width
                    g_DELAYS         : integer := 9											-- Delay count 
                   );
            port( 
			  clock_i      			: in     std_logic;										-- Clock signal 
			  nreset_i     			: in     std_logic;			         					-- Asynchronous reset signal 
              data_i                : in     std_logic_vector (g_DATA_WIDTH-1 downto 0);	-- Input data signal
              data_o                : out    std_logic_vector (g_DATA_WIDTH-1 downto 0)		-- Output data signal
            
            );
end Channel_Delay;
architecture architecture_Channel_Delay of Channel_Delay is
-----------------------------------------------------------------------------------------------------------------------
-- signal declarations
----------------------------------------------------------------------------------------------------------------------- 
type  T_data_reg                  is array (1 to g_DELAYS)  of std_logic_vector ((g_DATA_WIDTH-1)   downto 0);
signal s_data_delay               : T_data_reg;

begin

--****************************************************************************************
--** Process name  : p_Delay
--** Description   : This process implements programmable delay to the data input
--                   
--**************************************************************************************** 
p_Delay : process (nreset_i, clock_i) 
            begin
                  if(nreset_i = '0') then
                      s_data_delay <= (others =>(others=>'0'));
                  elsif(rising_edge(clock_i)) then
                      s_data_delay <= data_i & s_data_delay(1 to g_DELAYS-1);  
                  end if;                 
           end process p_Delay ;
 data_o  <= s_data_delay(g_DELAYS);


end architecture_Channel_Delay;
