--/******************************************************************************
--    Company      		: MICROSEMI

--    File Name    		: DUC_Top.vhd 
                   		
--    Description  		: This module instantiates the DUC modules for defined antennas

--    Targeted device 	: Family           Die          Package
--                   	  PolarFire     MPF300T_ES      MPF300T_ES

--    Author          	: India Solutions Team

--
-- SVN Revision Information:
-- SVN $Revision: 
-- SVN $Date:  $  
-- COPYRIGHT 2018 BY MICROSEMI 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM MICROSEMI CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
-- 

--******************************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.System_pack.all;
use work.dds_pack.all;

entity DUC_Top is        
  port( 
			 clock_i        			              : in     std_logic;                           -- Clock signal
			 nreset_i       			              : in     std_logic;                           -- Asynchronous reset signal
    -- DUC Inputs
    duc_data_vld_i_0                : in  std_logic;                              -- Input duc data valid signals  
    duc_chan_i_0                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals          
    duc_data_i_0				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals
    duc_data_vld_i_1                : in  std_logic;                              -- Input duc data valid signals 
    duc_chan_i_1                    : in  std_logic_vector (2   downto 0);        -- Input duc channel count signals     
    duc_data_i_1				                : in  std_logic_vector (15   downto 0);       -- Input duc data signals 
    duc_freqvalue_i                 : in  std_logic_vector(31 downto 0);          -- Input dds frequency value signal
    duc_freqword_ch_i               : in  std_logic_vector(1 downto 0);           -- Input dds frequency channel signal
    duc_freqword_en_i               : in  std_logic;                              -- Input dds frequency enable signal
    -- DUC Outputs   
    duc_I0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Inphase data signals
    duc_Q0_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant0 Quadrature data signals
    duc_I1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Inphase data signals
    duc_Q1_data_o_0                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant1 Quadrature data signals
    duc_data_vld_o_0                : out  std_logic;                             --- Output duc data valid signals
    duc_I0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Inphase data signals
    duc_Q0_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant2 Quadrature data signals
    duc_I1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Inphase data signals
    duc_Q1_data_o_1                 : out  std_logic_vector (15   downto 0);      -- Output duc Ant3 Quadrature data signals
    duc_data_vld_o_1                : out  std_logic
            );
end DUC_Top;
architecture architecture_DUC_Top of DUC_Top is
-----------------------------------------------------------------------------------------------------------------------
-- component declarations 
-----------------------------------------------------------------------------------------------------------------------
-- DUC_Antenna
component DUC_Antenna
  -- Port list
  port(
    -- Inputs
    chan_in_i                       : in  std_logic_vector(2 downto 0);
    clock_i                         : in  std_logic;
    data_i                          : in  std_logic_vector(15 downto 0);
    data_vld_i                      : in  std_logic;       
    cos_i                           : in std_logic_vector (g_DATAWIDTH-1 downto 0);
    sin_i                           : in std_logic_vector (g_DATAWIDTH-1 downto 0);
    chan_i                          : in std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
    nreset_i                        : in  std_logic;
    -- Outputs                      
    I0_data_o                       : out std_logic_vector(15 downto 0);
    I1_data_o                       : out std_logic_vector(15 downto 0);
    Q0_data_o                       : out std_logic_vector(15 downto 0);
    Q1_data_o                       : out std_logic_vector(15 downto 0);
    data_vld_o                      : out std_logic
  );
end component;
component dds_top
  port (
    clock_i                         : in std_logic;
    nreset_i                        : in std_logic;
    -- Phase word inputs            
    freqvalue_i                     : in std_logic_vector (g_PHASE_WIDTH-1 downto 0);
    freqword_en_i                   : in std_logic;
    freqword_ch_i                   : in std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
    -- Output sin cos               
    cos_o                           : out std_logic_vector (g_DATAWIDTH-1 downto 0);
    sin_o                           : out std_logic_vector (g_DATAWIDTH-1 downto 0);
    chan_o                          : out std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0)
  );
end component;

--------------------------------------------------------------------------------------------------------------------------
-- signal declaration
-------------------------------------------------------------------------------------------------------------------------- 
 signal s_cos                       : std_logic_vector (g_DATAWIDTH-1 downto 0);
 signal s_sin                       : std_logic_vector (g_DATAWIDTH-1 downto 0);
 signal s_chan                      : std_logic_vector (g_NUM_CHANNELS_WIDTH-1 downto 0);
 signal duc_data_vld_i              : T_Antenna_Txvalid;
 signal duc_chan_i                  : T_Antenna_chanin;
 signal	duc_data_i				              : T_Antenna_datain;
 signal duc_I0_data_o               : T_Antenna_datain;
 signal duc_Q0_data_o               : T_Antenna_datain;
 signal duc_I1_data_o               : T_Antenna_datain;
 signal duc_Q1_data_o               : T_Antenna_datain; 
 signal duc_data_vld_o              : T_Antenna_Txvalid;
begin

duc_data_vld_i(0)   <= duc_data_vld_i_0;
duc_chan_i(0)       <= duc_chan_i_0;
duc_data_i(0)       <= duc_data_i_0;      
duc_I0_data_o_0     <= duc_I0_data_o(0);     
duc_Q0_data_o_0     <= duc_Q0_data_o(0);    
duc_I1_data_o_0     <= duc_I1_data_o(0);    
duc_Q1_data_o_0     <= duc_Q1_data_o(0);    
duc_data_vld_o_0    <= duc_data_vld_o(0);    
duc_data_vld_i(1)   <= duc_data_vld_i_1;
duc_chan_i(1)       <= duc_chan_i_1;
duc_data_i(1)       <= duc_data_i_1;
duc_I0_data_o_1     <= duc_I0_data_o(1);     
duc_Q0_data_o_1     <= duc_Q0_data_o(1);    
duc_I1_data_o_1     <= duc_I1_data_o(1);    
duc_Q1_data_o_1     <= duc_Q1_data_o(1);    
duc_data_vld_o_1    <= duc_data_vld_o(1); 

Duc_Gen : for i in 0 to (g_NUM_Tx_DATAPATHS-1) generate
          begin
            p_antennadual :  DUC_Antenna                                            
            port map( 
              -- Inputs
              nreset_i      => nreset_i,
              data_vld_i    => duc_data_vld_i(i),
              clock_i       => clock_i,                                                   
              chan_in_i     => duc_chan_i(i),
              data_i        => duc_data_i(i),                                                   
              cos_i         => s_cos,
              sin_i         => s_sin,
              chan_i        => s_chan,
              -- Outputs
              data_vld_o    => duc_data_vld_o(i),
              I0_data_o     => duc_I0_data_o(i),
              Q0_data_o     => duc_Q0_data_o(i),
              I1_data_o     => duc_I1_data_o(i),
              Q1_data_o     => duc_Q1_data_o(i) 
            );
          end generate Duc_Gen;

U_dds_top: dds_top
  port map(
    clock_i                 => clock_i,
    nreset_i                => nreset_i,                      
    freqvalue_i             => duc_freqvalue_i,
    freqword_en_i           => duc_freqword_en_i,
    freqword_ch_i           => duc_freqword_ch_i,                      
    cos_o                   => s_cos,
    sin_o                   => s_sin,
    chan_o                  => s_chan
    );


end architecture_DUC_Top;
