library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.math_real.all;
use WORK.SYSTEM_PACK.all;
use work.DUC_HB3_INT_COEFFPACk.all;
entity DUC_HB3_INT is
port (clock_i: in std_logic;
NRESET_i: in STD_LOGIC;
data_vld_i: in STD_LOGIC;
Data_i: in std_logic_vectOR(g_DATAIN_WIDTH-1 downto 0);
DATA_O: out std_logic_vector(G_DATAOUT_Width-1 downto 0);
chan_in_i: in STD_LOGIC_vector(g_chan_width-1 downto 0);
chan_out_o: out std_logic_vector(g_chan_width-1 downto 0);
data_vlD_O: out STD_LOGIC);
end dUC_HB3_INT;

architecture o of DUC_Hb3_int is

attribute syn_preserve: boolean;

attribute SYn_preserve of O: architecture is true;

signal l: std_logic;

signal I: STD_LOGIC_VECTor(G_DATAIN_WIDTH-1 downto 0);

signal ol: std_logic_vector(g_datain_width-1 downto 0);

type ll is array (0 to G_dspcount-1) of std_logic_vector(0 downto 0);

type IL is array (1 to G_DSPcount-1) of std_logic_vector(0 downto 0);

signal OI: il;

signal li: ll;

type II is array (0 to G_dspcount-1) of std_loGIC_VECTOR((G_DATAIN_width-1) downto 0);

type O0 is array (1 to g_dspcount-1) of std_logic_vector((g_dataIN_WIDTH-1) downto 0);

signal L0: o0;

signal I0: II;

signal O1: II;

signal L1: II;

signal I1: std_lOGIC;

signal OOL: stD_LOGIC_VECTOR(0 downto 0);

signal lol: std_logic_vector(0 downto 0);

signal IOL: STD_LOGIC_VECTOR(g_coeFF_WIDTH-1 downto 0);

type oll is array (0 to g_dspCOUNT-1) of std_logIC_VECTOR((G_accwidth-1) downto 0);

signal LLL: OLL;

signal ILL: OLL;

type OIL is array (0 to g_dspcount-1) of STD_LOGIC_VECTOR((g_finaladdwidth-1) downto 0);

signal LIL: oll;

signal IIL: std_logic_vector(g_accwidth-1 downto 0);

signal o0l: std_LOGIC_VECTOR(g_DATAIN_WIDTH-1 downto 0);

signal L0L: std_logic_vector(g_finaladdwidtH-1 downto 0);

signal I0L: std_logic_vecTOR(G_FINALADDWIDth-1 downto 0);

signal o1l: STD_LOGIC_VECTOr((g_chan_widTH-1) downto 0);

signal L1L: std_logic_vecTOR((g_chan_width-1) downto 0);

signal i1l: STD_logic_vector((g_chan_width-1) downto 0);

signal OOI: std_logic_vECTOR(G_DATAOUT_WIDTh-1 downto 0);

signal loi: std_LOGIC_VECTOR(g_datain_width-1 downto 0);

signal IOI: STD_LOGIC_VECTOR(G_datain_width-1 downto 0);

signal oli: sTD_LOGIC_VECTOR(G_Accwidth-1 downto 0);

signal LLI: STD_LOGIc;

component DATA_SHIFTER
generic (G_DATA_WIDTH: integer := 16;
G_SHIFT_DELAY: integer := 3);
port (clock_i: in std_logic;
nreset_i: in STD_LOGIC;
shift_en_i: in std_logic;
DATA_I: in std_logic_vector((g_DATA_WIDTH-1) downto 0);
DATA_O: out STD_LOGIC_vector((G_DATA_WIDTH-1) downto 0));
end component;

component MULT_ADDSUb is
generic (G_A_WIDTH: INTEGER := 16;
G_B_WIDTH: INTEGER := 16;
G_D_width: integer := 16;
g_c_width: integer := 37;
g_cin_width: Integer := 37;
G_p_width: integer := 37);
port (CLOCK_I: in STD_LOGIC;
nreset_i: in std_logic;
A_I: in std_logic_vECTOR(G_A_WIDTH-1 downto 0);
B_I: in STD_LOGIC_vector(G_B_WIDTH-1 downto 0);
d_i: in STD_LOgic_vector(G_D_WIDTH-1 downto 0);
c_i: in STD_LOGIC_vector(g_c_width-1 downto 0);
CIN_I: in std_logic_vector(G_CIN_WIDTh-1 downto 0);
cdin_fdbk_sel_I: in STD_LOGIC_VECTor(1 downto 0);
cdout_o: out std_LOGIC_VECTOR(G_P_WIDTH-1 downto 0);
p_o: out std_loGIC_VECTOR(G_P_WIDTH-1 downto 0));
end component;

component macc_rom
generic (g_a_width: integer := 16;
g_b_width: integer := 16;
G_d_width: INTEGer := 16;
G_c_width: integer := 37;
g_cin_width: integer := 37;
g_p_width: integer := 37;
G_INIT: STD_LOGIC_VECTOR(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000");
port (CLOCK_I: in STD_LOGIC;
nrESET_I: in std_LOGIC;
a_i: in STD_logic_vector(g_a_width-1 downto 0);
B_I: in std_logic_vector(G_B_WIDTH-1 downto 0);
A_ROM_Addr_i: in std_lOGIC_VECTOR(3 downto 0);
D_I: in std_logic_vector(g_d_width-1 downto 0);
C_I: in std_logiC_VECTOR(g_c_WIDTH-1 downto 0);
cin_i: in std_LOGIC_VECTOR(g_cin_width-1 downto 0);
CDIN_FDbk_sel_i: in std_loGIC_VECTOR(1 downto 0);
cdout_o: out STD_Logic_vector(47 downto 0);
p_o: out std_logic_vector(G_P_WIDTH-1 downto 0));
end component;

component round_sat is
generic (g_unrnD_DATA_WIDTH: POSITIVE := 33;
g_rnd_data_widtH: POSITIVE := 16;
G_UNRND_fract_bits: positive := 30;
G_RND_FRACT_BITS: POSITive := 15);
port (clock_i: in STD_logic;
nreset_i: in STD_LOGIC;
data_i: in std_logic_vector(G_unrnd_data_width-1 downto 0);
data_o: out std_lOGIC_VECTOR(G_RND_DATA_WIDTh-1 downto 0));
end component;

begin
ILI:
process (NRESET_I,cloCK_I)
begin
if (nreset_i = '0') then
L <= '0';
elsif (RISING_EDGE(CLOCK_I)) then
L <= data_vld_i;
end if;
end process ILI;
oii:
process (nreset_i,CLOCK_I)
begin
if (nreset_i = '0') then
I <= ( others => '0');
OL <= ( others => '0');
elsif (RISIng_edge(clock_i)) then
i <= ol;
OL <= data_i;
end if;
end process oiI;
lii:
for iii in 1 to (g_dspcount-1)
generate
begin
P_FWD_Delay_shift: DATa_shifter
generic map (G_DATA_Width => 1,
G_SHIFT_DELAY => 1)
port map (CLOCK_I => CLOCK_I,
NRESET_I => nreset_i,
SHIFT_EN_i => '1',
DATA_I => oi(III),
DATA_O => LI(iii));
end generate lii;
LI(0)(0) <= L;
O0I:
for iii in 0 to (g_dsPCOUNT-2)
generate
begin
OI(iII+1) <= LI(III);
end generate o0i;
l0i:
for III in 1 to (G_dspcount-1)
generate
begin
P_FWD_DELAY_Ram: DATA_SHIFTer
generic map (G_DATA_WIDTH => G_DATAIN_WIDTh,
g_shift_delay => g_chancounT+1)
port map (CLOCK_I => clock_i,
nreset_I => nreset_i,
shift_en_i => li(iii)(0),
DATa_i => l0(iii),
DATA_O => i0(III));
end generate L0I;
i0(0) <= I;
I0I:
for iii in 0 to (G_DSPCOUNT-2)
generate
begin
l0(iii+1) <= i0(III);
end generate i0i;
O1(0) <= I0(G_DSPCOUNT-1);
i1 <= LI(G_DSPCOUNT-1)(0);
o1i:
if (G_HAS_SYMm = 1)
generate
L1I:
if (G_SYMM = 0)
generate
P_REV_delay_ram_0: DAta_shifter
generic map (G_DATA_WIDTH => g_datain_width,
g_shift_DELAY => 0)
port map (clock_i => CLOCK_I,
nreset_i => nreSET_I,
SHIFT_en_i => i1,
data_i => o1(0),
data_o => L1(0));
end generate L1I;
i1i:
if (g_symm = 1)
generate
p_rev_DELAY_RAM_0: DATA_SHIFTER
generic map (G_data_width => G_DATAIN_WIDTH,
G_SHIFT_delay => G_CHANCOUNT)
port map (CLOCK_I => clocK_I,
NRESET_I => nreset_I,
SHIFT_EN_I => i1,
DATA_I => O1(0),
DAta_o => l1(0));
end generate I1I;
P_FINAL_Delay_shift: data_shifter
generic map (g_data_width => 1,
g_shift_delaY => (G_Dspcount+4))
port map (CLOCK_I => CLOck_i,
NRESET_i => nreset_i,
SHIFT_EN_I => '1',
DATA_I => ool,
data_o => LOL);
ool(0) <= L;
OO0:
for iii in 1 to (g_dspcount-1)
generate
begin
P_REV_DELAY_RAM: DATA_SHIFTER
generic map (G_DATA_WIDTH => g_datain_width,
G_SHIFT_DELAY => G_CHANCOUNT-1)
port map (CLOCK_I => clock_i,
nreset_i => NRESET_I,
shift_en_i => '1',
DATA_I => o1(iii),
data_o => l1(iii));
end generate OO0;
lo0:
for iii in 0 to (g_dspcount-2)
generate
begin
O1(III+1) <= L1(iii);
end generate LO0;
end generate O1I;
IIL <= ( others => '0');
iol <= ( others => '0');
p_mult_acc0: MACC_rom
generic map (G_a_width => G_COEFF_WIDTH,
g_b_width => G_DATAIN_WIDTH,
G_d_width => G_DATAIN_WIDTh,
g_c_width => G_ACCWIDTH,
G_CIN_WIDth => g_accwidth,
g_P_WIDTH => G_accwidth,
g_init => G_INIT)
port map (CLOCk_i => clock_i,
NRESET_I => nRESET_I,
A_i => IOL,
b_i => i0(0),
A_ROM_addr_i => "0000",
D_I => L1(g_dspcount-1),
C_I => IIL,
cin_i => ill(0),
cdin_fdbk_sel_i => "00",
cdout_o => lll(0),
P_O => LIL(0));
IO0:
for iii in 1 to (g_dspcounT-1)
generate
begin
P_MULT_acc: MACC_ROM
generic map (G_A_width => G_COEFF_WIDTH,
G_B_WIDTH => g_datain_width,
g_d_widTH => G_DATain_width,
g_c_width => g_accwidTH,
g_cin_wiDTH => G_ACCWIDTH,
G_P_WIDTH => G_accwidth,
G_INit => g_init)
port map (clock_i => clock_i,
nreset_i => nreset_i,
a_i => iol,
B_I => i0(iII),
A_ROM_ADDR_I => std_logic_vector(to_UNSIGNED(III,
4)),
d_i => L1(g_dspcount-1-iii),
C_I => iil,
CIN_I => ILL(III),
CDIN_FDBK_Sel_i => "11",
cdout_o => LLL(III),
P_O => LIL(iiI));
end generate io0;
OL0:
for iii in 0 to (g_dspcOUNT-2)
generate
begin
ILL(iii+1) <= lll(III);
end generate ol0;
ILL(0) <= ( others => '0');
ll0:
process (NRESET_i,CLOCK_I)
begin
if (NRESET_i = '0') then
l0l <= ( others => '0');
elsif (RISING_EDGE(CLOCK_I)) then
L0L <= std_logic_vecTOR(RESIZE(signed(lil(g_dspcount-1)),
g_finaladDWIDTH));
end if;
end process ll0;
LOI <= i0(G_DSPCount-1);
p_center_delay_rAM: data_shifteR
generic map (g_data_widTH => G_DATAIN_WIDth,
G_SHIFT_delay => G_NUMCHANNELS+1)
port map (clock_i => Clock_i,
nreset_i => nreset_i,
shifT_EN_I => '1',
data_i => LOI,
data_o => IOI);
p_muLT_CENTER: MULT_ADDSUB
generic map (G_A_WIDTH => g_coeff_WIDTH,
G_B_WIDTH => G_DATAIN_WIDTH,
g_d_width => G_DATAIN_width,
g_c_widTH => g_accWIDTH,
G_CIn_width => g_accwidTH,
g_P_WIDTH => G_ACCWIDTH)
port map (CLOCK_I => clock_i,
nreset_i => Nreset_i,
a_i => g_center_tap,
b_i => ioi,
d_i => o0l,
C_I => iil,
CIN_i => iil,
cdin_FDBK_SEL_I => "00",
cDOUT_O => open ,
p_o => OLI);
o0l <= ( others => '0');
IL0:
process (NRESET_I,clock_i)
begin
if (nreset_i = '0') then
o1l <= ( others => '0');
elsif (rising_edge(clock_i)) then
if (lol(0) = '1') then
if (i1l = STD_LOGIC_vector(TO_UNSIGNED((G_NUMCHANNELS),
g_chan_width)) or i1l = STD_LOGIC_vector(TO_UNSIGned((0),
G_CHAN_WIDTh))) then
o1l <= ( others => '0');
else
o1l <= o1l+'1';
end if;
end if;
end if;
end process il0;
OI0: DATA_SHIFTER
generic map (g_datA_WIDTH => g_chan_width,
G_SHIFT_DELAY => (g_dspCOUNT+3))
port map (CLOCK_I => CLOCK_I,
NRESET_I => nreset_i,
SHIFT_EN_I => '1',
DATA_i => chan_in_I,
DATA_O => i1l);
li0:
process (NRESET_I,cLOCK_I)
begin
if (nreset_i = '0') then
LLI <= '0';
elsif (RISING_EDGE(CLOCK_I)) then
if (i1l > STD_LOGIC_VECTOR(to_UNSIGNED(G_NUMCHANNELS-1,
g_CHAN_WIDTH)) and LOL(0) = '1') then
LLI <= '1';
else
Lli <= '0';
end if;
end if;
end process li0;
ii0:
process (nreset_i,CLOCK_I)
begin
if (Nreset_i = '0') then
i0l <= ( others => '0');
elsif (RISING_EDGE(CLOCK_I)) then
if (lli = '0') then
I0l <= L0L;
else
I0L <= std_logic_vector(RESIZE(signeD(OLI),
g_finaladdwidtH));
end if;
end if;
end process ii0;
u_round_sat: round_sat
generic map (g_unrnd_data_width => G_finaladdwidth,
G_RND_DATA_WIDTH => G_DATAOUT_width,
G_UNRND_FRACt_bits => g_unrnd_fracwidth,
G_RND_fract_bits => G_DATAOUT_fracwidth)
port map (CLOCK_I => CLOCK_I,
NRESET_I => nreset_i,
data_i => i0l,
data_o => OOI);
data_o <= oOI;
O00:
process (NRESET_I,clock_i)
begin
if (NRESET_I = '0') then
L1L <= ( others => '0');
chaN_OUT_O <= ( others => '0');
elsif (Rising_edge(CLOCK_i)) then
if (LOL(0) = '1') then
L1L <= O1L;
end if;
chan_out_O <= l1l;
end if;
end process O00;
l00:
process (nreset_i,CLOCK_i)
begin
if (NRESET_I = '0') then
dATA_VLD_O <= '0';
elsif (RISING_EDGE(CLOCK_I)) then
DATA_VLD_O <= lol(0);
end if;
end process l00;
end;
