--/******************************************************************************
--    Company      		: MICROSEMI

--    File Name    		: ddc_axc_tdm_data.vhd 
                   		
--    Description  		: This module implements demuxing of axc data to cpri format  

--    Targeted device 	: Family           Die          Package
--                   	  PolarFire     MPF300T_ES      MPF300T_ES

--    Author          	: India Solutions Team

--
-- SVN Revision Information:
-- SVN $Revision: 
-- SVN $Date:  $  
-- COPYRIGHT 2018 BY MICROSEMI 
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS 
-- FROM MICROSEMI CORP.  IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM 
-- MICROSEMI FOR USE OF THIS FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND 
-- NO BACK-UP OF THE FILE SHOULD BE MADE. 
-- 

--******************************************************************************/
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity ddc_axc_tdm_data is
            generic(
                        g_NUM_AXC       : integer := 2;                                                 -- AXC count
                        g_AXC_RATE      : integer := 8;                                                 -- AXC Rate
                        g_NUM_ANTENNA   : integer := 4;                                                 -- RF ANTENNA COUNT
                        g_DATAWIDTH     : integer := 32                                                 -- DATA WIDTH
                );
                port (
                       nreset_i         : in std_logic;                                                 --Asynchronous reset signal
                       clock_i          : in std_logic;                                                 --Clock signal
                       data_i          : in std_logic_vector((g_NUM_AXC*g_DATAWIDTH)-1 downto 0);       --Input  ddc data signal                    
                       data_vld_i       : in std_logic;                                                 --Input ddc data valid signal
                       data_chan_i      : in std_logic_vector(g_NUM_ANTENNA-1 downto 0);                --Input ddc channel count signal
                       data_vld_o       : out std_logic_vector(g_NUM_AXC-1 downto 0);                   --Output axcdata valid signal
                       data_o           : out std_logic_vector((g_NUM_AXC*g_DATAWIDTH)-1 downto 0)      --Output axc data signal
                                     
);
end ddc_axc_tdm_data;
architecture architecture_ddc_axc_tdm_data of ddc_axc_tdm_data is
-------------------------------------------------------------------
-- Signals declaration
-------------------------------------------------------------------
signal s_wen         :  std_logic_vector(g_NUM_AXC-1 downto 0);
signal s_data        :  std_logic_vector((g_NUM_AXC*g_DATAWIDTH)-1 downto 0);

begin

--************************************************************************************************
--** process id  : P_wen
--** Description : This process generates write valid based on channel count 0
--************************************************************************************************
wen_proc: for i in 0 to (g_NUM_AXC-1) generate
          begin
                P_wen: process(clock_i,nreset_i)
                        begin
                             if(nreset_i  = '0') then                  
                                    s_wen(i) <=  '0';
                             elsif(rising_edge(clock_i)) then 
                                if(data_vld_i ='1' and data_chan_i = "0000") then                                                 
                                            s_wen(i) <= '1';                         
                                else
                                            s_wen(i) <=  '0';                  
                                    
                                end if;
                            end if;
                            end process;
end generate;

--************************************************************************************************
--** process id  : P_data
--** Description : This process generates write valid based on channel count 0
--************************************************************************************************
P_data: process(clock_i,nreset_i)
        begin
             if(nreset_i  = '0') then                  
                s_data <=  (others =>'0');
             elsif(rising_edge(clock_i)) then 
                s_data <= data_i;
             end if;   
      end process;

data_vld_o <= s_wen;
data_o     <= s_data;

end architecture_ddc_axc_tdm_data;
