library Ieee;
use ieee.std_loGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use woRK.system_pack.all;
use work.DDS_PACK.all;
entity DDS_TOP is
port (clock_i: in sTD_LOGIC;
nreset_i: in std_logic;
freqvalue_i: in STD_LOGIC_vector(g_phase_width-1 downto 0);
FREQWORD_EN_i: in std_logic;
freqword_ch_i: in std_lOGIC_VECTOR(g_NUM_CHANNELS_WIdth-1 downto 0);
COS_O: out std_lOGIC_VECTOR(G_datawidth-1 downto 0);
SIN_O: out std_logiC_VECTOR(G_DATAWIDTH-1 downto 0);
CHAN_O: out std_logic_vector(g_num_chanNELS_WIDTH-1 downto 0));
end dds_top;

architecture o of dds_top is

attribute syn_preserve: boolean;

attribute syn_preserve of O: architecture is TRUe;

constant L: Integer := INTEger(10 mod g_num_channels);

signal i: INTEGER range 0 to (g_num_channELS-1);

signal OL: integeR range 0 to (g_nUM_CHANNELS-1);

signal LL: STD_LOGIC;

signal IL: STD_LOGIC;

signal oi: STD_logic;

signal li: std_logic_vecTOR(G_PHASE_Width-1 downto 0);

signal Ii: sTD_LOGIC_VECTOr(G_num_channels_wiDTH-1 downto 0);

signal O0: integeR range 0 to (G_NUM_channels-1);

signal l0: Unsigned(g_phase_width-1 downto 0);

signal i0: unsigned(C_LUT_ADDRWidth-1 downto 0);

signal o1: STD_LOGIc_vector(c_frac_width-1 downto 0);

signal l1: STD_LOGIC_VEctor(C_FRAC_WIDTh-1 downto 0);

signal i1: STD_LOGIC_VECTOR(c_fraC_WIDTH-1 downto 0);

signal OOL: STD_LOGIC_VECTOR(c_frac_width-1 downto 0);

signal LOL: std_LOGIC_VECTOR(C_FRAC_width-1 downto 0);

signal iol: std_logic_vector(g_datawidth-1 downto 0);

signal oll: std_logic_vector(g_DATAWIDTH-1 downto 0);

signal LLL: STD_LOGIC_Vector(C_FRac_width-1 downto 0);

signal ILL: STD_LOGIC_VECTor(C_FRAC_width-1 downto 0);

signal oil: STD_logic_vector(C_frac_width downto 0);

signal lil: std_logiC_VECTOR(c_FRAC_WIDTH downto 0);

signal IIL: STD_LOGIC_vector(G_DATAWIDTH+C_FRAC_WIDTH-1 downto 0);

signal o0l: std_logic_vectoR(g_dataWIDTH+c_frac_widTH-1 downto 0);

signal l0l: STd_logic_vector(g_datawIDTH+c_fRAC_WIDTH downto 0);

signal i0l: std_loGIC_VECTOR(G_DATawidth+C_FRAC_Width downto 0);

signal o1l: Std_logic_vector(G_DATAWIDTH-1 downto 0);

signal L1L: STD_LOGIC_VEctor(g_datawidth-1 downto 0);

signal i1l: std_logic;

signal ooi: STD_LOGIc_vector(C_LUT_addrwidth-1 downto 0);

signal loi: std_logic_vectoR(c_LUT_ADDRWIDTH-1 downto 0);

signal ioi: std_logic_vector(C_FRac_width-1 downto 0);

signal OLI: STD_logic_vector(47 downto 0);

type LLI is array (0 to G_NUM_channels-1) of UNSIGNED((G_PHAse_width-1) downto 0);

type ILI is array (1 to l) of std_logic_vector((g_num_chanNELS_WIDTH-1) downto 0);

signal oii: ili;

signal LII: lli;

signal iii: Lli;

attribute SYN_RAMSTYLE: string;

attribute sYN_RAMSTYLE of iii: signal is "registers";

attribute syn_maxfan: INteger;

attribute SYN_MAXFAN of LII,OI,LI,OOI: signal is 1;

component SINCOs_ram
port (r_addr: in STD_Logic_vector(10 downto 0);
r_clk: in STD_LOGIC;
w_aDDR: in STD_logic_vector(10 downto 0);
w_clk: in std_loGIC;
W_DATA: in std_logic_vectoR(15 downto 0);
W_en: in STD_logic;
R_Data: out std_logic_veCTOR(15 downto 0));
end component SINCos_ram;

component mULT_ADDSUB is
generic (g_a_width: inTEGER := 16;
G_B_WIdth: integer := 16;
g_d_width: intEGER := 16;
G_C_Width: INTEGEr := 37;
g_cin_width: INTEGER := 37;
g_p_width: integeR := 37);
port (clock_i: in std_logic;
NReset_i: in std_logic;
a_i: in STD_LOGIC_VECTOR(G_A_WIDTH-1 downto 0);
b_i: in std_logic_vector(G_B_WIDTH-1 downto 0);
d_i: in STD_LOGIC_vector(g_d_width-1 downto 0);
C_I: in STD_LOGIC_vector(G_C_WIDTH-1 downto 0);
cin_i: in STD_LOGIC_VEctor(G_CIN_width-1 downto 0);
CDIN_FDBK_SEL_i: in std_logic_vector(1 downto 0);
cdout_O: out std_logic_vectoR(47 downto 0);
P_O: out std_logic_vector(G_p_width-1 downto 0));
end component;

begin
O0I:
process (CLOCK_I,nreset_i)
begin
if (nreset_i = '0') then
LL <= '0';
il <= '0';
elsif rising_edge(CLOCK_I) then
LL <= freqword_en_i;
IL <= Ll;
end if;
end process o0i;
OI <= ll and not (IL);
l0i:
process (clock_i,NRESET_I)
begin
if (NRESET_i = '0') then
LI <= ( others => '0');
II <= ( others => '0');
elsif risING_EDGE(clock_i) then
li <= freqvalue_i;
II <= freqword_ch_i;
end if;
end process l0i;
I0I:
process (nresET_I,CLOCk_i)
begin
if (NRESET_I = '0') then
i <= G_NUM_CHANNELs-1;
ol <= G_NUM_CHANNELs-1;
I1L <= '0';
elsif (rising_edge(CLOCK_I)) then
if (I = (g_num_channels-1)) then
I <= 0;
i1l <= '1';
else
i <= I+1;
I1l <= '0';
end if;
ol <= i;
end if;
end process I0I;
O1I:
process (clock_I,NRESEt_i)
begin
if (nresET_I = '0') then
for L1I in 0 to (G_NUM_CHANNELs-1)
loop
LII(l1i) <= UNSIGNED(G_PHASE_values(l1i));
end loop;
elsif RISING_EDGE(CLOCK_I) then
if (OI = '1') then
lii(o0) <= UNSIGNED(li);
end if;
end if;
end process o1i;
O0 <= to_inteGER(UNSIGNED(ii));
I1I:
process (clock_I,NRESET_I)
begin
if (nreset_i = '0') then
iii <= ( others => ( others => '0'));
elsif riSING_EDGE(cLOCK_I) then
for l1i in 0 to (g_NUM_CHANNELS-1)
loop
if (oI = '1') then
III(o0) <= ( others => '0');
elsif (i1l = '1') then
iii(L1I) <= IIi(l1i)+lii(L1I);
end if;
end loop;
end if;
end process i1i;
oo0:
process (CLOCK_i,nreset_i)
begin
if (NRESET_I = '0') then
l0 <= ( others => '0');
elsif rising_edge(clock_i) then
L0 <= iii(ol);
end if;
end process OO0;
LO0:
process (CLOCK_i,nreset_i)
begin
if (nreset_i = '0') then
i0 <= ( others => '0');
o1 <= ( others => '0');
elsif RISING_EDGE(clock_i) then
I0 <= l0(G_PHASE_width-1 downto (g_PHASE_WIDTH-C_LUT_ADDRWIDTH));
o1 <= STD_LOGIC_VECtor(l0((g_phase_width-c_lut_ADDRWIDTH-1) downto (G_PHASE_width-c_lut_ADDRWIDTH-c_frac_width)));
end if;
end process LO0;
IO0:
process (CLOCK_I,NREset_i)
begin
if (nreset_i = '0') then
LLL <= ( others => '0');
ILL <= ( others => '0');
elsif rising_edge(clock_i) then
lll <= O1;
iLL <= LLL;
end if;
end process iO0;
ol0:
process (clock_i,nreSET_I)
begin
if (nreset_i = '0') then
ooi <= ( others => '0');
lOI <= ( others => '0');
elsif RISING_EDGE(CLOCK_I) then
ooi <= std_logIC_VECTOR(I0);
lOI <= std_LOGIC_VECTOR(I0+512);
end if;
end process OL0;
U_COS_RAM: siNCOS_RAM
port map (r_adDR => loi,
r_clk => clock_i,
W_ADDR => ( others => '1'),
w_clk => '0',
W_DATA => ( others => '0'),
W_EN => '0',
R_DATA => IOL);
u_sin_ram: SINcos_ram
port map (r_adDR => OOI,
r_clk => clock_i,
w_adDR => ( others => '1'),
w_CLK => '0',
W_DATA => ( others => '0'),
w_en => '0',
r_data => oll);
LL0:
process (nreset_i,clOCK_I)
begin
if (NRESET_I = '0') then
OIL <= ( others => '0');
lil <= ( others => '0');
o0l <= ( others => '0');
IIL <= ( others => '0');
ool <= ( others => '0');
LOL <= ( others => '0');
elsif (rISING_EDGE(clock_i)) then
oiL <= ('0'&ill);
lil <= OIL;
O0L <= iol&X"00";
IIL <= oll&X"00";
ool <= X"00";
lol <= X"00";
end if;
end process;
ioi <= ( others => '0');
oli <= ( others => '0');
p_multadd_sin: mult_addsub
generic map (g_a_width => C_FRAC_width+1,
g_b_width => C_Frac_width,
g_d_WIDTH => c_frac_wiDTH,
g_c_width => g_dataWIDTH+C_FRAC_WIDTH,
g_cin_width => 48,
g_p_widtH => G_DATAWIDTH+C_FRAC_width+1)
port map (clock_i => clock_i,
NReset_i => nRESET_I,
A_I => LIL,
B_I => lol,
D_I => ioi,
C_i => iil,
CIN_I => oli,
CDIN_FDBK_SEl_i => "00",
CDOUT_O => open ,
p_o => i0l);
p_mulTADD_COS: muLT_ADDSUB
generic map (G_A_width => c_frac_width+1,
g_B_WIDTH => c_frac_width,
g_d_wIDTH => C_FRAC_WIdth,
g_c_width => G_DATAWIDTH+c_frac_width,
G_CIN_width => 48,
g_p_width => g_datawidtH+C_FRAc_width+1)
port map (clock_i => clock_I,
nreseT_I => NReset_i,
a_i => lil,
B_I => OOL,
D_I => ioi,
C_I => O0l,
CIN_i => OLI,
CDIN_FDbk_sel_i => "00",
cdout_o => open ,
p_o => l0L);
iL0:
process (nreset_i,CLOCK_I)
begin
if (nreset_I = '0') then
l1l <= ( others => '0');
O1L <= ( others => '0');
elsif (rising_edge(clock_i)) then
l1l <= I0L(23 downto 8);
o1l <= L0L(23 downto 8);
end if;
end process IL0;
SIN_O <= l1l;
COS_O <= o1l;
oi0:
if (l /= 0)
generate
lI0:
process (nreset_I,CLOCK_i)
begin
if (NRESET_i = '0') then
OII <= ( others => ( others => '0'));
elsif (rising_edge(clock_i)) then
oii <= STD_logic_vector(tO_UNSIGNED(i,
G_num_channels_width))&OII(1 to l-1);
end if;
end process LI0;
CHAN_o <= OII(l);
end generate OI0;
II0:
if (L = 0)
generate
CHAN_O <= Std_logic_vector(TO_UNSigned(I,
g_num_channels_widTH));
end generate II0;
end O;
