library ieee;
use ieee.std_logic_1164.all;
use IEEE.numERIC_STD.all;
entity round_sat is
generic (g_unrnd_data_width: POSITIVE := 33;
g_rnd_data_widtH: POSITIVE := 16;
g_unrnd_fract_bits: POSITIVE := 30;
g_rnd_fract_bits: positive := 15); port (clock_i: in STD_LOGIC;
nreset_i: in STD_LOGIC;
data_i: in std_logic_vector(g_unrnd_data_width-1 downto 0);
data_o: out STD_LOGIC_Vector(g_rnd_data_width-1 downto 0));
end ROUND_sat;

architecture O of ROUND_Sat is

constant OLLL: std_logic_vector(g_rnd_fraCT_BITS-1 downto 0) := ( others => '1');

constant LLLL: std_logic_vector(g_rnd_fract_bits-1 downto 0) := ( others => '0');

constant illl: STD_LOGIC_Vector(g_unrnd_frACT_BITS-g_rnd_fracT_BITS-2 downto 0) := ( others => '0');

constant OILL: std_logic_vector(g_unrnd_data_width-2 downto G_UNRnd_fract_bits) := ( others => '0');

constant lill: STD_LOGIC_VECTOR(G_UNRND_DATA_WIDTH-2 downto G_UNRND_FRACT_BITS) := ( others => '1');

signal iill: std_logic;

signal o0lL: std_logic;

signal l0ll: STd_logic;

signal I0Ll: STD_LOGIC;

begin
O0LL <= DAta_i(G_UNRND_DATA_width-1);
i0ll <= '0' when (DATA_I(G_unrnd_fract_bits-G_RND_FRACT_bits-2 downto 0) = illl and O0LL = '1') else
(data_i(g_unrnd_fract_bits-g_rnd_fract_bits-1));
l0ll <= '0' when ((data_i(G_UNRND_DATA_WIdth-1) = '0' and DATA_I(g_unrnd_data_wiDTH-2 downto G_unrnd_fract_bits) = oill) or (data_i(G_unrnd_data_width-1) = '1' and data_i(g_unrnd_data_width-2 downto G_UNRND_FRACT_bits) = LILL)) else
'1';
IILL <= '1' when (((O0Ll&data_i(G_UNRND_FRACt_bits-1 downto G_Unrnd_fract_bits-G_RND_FRACT_BITS)) = ('0'&OLLL)) or L0LL = '1') else
'0';
o1ll:
process (NRESET_I,clocK_I)
begin
if (nreset_i = '0') then
daTA_O <= ( others => '0');
elsif (Rising_edge(CLOCK_I)) then
if (Iill = '1') then
if (O0LL = '0') then
DATA_O <= '0'&olll;
else
data_o <= '1'&llll;
end if;
else
data_o <= STD_LOGIC_VECTOR(signed(data_i(G_UNRNd_fract_bits downto g_unrnd_fract_bits-G_RND_FRACT_BITS))+Signed(llll&i0ll));
end if;
end if;
end process o1ll;
end O;
