///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: CPRI_LPBCK.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::PolarFire> <Die::MPF300TS_ES> <Package::FCG1152>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

//`timescale <time_units> / <precision>

module CNTRL_LPBCK #(
//-----------------------------------------------------------------------------
// top-level parameters
//-----------------------------------------------------------------------------
//Config Mode = 0, CPRI COre is configured in slave mode
//COnfig Mode = 1, CPRI Core is configured in master mode
//parameter CONFIG_MODE = 0,
parameter no_of_AxC  = 1,
parameter data_width  = 32
)( 
input wire  [no_of_AxC-1:0]             axc_tx_clk,
input wire  [no_of_AxC-1:0]             axc_tx_resetn,  
input wire  [no_of_AxC-1:0]             axc_rx_clk,
input wire  [no_of_AxC-1:0]             axc_rx_resetn,               
//Signals to & from the transmitter interface
input wire  [no_of_AxC-1:0]             tx_req_in,
output wire [data_width*no_of_AxC-1:0]  data_o,
output reg  [no_of_AxC-1:0]             data_tx_valid,

//Signals to & from the reciever interface
output reg  [no_of_AxC-1:0]             rx_req_o,
input  wire [data_width*no_of_AxC-1:0]  data_i,
input  wire [no_of_AxC-1:0]             data_rx_valid
);

//---------------------------------------
//-----Signal Declaration----------------
//---------------------------------------
reg [no_of_AxC*10-1:0] raddr;
reg [no_of_AxC*10-1:0] waddr;

//---------------------------------------
//-----Logic Starts Here-----------------
//---------------------------------------
genvar i;

generate

for (i=0; i< no_of_AxC; i=i+1) begin 

//Iand Q Data is recived from the DUC and DDC blocks by this blocks
//This data is then interleaved in I0Q0I1Q1 format and is transmitted out of
//this block
	//
//cdcfifo
 //#(
////----Parameters----
  //.ADDR_WIDTH (IQ_buffer_depth),
  //.DATA_WIDTH (data_width)
//) fifo_lpbck
//(
   //.k_lim    (9'd511),
   //.wrrstn   (CPRI_RESETN),
   //.wrsrst   (1'b0),
   //.wrclk    (CPRI_CLK),
   //.wrreq    (wrreq[i]),
   //.wrdata   (wdata[i]),
   //.wrfull   (wrfull[i]),
   //.wrusedw  (/*wrusedw[i]*/),
   //.rdrstn   (axc_rx_resetn[i]),
   //.rdclk    (axc_rx_clk[i]),
   //.rdsrst   (1'b0),
   //.rdreq    (rdreq[i]),
   //.rddata   (axc_deinterleave_data[i]),
   //.rdempty  (rdempty[i]),
   //.rdusedw  (rdusedw[i])
//);

//lpckram#(
 //.ADDR_WIDTH(10),
 //.DATA_WIDTH(32)
//)u_buff_lpbk( 
   //.data(data_i[32*i +31 : 32*i]), 
   //.wren(data_rx_valid[i]), 
   //.wraddress(waddr[10*i +9 : 10*i]), 
   //.rdaddress(raddr[10*i +9 : 10*i]), 
   //.wrclock(axc_rx_clk[i]), 
   //.rdclock(axc_tx_clk[i]), 
//   //.q(data_o[32*i +31 : 32*i]));


BUFFER_LPBCK u_buff_lpbk (
    // Inputs
    .R_ADDR(raddr[10*i +9 : 10*i]),
    .R_CLK (axc_tx_clk[i]),
    .R_EN  (tx_req_in[i]),
    .W_ADDR(waddr[10*i +9 : 10*i]),
    .W_CLK (axc_rx_clk[i]),
    .W_DATA(data_i[32*i +31 : 32*i]),
    .W_EN  (data_rx_valid[i]), 
    // Outputs
    .R_DATA (data_o[32*i +31 : 32*i])
);

always @(posedge axc_tx_clk[i] or negedge axc_tx_resetn[i])
begin
  if (!axc_tx_resetn[i]) begin
    raddr [10*i +9 : 10*i]  <= {10{1'b0}};
  end
  else if (tx_req_in[i]) begin
    raddr [10*i +9 : 10*i]  <= raddr [10*i +9 : 10*i]  + 1'b1;
  end
end


always @(posedge axc_rx_clk[i] or negedge axc_rx_resetn[i])
begin
  if (!axc_rx_resetn[i]) begin
    waddr [10*i +9 : 10*i]  <= {10{1'b0}};
  end
  else if (data_rx_valid[i]) begin
    waddr [10*i +9 : 10*i]  <= waddr [10*i +9 : 10*i]  + 1'b1;
  end
end

always @(posedge axc_tx_clk[i] or negedge axc_tx_resetn[i])
begin
  if (!axc_tx_resetn[i]) begin
    data_tx_valid [i]  <= {10{1'b0}};
  end
  else begin
    data_tx_valid [i]  <= tx_req_in[i];
  end
end


always @(posedge axc_rx_clk[i] or negedge axc_rx_resetn[i])
begin
  if (!axc_rx_resetn[i]) begin
    rx_req_o [i]  <= {1{1'b0}};
  end
  else begin
    rx_req_o [i]  <= 1'b1;
  end
end



end
endgenerate
endmodule

