library ieee;
use ieee.STD_LOgic_1164.all;
use iEEE.numeric_std.all;
use ieee.STd_logic_signed.all;
entity complex_MULT is
generic (g_awidth: INTEGER := 16;
G_BWIDTH: INTEGEr := 16;
g_cwidth: inTEGER := 16); port (clock_i: in STD_LOGIC;
nreset_i: in STD_LOGIC;
areal_i: in STD_LOGIC_VECTOR(g_awidth-1 downto 0);
AIMAG_I: in std_logic_vector(g_awidth-1 downto 0);
BREal_i: in std_logic_vectOR(G_BWIDTH-1 downto 0);
bimag_i: in STD_LOGIC_VECtor(g_bwidth-1 downto 0);
creal_o: out STD_LOGIc_vector(G_CWIDTH-1 downto 0);
CIMAG_O: out std_logic_vector(g_cwidtH-1 downto 0));
end COMPLEX_mult;

architecture O of complex_mult is

attribute syn_preserve: boolean;

attribute syn_pRESERVE of o: architecture is tRUE;

signal ii1: SIGNED(G_AWIDTH-1 downto 0);

signal o01: SIGNED(g_awidth-1 downto 0);

signal L01: signed(g_bwidth-1 downto 0);

signal I01: signed(G_BWIDTH-1 downto 0);

signal o11: STD_LOGIC_VECTOR(47 downto 0);

signal L11: std_logic_VECTOR(47 downto 0);

signal i11: std_logic_vector(g_awiDTH+g_bwidth-1 downto 0);

signal OOOL: std_loGIC_VECTOR(G_AWIDth+G_BWIDTH-1 downto 0);

signal LOOL: STD_LOGIC_Vector(G_CWIDTH-1 downto 0);

signal ioOL: STD_LOGIC_VECtor(g_CWIDTH-1 downto 0);

signal OLOL: std_logic_vector(47 downto 0);

signal llol: STD_logic_vector(47 downto 0);

signal ILOL: STD_LOGic_vector(17 downto 0);

signal OIOL: std_logic_vECTOR(17 downto 0);

signal LIOL: std_logic_veCTOR(17 downto 0);

signal iiol: STD_LOgic_vector(17 downto 0);

signal O0OL: STD_LOGIC_VECTOR(17 downto 0);

signal l0ol: STD_logic_vector(17 downto 0);

signal i0ol: STD_LOGIC_VECTOR(17 downto 0);

signal o1OL: std_logic_vector(17 downto 0);

signal l1ol: STD_logic_vector(17 downto 0);

signal I1OL: std_logic_vector(17 downto 0);

signal ooll: STD_Logic_vector(17 downto 0);

signal loll: STD_LOGIC_VECTOR(17 downto 0);

component macc_pa
port (A: in STD_LOGIC_VECTOR(17 downto 0);
AL_N: in STD_LOGIC;
arshft17: in std_logic;
arshft17_ad_n: in std_logic;
ARSHFT17_BYPASS: in STD_LOGIC;
ARSHFT17_en: in STD_LOGIC;
ARSHFT17_SD_N: in STD_LOGIC;
ARSHFT17_SL_N: in STD_LOGIC;
a_bypass: in std_logic;
A_EN: in std_logic;
A_SRSt_n: in STD_LOGIC;
B: in std_lOGIC_VECTOR(17 downto 0);
b_bypass: in STD_LOGic;
B_EN: in STD_LOGIC;
B_SRST_N: in std_lOGIC;
C: in STD_Logic_vector(47 downto 0);
CARRYIN: in STD_LOGIC;
CDIN: in STD_logic_vector(47 downto 0);
cdin_fdbk_sel: in STD_LOGIc_vector(1 downto 0);
cdin_fdbk_sel_ad_n: in STD_LOGIC_VECtor(1 downto 0);
cdin_fdbk_sel_bypass: in STD_LOGIC;
cDIN_FDBK_SEL_EN: in std_logic;
cdin_fdbk_sel_SD_N: in std_logic_vector(1 downto 0);
CDIN_fdbk_sel_sl_n: in std_logic;
clk: in STD_LOGic;
c_aRST_N: in std_logic;
C_BYPASs: in STD_LOGIC;
C_en: in std_logiC;
c_srst_n: in STD_LOGIC;
d: in STD_LOGIC_VECTOR(17 downto 0);
dotp: in STD_LOGIC;
D_ARST_N: in STD_LOGIC;
d_bypass: in STD_LOGIC;
d_en: in std_logic;
D_SRst_n: in STD_LOGIC;
OVFL_CARRYOUT_SEL: in STD_LOGIC;
PASUB: in STD_LOGIC;
pasub_ad_n: in STD_LOGIC;
pasub_bypass: in STD_logic;
PASUB_EN: in std_logic;
PASUB_Sd_n: in STD_LOGIC;
pasub_sl_n: in STD_LOGIC;
p_bypass: in std_lOGIC;
P_EN: in std_logic;
p_srst_n: in STD_LOGIC;
SImd: in STD_LOGIC;
sub: in STD_LOGIC;
SUB_Ad_n: in STD_LOGIC;
SUB_BYPASS: in std_logiC;
SUB_EN: in stD_LOGIC;
SUB_SD_N: in std_logic;
SUB_SL_N: in std_logic;
CDOUT: out std_logic_vecTOR(47 downto 0);
OVFL_CARRYOUT: out STD_LOGIC;
p: out std_lOGIC_VECTOR(47 downto 0));
end component;

component ROUND_SAT
generic (G_Unrnd_data_width: positive := 33;
G_RNd_data_width: positive := 16;
G_UNRND_FRACT_Bits: positive := 30;
g_rnd_fract_bits: positive := 15);
port (CLOCK_I: in std_logic;
nRESET_I: in std_logic;
DATA_I: in STD_logic_vector(g_unrnd_data_WIDTH-1 downto 0);
data_o: out STD_LOGIC_VECTOR(G_rnd_data_width-1 downto 0));
end component rouND_SAT;

begin
ilol <= std_logic_vector(resize(signed(AREAL_i),
18));
IIol <= STD_LOGIC_vector(resize(SIGNED(aimag_i),
18));
I0ol <= std_logic_vector(REsize(SIGNED(breal_i),
18));
i1oL <= std_lOGIC_VECTOR(resize(SIGNED(bimag_i),
18));
IOLL:
process (NREset_i,CLOCK_I)
begin
if (NRESET_I = '0') then
OIOL <= ( others => '0');
o0ol <= ( others => '0');
o1ol <= ( others => '0');
ooll <= ( others => '0');
liol <= ( others => '0');
l0oL <= ( others => '0');
L1OL <= ( others => '0');
LOLL <= ( others => '0');
elsif (rising_edge(Clock_i)) then
OIOL <= ilol;
LIOL <= oiol;
O0OL <= IIOl;
l0ol <= o0ol;
O1OL <= i0ol;
l1ol <= o1ol;
OOLL <= I1OL;
LOLL <= OOll;
end if;
end process ioll;
llol <= ( others => '0');
macc_pa_0: MACC_pa
port map (A => ilol,
al_n => '1',
ARSHFT17 => '0',
ARSHFT17_AD_n => '1',
arshft17_bypass => '1',
ARSHFT17_EN => '0',
arshft17_sd_n => '1',
arshft17_sl_n => '1',
A_bypass => '0',
a_en => '1',
A_SRST_N => NRESET_I,
B => i0ol,
b_bypass => '0',
B_EN => '1',
b_srst_n => NRESET_I,
C => LLOL,
carryin => '0',
CDIN => LLol,
CDIN_fdbk_sel => "00",
CDIN_FDBK_SEL_AD_N => "11",
CDIN_FDBK_SEL_bypass => '0',
CDIN_FDBK_SEL_en => '1',
cdin_fdbk_sel_sd_N => "11",
CDIN_FDBK_SEL_sl_n => '1',
CLK => clock_i,
c_arst_n => nreset_i,
c_bypass => '0',
c_en => '1',
C_SRST_n => Nreset_i,
d => i1ol,
DOTP => '0',
D_ARST_n => '1',
D_BYPASS => '0',
d_en => '1',
D_SRST_n => nreset_i,
OVFL_CARRYOUt_sel => '0',
PASUB => '0',
pasub_ad_n => '1',
PASUb_bypass => '0',
PASUB_En => '1',
pASUB_SD_N => '1',
paSUB_SL_N => '1',
P_Bypass => '0',
P_EN => '1',
p_srst_n => nreSET_I,
simd => '0',
SUB => '0',
sub_ad_n => '1',
sub_bypASS => '1',
sub_en => '0',
SUB_SD_N => '1',
SUB_SL_N => '1',
cdout => open ,
ovfl_carryoUT => open ,
p => olol);
MACC_PA_1: macc_PA
port map (a => loll,
al_n => '1',
arshft17 => '0',
ARshft17_ad_n => '1',
ARSHFT17_BYPASs => '1',
ARSHFT17_en => '0',
ARSHFt17_sd_n => '1',
arshft17_sl_n => '1',
A_BYPASS => '0',
a_en => '1',
A_SRST_N => NRESET_I,
B => L0OL,
B_BYPASS => '0',
b_en => '1',
b_srst_n => nreset_i,
c => olol,
carryin => '0',
cDIN => llol,
cdin_fdbk_sel => "00",
cdin_fdbk_sel_ad_n => "11",
cdin_fdBK_SEL_BYPASS => '0',
cdin_fdbk_sel_en => '1',
cdin_fdbk_sel_SD_N => "11",
cdin_fdbk_sel_sl_n => '1',
clk => clock_i,
c_arst_n => NRESET_I,
C_BYPASS => '0',
C_EN => '1',
c_srst_n => nreset_i,
D => liol,
dotp => '0',
D_arst_n => '1',
D_BYPASS => '0',
d_en => '1',
D_SRST_N => NRESEt_i,
ovfl_carryout_sel => '0',
PASUB => '0',
PASUB_AD_N => '1',
pasub_bypass => '0',
PASUB_EN => '1',
pasuB_SD_N => '1',
pasub_sl_n => '1',
P_BYPASS => '0',
p_en => '1',
p_srst_n => NRESET_I,
SIMD => '0',
SUB => '1',
sub_ad_n => '1',
suB_BYPASS => '0',
sub_en => '1',
sub_sd_n => '1',
SUB_SL_N => '1',
cdout => open ,
oVFL_CARRYOUT => open ,
P => o11);
macc_pa_2: macc_pa
port map (a => L1OL,
al_n => '1',
ARShft17 => '0',
arshft17_ad_n => '1',
ARSHFT17_BYPASS => '1',
ARSHFT17_EN => '0',
ARSHFT17_SD_N => '1',
arshft17_SL_N => '1',
A_BYPASS => '0',
a_en => '1',
A_SRST_N => nreset_i,
b => L0OL,
B_bypass => '0',
B_EN => '1',
B_SRST_N => nreset_i,
c => OLOL,
carryin => '0',
cdin => LLOL,
CDin_fdbk_sel => "00",
cdin_fdbk_sel_ad_n => "11",
cdin_FDBK_SEL_BYPASs => '0',
CDIN_FDBK_SEL_EN => '1',
cdin_fdbk_sel_sd_n => "11",
CDIN_FDBk_sel_sl_n => '1',
clk => CLOCK_i,
c_arst_n => NRESET_i,
c_bypass => '0',
C_EN => '1',
C_srst_n => NRESET_I,
D => liol,
dotp => '0',
d_arst_n => '1',
d_bypass => '0',
d_en => '1',
D_Srst_n => NRESET_I,
ovfl_carryout_sEL => '0',
PASUB => '1',
PASub_ad_n => '1',
PASUB_BYPAss => '0',
PASUB_EN => '1',
pasub_sd_n => '1',
PASUB_SL_N => '1',
p_bypass => '0',
P_EN => '1',
p_SRST_N => nreset_i,
simd => '0',
SUB => '0',
SUB_AD_N => '1',
SUB_BYPASS => '1',
Sub_en => '0',
sub_sd_n => '1',
suB_SL_N => '1',
CDOUT => open ,
ovfl_carryout => open ,
P => l11);
i11 <= stD_LOGIC_VECTOR(Resize(signed(o11),
g_awidth+G_bwidth));
OOOL <= std_logic_vector(RESIZE(SIGNED(L11),
g_awidth+G_BWIDTH));
u_round_sat_creal: round_sat
generic map (g_unrnd_data_width => g_awidth+g_bwidth,
g_rnd_daTA_WIDTH => g_cwidth,
g_UNRND_FRACT_BITS => G_awidth+g_bwidth-2,
g_rnd_fract_bitS => g_cwidth-1)
port map (clock_I => CLOCK_I,
NRESET_I => nreSET_I,
data_i => i11,
Data_o => lool);
U_ROUNd_sat_cimag: ROUND_SAT
generic map (G_UNRND_DATA_WIDTH => g_AWIDTH+G_BWIDTH,
G_RND_DATA_width => G_Cwidth,
g_unrnd_fract_bits => g_awidth+G_BWIDTH-2,
g_rnd_fract_bits => G_cwidth-1)
port map (CLOCK_i => clock_i,
NRESET_I => nreset_i,
data_i => OOOl,
DATA_O => IOOL);
crEAL_O <= LOOL;
CIMAG_O <= Iool;
end;
