# Creating SmartDesign "MiV_SUBSYSTEM"
set sd_name {MiV_SUBSYSTEM}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {HREADYOUT_S7} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRLR_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HCLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HMASTLOCK_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HREADY_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HSEL_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HWRITE_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS1_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {HRDATA_S7} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HRESP_S7} -port_direction {IN} -port_range {[1:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[14:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HADDR_S7} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HBURST_S7} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPROT_S7} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HSIZE_S7} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HTRANS_S7} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HWDATA_S7} -port_direction {OUT} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[15:0]} -port_is_pad {1}

# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AHBmslave7} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"HADDR:HADDR_S7" \
"HTRANS:HTRANS_S7" \
"HWRITE:HWRITE_S7" \
"HSIZE:HSIZE_S7" \
"HBURST:HBURST_S7" \
"HPROT:HPROT_S7" \
"HWDATA:HWDATA_S7" \
"HSELx:HSEL_S7" \
"HMASTLOCK:HMASTLOCK_S7" \
"HRDATA:HRDATA_S7" \
"HREADY:HREADY_S7" \
"HREADYOUT:HREADYOUT_S7" \
"HRESP:HRESP_S7" } 

# Add CCC_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_0} -instance_name {CCC_0}



# Add CoreAHBLite0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBLite0} -instance_name {CoreAHBLite0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBLite0_0:REMAP_M0} -value {GND}



# Add COREAHBTOAPB30_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB30} -instance_name {COREAHBTOAPB30_0}



# Add CoreAPB3_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0_0}



# Add COREAXI4_INTERCONNECT_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAXI4_INTERCONNECT} -instance_name {COREAXI4_INTERCONNECT_0}



# Add coregpio_inout_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {coregpio_inout} -instance_name {coregpio_inout_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {coregpio_inout_0:INT}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {coregpio_inout_0:GPIO_IN} -value {GND}



# Add CoreJTAGDebug_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0_0}



# Add CORERESET_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {CORERESET_PF_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:FF_US_RESTORE} -value {GND}



# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}



# Add CoreUARTapb0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb0} -instance_name {CoreUARTapb0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb0_0:TXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb0_0:RXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb0_0:PARITY_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb0_0:OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb0_0:FRAMING_ERR}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}



# Add PF_DDR3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DDR3_C0} -instance_name {PF_DDR3_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DDR3_C0_0:PLL_LOCK}



# Add PF_Init_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_Init} -instance_name {PF_Init_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_Init_0:AUTOCALIB_DONE}



# Add SPI_Controller_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {SPI_Controller} -instance_name {SPI_Controller_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_0:SPISS} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_0:SPISS} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_0:SPISS} -pin_slices {[7:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPISS[7:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPIINT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPIRXAVAIL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPITXRFM}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPISSI} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPICLKI} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPIOEN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_0:SPIMODE}



# Add SPI_Controller_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {SPI_Controller} -instance_name {SPI_Controller_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[0:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[4:4]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[6:6]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SPI_Controller_1:SPISS} -pin_slices {[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISS[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPIINT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPIRXAVAIL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPITXRFM}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPISSI} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPICLKI} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPIOEN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SPI_Controller_1:SPIMODE}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "PF_DDR3_C0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0:OUT0_FABCLK_0" "COREAHBTOAPB30_0:HCLK" "COREAXI4_INTERCONNECT_0:ACLK" "CORERESET_PF_C0_0:CLK" "CORERESET_PF_C1_0:CLK" "CoreAHBLite0_0:HCLK" "CoreUARTapb0_0:PCLK" "HCLK" "MIV_RV32_C0_0:CLK" "PF_DDR3_C0_0:PLL_REF_CLK" "SPI_Controller_0:PCLK" "SPI_Controller_1:PCLK" "coregpio_inout_0:PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0:PLL_LOCK_0" "CORERESET_PF_C0_0:PLL_LOCK" "CORERESET_PF_C1_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0:PLL_POWERDOWN_N_0" "CORERESET_PF_C0_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0:REF_CLK_0" "REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "PF_DDR3_C0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "PF_DDR3_C0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "PF_DDR3_C0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB30_0:HRESETN" "COREAXI4_INTERCONNECT_0:ARESETN" "CORERESET_PF_C0_0:FABRIC_RESET_N" "CoreAHBLite0_0:HRESETN" "CoreUARTapb0_0:PRESETN" "MIV_RV32_C0_0:RESETN" "PRESETN" "SPI_Controller_0:PRESETN" "SPI_Controller_1:PRESETN" "coregpio_inout_0:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4_INTERCONNECT_0:S_CLK0" "PF_DDR3_C0_0:SYS_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:BANK_x_VDDI_STATUS" "CORERESET_PF_C0_0:BANK_y_VDDI_STATUS" "CORERESET_PF_C1_0:BANK_x_VDDI_STATUS" "CORERESET_PF_C1_0:BANK_y_VDDI_STATUS" "PF_Init_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:EXT_RST_N" "CTRLR_READY" "PF_DDR3_C0_0:CTRLR_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:FPGA_POR_N" "CORERESET_PF_C1_0:FPGA_POR_N" "PF_Init_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:INIT_DONE" "CORERESET_PF_C1_0:INIT_DONE" "DEVICE_INIT_DONE" "PF_Init_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:FABRIC_RESET_N" "PF_DDR3_C0_0:SYS_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "PF_DDR3_C0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb0_0:RX" "RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb0_0:TX" "TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "PF_DDR3_C0_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR3_C0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR3_C0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR3_C0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR3_C0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR3_C0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISCLKO0" "SPI_Controller_0:SPISCLKO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISCLKO1" "SPI_Controller_1:SPISCLKO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISDI0" "SPI_Controller_0:SPISDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISDI1" "SPI_Controller_1:SPISDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISDO0" "SPI_Controller_0:SPISDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISDO1" "SPI_Controller_1:SPISDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISS0_0" "SPI_Controller_0:SPISS[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISS0_1" "SPI_Controller_0:SPISS[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SPISS1_0" "SPI_Controller_1:SPISS[2:2]" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "PF_DDR3_C0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "PF_DDR3_C0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM" "PF_DDR3_C0_0:DM" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "PF_DDR3_C0_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "PF_DDR3_C0_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "PF_DDR3_C0_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "coregpio_inout_0:GPIO_OUT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHBmslave7" "CoreAHBLite0_0:AHBmslave7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB30_0:AHBslave" "CoreAHBLite0_0:AHBmslave6" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB30_0:APBmaster" "CoreAPB3_0_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4_INTERCONNECT_0:AXI4mmaster0" "MIV_RV32_C0_0:AXI4_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4_INTERCONNECT_0:AXI4mslave0" "PF_DDR3_C0_0:AXI4slave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite0_0:AHBmmaster0" "MIV_RV32_C0_0:AHBL_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave0" "CoreUARTapb0_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave1" "coregpio_inout_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave2" "SPI_Controller_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave3" "SPI_Controller_1:APB_bif" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "MiV_SUBSYSTEM"
generate_component -component_name ${sd_name}
