library IEEE;
use ieee.STD_LOGIC_1164.all;
use ieeE.numeric_std.all;
use ieee.std_logic_signed.all;
library polarfire;
use polarfire.all;
entity mult_addsub is
generic (G_A_width: integer := 16;
G_B_WIDTH: Integer := 16;
g_d_width: integer := 16;
g_c_width: INTEGER := 37;
G_CIN_WIDTH: integer := 37;
G_P_width: INTEGEr := 37); port (cLOCK_I: in stD_LOGIC;
nreset_i: in STD_logic;
A_I: in std_logic_vector(G_A_WIDTH-1 downto 0);
b_i: in sTD_LOGIC_VECTOR(g_b_width-1 downto 0);
d_i: in STD_LOgic_vector(g_d_width-1 downto 0);
C_I: in std_logic_vector(g_c_width-1 downto 0);
CIN_I: in STD_LOGic_vector(g_cin_width-1 downto 0);
CDIN_FDBK_Sel_i: in std_logic_vectOR(1 downto 0);
CDOUT_O: out STD_LOGIC_vector(47 downto 0);
p_o: out std_logic_vector(G_p_width-1 downto 0));
end mult_adDSUB;

architecture L00i of mulT_ADDSUB is

constant i00i: integer := 18;

constant o1il: INTEGER := 48;

signal a: STD_logic_vector(17 downto 0);

signal AL_N: STD_LOGIC;

signal ARSHFT17: STD_LOGIC;

signal arshft17_ad_n: std_logic;

signal arshft17_bypass: std_logic;

signal ARSHFT17_EN: STD_LOGIC;

signal arshft17_sd_n: std_logic;

signal arshft17_sl_n: Std_logic;

signal A_BYPASS: sTD_LOGIC;

signal A_EN: STD_LOGIC;

signal a_SRST_N: std_logic;

signal b: STD_LOGIC_VEctor(17 downto 0);

signal B_BYPASS: STD_LOGIC;

signal b_en: std_logic;

signal B_SRST_n: STD_logic;

signal C: std_logic_VECTOR(47 downto 0);

signal carryin: STD_logic;

signal CDin: std_logic_vectOR(47 downto 0);

signal cdin_fdbK_SEL: std_logic_vector(1 downto 0);

signal cdin_fdbk_sel_ad_n: std_logic_vector(1 downto 0);

signal CDIn_fdbk_sel_bypass: std_loGIC;

signal cdin_fdbk_sEL_EN: std_logiC;

signal cdin_fdbK_SEL_SD_N: std_logic_vector(1 downto 0);

signal CDIN_fdbk_sel_sl_n: std_logic;

signal CLK: std_logic;

signal C_ARST_N: STD_LOGIC;

signal c_bypass: STD_LOGIC;

signal c_en: std_logic;

signal C_SRST_N: STD_LOGIC;

signal DOTP: sTD_LOGIC;

signal d: std_logic_VECTOR(17 downto 0);

signal D_ARST_N: STD_LOGIC;

signal d_bypass: std_logiC;

signal D_en: STD_LOGIC;

signal d_srst_n: std_logic;

signal ovfl_carryout_sel: stD_LOGIC;

signal pasub: std_logic;

signal PASUb_ad_n: STd_logic;

signal PASUB_BYPASS: STD_LOGIC;

signal pasub_en: std_logic;

signal PASUB_SD_N: STD_LOGIC;

signal pasub_sl_n: std_logic;

signal P_BYPASS: std_logic;

signal P_EN: std_logIC;

signal P_SRSt_n: STD_LOGIC;

signal simd: std_logic;

signal sUB: std_logic;

signal SUB_AD_N: STD_LOGIC;

signal sub_bypASS: std_logic;

signal SUB_EN: STD_LOGIC;

signal sub_sd_n: STd_logic;

signal sUB_SL_N: std_logic;

signal Cdout: std_logic_VECTOR(47 downto 0);

signal O10I: std_logic_vecTOR(47 downto 0);

component MACC_PA
port (A: in STD_LOGIC_VEctor(17 downto 0);
al_n: in std_logic;
arshft17: in std_logic;
arshft17_ad_n: in std_logic;
arshft17_bypass: in std_logic;
arshft17_en: in std_logic;
ARshft17_sd_n: in STD_LOGic;
ARSHFT17_sl_n: in std_logic;
a_bypass: in STD_LOgic;
A_EN: in std_logic;
a_srst_n: in STD_LOGIC;
B: in STD_LOGIC_VECTOR(17 downto 0);
b_bypass: in STD_LOGIC;
B_EN: in std_logic;
b_srst_n: in std_logic;
c: in STD_LOgic_vector(47 downto 0);
CARRYIN: in std_logic;
cdin: in STD_logic_vector(47 downto 0);
cdin_fdbk_sel: in STD_logic_vector(1 downto 0);
cdin_fdbk_sel_ad_n: in std_logic_vector(1 downto 0);
CDIn_fdbk_sel_bypass: in std_logic;
cdin_fdbk_sel_en: in std_logic;
cdin_fdbk_sel_sd_n: in STD_LOGIC_vector(1 downto 0);
cdin_fdbk_sel_sl_n: in std_logic;
CLK: in std_logic;
C_ARST_N: in STD_LOGIC;
c_bypass: in STD_LOGIC;
c_en: in STD_LOGIc;
c_srsT_N: in std_logic;
D: in STD_logic_vector(17 downto 0);
dotp: in STD_LOGIC;
d_ARST_N: in std_logic;
D_BYpass: in STD_LOGIC;
D_en: in std_logic;
D_SRST_N: in stD_LOGIC;
ovfl_carryout_seL: in std_logic;
pasub: in STD_LOGIC;
PASUB_AD_N: in std_logic;
PASUB_BYPASS: in std_loGIC;
PASUB_EN: in std_logIC;
PASUB_SD_N: in std_LOGIC;
pasub_sl_n: in STD_LOGIC;
P_bypass: in STD_LOGIC;
P_EN: in std_logiC;
P_SRST_N: in std_logic;
simd: in STD_LOGic;
sub: in STD_LOGIC;
SUb_ad_n: in std_loGIC;
SUB_BYPass: in STD_LOGIC;
Sub_en: in stD_LOGIC;
SUB_SD_N: in std_logic;
SUB_SL_N: in std_logic;
CDOUT: out std_logic_vector(47 downto 0);
ovfl_carryout: out std_logic;
P: out STD_LOGIC_VECTOR(47 downto 0));
end component;

begin
clk <= clock_i;
simd <= '0';
dotp <= '0';
A <= std_logic_vector(resize(signed(A_I),
i00i));
B <= STD_LOGIC_VEctor(rESIZE(signed(b_i),
i00i));
D <= std_LOGIC_VECTOR(resize(SIGNED(d_i),
i00i));
C <= STD_LOGIC_VECTOR(resize(SIGNED(C_I),
O1IL));
cdin <= std_logic_vector(RESIZE(signed(ciN_I),
O1IL));
OVFl_carryout_sel <= '0';
carryin <= '0';
A_Bypass <= '0';
B_BYPASS <= '0';
D_BYPASS <= '0';
p_bypass <= '0';
C_BYPASs <= '0';
AL_N <= '1';
c_arst_n <= nreset_i;
d_arst_n <= nreset_i;
a_srst_n <= nreset_i;
b_srst_n <= nreset_i;
d_srst_n <= NRESEt_i;
p_srst_n <= NRESET_i;
C_SRST_N <= nreSET_I;
a_en <= '1';
b_en <= '1';
d_en <= '1';
P_en <= '1';
C_en <= '1';
arshft17 <= '0';
ARshft17_bypass <= '1';
arshft17_sl_n <= '1';
arshft17_ad_n <= '1';
ARSHFT17_sd_n <= '1';
ARSHFT17_EN <= '1';
cdin_fdbk_sel <= cdin_fdbk_sel_I;
CDIn_fdbk_sel_ad_n <= "11";
cdIN_FDBK_SEL_BYPASS <= '0';
cdin_fdbk_sel_en <= '1';
CDIN_FDBK_SEL_SD_N <= "11";
CDIN_fdbk_sel_sl_n <= '1';
pasub <= '0';
PASUB_ad_n <= '1';
PASUB_BYPASS <= '0';
PASUb_en <= '1';
pasub_sd_n <= '1';
PASUB_SL_N <= '1';
SUB <= '0';
sub_bypass <= '1';
sub_sl_n <= '1';
sub_ad_N <= '1';
sub_sD_N <= '1';
SUB_EN <= '1';
MACC_PA_0: MACC_PA
port map (a => a,
al_n => AL_N,
ARSHFT17 => Arshft17,
arshft17_ad_n => arshfT17_AD_N,
ARSHFT17_bypass => arshfT17_BYPASS,
ARSHFT17_EN => arshft17_en,
arshft17_sd_n => aRSHFT17_SD_N,
arshft17_sl_n => ARSHFT17_SL_N,
A_BYPass => a_bypaSS,
A_EN => a_en,
a_srst_n => A_SRST_N,
B => B,
B_BYPASS => B_BYPASS,
B_En => b_en,
B_srst_n => b_srst_n,
C => c,
carryin => CARRyin,
cdin => cdin,
cdin_fdbk_SEL => cdin_fdbk_sel,
CDIN_fdbk_sel_ad_n => Cdin_fdbk_sel_ad_n,
CDIN_FDBK_sel_bypass => CDIN_FDBK_SEL_bypass,
CDIN_FDBK_SEL_EN => cdin_fdbk_sel_en,
CDIN_FDBK_SEL_SD_N => cdin_fdbK_SEL_SD_N,
cdin_fdbk_sel_sl_n => CDIN_FDBK_sel_sl_n,
clk => CLK,
C_ARST_n => c_arst_n,
c_bypass => c_bypasS,
c_en => c_en,
c_srst_n => c_srst_n,
d => d,
DOTP => DOTP,
D_ARST_N => D_ARST_N,
D_Bypass => D_Bypass,
D_en => D_EN,
D_SRST_N => D_SRST_n,
ovfl_carryout_sel => OVFL_CARRYOUt_sel,
PASUB => PASUB,
pasub_ad_n => PASUB_AD_N,
PASUB_BYPASs => pasub_bypass,
pasub_en => pasub_en,
PASUB_Sd_n => PAsub_sd_n,
PAsub_sl_n => pasub_sl_n,
p_bypASS => p_BYPASS,
p_en => P_EN,
p_srst_n => p_srst_N,
simd => simd,
sub => Sub,
SUB_AD_N => SUB_AD_N,
SUB_BYPASS => SUB_BYPASS,
SUB_EN => SUB_EN,
SUB_SD_N => SUB_SD_N,
SUB_sl_n => sub_sl_n,
CDOUT => CDout,
OVfl_carryout => open ,
p => O10i);
CDOUT_O <= STd_logic_vector(RESIZE(signed(cdout),
o1il));
P_O <= STD_LOGIC_VEctor(reSIZE(SIGNED(o10I),
G_P_WIDTH));
end l00i;
