library ieee;
use ieee.std_logic_1164.all;
use Ieee.numerIC_STD.all;
use IEEE.Std_logic_unsigned.all;
use ieee.MATH_REAL.all;
use woRK.SYSTEM_PACK.all;
use work.DDC_hb3_dec_coeffpack.all;
entity DDC_HB3_DEC is
port (CLOCK_I: in std_logic;
NRESET_i: in STD_LOGIC;
DATA_vld_i: in STD_LOGIC;
DATA_I: in std_logic_vectoR(G_DATain_width-1 downto 0);
DATA_O: out STD_LOGIC_Vector(G_DATAOUT_WIDTH-1 downto 0);
CHan_i: in stD_LOGIC_VECTOR(G_chan_width-1 downto 0);
CHAN_O: out std_logic_VECTOR(g_chan_width-1 downto 0);
DATA_VLD_O: out std_logiC);
end ddc_hb3_DEC;

architecture o of ddc_hb3_DEC is

attribute syn_preserve: boolean;

attribute SYN_PREserve of O: architecture is TRue;

component DATA_shifter
generic (G_DATa_width: INTEGer := 16;
G_SHIft_delay: INTEGER := 3);
port (clock_i: in STD_logic;
nreset_i: in STD_LOGIC;
shift_EN_I: in STD_logic;
DATA_I: in std_logic_vector((g_datA_WIDTH-1) downto 0);
DATA_O: out std_logic_vector((g_data_width-1) downto 0));
end component;

component mult_addsub is
generic (g_a_WIDTH: integer := 16;
G_B_WIDTH: inTEGER := 16;
g_d_width: INTEGER := 16;
g_c_width: INTEGER := 37;
g_cin_width: INTeger := 37;
g_p_width: INTEGER := 37);
port (clock_I: in std_logic;
nreset_i: in STD_LOGIC;
A_I: in std_logic_vectoR(G_A_WIDTH-1 downto 0);
B_I: in std_logic_veCTOR(G_b_width-1 downto 0);
d_i: in STD_LOGIC_VECTOR(G_D_WIDTH-1 downto 0);
c_i: in sTD_LOGIC_VECTOR(g_c_width-1 downto 0);
cin_i: in std_logic_vector(g_CIN_WIDTH-1 downto 0);
cDIN_FDBK_SEL_I: in std_logic_vectoR(1 downto 0);
CDOUT_O: out STD_logic_vector(G_p_width-1 downto 0);
p_o: out STD_LOGIC_VECTOR(G_P_WIDTH-1 downto 0));
end component;

component MACC_ROM
generic (g_a_WIDTH: integer := 16;
g_b_width: integer := 16;
g_d_width: INTEGEr := 16;
g_c_width: INTEGER := 37;
g_cin_width: INTEGEr := 37;
G_p_width: INTEGER := 37;
g_init: STD_logic_vector(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000");
port (CLOCK_I: in STD_LOGIC;
NRESET_I: in std_logic;
a_i: in std_logiC_VECTOR(G_A_WIDTH-1 downto 0);
b_i: in STD_LOGIC_VECTOR(g_b_width-1 downto 0);
a_rom_adDR_I: in std_logic_VECTOR(3 downto 0);
d_I: in STD_LOGIC_VECTOR(G_D_WIDTH-1 downto 0);
c_i: in STD_LOgic_vector(G_C_WIDth-1 downto 0);
cin_i: in std_logic_vector(G_CIN_WIDTh-1 downto 0);
CDIN_FDbk_sel_i: in STD_LOGIC_VECTOr(1 downto 0);
cDOUT_O: out STD_LOGIC_vector(47 downto 0);
p_o: out STD_LOGIC_vector(G_P_WIDTh-1 downto 0));
end component;

component ROUND_SAT
generic (G_UNRND_DATa_width: posITIVE := 33;
g_rnd_data_wIDTH: positive := 16;
G_unrnd_fract_bits: positiVE := 30;
g_rnd_fract_bits: positive := 15);
port (CLOCK_I: in std_logic;
NRESET_I: in STD_logic;
DATA_I: in std_logiC_VECTOR(g_unrnd_data_wIDTH-1 downto 0);
DATA_O: out STD_LOGIC_VECTOR(g_rnd_data_width-1 downto 0));
end component;

signal l: STD_LOGIC;

signal I: std_logic;

signal ol: STD_LOGIC_VECTOr(G_DATain_width-1 downto 0);

signal LL: std_lOGIC_VECTOR(G_CHAN_WIDTH-1 downto 0);

signal IL: std_logic;

signal oi: STD_LOGIC;

type Li is array (1 to G_numchannels) of std_logic_vector((G_DATAin_width-1) downto 0);

signal II: li;

type o0 is array (1 to G_numchannels+1) of STD_LOGIC_VECtor(0 downto 0);

signal L0: o0;

signal I0: std_logic_vectoR(0 downto 0);

type o1 is array (1 to g_chandelay) of std_logic_vectOR((g_cHAN_WIDTH-1) downto 0);

signal l1: o1;

type I1 is array (1 to G_EVENODDDELAY) of std_logic_vector(0 downto 0);

signal ool: i1;

signal lol: STD_LOGIC_VECTOR(0 downto 0);

signal iol: STD_LOGIC_VECTOR(G_DATAIN_WIDTh-1 downto 0);

signal OLL: std_logic_vector(g_datain_width-1 downto 0);

signal LLL: std_logic_vector(G_datain_width-1 downto 0);

type ILl is array (0 to g_dspcount-1) of STD_LOGIC_VECTOr(0 downto 0);

type OIL is array (1 to G_DSPCOUNT-1) of std_LOGIC_VECTOR(0 downto 0);

signal lIL: OIL;

signal iil: ILL;

type O0L is array (0 to G_DSPCOUNT-1) of std_logIC_VECTOR((G_DATAIN_WIDTH-1) downto 0);

type l0l is array (1 to G_Dspcount-1) of std_LOGIC_VECTOR((g_dataiN_WIDTH-1) downto 0);

signal I0L: L0L;

signal o1l: O0L;

signal l1l: O0L;

signal I1L: O0l;

signal OOI: std_logic;

signal loi: STD_logic_vector(0 downto 0);

signal IOI: std_logic_vector(G_COEFF_WIDTH-1 downto 0);

type OLI is array (0 to g_dspcount-1) of STD_logic_vector((g_accwidth-1) downto 0);

signal LLI: oli;

signal ILI: oli;

type oiI is array (0 to g_dspcount-1) of STD_LOGIC_VECTOR((g_finaladdwidth-1) downto 0);

signal lii: STD_LOGIC_VECTOR(G_ACCWIDTH-1 downto 0);

signal III: Std_logic_vector(G_DATAIN_width-1 downto 0);

signal o0i: STD_LOGIC_VECTOR(g_finalADDWIDTH-1 downto 0);

signal L0I: STD_Logic_vector(G_DATAOUT_WIDTH-1 downto 0);

signal I0I: std_logic_vector(G_DATAIN_WIDTH-1 downto 0);

signal o1i: STD_LOGIC_VECTor(G_DATAIN_WIDTH-1 downto 0);

signal l1i: STD_LOGIC_VECTor(g_finalADDWIDTH-1 downto 0);

begin
i1i:
process (NRESET_I,clock_i)
begin
if (NRESet_i = '0') then
OL <= ( others => '0');
elsif (RISINg_edge(clock_i)) then
OL <= DATA_I;
end if;
end process i1i;
OO0:
process (nreset_i,clock_i)
begin
if (nreset_i = '0') then
l <= '0';
LL <= ( others => '0');
elsif (RISING_Edge(CLOCK_I)) then
l <= data_vld_i;
ll <= CHAN_I;
end if;
end process oo0;
lo0:
process (NREset_i,clock_i)
begin
if (Nreset_i = '0') then
il <= '0';
elsif (rising_edge(CLOCK_I)) then
if (l = '1' and LL = STD_logic_vector(TO_UNSIGNED((G_NUmchannels-1),
g_chan_wIDTH))) then
il <= not (il);
end if;
end if;
end process lo0;
io0:
process (NRESET_I,CLOCk_i)
begin
if (NRESET_I = '0') then
IOL <= ( others => '0');
oll <= ( others => '0');
elsif (rising_edge(CLOCK_i)) then
case IL is
when '1' =>
OLL <= OL;
IOL <= ( others => '0');
when others =>
iOL <= ol;
oll <= ( others => '0');
end case;
end if;
end process IO0;
OL0:
process (NRESET_I,CLOCK_i)
begin
if (nreset_i = '0') then
II <= ( others => ( others => '0'));
elsif (RISING_EDGE(CLOCK_I)) then
ii <= IOL&ii(1 to g_numchANNELS-1);
end if;
end process ol0;
LLL <= ii(g_numCHANNELS);
LL0:
process (NRESET_I,CLOCK_I)
begin
if (NRESEt_i = '0') then
l0 <= ( others => ( others => '0'));
elsif (RISING_EDGE(CLOCK_I)) then
L0 <= I0&l0(1 to g_numchannels);
end if;
end process ll0;
I0(0) <= l;
I <= L0(g_numchannels)(0);
IL0:
for OI0 in 1 to (g_dspCOUNT-1)
generate
begin
p_fwd_delay_shift: data_shifter
generic map (g_data_width => 1,
g_shift_delay => 1)
port map (clock_I => CLOCK_I,
nreset_i => nreset_i,
shift_en_i => '1',
data_i => lil(OI0),
data_o => IIl(Oi0));
end generate IL0;
IIL(0)(0) <= i;
LI0:
for oi0 in 0 to (g_dspcount-2)
generate
begin
LIL(OI0+1) <= IIL(oi0);
end generate LI0;
ii0:
for OI0 in 1 to (G_DSPCOUNT-1)
generate
begin
p_fwd_delay_ram: DATA_SHIFTER
generic map (G_DAta_width => G_datain_width,
G_SHIFT_DELAY => g_chancount+1)
port map (clocK_I => CLOCK_I,
nreset_i => NRESet_i,
SHIFT_EN_i => IIL(OI0)(0),
data_i => I0L(Oi0),
DATA_O => O1L(OI0));
end generate II0;
O1L(0) <= lLL;
O00:
for OI0 in 0 to (g_dspcount-2)
generate
begin
I0L(oi0+1) <= O1L(oi0);
end generate o00;
l1l(0) <= o1l(G_DSPCOUNT-1);
OOI <= iil(G_DSPCOUNT-1)(0);
l00:
if (G_HAS_SYMM = 1)
generate
i00:
if (g_symm = 0)
generate
P_REV_DELAY_RAM_0: DATA_SHIFTER
generic map (g_datA_WIDTH => G_DATAIN_WIDTH,
g_sHIFT_DELAY => 0)
port map (CLOCK_I => CLOCK_i,
nreseT_I => nreset_i,
SHIFT_en_i => ooi,
Data_i => L1L(0),
DATA_O => i1l(0));
end generate i00;
O10:
if (g_symm = 1)
generate
p_rev_delay_ram_0: DATA_SHIFTER
generic map (g_data_width => G_datain_width,
g_shiFT_DELAY => g_chancount)
port map (CLOCK_I => clock_I,
NRESET_i => nreset_i,
shift_en_i => ooi,
data_i => l1l(0),
data_o => i1l(0));
end generate o10;
p_final_delay_shift: DATA_shifter
generic map (g_data_width => 1,
G_SHIFT_delay => (G_DSPCOUNT+3))
port map (CLOCK_I => CLOCK_I,
NReset_i => nreseT_I,
shift_en_i => '1',
data_i => LOI,
DATA_O => open );
loi(0) <= i;
L10:
for oi0 in 1 to (g_dspcount-1)
generate
begin
p_rEV_DELAY_RAM: data_shifter
generic map (G_data_width => G_datain_width,
g_sHIFT_DELAY => g_chancount-1)
port map (CLOCK_I => CLOCK_I,
nresET_I => NRESET_I,
SHIFT_en_i => iil(G_DSPCOUNT-OI0-1)(0),
data_i => l1l(oi0),
DATA_O => I1L(oi0));
end generate l10;
i10:
for oi0 in 0 to (g_dspcount-2)
generate
begin
L1L(OI0+1) <= i1l(OI0);
end generate I10;
end generate L00;
LII <= ( others => '0');
IOI <= ( others => '0');
p_mult_acc0: MACC_Rom
generic map (g_a_WIDTH => g_coeff_width,
G_B_WIDTH => G_datain_width,
G_D_WIDTH => g_dataiN_WIDTH,
G_C_Width => G_ACCWIDTH,
g_cin_width => G_ACCWIDTH,
g_p_width => G_FINALADDWidth,
g_init => G_INIT)
port map (clock_i => clock_i,
Nreset_i => nreset_i,
A_I => ioi,
b_i => O1L(0),
A_ROM_ADDR_I => "0000",
D_I => I1L(g_dspcoUNT-1),
c_i => LII,
CIN_I => ILI(0),
cDIN_FDBK_SEL_I => "00",
cdOUT_O => LLI(0),
P_o => open );
oo1:
for OI0 in 1 to (G_DSPcount-1)
generate
begin
p_MULT_ACC: MACc_rom
generic map (G_A_WIDTH => G_COEFF_WIDTH,
g_b_width => g_datain_width,
g_D_WIDTH => g_datAIN_WIDTH,
g_c_wIDTH => g_accwidth,
G_CIN_width => G_ACCWIDTH,
G_p_width => G_FINALADDwidth,
g_init => G_INIT)
port map (clock_i => clock_i,
nreset_i => nreset_i,
a_i => ioi,
b_i => o1l(OI0),
A_ROM_ADDR_I => std_LOGIC_VECTOR(TO_UNSIGNED(OI0,
4)),
D_I => I1L(G_DSPCOUNT-1-OI0),
c_i => lii,
CIN_I => ILI(oi0),
cDIN_FDBK_SEL_I => "11",
cdout_O => lli(oi0),
p_o => open );
end generate oo1;
lo1:
for oi0 in 0 to (G_DSPCOUNT-2)
generate
begin
ili(OI0+1) <= LLI(oi0);
end generate LO1;
ILI(0) <= ( others => '0');
I0I <= OLL;
P_CENTER_DElay_ram: DATA_SHIFTER
generic map (G_data_width => G_Datain_width,
G_SHIFT_Delay => (g_dsPCOUNT*G_CHANCOUNT)+(G_DSPCOUNT))
port map (CLOCK_I => clock_i,
NRESET_I => nreset_i,
SHIFT_EN_I => '1',
DATA_I => i0I,
daTA_O => o1i);
p_mult_centER: MULT_ADDSUb
generic map (g_a_width => G_COEFF_WIDth,
g_b_widtH => g_datain_wIDTH,
g_d_width => G_DATain_width,
G_C_WIDTH => g_aCCWIDTH,
g_cin_width => g_accwidth,
G_P_WIDTH => G_FINALaddwidth)
port map (CLOCK_I => CLOCK_I,
nresET_I => nreset_i,
A_I => G_CENter_tap,
B_I => O1I,
d_i => III,
C_I => lII,
cin_i => lli(g_dspcount-1),
CDIN_FDBK_SEL_I => "11",
CDOUT_O => open ,
p_o => l1i);
iii <= ( others => '0');
io1:
process (nreset_i,cloCK_I)
begin
if (nreset_i = '0') then
O0I <= ( others => '0');
elsif (rising_edge(CLOCK_I)) then
o0i <= l1i;
end if;
end process IO1;
U_ROUND_SAT: round_sat
generic map (g_unrnd_DATA_WIDTH => G_FINALADdwidth,
G_Rnd_data_width => G_Dataout_width,
g_unrnd_fract_biTS => g_unrnD_FRACWIDTH,
g_rND_FRACT_BITS => G_DATAOUT_FRAcwidth)
port map (CLOCK_I => clock_i,
NRESET_I => NRESET_I,
DATa_i => O0I,
DATA_O => l0i);
ol1:
process (NRESET_I,CLOCK_I)
begin
if (nreset_i = '0') then
L1 <= ( others => ( others => '0'));
CHAN_O <= ( others => '0');
elsif (RISING_EDGE(CLOCK_I)) then
l1 <= LL&L1(1 to g_chandelay-1);
chan_o <= L1(g_chandelay);
end if;
end process oL1;
ll1:
process (NRESET_i,clock_i)
begin
if (nreset_i = '0') then
OOL <= ( others => ( others => '0'));
DATA_VLD_O <= '0';
elsif (rising_edge(CLOCK_I)) then
ooL <= lol&OOL(1 to G_evenodddelay-1);
data_vld_o <= OI;
end if;
end process LL1;
lol(0) <= il;
OI <= ool(g_evenodddelay)(0);
data_o <= l0i;
end o;
