library Ieee;
use ieee.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.std_logic_signed.all;
library polarfire;
use POLARfire.all;
entity macc_rom is
generic (G_A_WIDTH: integer := 16;
g_b_wIDTH: INTEGER := 16;
g_d_width: integer := 16;
g_C_WIDTH: INTEGER := 37;
G_CIN_WIDth: integer := 37;
g_p_width: integer := 37;
g_init: std_logic_vector(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000"); port (clock_i: in std_logic;
NRESET_I: in STD_LOGIC;
A_I: in std_logic_vector(g_a_width-1 downto 0);
B_I: in std_logic_vECTOR(g_b_wiDTH-1 downto 0);
a_rOM_ADDR_I: in std_logic_vector(3 downto 0);
d_I: in STD_LOGIC_VECTOR(G_D_WIDTH-1 downto 0);
c_i: in STD_LOGIC_VECTOR(G_c_width-1 downto 0);
cin_i: in STD_LOGic_vector(g_cin_width-1 downto 0);
cDIN_FDBK_SEL_I: in std_logic_vector(1 downto 0);
CDOUT_O: out std_loGIC_VECTOR(47 downto 0);
p_o: out STD_LOGIC_VECTOR(G_P_WIDTH-1 downto 0));
end maCC_ROM;

architecture o of MACC_ROM is

component MACC_PA_BC_ROM
generic (INIT: std_logic_vector(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000");
port (a: in STD_LOGIC_vector(17 downto 0);
AL_N: in STD_LOGIC;
ARSHFT17: in STD_LOGIC;
ARSHFT17_AD_N: in STD_LOGIC;
ARShft17_bypass: in STD_logic;
ARSHFT17_en: in STD_logic;
ARshft17_sd_n: in std_logic;
arSHFT17_SL_N: in STD_LOGIC;
a_byPASS: in std_logic;
a_en: in STD_LOGIc;
A_SRST_N: in STD_LOGIC;
B: in STD_LOgic_vector(17 downto 0);
b2_bypASS: in std_logic;
b2_en: in std_logic;
b2_srst_n: in std_logic;
b_bypass: in std_logic;
b_en: in std_logic;
B_SRST_n: in Std_logic;
c: in STD_LOGIC_vector(47 downto 0);
carryin: in std_lOGIC;
cdin: in STD_LOgic_vector(47 downto 0);
CDIn_fdbk_sel: in STD_LOGIC_VECtor(1 downto 0);
CDIN_FDBK_SEL_ad_n: in std_logic_vector(1 downto 0);
cdin_fdbk_sel_bYPASS: in std_loGIC;
cdin_fdBK_SEL_EN: in std_logIC;
CDIN_FDBK_SEL_SD_N: in std_logic_VECTOR(1 downto 0);
cdiN_FDBK_SEL_SL_N: in Std_logic;
clk: in STD_LOGIC;
c_arst_n: in Std_logic;
C_BYPASS: in std_logic;
C_EN: in std_logic;
C_srst_n: in STD_LOGIC;
d: in std_logIC_VECTOR(17 downto 0);
DOTP: in STD_LOGIC;
d_ARST_N: in std_logic;
D_BYPAss: in sTD_LOGIC;
D_en: in STD_LOGIC;
D_SRST_N: in std_logic;
ovfl_carryout_sel: in std_logic;
PASUB: in std_logic;
PASUB_AD_N: in STD_LOGIC;
PASUB_BYPASS: in STD_LOGIC;
pasub_en: in STD_LOGIC;
pasub_SD_N: in std_logic;
PASUB_SL_n: in STD_LOGIC;
p_bypass: in STD_LOgic;
P_EN: in std_logic;
P_SRST_N: in std_logIC;
rom_addr: in STD_LOGIC_VECTOR(3 downto 0);
SIMD: in STD_LOGIC;
sub: in STD_LOGIC;
sub_ad_n: in STD_LOGIC;
sub_BYPASS: in sTD_LOGIC;
SUB_EN: in std_logic;
SUB_SD_N: in STD_LOGIC;
sub_sl_n: in std_logic;
usE_ROM: in std_logic;
B2: out STD_LOGIC_VECTOR(17 downto 0);
bcout: out STD_LOGIC_VECTOR(17 downto 0);
cdout: out stD_LOGIC_VECTOR(47 downto 0);
OVFL_CARRYOUT: out STD_LOGIC;
p: out STD_LOGIC_VECTOR(47 downto 0));
end component;

signal A: std_logic_vector(17 downto 0);

signal AL_N: STD_LOGIC;

signal arshft17: std_logic;

signal ARSHFT17_ad_n: STD_LOGic;

signal ARSHFT17_BYPASS: STD_LOGIC;

signal arshft17_en: std_logic;

signal ARSHft17_sd_n: STD_logic;

signal ARSHFT17_SL_N: STD_LOGIC;

signal a_bypass: std_logic;

signal A_EN: std_logic;

signal A_SRST_N: std_loGIC;

signal b: STD_LOGIC_VECTOR(17 downto 0);

signal b2_bypass: std_logic;

signal B2_EN: STD_LOGIC;

signal b2_srst_n: std_logic;

signal B_BYPASS: std_lOGIC;

signal B_EN: STD_LOGIC;

signal B_SRST_N: STD_LOGIC;

signal c: STD_LOGIC_VEctor(47 downto 0);

signal CARryin: std_logic;

signal CDIN: std_logic_vector(47 downto 0);

signal CDIN_FDBK_SEL: std_logic_vECTOR(1 downto 0);

signal cdin_fdbk_seL_AD_N: std_logic_vector(1 downto 0);

signal CDIN_FDBK_SEL_bypass: std_logic;

signal cdiN_FDBK_sel_en: STD_logic;

signal cdin_fdbk_sel_sd_n: STD_LOGIC_vector(1 downto 0);

signal cdin_fdbk_sel_SL_N: STD_LOGIC;

signal clk: std_logic;

signal c_arsT_N: std_logic;

signal C_BYpass: STD_LOGIC;

signal c_en: STD_LOgic;

signal C_SRST_N: stD_LOGIC;

signal dotp: std_logic;

signal d: std_logic_vectoR(17 downto 0);

signal d_ARST_N: STD_LOGIC;

signal d_bypass: std_logic;

signal D_en: STD_LOGIC;

signal D_SRST_N: STD_LOGIC;

signal OVFL_CARRYOUT_sel: STD_LOgic;

signal pasub: std_logic;

signal PASUB_AD_N: STD_LOGIC;

signal pasub_bYPASS: std_logiC;

signal PASUB_En: STD_LOGIC;

signal pasub_sd_n: std_logic;

signal PASUB_SL_N: STD_LOGIC;

signal p_bypass: Std_logic;

signal p_en: std_logic;

signal P_SRST_N: std_LOGIC;

signal SIMd: STD_LOGIC;

signal sub: STD_LOGIC;

signal sub_ad_n: std_logic;

signal SUB_BYPASS: std_lOGIC;

signal SUB_EN: sTD_LOGIC;

signal Sub_sd_n: STD_logic;

signal SUB_SL_N: std_loGIC;

signal USE_ROM: STD_LOGIC;

signal cdout: STD_LOGIC_VECTor(47 downto 0);

signal l: STD_LOGIC_VECTOR(47 downto 0);

constant i: integer := 18;

constant OL: INTEGER := 48;

begin
clk <= CLOck_i;
simd <= '0';
DOTP <= '0';
a <= std_logic_vector(resize(SIGNEd(a_i),
i));
b <= std_logic_vector(resize(siGNED(B_I),
i));
D <= STD_LOGIC_VECTOR(resize(SIGNed(d_i),
i));
c <= std_logic_VECTOR(resize(SIGNED(C_I),
OL));
cdin <= STD_Logic_vector(resize(signed(CIN_I),
ol));
OVFL_CARRyout_sel <= '0';
carryin <= '0';
A_BYPASS <= '0';
b_bypass <= '0';
b2_bypass <= '0';
d_bypass <= '0';
p_bypass <= '0';
c_bypass <= '0';
AL_N <= '1';
C_ARST_N <= Nreset_i;
D_arst_n <= NREset_i;
a_srst_n <= NReset_i;
B_SRST_N <= NRESET_I;
B2_SRST_N <= NRESET_I;
D_SRST_N <= nreset_I;
p_srst_n <= nreset_i;
c_srst_n <= NRESET_I;
A_EN <= '1';
B_En <= '1';
b2_en <= '1';
d_en <= '1';
p_en <= '1';
c_en <= '1';
ARSHFT17 <= '0';
ARSHFt17_bypass <= '1';
arshft17_SL_N <= '1';
ARSHFT17_AD_N <= '1';
ARSHFT17_SD_N <= '1';
arshft17_EN <= '1';
cdin_fdbk_seL <= CDIN_Fdbk_sel_i;
cdin_fdbk_sel_AD_N <= "11";
cdin_fdbk_sel_bypass <= '1';
CDIN_fdbk_sel_en <= '1';
CDIN_FDbk_sel_sd_n <= "11";
cdin_fdbk_sel_sl_n <= '1';
PASUB <= '0';
pasub_ad_n <= '1';
pasub_bypass <= '0';
PASUB_EN <= '1';
PASUB_SD_N <= '1';
pasub_sl_n <= '1';
SUB <= '0';
SUB_BYPass <= '1';
sub_SL_N <= '1';
SUB_AD_N <= '1';
sub_sd_n <= '1';
SUb_en <= '1';
USE_ROM <= '1';
MACc_pa_bc_rom_0: macc_pa_bc_rom
generic map (init => g_init)
port map (a => a,
AL_n => Al_n,
ARSHFT17 => aRSHFT17,
ARSHFT17_Ad_n => arshft17_ad_n,
ARSHFT17_BYPASS => ARSHFT17_BYPASS,
arshft17_en => arshft17_en,
ARSHFT17_SD_N => arshft17_sd_n,
ARSHFT17_SL_N => arshft17_sl_n,
a_bypass => a_bYPASS,
a_eN => a_en,
a_srst_n => a_srst_N,
B => b,
b2_bypass => b2_bypass,
B2_en => B2_En,
B2_SRST_n => B2_SRst_n,
B_BYPass => b_bypass,
b_en => b_en,
b_srst_n => b_srst_n,
c => c,
carryin => carryin,
cdin => Cdin,
cdin_fdbk_sel => cdIN_FDBK_SEL,
CDIN_FDBK_Sel_ad_n => CDIN_FDBK_SEL_AD_N,
cdin_fdbk_sel_bypass => cdin_fdbk_sel_bypass,
CDIN_FDBK_SEL_EN => cdin_fdbk_sel_en,
CDIN_FDBK_SEL_SD_n => cdin_fdbk_sel_sd_N,
CDIN_FDBK_SEL_sl_n => CDIN_FDBK_SEL_SL_N,
clk => CLK,
C_ARST_N => C_ARST_N,
C_BYPASS => C_BYPASS,
c_EN => C_EN,
c_srst_n => c_srst_n,
d => D,
dotp => dotp,
D_ARST_n => d_arst_n,
d_bypasS => d_bypass,
d_en => d_en,
d_srst_N => d_SRST_N,
OVFL_CARRYOUT_SEL => ovfl_carryout_sel,
pASUB => pasub,
PASUB_AD_N => PASUB_AD_N,
pasub_bypass => PASUB_BYPASS,
PASUB_EN => pasub_en,
pasub_sd_n => PASUB_SD_N,
PASUB_SL_N => pasub_sl_n,
p_bypasS => P_BYPASS,
P_EN => P_EN,
P_SRST_n => p_srst_n,
ROM_Addr => a_rom_addr_i,
simd => simd,
SUB => SUB,
SUB_AD_N => sub_ad_n,
sub_byPASS => SUB_BYPASS,
SUB_EN => SUB_EN,
SUB_SD_N => sub_sd_n,
sub_sl_n => sub_sl_n,
USE_ROM => USe_rom,
b2 => open ,
bcout => open ,
cdout => cdout,
Ovfl_carryout => open ,
p => l);
CDOUT_O <= std_logic_vecTOR(resize(SIGNED(Cdout),
OL));
p_o <= std_logic_vector(REsize(signeD(L),
g_p_WIDTH));
end o;
