library Ieee;
use IEEE.std_loGIC_1164.all;
use IEEE.numeric_std.all;
use ieee.STD_LOGIC_unsigned.all;
use IEEE.mATH_REAL.all;
use WORK.system_pack.all;
use WORk.DDC_HB2_DEC_COEFFpack.all;
entity ddc_hb2_dec is
port (CLOCK_I: in STd_logic;
NRESET_I: in std_logic;
data_vld_i: in STD_LOGIC;
DATA_I: in STD_LOGIC_VECTOR(g_datain_width-1 downto 0);
DATA_O: out std_LOGIC_VECTOR(g_daTAOUT_WIDTH-1 downto 0);
chan_i: in std_logic_vector(G_CHAN_WIDTH-1 downto 0);
Chan_o: out std_lOGIC_VECTOR(G_CHAN_WIDTH-1 downto 0);
DATA_VLD_O: out STD_LOGIC);
end ddc_HB2_DEC;

architecture O of DDC_HB2_DEC is

attribute syn_preserve: boolean;

attribute syn_preservE of o: architecture is true;

component data_SHIFTER
generic (G_DATA_WIDTH: INTEGER := 16;
G_SHIFT_DELAY: INTEGER := 3);
port (Clock_i: in STD_LOGIC;
nreset_i: in STD_LOGIC;
SHIFT_EN_I: in std_logic;
data_i: in STD_logic_vector((G_DAta_width-1) downto 0);
data_o: out STD_LOGIC_VECTOR((G_DATA_WIDTH-1) downto 0));
end component;

component MULT_ADDSUB is
generic (G_a_width: integer := 16;
G_B_WIDTh: INTEGER := 16;
G_D_width: INTEGER := 16;
G_C_Width: INTEGER := 37;
G_CIN_WIDTH: INTEGER := 37;
G_P_WIDTH: integer := 37);
port (clock_I: in std_logic;
NRESET_I: in std_logic;
a_i: in sTD_LOGIC_VECTOR(G_a_width-1 downto 0);
b_i: in STD_logic_vector(G_b_width-1 downto 0);
d_i: in STD_LOGIC_VEctor(g_d_widtH-1 downto 0);
C_i: in std_LOGIC_VECTOR(G_c_width-1 downto 0);
CIN_I: in std_logic_vector(G_CIN_WIDth-1 downto 0);
CDin_fdbk_sel_i: in STD_LOGIC_VECTOR(1 downto 0);
cdout_o: out std_logic_vECTOR(G_P_WIDTh-1 downto 0);
p_o: out STD_LOGIC_VEctor(G_P_WIDTH-1 downto 0));
end component;

component MACC_ROM
generic (G_A_WIDTH: integer := 16;
G_B_WIDTH: iNTEGER := 16;
G_D_WIDTH: INTEGER := 16;
G_C_width: INTEGER := 37;
g_CIN_WIDTH: integER := 37;
G_P_WIDTH: integER := 37;
g_init: std_logic_vecTOR(287 downto 0) := X"000000000000000000000000000000000000000000000000000000000000000000000000");
port (CLOCK_I: in STD_LOGIC;
NRESET_I: in std_logic;
a_i: in sTD_LOGIC_VECTOR(g_a_width-1 downto 0);
B_I: in std_logic_vector(G_B_WIDTH-1 downto 0);
A_ROm_addr_i: in STD_LOGic_vector(3 downto 0);
D_I: in std_logic_vector(G_D_WIDth-1 downto 0);
C_I: in std_logic_vector(g_c_WIDTH-1 downto 0);
cin_i: in STd_logic_vector(g_cin_widtH-1 downto 0);
cdin_fdbk_sEL_I: in std_logic_vector(1 downto 0);
CDOUT_O: out std_logic_vector(47 downto 0);
P_O: out std_LOGIC_VECTOR(g_p_width-1 downto 0));
end component;

component ROUND_SAT
generic (G_UNRND_DATA_WIDth: POsitive := 33;
G_RND_DATA_width: POSITIVe := 16;
G_UNRND_FRACt_bits: POsitive := 30;
G_RND_fract_bits: POSitive := 15);
port (clock_i: in std_logic;
NRESET_I: in STd_logic;
DATA_I: in std_logic_VECTOR(G_UNRNd_data_width-1 downto 0);
DATA_o: out sTD_LOGIC_VECTOR(G_RND_DATa_width-1 downto 0));
end component;

signal l: std_logic;

signal i: STD_LOGIC;

signal OL: std_logic_vector(G_datain_width-1 downto 0);

signal ll: STD_LOGIC_VECTOR(G_CHAN_WIDTH-1 downto 0);

signal iL: STD_LOGic;

signal OI: std_logic;

type li is array (1 to g_nuMCHANNELS) of STD_logic_vector((G_DATAIN_WIDTH-1) downto 0);

signal ii: li;

type o0 is array (1 to g_NUMCHANNELS+1) of STD_LOGIC_VECtor(0 downto 0);

signal l0: O0;

signal I0: std_logic_vector(0 downto 0);

type o1 is array (1 to g_cHANDELAY) of stD_LOGIC_VECTOR((g_chan_width-1) downto 0);

signal l1: O1;

type I1 is array (1 to g_evenodddELAY) of stD_LOGIC_VECTOR(0 downto 0);

signal ool: i1;

signal LOL: std_logic_vECTOR(0 downto 0);

signal IOL: std_logic_vector(g_datain_width-1 downto 0);

signal oll: std_logic_vector(G_DATAin_width-1 downto 0);

signal lll: STD_LOGIC_VECTor(g_datain_widTH-1 downto 0);

type ill is array (0 to G_dspcount-1) of stD_LOGIC_VECTOR(0 downto 0);

type oil is array (1 to G_DSPCOUNT-1) of STD_Logic_vector(0 downto 0);

signal LIL: oil;

signal IIL: ill;

type o0l is array (0 to G_DSPCOUNT-1) of std_logic_vector((G_DATAIN_WIDTH-1) downto 0);

type L0L is array (1 to g_DSPCOUNT-1) of std_logic_vector((g_datain_width-1) downto 0);

signal I0L: L0L;

signal O1L: O0l;

signal l1l: O0L;

signal i1l: O0L;

signal ooi: sTD_LOGIC;

signal LOI: std_logic_vector(0 downto 0);

signal IOI: std_logic_vector(G_Coeff_width-1 downto 0);

type oli is array (0 to g_dspcount-1) of STD_LOGIC_vector((g_accwidth-1) downto 0);

signal Lli: OLI;

signal ili: OLI;

type oii is array (0 to g_dspcount-1) of std_logic_veCTOR((G_Finaladdwidth-1) downto 0);

signal LII: std_logic_vectOR(g_accwidth-1 downto 0);

signal iii: std_loGIC_VECTOR(g_datain_width-1 downto 0);

signal O0I: STd_logic_vector(g_finaladdwidth-1 downto 0);

signal l0i: std_logic_VECTOR(G_dataout_width-1 downto 0);

signal I0I: std_logic_vector(G_DATAIN_WIDTH-1 downto 0);

signal o1i: STD_LOGIC_vector(G_DATAIN_WIDth-1 downto 0);

signal l1i: std_logIC_VECTOR(g_finaladdwidtH-1 downto 0);

begin
i1i:
process (NRESET_I,clock_i)
begin
if (NRESEt_i = '0') then
OL <= ( others => '0');
elsif (risinG_EDGE(clock_i)) then
ol <= data_I;
end if;
end process I1I;
oo0:
process (NRESET_I,CLOCK_i)
begin
if (nreset_i = '0') then
L <= '0';
ll <= ( others => '0');
elsif (rising_edge(clock_i)) then
l <= datA_VLD_I;
LL <= CHAN_I;
end if;
end process oo0;
lo0:
process (nreset_i,clock_i)
begin
if (nreset_i = '0') then
IL <= '0';
elsif (RISINg_edge(CLOCK_I)) then
if (L = '1' and LL = STD_LOGIC_Vector(TO_UNSIGNED((G_NUMCHANNELS-1),
g_chan_width))) then
IL <= not (il);
end if;
end if;
end process lo0;
io0:
process (nreset_i,clock_i)
begin
if (nreset_i = '0') then
iol <= ( others => '0');
oll <= ( others => '0');
elsif (RISING_EDGE(clock_i)) then
case il is
when '1' =>
oll <= ol;
iol <= ( others => '0');
when others =>
iol <= ol;
OLL <= ( others => '0');
end case;
end if;
end process io0;
ol0:
process (Nreset_i,clock_i)
begin
if (nreset_i = '0') then
ii <= ( others => ( others => '0'));
elsif (RISING_EDGE(clock_i)) then
ii <= IOL&ii(1 to g_numchannels-1);
end if;
end process OL0;
LLL <= II(G_NUMCHANNELS);
LL0:
process (NRESET_I,Clock_i)
begin
if (nreset_i = '0') then
L0 <= ( others => ( others => '0'));
elsif (rising_EDGE(Clock_i)) then
L0 <= i0&L0(1 to g_numchannels);
end if;
end process ll0;
I0(0) <= l;
I <= L0(g_numchannels)(0);
il0:
for OI0 in 1 to (g_dspcount-1)
generate
begin
P_Fwd_delay_shift: DATA_SHIFTer
generic map (g_data_WIDTH => 1,
g_shift_delay => 1)
port map (cloCK_I => clock_i,
NRESET_i => nreset_i,
shift_en_i => '1',
DATA_I => LIL(oi0),
DATA_O => IIL(OI0));
end generate IL0;
iil(0)(0) <= i;
li0:
for OI0 in 0 to (G_DSpcount-2)
generate
begin
LIL(oi0+1) <= iil(oi0);
end generate li0;
II0:
for Oi0 in 1 to (G_DSPCOUNT-1)
generate
begin
p_fwd_delay_rAM: DATA_Shifter
generic map (G_DATA_WIDTH => G_DATAIN_WIDTH,
g_shift_delay => G_CHANCOUNT+1)
port map (CLock_i => CLOCK_I,
nreset_i => nreset_i,
shift_EN_I => iil(oi0)(0),
data_i => i0l(oi0),
data_o => o1l(oi0));
end generate ii0;
o1l(0) <= lll;
O00:
for oi0 in 0 to (G_DSPCOUNT-2)
generate
begin
I0L(Oi0+1) <= o1l(OI0);
end generate O00;
l1l(0) <= O1L(g_dspcount-1);
ooi <= iil(g_dspcount-1)(0);
l00:
if (G_HAS_SYMm = 1)
generate
I00:
if (G_SYMM = 0)
generate
p_rev_DELAY_RAM_0: data_shiftER
generic map (G_DATA_WIDTH => G_DATAin_width,
G_SHIFT_Delay => 0)
port map (CLOCK_i => clock_i,
NRESEt_i => nreset_i,
SHIFT_EN_I => OOi,
DATA_I => L1L(0),
data_o => i1l(0));
end generate i00;
o10:
if (G_SYMM = 1)
generate
P_REV_DELAY_RAm_0: dATA_SHIFTER
generic map (g_data_width => G_datain_width,
g_SHIFT_DELAY => g_chancount)
port map (clock_i => clock_i,
NRESET_I => NRESET_I,
SHIft_en_i => ooi,
DATA_I => L1l(0),
data_o => I1L(0));
end generate o10;
p_final_delay_shift: data_shifter
generic map (g_data_width => 1,
G_SHIFT_DElay => (G_dspcount+3))
port map (CLOCK_I => clock_I,
NRESET_I => nreset_i,
SHIFT_EN_I => '1',
DATA_i => LOI,
DATA_O => open );
LOI(0) <= I;
L10:
for OI0 in 1 to (g_dspcount-1)
generate
begin
P_REV_DELAY_RAM: data_SHIFTER
generic map (g_data_width => G_DATAIN_WIdth,
g_sHIFT_DELAY => G_CHANCOunt-1)
port map (clock_i => CLOCK_i,
nreset_i => nreset_i,
shifT_EN_I => IIL(g_dspcount-oi0-1)(0),
data_i => l1l(oi0),
data_o => i1l(oi0));
end generate l10;
I10:
for OI0 in 0 to (g_dspcount-2)
generate
begin
L1L(OI0+1) <= i1l(OI0);
end generate I10;
end generate L00;
lii <= ( others => '0');
IOI <= ( others => '0');
P_mult_acc0: macc_roM
generic map (g_a_width => g_coeff_width,
g_b_widtH => G_DAtain_width,
g_D_WIDTH => g_datain_width,
G_C_WIDTH => g_accwidth,
G_CIN_WIDTh => G_ACCWIDTH,
g_p_wiDTH => G_finaladdwidth,
G_INIT => g_init)
port map (CLOCk_i => CLOCK_I,
nreset_i => nreset_i,
A_I => IOi,
B_I => O1L(0),
a_rom_addr_i => "0000",
d_i => i1L(G_DSPCOUNT-1),
c_i => LII,
cin_i => ILI(0),
cDIN_FDBK_SEL_I => "00",
cdout_o => lli(0),
P_O => open );
oo1:
for OI0 in 1 to (G_DSPCOUNT-1)
generate
begin
P_MULT_Acc: macc_rom
generic map (G_A_WIDTH => G_COEFF_WIDTH,
g_b_width => G_Datain_width,
g_d_WIDTH => g_datain_width,
G_C_WIDTh => G_ACCWIDTH,
g_cin_width => G_ACCWIdth,
g_p_widTH => g_finaladdwidth,
G_INIT => g_init)
port map (clock_I => CLOCK_I,
NRESET_I => nreset_i,
A_I => iOI,
b_i => o1l(OI0),
A_ROM_ADDR_I => STD_LOGIC_VECTOR(TO_UNSIgned(OI0,
4)),
d_i => I1L(g_dsPCOUNT-1-Oi0),
C_I => LII,
cIN_I => ILI(OI0),
CDIN_FDBK_SEL_I => "11",
cdout_o => LLI(OI0),
P_O => open );
end generate oo1;
lo1:
for oi0 in 0 to (g_dspcOUNT-2)
generate
begin
ILI(OI0+1) <= LLI(oi0);
end generate LO1;
ili(0) <= ( others => '0');
i0i <= oll;
P_center_delay_ram: Data_shifter
generic map (g_data_width => g_datain_width,
G_SHIFT_DELAY => (G_Dspcount*g_chancount)+(G_DSPCOunt))
port map (cloCK_I => CLOCK_I,
NRESET_I => nreset_i,
SHIFT_EN_I => '1',
DATA_I => i0i,
DATA_O => O1I);
P_mult_center: MULT_ADDSUB
generic map (G_A_WIdth => G_COEFF_WIDTH,
G_B_WIDth => G_DATAIN_WIDTH,
g_d_width => G_DATAIN_WIDTH,
G_c_width => g_accwidth,
G_CIN_WIDTH => g_accwidth,
G_P_WIDTH => G_FINALADDWIDTH)
port map (CLOCK_I => CLOCK_I,
NReset_i => NRESET_I,
A_I => G_Center_tap,
B_I => O1I,
D_I => iii,
C_I => lii,
CIN_I => LLi(G_DSPCOUNT-1),
CDin_fdbk_sel_i => "11",
CDOUT_O => open ,
p_o => L1I);
iII <= ( others => '0');
IO1:
process (NRESEt_i,clock_i)
begin
if (NRESET_I = '0') then
o0i <= ( others => '0');
elsif (rising_edge(CLOCK_I)) then
O0i <= l1i;
end if;
end process IO1;
u_rounD_SAT: Round_sat
generic map (G_UNRND_DATA_Width => g_finaladdwidth,
G_RND_DATA_width => G_DATAOUT_Width,
G_UNRND_FRACT_Bits => g_unrnd_FRACWIDTH,
g_rnd_fract_BITS => G_DATAOUT_FRACWIDTh)
port map (clock_i => CLOCK_I,
NRESET_I => nreset_i,
data_i => O0I,
data_O => L0I);
OL1:
process (NRESET_I,CLOCK_I)
begin
if (nRESET_I = '0') then
l1 <= ( others => ( others => '0'));
chan_o <= ( others => '0');
elsif (rising_edge(cLOCK_I)) then
l1 <= Ll&l1(1 to g_chanDELAY-1);
CHAN_O <= l1(G_CHANDELAY);
end if;
end process ol1;
LL1:
process (NRESET_I,CLOCK_I)
begin
if (NRESET_I = '0') then
OOL <= ( others => ( others => '0'));
data_vld_O <= '0';
elsif (rising_edge(CLOCK_I)) then
ool <= LOL&OOL(1 to G_EVENODDDELAY-1);
DATA_vld_o <= OI;
end if;
end process ll1;
LOL(0) <= IL;
oi <= ool(G_EVENODDDELAy)(0);
Data_o <= L0I;
end O;
