# Creating SmartDesign "CPRI_TOP"
set sd_name {CPRI_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CPRI_RESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRL_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HSEL_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HWRITE_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {HREADYOUT_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_CLK_G} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_STABLE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {axc_rxdata_resetn} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {axc_txdata_resetn} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {cpri_ready} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {HADDR_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HBURST_i} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPROT_i} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HSIZE_i} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HTRANS_i} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HWDATA_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_rx_clk} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_rx_req} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_rx_resetn} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_tx_clk} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_tx_data} -port_direction {IN} -port_range {[127:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_tx_resetn} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_tx_valid} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {HRDATA_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HRESP_o} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_rx_data} -port_direction {OUT} -port_range {[127:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_rx_valid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {axc_tx_req} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AHB_SLV} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"HADDR:HADDR_i" \
"HTRANS:HTRANS_i" \
"HWRITE:HWRITE_i" \
"HSIZE:HSIZE_i" \
"HBURST:HBURST_i" \
"HPROT:HPROT_i" \
"HWDATA:HWDATA_i" \
"HSELx:HSEL_i" \
"HRDATA:HRDATA_o" \
"HREADYOUT:HREADYOUT_o" \
"HRESP:HRESP_o" } 

# Add AND3_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_0}



# Add CNTRL_LPBCK_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {CNTRL_LPBCK} -hdl_file {hdl\CNTRL_LPBCK.v} -instance_name {CNTRL_LPBCK_0}



# Add CNTRL_LPBCK_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {CNTRL_LPBCK} -hdl_file {hdl\CNTRL_LPBCK.v} -instance_name {CNTRL_LPBCK_1}



# Add CNTRL_LPBCK_2 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {CNTRL_LPBCK} -hdl_file {hdl\CNTRL_LPBCK.v} -instance_name {CNTRL_LPBCK_2}



# Add CPRI_IP0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CPRI_IP0} -instance_name {CPRI_IP0_0}



# Add PF_TX_PLL_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C1} -instance_name {PF_TX_PLL_C1_0}



# Add PF_XCVR_ERM_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C1} -instance_name {PF_XCVR_ERM_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_TX_DISPFNC} -value {GND}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:A" "CPRI_RESETN" "PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:B" "CPRI_IP0_0:RX_READY" "PF_XCVR_ERM_C1_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:C" "PF_TX_PLL_C1_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:Y" "CNTRL_LPBCK_0:axc_rx_resetn" "CNTRL_LPBCK_0:axc_tx_resetn" "CNTRL_LPBCK_1:axc_rx_resetn" "CNTRL_LPBCK_1:axc_tx_resetn" "CNTRL_LPBCK_2:axc_rx_resetn" "CNTRL_LPBCK_2:axc_tx_resetn" "CPRI_IP0_0:CPRI_RX_RESETN" "CPRI_IP0_0:CPRI_TX_RESETN" "CPRI_IP0_0:rx_ctrl_AxC_rstn" "CPRI_IP0_0:rx_eth_rstn" "CPRI_IP0_0:rx_vss_rstn" "CPRI_IP0_0:tx_ctrl_AxC_rstn" "CPRI_IP0_0:tx_eth_rstn" "CPRI_IP0_0:tx_vss_rstn" "axc_rxdata_resetn" "axc_txdata_resetn" "cpri_ready" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:axc_rx_clk" "CNTRL_LPBCK_1:axc_rx_clk" "CNTRL_LPBCK_2:axc_rx_clk" "CPRI_IP0_0:CPRI_RX_CLK" "CPRI_IP0_0:rx_ctrl_AxC_clk" "CPRI_IP0_0:rx_eth_clk" "CPRI_IP0_0:rx_vss_clk" "LANE0_RX_CLK_R" "PF_XCVR_ERM_C1_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:axc_tx_clk" "CNTRL_LPBCK_1:axc_tx_clk" "CNTRL_LPBCK_2:axc_tx_clk" "CPRI_IP0_0:CPRI_TX_CLK" "CPRI_IP0_0:tx_ctrl_AxC_clk" "CPRI_IP0_0:tx_eth_clk" "CPRI_IP0_0:tx_vss_clk" "LANE0_TX_CLK_R" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:data_rx_valid" "CPRI_IP0_0:rx_vss_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:data_tx_valid" "CPRI_IP0_0:tx_vss_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:rx_req_o" "CPRI_IP0_0:rx_vss_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:tx_req_in" "CPRI_IP0_0:tx_vss_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:data_rx_valid" "CPRI_IP0_0:rx_ctrl_AxC_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:data_tx_valid" "CPRI_IP0_0:tx_ctrl_AxC_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:rx_req_o" "CPRI_IP0_0:rx_ctrl_AxC_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:tx_req_in" "CPRI_IP0_0:tx_ctrl_AxC_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:data_rx_valid" "CPRI_IP0_0:rx_eth_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:data_tx_valid" "CPRI_IP0_0:tx_eth_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:rx_req_o" "CPRI_IP0_0:rx_eth_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:tx_req_in" "CPRI_IP0_0:tx_eth_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:HCLK_i" "HCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:HRESETN_i" "HRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:RX_VALID" "LANE0_RX_VAL" "PF_XCVR_ERM_C1_0:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRL_ARST_N" "PF_XCVR_ERM_C1_0:CTRL_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRL_CLK_0" "PF_XCVR_ERM_C1_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N_0" "PF_XCVR_ERM_C1_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P_0" "PF_XCVR_ERM_C1_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RX_CLK_G" "PF_XCVR_ERM_C1_0:LANE0_RX_CLK_G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N_0" "PF_XCVR_ERM_C1_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P_0" "PF_XCVR_ERM_C1_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TX_CLK_STABLE" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:REF_CLK" "PF_XCVR_ERM_C1_0:LANE0_CDR_REF_CLK_0" "REF_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:data_i" "CPRI_IP0_0:rx_vss_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_0:data_o" "CPRI_IP0_0:tx_vss_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:data_i" "CPRI_IP0_0:rx_ctrl_AxC_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_1:data_o" "CPRI_IP0_0:tx_ctrl_AxC_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:data_i" "CPRI_IP0_0:rx_eth_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CNTRL_LPBCK_2:data_o" "CPRI_IP0_0:tx_eth_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:CHAR_8B_10B" "PF_XCVR_ERM_C1_0:LANE0_8B10B_TX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_rx_clk" "axc_rx_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_rx_data" "axc_rx_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_rx_req" "axc_rx_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_rx_resetn" "axc_rx_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_rx_valid" "axc_rx_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_tx_clk" "axc_tx_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_tx_data" "axc_tx_data" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_tx_req" "axc_tx_req" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_tx_resetn" "axc_tx_resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:axc_tx_valid" "axc_tx_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:rx_line_data" "PF_XCVR_ERM_C1_0:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CPRI_IP0_0:tx_line_data" "PF_XCVR_ERM_C1_0:LANE0_TX_DATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHB_SLV" "CPRI_IP0_0:AHB_Slv" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C1_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "CPRI_TOP"
generate_component -component_name ${sd_name}
