# Creating SmartDesign "RISCV_TOP"
set sd_name {RISCV_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {HREADYOUT_S7} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {clk} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CTRLR_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HCLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HMASTLOCK_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HREADY_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HSEL_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HWRITE_S7} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PRESETN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS0_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS1_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {HRDATA_S7} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HRESP_S7} -port_direction {IN} -port_range {[1:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[15:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[2:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[14:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HADDR_S7} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HBURST_S7} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HPROT_S7} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HSIZE_S7} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HTRANS_S7} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HWDATA_S7} -port_direction {OUT} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[15:0]} -port_is_pad {1}

# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AHBmslave7} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"HADDR:HADDR_S7" \
"HTRANS:HTRANS_S7" \
"HWRITE:HWRITE_S7" \
"HSIZE:HSIZE_S7" \
"HBURST:HBURST_S7" \
"HPROT:HPROT_S7" \
"HWDATA:HWDATA_S7" \
"HSELx:HSEL_S7" \
"HMASTLOCK:HMASTLOCK_S7" \
"HRDATA:HRDATA_S7" \
"HREADY:HREADY_S7" \
"HREADYOUT:HREADYOUT_S7" \
"HRESP:HRESP_S7" } 

# Add MiV_SUBSYSTEM_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MiV_SUBSYSTEM} -instance_name {MiV_SUBSYSTEM_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "MiV_SUBSYSTEM_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "MiV_SUBSYSTEM_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "MiV_SUBSYSTEM_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "MiV_SUBSYSTEM_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "MiV_SUBSYSTEM_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CTRLR_READY" "MiV_SUBSYSTEM_0:CTRLR_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HCLK" "MiV_SUBSYSTEM_0:HCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HRESETN" "MiV_SUBSYSTEM_0:resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:ODT" "ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:PRESETN" "PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:REF_CLK_0" "clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:RX" "RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISCLKO0" "SPISCLKO0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISCLKO1" "SPISCLKO1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISDI0" "SPISDI0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISDI1" "SPISDI1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISDO0" "SPISDO0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISDO1" "SPISDO1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISS0_0" "SPISS0_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISS0_1" "SPISS0_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:SPISS1_0" "SPISS1_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:TX" "TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_SUBSYSTEM_0:WE_N" "WE_N" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "MiV_SUBSYSTEM_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "MiV_SUBSYSTEM_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM" "MiV_SUBSYSTEM_0:DM" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "MiV_SUBSYSTEM_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "MiV_SUBSYSTEM_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "MiV_SUBSYSTEM_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "MiV_SUBSYSTEM_0:GPIO_OUT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHBmslave7" "MiV_SUBSYSTEM_0:AHBmslave7" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "RISCV_TOP"
generate_component -component_name ${sd_name}
