/*******************************************************************************
 * (c) Copyright 2015 Microsemi Corporation.  All rights reserved.
 *
 *
 *
 * SVN $Revision: $
 * SVN $Date: $
 */

#ifndef __MR_REGISTERS_H__
	#define __MR_REGISTERS_H__

#if 0 // these defines were replaced by a enum typedef in indirectRamSel.h
/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants for Internal RAM Selection */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	PKT_STORE_SEL			0
#define	PROBE_STORE_SEL			1
#define	XCONN_STORE_SEL			2
#define	RMEP_ERR_STORE_SEL		3
#define	RX_LMEP_MAP_SEL			4
#define	CPU_SYS_CAPT_FIFO_SEL	5
#define	RMEP_RAM_SEL			6
#define	XCONN_RAM_SEL			7
#define	RMEP_ERR_RAM_SEL		8
#define	TX_LMEP_MAP_SEL			9
#define	EXT_SRAM_SEL			10
#define	CARRMAC_SEL				11
#define	SYSMAC_SEL				12
#define	RX_CARR_DATA_FIFO_SEL	13
#define	LINE_STATS_RAM_SEL		14
#define	CPU_SYS_CAPT_INFO_FIFO_SEL	15
#define VLAN_INFO_RAM_SEL		16
#define	LBM_STORE_SEL			17
#define LBR_RAM_SEL				18
#define	MC_LBR_STORE_SEL		19
#define	PORT_MAC_RAM_SEL		20
#define PM_STATS_RAM_SEL		10		//previously 21
#define RMEP_MAP_RAM_SEL		4		// The RMep Table is in the same ram as rxLMepMap but starts at offset 512
#define PM_DB_RAM_SEL			22
#define TX_LB_RAM_SEL			24
#define TLV_RAM_SEL				25
#define	CPU_CAPT_FIFO_SEL		26
#define	CPU_CAPT_INFO_FIFO_SEL	27
#define	POLICER_CFG_RAM_SEL		28
#define	POLICER_CTXT_RAM_SEL	29
#define	CPU_SYS_TX_RAM_SEL		30
#define	POLICER_STATS_RAM_SEL	31
#endif
/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants for Register Addresses*/
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define IND_CTRL_REG_ADDR		0x5000
#define IND_RD_DATA_REG_ADDR	0x5004
#define IND_WR_DATA_REG_ADDR	0x5008

#define	LMEP_BA_REG_ADDR			0x00000
#define	VLANPORT_BA_REG_ADDR		0x00100
#define	DIRLVL_BA_REG_ADDR			0x00104
#define	RMEP_BA_REG_ADDR			0x0010c
#define	DATABASE_BA_REG_ADDR		0x00110
#define	SEQERR_BA_REG_ADDR			0x00114
#define	CCM_TX_TEMPL_BA_REG_ADDR	0x00200
#define	PM_TX_TEMPL_BA_REG_ADDR		0x00204
#define	LB_TX_TEMPL_BA_REG_ADDR		0x00208
#define	HW_TYPE_REG_ADDR			0x0020C
#define	REVISION_REG_ADDR			0x00210
#define	BUILD_CFG0_REG_ADDR			0x00214
#define	BUILD_CFG1_REG_ADDR			0x00218
#define	PM_STATS_BA_REG_ADDR		0x00220

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for the HW_TYPE Register MASKing */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define HW_TYPE_REG_NUM_PM_SVC_MASK		0xFFFF0000
#define HW_TYPE_REG_NUM_PM_SVC_OFFSET	16
#define HW_TYPE_REG_HW_TYPE_MASK		0x00000001
#define HW_TYPE_REG_HW_TYPE_OFFSET		0

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for the Config Register MASKing */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define BUILD_CFG0_REG_NUM_LMEPS_MASK	0x0000FFFF
#define BUILD_CFG0_REG_NUM_LMEPS_OFFSET	0
#define BUILD_CFG0_REG_NUM_RMEPS_MASK	0xFFFF0000
#define BUILD_CFG0_REG_NUM_RMEPS_OFFSET	16
#define BUILD_CFG1_REG_NUM_LB_MASK		0x0000000F
#define BUILD_CFG1_REG_NUM_LB_OFFSET	0
#define BUILD_CFG1_REG_NUM_PORTS_MASK	0x00000FF0
#define BUILD_CFG1_REG_NUM_PORTS_OFFSET	4
#define BUILD_CFG1_REG_COM_RAM_MASK		0xFFFFF000
#define BUILD_CFG1_REG_COM_RAM_OFFSET	12

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for Hardware Type register MASKing */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	MR_DEVICE_IS_XILINX				0x0001
#define	MR_DEVICE_CMD_IF_TYPE_MASK		0x000E
#define	MR_DEVICE_SYS_NOT_PRESENT		0x0010
#define	MR_DEVICE_USE_EXT_CARR_PHY		0x0020
#define	MR_DEVICE_CARR_PHY_IF_TYPE		0x00C0
#define	MR_DEVICE_USE_EXT_SYS_PHY		0x0100			// only relevant if SYS is present
#define	MR_DEVICE_SYS_PHY_IF_TYPE		0x0600			// only relevant if SYS is present

/* ----------------------------------------------------------------------------------------------------------------------------------*/
// These are special addresses reserved for accessing internal API values
// They do not access HW registers.
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	API_REG_ST_ADDR					0x0500
#define API_REG_VLANPORT_RAM_SIZE		0x0501
#define API_REG_RMEP_RAM_SIZE 			0x0502
#define API_REG_LMEP_RAM_SIZE 			0x0503
#define API_REG_DB_RAM_SIZE 			0x0504
#define API_REG_DIRLVL_RAM_SIZE 		0x0505
#define API_REG_CCMTXTEMPL_RAM_SIZE 	0x0506
#define API_REG_PMTXTEMPL_RAM_SIZE 		0x0507
#define API_REG_LBTXTEMPL_RAM_SIZE 		0x0508
#define API_REG_SEQERR_RAM_SIZE 		0x0509
#define API_REG_RXNUM_RAM_SIZE 			0x050A
#define API_REG_TXNUM_RAM_SIZE			0x050B
#define API_REG_RMEPSM_RAM_SIZE			0x0512
#define API_REG_XCONNSM_RAM_SIZE 		0x0513
#define API_REG_RMEPERRSM_RAM_SIZE		0x0514
#define API_REG_PVIDTBLSIZE				0x0515
#define API_REG_LINESTATS_RAM_SIZE		0x0516
#define API_REG_PORTMAC_RAM_SIZE 		0x0517
#define API_REG_MCLBR_RAM_SIZE			0x0518
#define API_REG_LBMSTORE_RAM_SIZE		0x0519
#define API_REG_PMSTATS_RAM_SIZE		0x0520
#define API_REG_PMDB_RAM_SIZE			0x0521
#define API_REG_LBR_RAM_SIZE			0x0522
#define API_REG_RMEPL12_BDRY_IDX		0x0523
#define API_REG_RMEPL3_BDRY_IDX			0x0524
#define	API_REG_TLV_ORDER				0x0525
#define	API_REG_API_REVISION			0x0526
#define	API_REG_END_ADDR				0x05FF

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants for HW Register Addresses*/
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	DEV_CFG_REG_ADDR		0x01000
#define	TPID1_REG_ADDR			0x01004
#define	PVID_REG_ADDR			0x01008
#define	CFM_DEFN1_REG_ADDR		0x0100C
#define	CFM_DEFN2_REG_ADDR		0x01010
#define	NUM_MEPS_REG_ADDR		0x01014
#define	CCM_VAL_EN_REG_ADDR		0x01018
#define	PROBE_CTRL_REG_ADDR		0x0101C
#define	PROBE_MASK_REG_ADDR		0x01020
#define	HDR_CFG_REG_ADDR		0x01024
#define	CFM_DEFN3_REG_ADDR		0x01028
#define	CFM_DEFN4_REG_ADDR		0x0102C
#define	NUM_PM_MEPS_REG_ADDR	0x01034

// Bitmasks for CCM_VAL_EN_REG_ADDR
#define	CCM_VAL_EN_REG_CAP_LTM_MASK			0x00010000
#define	CCM_VAL_EN_REG_CAP_LTR_MASK			0x00020000

// Bitmasks for DEV_CFG_REG
#define	DEV_CFG_REG_DEMARC_MASK				0x00000001
#define	DEV_CFG_REG_DEMARC_OFFSET			0

#define	DEV_CFG_REG_POL_PORT_ONLY_MASK		0x00000004
#define	DEV_CFG_REG_POL_PORT_ONLY_OFFSET	2

#define DEV_CFG_REG_PORT0_COS_DSCP_MASK		0x00000008
#define DEV_CFG_REG_PORT0_COS_DSCP_OFFSET	3
#define DEV_CFG_REG_PORT1_COS_DSCP_MASK		0x00000010
#define DEV_CFG_REG_PORT1_COS_DSCP_OFFSET	4

#define	DEV_CFG_REG_P0_COLOR_AWARE_MASK		0x00000020
#define	DEV_CFG_REG_P0_COLOR_AWARE_OFFSET	5
#define	DEV_CFG_REG_P0_COLOR_FWD_MASK		0x00000040
#define	DEV_CFG_REG_P0_COLOR_FWD_OFFSET		6

#define DEV_CFG_REG_SAFILTER_WHITELIST_MASK	0x00000080
#define DEV_CFG_REG_SAFILTER_WHITELIST_OFFSET 7
#define DEV_CFG_REG_SAFILTER_BLACKLIST_MASK 0x00000100
#define DEV_CFG_REG_SAFILTER_BLACKLIST_OFFSET 8
//#define	DEV_CFG_REG_PORT_NUM_MASK			0x000001FE
//#define	DEV_CFG_REG_PORT_NUM_OFFSET			1
#define	DEV_CFG_REG_P0_TUNNEL_MASK			0x00000200
#define	DEV_CFG_REG_P0_TUNNEL_OFFSET		9
#define	DEV_CFG_REG_EN_INIT_WAIT_MASK		0x00000400
#define	DEV_CFG_REG_EN_INIT_WAIT_OFFSET		10
#define	DEV_CFG_REG_NUM_GC_REQD_MASK		0x00001800
#define	DEV_CFG_REG_NUM_GC_REQD_OFFSET		11
#define	DEV_CFG_REG_DSCP_V6_EN_MASK			0x00002000
#define	DEV_CFG_REG_DSCP_V6_EN_OFFSET		13
#define	DEV_CFG_REG_P0_ALL_TO_ONE_MASK		0x00004000
#define	DEV_CFG_REG_P0_ALL_TO_ONE_OFFSET	14
#define	DEV_CFG_REG_P1_ALL_TO_ONE_MASK		0x00008000
#define	DEV_CFG_REG_P1_ALL_TO_ONE_OFFSET	15
#define DEV_CFG_REG_P0_USE_DEI_MASK			0x00010000
#define DEV_CFG_REG_P0_USE_DEI_OFFSET		16
#define DEV_CFG_REG_P1_USE_DEI_MASK			0x00020000
#define DEV_CFG_REG_P1_USE_DEI_OFFSET		17

#define DEV_CFG_REG_P0_ADMIT_RULE_MASK		0x000C0000
#define DEV_CFG_REG_P0_ADMIT_RULE_OFFSET	18
#define DEV_CFG_REG_P1_ADMIT_RULE_MASK		0x00300000
#define DEV_CFG_REG_P1_ADMIT_RULE_OFFSET	20

#define	DEV_CFG_REG_P0_TAG_TYPE_MASK		0x0C00000
#define	DEV_CFG_REG_P0_TAG_TYPE_OFFSET		22
#define	DEV_CFG_REG_P1_TAG_TYPE_MASK		0x3000000
#define	DEV_CFG_REG_P1_TAG_TYPE_OFFSET		24

#define	DEV_CFG_REG_P1_COLOR_AWARE_MASK		0x04000000
#define	DEV_CFG_REG_P1_COLOR_AWARE_OFFSET	26
#define	DEV_CFG_REG_P1_COLOR_FWD_MASK		0x08000000
#define	DEV_CFG_REG_P1_COLOR_FWD_OFFSET		27

#define	DEV_CFG_REG_POLICER_EN_MASK			0x10000000
#define	DEV_CFG_REG_POLICER_EN_OFFSET		28

#define DEV_CFG_REG_PM_INIT_DONE_MASK			0x80000000
#define DEV_CFG_REG_INIT_DONE_OFFSET		31
// Bitmasks for TPID1_REG
#define	TPID1_REG_CTAG_MASK					0x0000FFFF
#define	TPID1_REG_CTAG_OFFSET				0
#define	TPID1_REG_STAG_MASK					0xFFFF0000
#define	TPID1_REG_STAG_OFFSET				16

// Bitmasks for PVID_REG
#define PVID_REG_PORT0_PVID_MASK			0x0000FFFF
#define PVID_REG_PORT0_PVID_OFFSET			0
#define PVID_REG_PORT1_PVID_MASK			0xFFFF0000
#define PVID_REG_PORT1_PVID_OFFSET			16

// Bitmasks for TPID2_REG
//#define	TPID2_REG_ITAG_MASK					0x0000FFFF
//#define	TPID2_REG_ITAG_OFFSET				0

// Bitmasks for CFM_DEFN1_REG
#define	CFM_DEFN1_REG_ETYPE_MASK			0x0000FFFF
#define	CFM_DEFN1_REG_ETYPE_OFFSET			0
#define	CFM_DEFN1_REG_SLM_OPCODE_MASK		0x00FF0000
#define	CFM_DEFN1_REG_SLM_OPCODE_OFFSET		16
#define	CFM_DEFN1_REG_SLR_OPCODE_MASK		0xFF000000
#define	CFM_DEFN1_REG_SLR_OPCODE_OFFSET		24

// Bitmasks for CFM_DEFN2_REG
#define	CFM_DEFN2_REG_MR_CCM_OPCODE_MASK		0x000000FF
#define	CFM_DEFN2_REG_MR_CCM_OPCODE_OFFSET		0
#define	CFM_DEFN2_REG_MR_LMM_OPCODE_MASK		0x0000FF00
#define	CFM_DEFN2_REG_MR_LMM_OPCODE_OFFSET		8
#define	CFM_DEFN2_REG_MR_LMR_OPCODE_MASK		0x00FF0000
#define	CFM_DEFN2_REG_MR_LMR_OPCODE_OFFSET		16
#define	CFM_DEFN2_REG_MR_IDM_OPCODE_MASK		0xFF000000
#define	CFM_DEFN2_REG_MR_IDM_OPCODE_OFFSET		24

// Bitmasks for CFM_DEFN3_REG
#define	CFM_DEFN3_REG_MR_DMM_OPCODE_MASK		0x000000FF
#define	CFM_DEFN3_REG_MR_DMM_OPCODE_OFFSET		0
#define	CFM_DEFN3_REG_MR_DMR_OPCODE_MASK		0x0000FF00
#define	CFM_DEFN3_REG_MR_DMR_OPCODE_OFFSET		8
#define	CFM_DEFN3_REG_MR_LBM_OPCODE_MASK		0x00FF0000
#define	CFM_DEFN3_REG_MR_LBM_OPCODE_OFFSET		16
#define	CFM_DEFN3_REG_MR_LBR_OPCODE_MASK		0xFF000000
#define	CFM_DEFN3_REG_MR_LBR_OPCODE_OFFSET		24

// Bitmasks for CFM_DEFN4_REG
#define	CFM_DEFN4_REG_MR_TST_OPCODE_MASK		0x000000FF
#define	CFM_DEFN4_REG_MR_TST_OPCODE_OFFSET		0
#define	CFM_DEFN4_REG_LCK_OPCODE_MASK		0x0000FF00
#define	CFM_DEFN4_REG_LCK_OPCODE_OFFSET		8
#define	CFM_DEFN4_REG_AIS_OPCODE_MASK		0x00FF0000
#define	CFM_DEFN4_REG_AIS_OPCODE_OFFSET		16

// Bitmasks for NUM_MEPS_REG
#define	NUM_MEPS_REG_LMEP_NUM_MASK			0x00003FFF
#define	NUM_MEPS_REG_LMEP_NUM_OFFSET		0
#define	NUM_MEPS_REG_RMEP_NUM_MASK			0x0FFFC000
#define	NUM_MEPS_REG_RMEP_NUM_OFFSET		14

// Bitmasks for PROBE_CTRL_REG
#define	PROBE_CTRL_REG_LMEP_NUM_MASK		0x00003FFF
#define	PROBE_CTRL_REG_LMEP_NUM_OFFSET		0
#define	PROBE_CTRL_REG_RMEP_NUM_MASK		0x0FFFC000
#define	PROBE_CTRL_REG_RMEP_NUM_OFFSET		14
#define	PROBE_CTRL_REG_XCON_ERR_SEL_MASK	0x10000000
#define	PROBE_CTRL_REG_XCON_ERR_SEL_OFFSET	28
#define	PROBE_CTRL_REG_RMEP_ERR_SEL_MASK	0x20000000
#define	PROBE_CTRL_REG_RMEP_ERR_SEL_OFFSET	29
#define	PROBE_CTRL_REG_CLR_INT_MASK			0x40000000
#define	PROBE_CTRL_REG_CLR_INT_OFFSET		30
#define	PROBE_CTRL_REG_PROBE_EN_MASK		0x80000000
#define	PROBE_CTRL_REG_PROBE_EN_OFFSET		31

// Bitmasks for PROBE_MASK_REG
#define	PROBE_MASK_REG_LMEP_SEL_MASK		0x00003FFF
#define	PROBE_MASK_REG_LMEP_SEL_OFFSET		0
#define	PROBE_MASK_REG_RMEP_SEL_MASK		0x0FFFC000
#define	PROBE_MASK_REG_RMEP_SEL_OFFSET		14
#define	PROBE_MASK_REG_XCON_ERR_SEL_MASK	0x10000000
#define	PROBE_MASK_REG_XCON_ERR_SEL_OFFSET	28
#define	PROBE_MASK_REG_RMEP_ERR_SEL_MASK	0x20000000
#define	PROBE_MASK_REG_RMEP_ERR_SEL_OFFSET	29

// Bitmasks for CFM_DEFN4_REG
#define	HDR_CFG_REG_HDR_LEN_MASK			0x00000007
#define	HDR_CFG_REG_HDR_LEN_OFFSET			0
#define	HDR_CFG_REG_PID_START_MASK			0x000007F0
#define	HDR_CFG_REG_PID_START_OFFSET		4
#define	HDR_CFG_REG_VID_START_MASK			0x0003F800
#define	HDR_CFG_REG_VID_START_OFFSET		11
#define	HDR_CFG_REG_DIR_START_MASK			0x01FC0000
#define	HDR_CFG_REG_DIR_START_OFFSET		18

#define	NUM_3P3MS_MEPS_REG_ADDR	0x01100
#define	NUM_10MS_MEPS_REG_ADDR	0x01104
#define	NUM_100MS_MEP_REG_ADDR	0x01108
#define	NUM_1S_MEPS_REG_ADDR	0x0110c
#define	NUM_10S_MEPS_REG_ADDR	0x01110
#define	NUM_1M_MEPS_REG_ADDR	0x01114
#define	NUM_10M_MEPS_REG_ADDR	0x01118
#define	ST_3P3MS_REG_ADDR		0x0111c
#define	END_3P3MS_REG_ADDR		0x01120
#define	ST_10MS_REG_ADDR		0x01124
#define	END_10MS_REG_ADDR		0x01128
#define	ST_100MS_REG_ADDR		0x0112c
#define	END_100MS_REG_ADDR		0x01130
#define	ST_1S_REG_ADDR			0x01134
#define	END_1S_REG_ADDR			0x01138
#define	ST_10S_REG_ADDR			0x0113c
#define	END_10S_REG_ADDR		0x01140
#define	ST_1M_REG_ADDR			0x01144
#define	END_1M_REG_ADDR			0x01148
#define	ST_10M_REG_ADDR			0x0114c
#define	END_10M_REG_ADDR		0x01150
#define	TX_CFM_IVAL_REG_ADDR	0x01154
#define	TX_OAM_RATE_REG_ADDR	0x01158
#define TEST_DIV_REG_ADDR		0x0115C
#define	TX_INIT_REG_ADDR		0x01160
#define	CPU_TX_REG_ADDR			0x01164
#define	TX_ARB_SETUP_REG_ADDR	0x01164	// is this and associated Fns redundant?
#define	SYS_PVID_REG_ADDR		0x01168

#define TX_OAM_RATE_REG_RATE_MASK		0x000001FF
#define TX_OAM_RATE_REG_RATE_OFFSET		0

#define TX_INIT_REG_TX_EN_MASK			0x00000001
#define TX_INIT_REG_TX_EN_OFFSET		0
#define TX_INIT_REG_SFP_TX_DIS_MASK		0x00000002
#define TX_INIT_REG_SFP_TX_DIS_OFFSET	1
#define	TX_INIT_REG_TX_IDLE_MASK		0x00000010
#define	TX_INIT_REG_TX_IDLE_OFFSET		4

#define SYS_PVID_REG_VLAN_MASK			0x00000FFF
#define SYS_PVID_REG_VLAN_OFFSET		0
#define SYS_PVID_REG_DE_MASK			0x00001000
#define SYS_PVID_REG_DE_OFFSET			12
#define SYS_PVID_REG_PRIO_MASK			0x0000E000
#define SYS_PVID_REG_PRIO_OFFSET		13

#define CPU_TX_PKT_START_BUSY_MASK			0x00000001
#define CPU_TX_PKT_RDY_OFFSET		0
#define CPU_TX_BURST_VAL_MASK		0x0000000E
#define CPU_TX_BURST_VAL_OFFSET	1
#define CPU_TX_RATE_LIMIT_MASK		0x00000010
#define CPU_TX_RATE_LIMIT_OFFSET	4
#define CPU_TX_PKT_PORT_MASK		0x00000020
#define CPU_TX_PKT_PORT_OFFSET		5

#define	RMEP_CTLR_CYC_REG_ADDR	0x02000
#define	ERR_CTLR_CYC_REG_ADDR	0x02004
#define	TO_VAL_3P3MS_REG_ADDR	0x02008
#define	TO_VAL_10MS_REG_ADDR	0x0200c
#define	TO_VAL_100MS_REG_ADDR	0x02010
#define	TO_VAL_1S_REG_ADDR		0x02014
#define	TO_VAL_10S_REG_ADDR		0x02018
#define	TO_VAL_1M_REG_ADDR		0x0201c
#define	TO_VAL_10M_REG_ADDR		0x02020

#define	INT_REASON_REG_ADDR		0x03000
#define	INT_MASK_REG_ADDR		0x03004
#define	CONN_INT_REG_ADDR		0x03008
#define	XCONN_INT_REG_ADDR		0x0300C
#define	RMEP_ERR_INT_REG_ADDR	0x03010
#define	SA_CNG_INT_REG_ADDR		0x03014
#define	RDI_CNG_INT_REG_ADDR	0x03018
#define	TLV_CNG_INT_REG_ADDR	0x0301C
#define	MISCFG1_INT_REG_ADDR	0x0302C
#define	MISCFG2_INT_REG_ADDR	0x03030
#define	RPT_EN_REG_ADDR			0x03034

#define	CONN_INT_REG_RMEP_NUM_MASK			0xFFFC
#define	CONN_INT_REG_RMEP_NUM_OFFSET		2
#define	CONN_INT_REG_VALUE_MASK				0x2
#define	CONN_INT_REG_VALUE_OFFSET			1
#define	CONN_INT_REG_CLR_INT_MASK			0x1
#define	CONN_INT_REG_CLR_INT_OFFSET			0
#define	XCONN_INT_REG_REASON_MASK			0x70000
#define	XCONN_INT_REG_REASON_OFFSET			16
#define	XCONN_INT_REG_LMEP_NUM_MASK			0xFFFC
#define	XCONN_INT_REG_LMEP_NUM_OFFSET		2
#define	XCONN_INT_REG_VALUE_MASK			0x2
#define	XCONN_INT_REG_VALUE_OFFSET			1
#define	XCONN_INT_REG_CLR_INT_MASK			0x1
#define	XCONN_INT_REG_CLR_INT_OFFSET		0
#define	RMEP_ERR_INT_REG_REASON_MASK		0x70000
#define	RMEP_ERR_INT_REG_REASON_OFFSET		16
#define	RMEP_ERR_INT_REG_LMEP_NUM_MASK		0xFFFC
#define	RMEP_ERR_INT_REG_LMEP_NUM_OFFSET	2
#define	RMEP_ERR_INT_REG_VALUE_MASK			0x2
#define	RMEP_ERR_INT_REG_VALUE_OFFSET		1
#define	RMEP_ERR_INT_REG_CLR_INT_MASK		0x1
#define	RMEP_ERR_INT_REG_CLR_INT_OFFSET		0
#define	RMEP_ERR_INT_REG_LMEP_NUM_MASK		0xFFFC
#define	RMEP_ERR_INT_REG_LMEP_NUM_OFFSET	2
#define	RMEP_ERR_INT_REG_VALUE_MASK			0x2
#define	RMEP_ERR_INT_REG_VALUE_OFFSET		1
#define	RMEP_ERR_INT_REG_CLR_INT_MASK		0x1
#define	RMEP_ERR_INT_REG_CLR_INT_OFFSET		0
#define	SA_CNG_INT_REG_LMEP_NUM_MASK		0x7FFE
#define	SA_CNG_INT_REG_LMEP_NUM_OFFSET		1
#define	SA_CNG_INT_REG_CLR_INT_MASK			0x1
#define	SA_CNG_INT_REG_CLR_INT_OFFSET		0
#define	RDI_CNG_INT_REG_VALUE_MASK			0x8000
#define	RDI_CNG_INT_REG_VALUE_OFFSET		15
#define	RDI_CNG_INT_REG_RMEP_NUM_MASK		0x7FFE
#define	RDI_CNG_INT_REG_RMEP_NUM_OFFSET		1
#define	RDI_CNG_INT_REG_CLR_INT_MASK		0x1
#define	RDI_CNG_INT_REG_CLR_INT_OFFSET		0
#define	TLV_CNG_INT_REG_RMEP_NUM_MASK		0x7FFE
#define	TLV_CNG_INT_REG_RMEP_NUM_OFFSET		1
#define	TLV_CNG_INT_REG_CLR_INT_MASK		0x1
#define	TLV_CNG_INT_REG_CLR_INT_OFFSET		0


#define	PROC_PKT_CNT_REG_ADDR	0x04000
#define	MISCONFIG_CNT_REG_ADDR	0x04004

#define	SW_RESET_CNTR_REG_ADDR	0x08000

#define	LB_CONFIG_REG_ADDR		0x09000
#define	LB_BURST_REG_ADDR		0x09004
#define	LB_BURST_SIZE_REG_ADDR	0x09008
#define	LB_RESET_REG_ADDR		0x0900c
#define	LBM_PCP_REG_ADDR		0x09010
#define	LB_HD_REG_ADDR			0x09014
#define	FRC_LLBR_SCAN_REG_ADDR	0x09018
#define	LBR_TIME_OUT_REG_ADDR	0x0901c
#define	MC_LIST_HD_REG_ADDR		0x09020
#define	LBR_ERR_REG_ADDR		0x09024
#define	CLR_LBR_ERR_REG_ADDR	0x09028
#define	LB_RATE_012_REG_ADDR	0x0902C
#define	LB_RATE_345_REG_ADDR	0x09030
#define	LB_RATE_67_REG_ADDR		0x09034

#define	LBR_ERR_REG_SEQ_ERR_FLAG_MASK			0x000000FF
#define	LBR_ERR_REG_SEQ_ERR_FLAG_OFFSET			0
#define	LBR_ERR_REG_TOUT_ERR_FLAG_MASK			0x0000FF00
#define	LBR_ERR_REG_TOUT_ERR_FLAG_OFFSET		8
#define	LBR_ERR_REG_IGDE_ALL_CHNLS_MASK			0x00FF0000
#define	LBR_ERR_REG_IGDE_ALL_CHNLS_OFFSET		16
#define	LBR_ERR_REG_IGDE_CHNL0_MASK				0x00010000
#define	LBR_ERR_REG_IGDE_CHNL0_OFFSET			16

#define LB_CONFIG_REG_PKT_SIZE_MASK				(0x00FFFFFF)
#define LB_CONFIG_REG_PKT_SIZE_OFFSET			(0)
#define LB_CONFIG_REG_BURST_MODE_EN_MASK		(0x10000000)
#define LB_CONFIG_REG_BURST_MODE_EN_OFFSET		(28)
#define LB_CONFIG_REG_PORT_SEL_MASK				(0x20000000)
#define LB_CONFIG_REG_PORT_SEL_OFFSET			(29)
#define LB_CONFIG_REG_BURST_ACTIVE_MASK			(0x80000000)
#define LB_CONFIG_REG_BURST_ACTIVE_OFFSET		(31)

#define LB_BURST_SIZE_MASK						(0x000007FF)
#define LB_BURST_SIZE_OFFSET					(0)

#define LB_BURST_REG_BURST_CNT_MASK				(0x000007FF)
#define LB_BURST_REG_BURST_CNT_OFFSET			(0)
#define LB_BURST_REG_BURST_IBG_MASK				(0xFFFFF800)
#define LB_BURST_REG_BURST_IBG_OFFSET			(11)

#define	LB_RATE_X_REG_C0C3C6_RATE_MASK			(0x000003FF)
#define	LB_RATE_X_REG_C0C3C6_RATE_OFFSET		(0)
#define	LB_RATE_X_REG_C1C4C7_RATE_MASK			(0x000FFC00)
#define	LB_RATE_X_REG_C1C4C7_RATE_OFFSET		(10)
#define	LB_RATE_X_REG_C2C5_RATE_MASK			(0x3FF00000)
#define	LB_RATE_X_REG_C2C5_RATE_OFFSET			(20)

#define	LB_RESET_REG_CHNL_DISABLE_MASK			(0x00000001)
#define	LB_RESET_REG_ALL_CHNL_RESET_MASK		(0x000000FF)
#define	LB_RESET_REG_STATS_CLR_MASK				(0x00000100)
#define	LB_RESET_REG_ALL_STATS_CLR_MASK			(0x0000FF00)

#define	PM_CFG_REG_ADDR			0x09100
#define	MIN_NUM_TX_REG_ADDR		0x09104
#define	MIN_NUM_LOSS_REG_ADDR	0x09108
#define	SEC_PNTR_REG_ADDR		0x0910C
#define	PM_NE_TX_CNTR_REG_ADDR	0x09110
#define	PM_FE_RX_CNTR_REG_ADDR	0x09114
#define	PM_FE_TX_CNTR_REG_ADDR	0x09118
#define	PM_NE_RX_CNTR_REG_ADDR	0x0911C

#define PM_CFG_REG_LMM_CNTR_MASK			0xF0000000
#define PM_CFG_REG_LMM_CNTR_OFFSET			28
#define PM_CFG_REG_DMM_BIN_SEL_MASK			0x0C000000
#define PM_CFG_REG_EN_LMM_CNTR_OFFSET		26
#define PM_CFG_REG_EN_CNTR_LOCK_MASK		0x02000000
#define PM_CFG_REG_EN_CNTR_LOCK_OFFSET		25
#define PM_CFG_REG_CNTR_LOCK_PMNUM_MASK		0x01FFFF00
#define PM_CFG_REG_CNTR_LOCK_PMNUM_OFFSET	8
#define PM_CFG_REG_FDV_SES_THRES_MASK		0x000000F0
#define PM_CFG_REG_FDV_SES_THRES_OFFSET		4
#define PM_CFG_REG_FD_SES_THRES_MASK		0x0000000F
#define PM_CFG_REG_FD_SES_THRES_OFFSET		0

#define LAT_BKT0_REG_ADDR		0x91FC		// Caution NOT a real reg... It's used as the base for the remaining Lat reg
#define LAT_BKT1_REG_ADDR		0x9200
#define LAT_BKT2_REG_ADDR		0x9204
#define LATT_BKT3_REG_ADDR		0x9208
#define JITT_BKT0_REG_ADDR		0x9208		// Caution NOT a Jitter bucket reg... It's used as the base for the remaining Jitt reg
#define JITT_BKT1_REG_ADDR		0x920C
#define JITT_BKT2_REG_ADDR		0x9210
#define JITT_BKT3_REG_ADDR		0x9214

#define RTC_VAL_LOWER_REG_ADDR	0x0A000
#define RTC_VAL_UPPER_REG_ADDR	0x0A004
#define RTC_ROLLOVER_REG_ADDR	0x0A008
#define RTC_ADJUST_REG_ADDR		0x0A00C
#define RTC_ADJ_VAL_REG_ADDR	0x0A010

#define EFM_CONFIG_REG_ADDR			0x0B000
#define EFM_DISC_REAS_REG_ADDR		0x0B004
#define EFM_DISC_ST_REG_ADDR		0x0B008
#define LAST_REM_TLV_0_REG_ADDR		0x0B010
#define LAST_REM_TLV_1_REG_ADDR		0x0B014
#define LAST_REM_TLV_2_REG_ADDR		0x0B018
#define LAST_REM_TLV_3_REG_ADDR		0x0B01C
#define ERR_FR_THRES_REG_ADDR		0x0B020
#define ERR_FR_SEC_THRES_REG_ADDR	0x0B024
#define ERR_FR_WIN_REG_ADDR			0x0B028
#define ERR_FR_SEC_WIN_REG_ADDR		0x0B02C
#define EFM_FR_0_REG_ADDR			0x0B030
#define EFM_FR_1_REG_ADDR			0x0B034
#define EFM_FR_2_REG_ADDR			0x0B038
#define EFM_FR_3_REG_ADDR			0x0B03C
#define EFM_FRS_0_REG_ADDR			0x0B040
#define EFM_FRS_1_REG_ADDR			0x0B044
#define EFM_FRS_2_REG_ADDR			0x0B048


#define CPU_PKT_CNTR_REG_ADDR			0x0C000
#define CPU_PKT_CNTR_CTRL_REG_ADDR		0x0C004
#define CPU_PKT_FIFO_TAIL_REG_ADDR		0x0C008
#define CPU_PKT_CLR_INT_REG_ADDR		0x0C00C
#define PORT_0_MAC_LOW_REG_ADDR			0x0C010
#define PORT_0_MAC_UP_REG_ADDR			0x0C014
#define CPU_SYS_PKT_CNTR_REG_ADDR		0x0C020
#define CPU_SYS_PKT_CNTR_CTRL_REG_ADDR	0x0C024
#define CPU_SYS_PKT_FIFO_TAIL_REG_ADDR	0x0C028
#define CPU_SYS_PKT_INT_CLR_REG_ADDR	0x0C02C
#define BRIDGE_RX_ADDR_DEST_REG_ADDR	0x0C030
#define	MRP_RX_ADDR_DEST_REG_ADDR		0x0C034
#define CPU_MGNT_MAC_LOW_REG_ADDR		0x0C038
#define CPU_MGNT_MAC_UP_REG_ADDR		0x0C03C
#define CPU_MGNT_VLAN_CTRL_REG_ADDR		0x0C040
#define PORT_1_MAC_LOW_REG_ADDR			0x0C044
#define PORT_1_MAC_UP_REG_ADDR			0x0C048

#define CPU_MGNT_VLAN_CTRL_VLAN_MASK			0x00000FFF
#define CPU_MGNT_VLAN_CTRL_VLAN_OFFSET			0
#define CPU_MGNT_VLAN_CTRL_MATCH_MAC_MASK		0x00001000
#define CPU_MGNT_VLAN_CTRL_MATCH_MAC_OFFSET		12
#define CPU_MGNT_VLAN_CTRL_MATCH_VLAN_MASK		0x00002000
#define CPU_MGNT_VLAN_CTRL_MATCH_VLAN_OFFSET	13
#define CPU_MGNT_VLAN_CTRL_TUNNEL_TAG_MASK		0xFFFF0000
#define CPU_MGNT_VLAN_CTRL_TUNNEL_TAG_OFFSET	16

#define CPU_PKT_CNTR_MASK					0xFF
#define CPU_PKT_FIFO_TAIL_PKT_TAIL_OFFSET 	0
#define CPU_PKT_FIFO_TAIL_INFO_TAIL_OFFSET 	12
#define CPU_PKT_FIFO_TAIL_PKT_TAIL_MASK 	0x00000FFF
#define CPU_PKT_FIFO_TAIL_INFO_TAIL_MASK 	0x000FF000

#define CPU_PKT_CNTR_CTRL_FLUSH_FIFO_MASK	0x1
#define CPU_PKT_CNTR_CTRL_DEC_PKT_MASK		0x2
#define CPU_PKT_CNTR_CTRL_DEBUG_FIFO_THRESH_MASK		0x20180			//Default Sys Fifo full and Almost full threshold values

#define CPU_SYS_PKT_CNTR_MASK					0xFF
#define CPU_SYS_PKT_FIFO_TAIL_PKT_TAIL_OFFSET 	0
#define CPU_SYS_PKT_FIFO_TAIL_INFO_TAIL_OFFSET 	12
#define CPU_SYS_PKT_FIFO_TAIL_PKT_TAIL_MASK 	0x00000FFF
#define CPU_SYS_PKT_FIFO_TAIL_INFO_TAIL_MASK 	0x000FF000

#define CPU_SYS_PKT_CNTR_CTRL_FLUSH_FIFO_MASK	0x1
#define CPU_SYS_PKT_CNTR_CTRL_DEC_PKT_MASK		0x2

#define CPU_SYS_PKT_INT_CLR_MASK				0x1

#define POLICE_FWD_CLASS_REG_ADDR	0x0D100
#define POLICE_VLAN_CFG0_REG_ADDR	0x0D104
#define POLICE_VLAN_CFG1_REG_ADDR	0x0D108
#define POLICE_VLAN_CFG2_REG_ADDR	0x0D110
#define POLICE_VLAN_CFG3_REG_ADDR	0x0D114
#define POLICE_VLAN_CFG4_REG_ADDR	0x0D118
#define POLICE_VLAN_CFG5_REG_ADDR	0x0D11C
#define POLICE_VLAN_CFG6_REG_ADDR	0x0D120
#define POLICE_VLAN_CFG7_REG_ADDR	0x0D124

// Bit masks for POLICE_VLAN_CFG0-7
#define	POLICE_VLAN_CFG_REG_VLAN_E_MASK				0x00000FFF
#define	POLICE_VLAN_CFG_REG_VLAN_E_OFFSET			0
#define	POLICE_VLAN_CFG_REG_VLAN_O_MASK				0x00FFF000
#define	POLICE_VLAN_CFG_REG_VLAN_O_OFFSET			12
#define	POLICE_VLAN_CFG_REG_VLAN_ONLY_E_MASK		0x01000000
#define	POLICE_VLAN_CFG_REG_VLAN_ONLY_E_OFFSET		24
#define	POLICE_VLAN_CFG_REG_VLAN_ONLY_O_MASK		0x02000000
#define	POLICE_VLAN_CFG_REG_VLAN_ONLY_O_OFFSET		25
#define	POLICE_VLAN_CFG_REG_DSCP_ONLY_E_MASK		0x04000000
#define	POLICE_VLAN_CFG_REG_DSCP_ONLY_E_OFFSET		26
#define	POLICE_VLAN_CFG_REG_DSCP_ONLY_O_MASK		0x08000000
#define	POLICE_VLAN_CFG_REG_DSCP_ONLY_O_OFFSET		27

// Bit masks for POLICE_FWD_CLASS_REG
#define POLICE_FWD_CLASS_REG_PCP_MODE_MASK		0x01000000
#define POLICE_FWD_CLASS_REG_PCP_MODE_OFFSET	24
#define POLICE_FWD_CLASS_REG_EN_MASK			0x02000000
#define POLICE_FWD_CLASS_REG_EN_OFFSET			25
#define POLICE_FWD_CLASS_REG_PORT_ONLY_MASK		0x0C000000
#define POLICE_FWD_CLASS_REG_PORT_ONLY_OFFSET	26

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for RPT_EN_REG_ADDR */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	HW_INT_DISABLE	0x100		//Hardware Interrupt disable bit (bit 8 of register)
/* ----------------------------------------------------------------------------------------------------------------------------------*/


/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for the Interrupt MASK generation */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	DISABLE_ALL_INT_MASK		0x0000
#define	PROBE_STORE_FULL_INT_MASK	0x0001
#define	CONN_INT_MASK				0x0002
#define	XCONN_INT_MASK				0x0004
#define	RMEP_ERR_INT_MASK			0x0008
#define	SA_CNG_INT_MASK				0x0010
#define	RDI_CNG_INT_MASK			0x0020
#define ANY_TLV_CNG_INT_MASK		0x0040
#define	RSVD_1_INT_MASK				0x0080
#define	RSVD_2_INT_MASK				0x0100
#define	RSVD_3_INT_MASK				0x0200
#define RSVD_4_INT_MASK				0x0400
#define EFM_DISC_INT_MASK			0x0800
#define CAPT_PKT_INT_MASK			0x1000
#define SYS_CAPT_PKT_INT_MASK		0x2000
#define EFM_FR_INT_MASK				0x4000
#define EFM_FRS_INT_MASK			0x8000

/* ----------------------------------------------------------------------------------------------------------------------------------*/

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for the Report MASK enable/disable */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	DISABLE_ALL_RPT_MASK		0
#define	CONN_RPT_MASK				1
#define	XCONN_RPT_MASK				2
#define	RMEP_ERR_RPT_MASK			4
#define	SA_CNG_RPT_MASK				8
#define	RDI_CNG_RPT_MASK			16
#define PS_TLV_CNG_RPT_MASK			32
#define IS_TLV_CNG_RPT_MASK			64
#define SEND_TLV_CNG_RPT_MASK		128
#define ORG_TLV_CNG_RPT_MASK		256

/* ----------------------------------------------------------------------------------------------------------------------------------*/

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for CCM Packet Validation */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	CHK_DISABLE_ALL				0
#define	CHK_MD_NAME_LEN				1
#define	CHK_SHORT_MA_NAME_PRES		2
#define	CHK_SHORT_MA_NAME_LEN		4
#define	CHK_CHASSID_ID_LEN			8
#define	CHK_SENDER_TLV_LEN			16
#define CHK_SA_MAC_UNI				32
#define CHK_PS_TLV_VALUE			64
#define CHK_IF_TLV_VALUE			128
#define CHK_MR_CCM_1ST_OFFSET			256
#define CHK_MEPID					512
#define CHK_FORCE_ETLV				1024
#define CHK_ALL						0x7FF
/* ----------------------------------------------------------------------------------------------------------------------------------*/

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants used for CCM Packet Validation */
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	MC_LIST_HEAD_MASK		0x7F
#define MC_LIST_FULL_MASK		0x40

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants for ROW Access to PM Stats RAM entries*/
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define PM_STATS_RAM_FL_THRES_ROW		0
#define PM_STATS_RAM_LAST_NE_TX_ROW		1
#define PM_STATS_RAM_LAST_FE_RX_ROW		2
#define PM_STATS_RAM_NE_TX_CNTR_ROW		3
#define PM_STATS_RAM_FE_RX_CNTR_ROW		4
#define PM_STATS_RAM_LAST_FE_TX_ROW		5
#define PM_STATS_RAM_LAST_NE_RX_ROW		6
#define PM_STATS_RAM_FE_TX_CNTR_ROW		7
#define PM_STATS_RAM_NE_RX_CNTR_ROW		8
#define PM_STATS_RAM_SES_CNTR_ROW		12
#define PM_STATS_RAM_ES_CNTR_ROW		13
#define PM_STATS_RAM_ALM_MEP_NUMS_ROW	15
#define PM_STATS_RAM_LAST_JITTER_ROW	16
#define PM_STATS_RAM_LAST_DELAY_ROW		17
#define PM_STATS_RAM_FD_PKT_CNTR_ROW	18
#define PM_STATS_RAM_SUM_LAT_LOW_ROW	19
#define PM_STATS_RAM_SUM_LAT_UPP_ROW	20
#define PM_STATS_RAM_SUM_JITT_LOW_ROW	21
#define PM_STATS_RAM_SUM_JITT_UPP_ROW	22
#define PM_STATS_RAM_FD_THRES_ROW		23
#define PM_STATS_RAM_FD_ERR_CNTR_ROW	24
#define PM_STATS_RAM_FDV_THRES_ROW		25
#define PM_STATS_RAM_FDV_ERR_CNTR_ROW	26
#define PM_STATS_RAM_MIN_LAT_ROW		27
#define PM_STATS_RAM_MAX_LAT_ROW		28
#define PM_STATS_RAM_MIN_JITT_ROW		29
#define PM_STATS_RAM_MAX_JITT_ROW		30
#define PM_STATS_RAM_LAT_BKT0_ROW		31
#define PM_STATS_RAM_LAT_BKT1_ROW		32
#define PM_STATS_RAM_LAT_BKT2_ROW		33
#define PM_STATS_RAM_LAT_BKT3_ROW		34
#define PM_STATS_RAM_JITT_BKT0_ROW		35
#define PM_STATS_RAM_JITT_BKT1_ROW		36
#define PM_STATS_RAM_JITT_BKT2_ROW		37
#define PM_STATS_RAM_JITT_BKT3_ROW		38

/* ----------------------------------------------------------------------------------------------------------------------------------*/
/* Define Constants for Field Access to PM Stats RAM entries*/
/* ----------------------------------------------------------------------------------------------------------------------------------*/
#define	PM_STATS_RAM_EN_DTL_PM_MASK			0x00000040
#define	PM_STATS_RAM_EN_DTL_PM_OFFSET		6
#define	PM_STATS_RAM_ES_FLAG_MASK			0x00000004
#define	PM_STATS_RAM_ES_FLAG_OFFSET			2
#define	PM_STATS_RAM_SES_FLAG_MASK			0x00000008
#define	PM_STATS_RAM_SES_FLAG_OFFSET		3
#define	PM_STATS_RAM_EN_1LMR_MASK			0x01000000
#define	PM_STATS_RAM_EN_1LMR_OFFSET			24
#define	PM_STATS_RAM_LOSS_CFG_MASK			0x10000000
#define	PM_STATS_RAM_LOSS_CFG_OFFSET		28
#define	PM_STATS_RAM_DLY_CFG_MASK			0x20000000
#define	PM_STATS_RAM_DLY_CFG_OFFSET			29
#define	PM_STATS_RAM_EN_ALM_MASK			0x40000000
#define	PM_STATS_RAM_EN_ALM_OFFSET			30
#define	PM_STATS_RAM_LMEP_NUM_MASK			0x00003FFF
#define	PM_STATS_RAM_LMEP_NUM_OFFSET		0
#define	PM_STATS_RAM_RMEP_NUM_MASK			0x0FFFC000
#define	PM_STATS_RAM_RMEP_NUM_OFFSET		14
#define	PM_STATS_RAM_EN_FL_MASK				0x04000000
#define	PM_STATS_RAM_EN_FL_OFFSET			26
#define PM_STATS_RAM_FLT_DIV_128_MASK		0x02000000
#define	PM_STATS_RAM_FLT_DIV_128_OFFSET		25
#define PM_STATS_RAM_FL_THRES_MASK			0x00FFFF80
#define PM_STATS_RAM_FL_THRES_OFFSET		7
#define PM_STATS_RAM_FIRST_LMR_MASK			0x01000000
#define PM_STATS_RAM_FIRST_LMR_OFFSET		24
#define PM_STATS_RAM_FD_THRES_MASK			0x00FFFFF0
#define PM_STATS_RAM_FD_THRES_OFFSET		4
#define PM_STATS_RAM_FD_ERR_CNTR_MASK		0x0000000F
#define PM_STATS_RAM_FD_ERR_CNTR_OFFSET		0
#define PM_STATS_RAM_FDV_THRES_MASK			0x00FFFFF0
#define PM_STATS_RAM_FDV_THRES_OFFSET		4
#define PM_STATS_RAM_FDV_ERR_CNTR_MASK		0x0000000F
#define PM_STATS_RAM_FDV_ERR_CNTR_OFFSET	0
#define PM_STATS_RAM_EN_FD_MASK				0x04000000
#define PM_STATS_RAM_EN_FD_OFFSET			26
#define PM_STATS_RAM_LAST_DELAY_MASK		0x3FFFFFFF
#define PM_STATS_RAM_LAST_DELAY_OFFSET		0
#define PM_STATS_RAM_FIRST_RX_MASK			0xC0000000
#define PM_STATS_RAM_FIRST_RX_OFFSET		30

// TX_LMEP_NUM_RAM bit masks
#define TX_LMEP_NUM_RAM_CCM_MASK			0xFF000000
#define TX_LMEP_NUM_RAM_PM_MASK				0x00FFFFFF

#define TX_LMEP_NUM_RAM_CCM_VALID_MASK		0x80000000
#define TX_LMEP_NUM_RAM_CCM_VALID_OFFSET	31
#define TX_LMEP_NUM_RAM_CCM_EN_MASK			0x40000000
#define TX_LMEP_NUM_RAM_CCM_EN_OFFSET		30
#define TX_LMEP_NUM_RAM_CCM_INT_MASK		0x38000000
#define TX_LMEP_NUM_RAM_CCM_INT_OFFSET		27
#define TX_LMEP_NUM_RAM_CCM_AIS_MASK		0x04000000
#define TX_LMEP_NUM_RAM_CCM_AIS_OFFSET		26
#define TX_LMEP_NUM_RAM_CCM_LCK_MASK		0x02000000
#define TX_LMEP_NUM_RAM_CCM_LCK_OFFSET		25
#define TX_LMEP_NUM_RAM_CCM_PORT_MASK		0x01000000
#define TX_LMEP_NUM_RAM_CCM_PORT_OFFSET		24

#define PM_NUM_RAM_PM_VALID_MASK		0x00800000
#define PM_NUM_RAM_PM_VALID_OFFSET		23
#define PM_NUM_RAM_DELAY_EN_MASK		0x00400000
#define PM_NUM_RAM_DELAY_EN_OFFSET		22
#define PM_NUM_RAM_LOSS_EN_MASK			0x00200000
#define PM_NUM_RAM_LOSS_EN_OFFSET		21
#define PM_NUM_RAM_IDM_SVC_MASK			0x00100000
#define PM_NUM_RAM_IDM_SVC_OFFSET		20
#define PM_NUM_RAM_SLM_SVC_MASK			0x00080000
#define PM_NUM_RAM_SLM_SVC_OFFSET		19
#define PM_NUM_RAM_DMM_SVC_MASK			0x00040000
#define PM_NUM_RAM_DMM_SVC_OFFSET		18
#define PM_NUM_RAM_LOSS_INT_MASK		0x00038000
#define PM_NUM_RAM_LOSS_INT_OFFSET		15
#define PM_NUM_RAM_DLY_INT_MASK			0x00007000
#define PM_NUM_RAM_DLY_INT_OFFSET		12
#define PM_NUM_RAM_PORT_MASK			0x00000800
#define PM_NUM_RAM_PORT_OFFSET			11
#define	PM_NUM_RAM_PM_SVC_FIELD_MASK	0x00F80000
#define PM_NUM_RAM_PM_SVC_FIELD_OFFSET	19

#if 0
#define PM_NUM_RAM_PM_LMEP_NUM_MASK		0x00003FFF
#define PM_NUM_RAM_PM_LMEP_NUM_OFFSET	0
#define PM_NUM_RAM_PM_PRIO_MASK			0x0001C000
#define PM_NUM_RAM_PM_PRIO_OFFSET		14
#define PM_NUM_RAM_PM_RMEP_NUM_MASK		0x7FFE0000
#define PM_NUM_RAM_PM_RMEP_NUM_OFFSET	17
#endif


// Constants for accessing the vlanInfo Table
#define	VLAN_INFO_RAM_CFM_IDX_MASK				0x000000FF
#define VLAN_INFO_RAM_CFM_IDX_OFFSET			0
#define	VLAN_INFO_RAM_EVC_IDX_MASK				0x00007F00
#define VLAN_INFO_RAM_EVC_IDX_OFFSET			8
#define	VLAN_INFO_RAM_CFM_VALID_MASK			0x00008000
#define VLAN_INFO_RAM_CFM_VALID_OFFSET			15
#define	VLAN_INFO_RAM_VLAN_FILT_MASK			0x00010000
#define VLAN_INFO_RAM_VLAN_FILT_OFFSET			16
#define	VLAN_INFO_RAM_VLAN_FILT_RESTORE_MASK	0x00020000
#define VLAN_INFO_RAM_VLAN_FILT_RESTORE_OFFSET	17

// Constants for accessing the dirLvl Table
#define	DIR_LVL_TBL_DOWN_MASK				0x000000FF
#define DIR_LVL_TBL_DOWN_OFFSET				0
#define	DIR_LVL_TBL_UP_MASK					0x0000FF00
#define DIR_LVL_TBL_UP_OFFSET				8
#define	DIR_LVL_TBL_LIST_IDX_MASK			0x3FFF0000
#define DIR_LVL_TBL_LIST_IDX_OFFSET			16
#define	DIR_LVL_TBL_MIP_DOWN_MASK			0x000000FF
#define DIR_LVL_TBL_MIP_DOWN_OFFSET			0
#define	DIR_LVL_TBL_MIP_UP_MASK				0x0000FF00
#define DIR_LVL_TBL_MIP_UP_OFFSET			8
#define DIR_LVL_NOT_IN_USE_MASK				0x80000000

// Constants for accessing the rxLMepNum RAM
// lower segment of rxLMepNum RAM:
#define	RX_LMEP_NOT_IN_USE_MASK					0x00000003	// The LSB 2 bits have dual purpose. 00 or 11 means not in use; 01=MEP, 10=MIP
#define	RX_LMEP_NOT_IN_USE_OFFSET				0
#define	RX_LMEP_MP_TYPE_MASK					0x00000003	// The LSB 2 bits have dual purpose. 00 or 11 means not in use; 01=MEP, 10=MIP
#define	RX_LMEP_MP_TYPE_OFFSET					0
#define	RX_LMEP_NUM_LVL_MASK_MASK				0x000003FC
#define	RX_LMEP_NUM_LVL_MASK_OFFSET				2
#define	RX_LMEP_NUM_RAM_IDM_PRIO_MASK			0x00001C00
#define RX_LMEP_NUM_RAM_IDM_PRIO_OFFSET			10
// upper segment of rxLMepNum RAM:
#define	RX_LMEP_NUM_RAM_LMEP_NUM_MASK			0x000003FF
#define RX_LMEP_NUM_RAM_LMEP_NUM_OFFSET			0
#define	RX_LMEP_NUM_RAM_IDM_PM_NUM_MASK			0x003FFC00
#define RX_LMEP_NUM_RAM_IDM_PM_NUM_OFFSET		10
#define	RX_LMEP_NUM_RAM_MEP_ENABLE_MASK			0x00400000
#define RX_LMEP_NUM_RAM_MEP_ENABLE_OFFSET		22

// Constants for accessing the lMep RAM
#define	LMEP_RAM_MEPID_MASK					0x00001FFF
#define LMEP_RAM_MEPID_OFFSET				0
#define	LMEP_RAM_INTERVAL_MASK				0x0000E000
#define LMEP_RAM_INTERVAL_OFFSET			13
#define LMEP_RAM_MA_NUM_MASK				0x00FF0000
#define LMEP_RAM_MA_NUM_OFFSET				16
#define LMEP_RAM_MD_NUM_MASK				0xFF000000
#define LMEP_RAM_MD_NUM_OFFSET				24
#define LMEP_NOT_IN_USE_MASK				0xFFFF0000

// Constants for accessing the rMep DB RAM
#define	RMEP_DB_RAM_TLV_DWORD_SIZE			14
#define RMEP_DB_NOT_IN_USE_MASK				0x80000000
#define	RMEP_DB_RAM_MEPID_MASK				0xFFF80000
#define RMEP_DB_RAM_MEPID_OFFSET			19
#define	RMEP_DB_RAM_RMEP_IDX_MASK			0x00003FFF
#define RMEP_DB_RAM_RMEP_IDX_OFFSET			0
#define	RMEP_DB_RAM_SEQ_NUM_MASK			0xFFFFFFFF
#define	RMEP_DB_RAM_SEQ_NUM_OFFSET			0
#define	RMEP_DB_RAM_PRIO_0_LC_MASK			0x00007FFF
#define	RMEP_DB_RAM_PRIO_0_LC_OFFSET		0
#define	RMEP_DB_RAM_PRIO_0_LC_VAL_MASK		0x00008000
#define	RMEP_DB_RAM_PRIO_0_LC_VAL_OFFSET	15
#define	RMEP_DB_RAM_PRIO_1_LC_MASK			0x7FFF0000
#define	RMEP_DB_RAM_PRIO_1_LC_OFFSET		16
#define	RMEP_DB_RAM_PRIO_1_LC_VAL_MASK		0x80000000
#define	RMEP_DB_RAM_PRIO_1_LC_VAL_OFFSET	31
#define	RMEP_DB_RAM_PRIO_2_LC_MASK			0x00007FFF
#define	RMEP_DB_RAM_PRIO_2_LC_OFFSET		0
#define	RMEP_DB_RAM_PRIO_2_LC_VAL_MASK		0x00008000
#define	RMEP_DB_RAM_PRIO_2_LC_VAL_OFFSET	15
#define	RMEP_DB_RAM_PRIO_3_LC_MASK			0x7FFF0000
#define	RMEP_DB_RAM_PRIO_3_LC_OFFSET		16
#define	RMEP_DB_RAM_PRIO_3_LC_VAL_MASK		0x80000000
#define	RMEP_DB_RAM_PRIO_3_LC_VAL_OFFSET	31
#define	RMEP_DB_RAM_PRIO_4_LC_MASK			0x00007FFF
#define	RMEP_DB_RAM_PRIO_4_LC_OFFSET		0
#define	RMEP_DB_RAM_PRIO_4_LC_VAL_MASK		0x00008000
#define	RMEP_DB_RAM_PRIO_4_LC_VAL_OFFSET	15
#define	RMEP_DB_RAM_PRIO_5_LC_MASK			0x7FFF0000
#define	RMEP_DB_RAM_PRIO_5_LC_OFFSET		16
#define	RMEP_DB_RAM_PRIO_5_LC_VAL_MASK		0x80000000
#define	RMEP_DB_RAM_PRIO_5_LC_VAL_OFFSET	31
#define	RMEP_DB_RAM_PRIO_6_LC_MASK			0x00007FFF
#define	RMEP_DB_RAM_PRIO_6_LC_OFFSET		0
#define	RMEP_DB_RAM_PRIO_6_LC_VAL_MASK		0x00008000
#define	RMEP_DB_RAM_PRIO_6_LC_VAL_OFFSET	15
#define	RMEP_DB_RAM_PRIO_7_LC_MASK			0x7FFF0000
#define	RMEP_DB_RAM_PRIO_7_LC_OFFSET		16
#define	RMEP_DB_RAM_PRIO_7_LC_VAL_MASK		0x80000000
#define	RMEP_DB_RAM_PRIO_7_LC_VAL_OFFSET	31

// Constants for accessing the rMep RAM (trie Table)
/*
#define	RMEP_TBL_NOT_IN_USE_MASK			0x0003FFE0
#define	RMEP_TBL_RAM_RMEP_NUM_MASK			0x0000001F
#define	RMEP_TBL_RAM_RMEP_NUM_OFFSET		0
#define	RMEP_TBL_RAM_MEPID_MASK				0x0003FFE0
#define	RMEP_TBL_RAM_MEPID_OFFSET			5
*/
#define	RMEP_TBL_NOT_IN_USE_MASK			0x00001FFF
#define	RMEP_TBL_RAM_MEPID_MASK				0x00001FFF
#define	RMEP_TBL_RAM_MEPID_OFFSET			0
#define	RMEP_TBL_RAM_RMEP_NUM_MASK			0x001FE000
#define	RMEP_TBL_RAM_RMEP_NUM_OFFSET		13

// Constants for accessing the TxTemplate RAM (trie Table)
#define TX_TEMPL_RAM_DELAY_PKT_SIZE_MASK	0x00003FFF
#define TX_TEMPL_RAM_DELAY_PKT_SIZE_OFFSET	0
#define TX_TEMPL_RAM_LOSS_PKT_SIZE_MASK		0x0FFFC000
#define TX_TEMPL_RAM_LOSS_PKT_SIZE_OFFSET	14
#define TX_TEMPL_RAM_HDR_SIZE_MASK			0xF0000000
#define TX_TEMPL_RAM_HDR_SIZE_OFFSET		28


// Constants for accessing the LBR LMepNum RAM
#define LBR_LMEP_NUM_RAM_EVEN_LMEP_NUM_MASK		0x7FFF
#define LBR_LMEP_NUM_RAM_EVEN_LMEP_NUM_OFFSET	0
#define LBR_LMEP_NUM_RAM_EVEN_MC_MASK			0x8000
#define LBR_LMEP_NUM_RAM_EVEN_MC_OFFSET			15
#define LBR_LMEP_NUM_RAM_ODD_LMEP_NUM_MASK		0x7FFF0000
#define LBR_LMEP_NUM_RAM_ODD_LMEP_NUM_OFFSET	16
#define LBR_LMEP_NUM_RAM_ODD_MC_MASK			0x80000000
#define LBR_LMEP_NUM_RAM_ODD_MC_OFFSET			31

// Constants for accessing the Policer Config RAM
#define POL_CFG_RAM_CBS_EBS_DWORD			0
#define POL_CFG_RAM_CIR_DWORD				1
#define POL_CFG_RAM_EIR_DWORD				2
#define POL_CFG_RAM_COUPLING_DWORD			3
#define POL_CFG_RAM_CBS_MASK				0x0000FFFF
#define POL_CFG_RAM_CBS_OFFSET				0
#define POL_CFG_RAM_EBS_MASK				0xFFFF0000
#define POL_CFG_RAM_EBS_OFFSET				16
#define POL_CFG_RAM_CIR_MASK				0xFFFFFFFF
#define POL_CFG_RAM_CIR_OFFSET				0
#define POL_CFG_RAM_EIR_MASK				0xFFFFFFFF
#define POL_CFG_RAM_EIR_OFFSET				0
#define POL_CFG_RAM_COUPLING_MASK			0x00000001
#define POL_CFG_RAM_COUPLING_OFFSET			0
#define POL_CFG_RAM_COLOR_MODE_MASK			0x00000002
#define POL_CFG_RAM_COLOR_MODE_OFFSET		1

// Constants for accessing the Policer Stats RAM
#define POL_CFG_RAM_GREEN_DWORD				0
#define POL_CFG_RAM_YELLOW_DWORD			1
#define POL_CFG_RAM_RED_DWORD				2
#define POL_CFG_RAM_DISCARD_DWORD			3

// Constants for accessing the CPU Captured INFO FIFO
#define CPU_CAPT_INFO_FIFO_PKT_REASON_MASK		0x0000001F
#define CPU_CAPT_INFO_FIFO_PKT_REASON_OFFSET	0
#define CPU_CAPT_INFO_FIFO_PKT_SIZE_MASK		0x0001FFE0
#define CPU_CAPT_INFO_FIFO_PKT_SIZE_OFFSET		5

// Constants for accessing the I2C interface in the SFP hardware
#define I2C_PIN_STATS_REG_ADDR		(0xD000)
#define I2C_CTRL_REG_ADDR			(0xD004)
#define I2C_VERSION_REG_ADDR		(0xD008)
#define I2C_CLK_CNTR_REG_ADDR		(0xD00C)
#define I2C_LPDDR_RESULT_REG_ADDR	(0xD010)

#define I2C_PIN_STATS_LOS_MASK					(0x01)		// Write to 1 when MACs are initialised
#define I2C_PIN_STATS_START_LPDDR_TEST_MASK		(0x20)
#define I2C_PIN_STATS_LPDDR_TEST_RUNNING_MASK	(0x40)

#define I2C_CTRL_ENABLE_OPTICS_MASK				(0x20)
#define I2C_CTRL_DISABLE_OPTICS_MASK			(0x10)

//Constants for accessing the SA Filter table
#define SA_FILTER_RANGE0_REG_ADDR		(0xD020)
#define SA_FILTER_RANGE1_REG_ADDR		(0xD024)
#define SA_FILTER_RANGE2_REG_ADDR		(0xD028)
#define SA_FILTER_RANGE3_REG_ADDR		(0xD02C)
#define SA_FILTER_RANGE4_REG_ADDR		(0xD034)
#define SA_FILTER_RANGE5_REG_ADDR		(0xD038)
#define SA_FILTER_RANGE6_REG_ADDR		(0xD03C)
#define SA_FILTER_RANGE7_REG_ADDR		(0xD040)
#define SA_FILTER_RANGE8_REG_ADDR		(0xD044)
#define SA_FILTER_RANGE9_REG_ADDR		(0xD048)

// Constants for accessing the EVC Table
#define EVC_TBL_TX_VID_MASK						(0x00000FFF)
#define EVC_TBL_TX_VID_OFFSET					(0)
#define EVC_TBL_PUSH_TAG_TYPE_MASK				(0x00001000)
#define EVC_TBL_PUSH_TAG_TYPE_OFFSET			(12)
#define EVC_TBL_TAG_ACTION_MASK					(0x00006000)
#define EVC_TBL_TAG_ACTION_OFFSET				(13)
#define EVC_TBL_COS_DSCP_MASK					(0x00008000)
#define EVC_TBL_COS_DSCP_OFFSET					(15)
#define EVC_TBL_USE_PCP_EVC_COL_MASK			(0x00010000)
#define EVC_TBL_USE_PCP_EVC_COL_OFFSET			(16)
#define EVC_TBL_COS_PRESERVE_MASK				(0x00020000)
#define EVC_TBL_COS_PRESERVE_OFFSET				(17)

#define EVC_TBL_RX_HIGHEST_MEP_LVL_MASK			(0x00000007)
#define EVC_TBL_RX_HIGHEST_MEP_LVL_OFFSET		(0)
#define EVC_TBL_RX_HIGHEST_MEP_LVL_VAL_MASK		(0x00000008)
#define EVC_TBL_RX_HIGHEST_MEP_LVL_VAL_OFFSET	(3)
#define EVC_TBL_TX_HIGHEST_MEP_LVL_MASK			(0x00000070)
#define EVC_TBL_TX_HIGHEST_MEP_LVL_OFFSET		(4)
#define EVC_TBL_TX_HIGHEST_MEP_LVL_VAL_MASK		(0x00000080)
#define EVC_TBL_TX_HIGHEST_MEP_LVL_VAL_OFFSET	(7)


// Constants for accessing the COS Tables
#define COS_TBL_PRIO_MASK		(0xE)
#define COS_TBL_PRIO_OFFSET		(1)
#define COS_TBL_DE_MASK			(0x1)
#define COS_TBL_DE_OFFSET		(0)
#define	DSCP_TBL_DISCARD_MASK	(0x10)
#define DSCP_TBL_DISCARD_OFFSET	(4)

// Constants for accessing the Flow Num Table
#define FLOW_NUM_TBL_PCP_EVC_COL_MASK		(0x00000001)
#define FLOW_NUM_TBL_PCP_EVC_COL_OFFSET		(0)
#define FLOW_NUM_TBL_MAP_PCP_PRIO_MASK		(0x0000000E)
#define FLOW_NUM_TBL_MAP_PCP_PRIO_OFFSET	(1)
#define FLOW_NUM_TBL_PCP_DISCARD_MASK		(0x00000010)
#define FLOW_NUM_TBL_PCP_DISCARD_OFFSET		(4)
#define FLOW_NUM_TBL_COL_FWD_MASK			(0x00000020)
#define FLOW_NUM_TBL_COL_FWD_OFFSET			(5)
#define FLOW_NUM_TBL_COL_AWARE_MASK			(0x00000040)
#define FLOW_NUM_TBL_COL_AWARE_OFFSET		(6)
#define FLOW_NUM_TBL_FLOW_NUM_MASK			(0x0000FF80)
#define FLOW_NUM_TBL_FLOW_NUM_OFFSET		(7)
#endif
