# Creating SmartDesign "top"
set sd_name {PF_EVALKIT_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {IRQ_28} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IRQ_30} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REFCLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX1_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX1_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {LINK_OK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDC} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RD_BC_ERROR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_SEL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISCLKO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SPISS} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX1_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX1_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {coma_mode} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {PHY_MDIO} -port_direction {INOUT} -port_is_pad {1}


sd_invert_pins -sd_name ${sd_name} -pin_names {coma_mode}
# Add AND2_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_2}



# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}



# Add core_jatg_debug_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {core_jatg_debug_0} -instance_name {core_jatg_debug_0_0}



# Add Core_reset_pf_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Core_reset_pf} -instance_name {Core_reset_pf_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Core_reset_pf_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Core_reset_pf_0:FF_US_RESTORE} -value {GND}



# Add CoreAPB3_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0_0}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave0} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave0} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave0} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave0} -pin_names {CoreAPB3_0_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave1} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave1} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave1} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave1} -pin_names {CoreAPB3_0_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave2} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave2} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave2} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave2} -pin_names {CoreAPB3_0_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave3} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave3} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave3} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave3} -pin_names {CoreAPB3_0_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PSELS4}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PRDATAS4}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PREADYS4}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave4} -pin_names {CoreAPB3_0_0:PSLVERRS4}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave5} -pin_names {CoreAPB3_0_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave5} -pin_names {CoreAPB3_0_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave5} -pin_names {CoreAPB3_0_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreAPB3_0_0:APBmslave5} -pin_names {CoreAPB3_0_0:PWDATAS}



# Add COREAXI4INTERCONNECT_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAXI4INTERCONNECT_C0} -instance_name {COREAXI4INTERCONNECT_C0_0}



# Add CORESPI_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORESPI_0} -instance_name {CORESPI_0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[4:4]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[6:6]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_0_0:SPISS} -pin_slices {[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISS[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPIINT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPIRXAVAIL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPITXRFM}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPISSI} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPICLKI} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPIOEN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_0_0:SPIMODE}



# Add CORETSE_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORETSE_0} -instance_name {CORETSE_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:MRXDAT} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:MRXDAT} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:MRXDAT} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:MRXDAT} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[0:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[4:4]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[6:6]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[8:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_0:ANX_STATE} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:ANX_STATE[9:9]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_0:STBP} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_0:MTXCFRM} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:MTXHWM}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_0:SIGNAL_DETECT} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:SYNC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:TSM_INTR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_0:TSM_CONTROL}



# Add CORETSE_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORETSE_0} -instance_name {CORETSE_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:MRXDAT} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:MRXDAT} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:MRXDAT} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:MRXDAT} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[0:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[4:4]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[6:6]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[8:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[8:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORETSE_1:ANX_STATE} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:ANX_STATE[9:9]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_1:STBP} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_1:MTXCFRM} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:MTXHWM}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORETSE_1:SIGNAL_DETECT} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:SYNC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:TSM_INTR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORETSE_1:TSM_CONTROL}



# Add CoreUARTapb_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR}



# Add INBUF_DIFF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INBUF_DIFF} -instance_name {INBUF_DIFF_0}



# Add MIV_RV32_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C2} -instance_name {MIV_RV32_C2_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32_C2_0:MSYS_EI} -pin_slices {[0:0]}
sd_invert_pins -sd_name ${sd_name} -pin_names {MIV_RV32_C2_0:MSYS_EI[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32_C2_0:MSYS_EI} -pin_slices {[1:1]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C2_0:MSYS_EI[1:1]} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C2_0:EXT_IRQ} -value {GND}



# Add OAM_IP_top_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Ethernet_OAM_C0} -instance_name {OAM_IP_top_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {OAM_IP_top_0:carr_mac_rx_err_in} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {OAM_IP_top_0:carr_mac_tx_err_out}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {OAM_IP_top_0:sys_mac_rx_err_in} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {OAM_IP_top_0:sys_mac_tx_err_out}



# Add PF_CCC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_0} -instance_name {PF_CCC_0_0}



# Add pf_init_monitor_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {pf_init_monitor_0} -instance_name {pf_init_monitor_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pf_init_monitor_0_0:AUTOCALIB_DONE}



# Add PF_IOD_CDR_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_CDR_C0} -instance_name {PF_IOD_CDR_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_CDR_C0_0:STREAM_START} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_CDR_C0_0:RX_VAL}



# Add PF_IOD_CDR_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_CDR_C0} -instance_name {PF_IOD_CDR_C0_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_CDR_C0_1:STREAM_START} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_CDR_C0_1:RX_VAL}



# Add PF_IOD_CDR_CCC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_IOD_CDR_CCC_C0} -instance_name {PF_IOD_CDR_CCC_C0_0}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_IOD_CDR_CCC_C0_0:CDR_CLOCKS} -pin_names {PF_IOD_CDR_CCC_C0_0:PLL_LOCK}



# Add PF_SRAM_AHBL_AXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {PF_SRAM_AHBL_AXI_C0_0}



# Add PF_SYSTEM_SERVICES_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SYSTEM_SERVICES_C0} -instance_name {PF_SYSTEM_SERVICES_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:A" "COREAXI4INTERCONNECT_C0_0:ARESETN" "CORESPI_0_0:PRESETN" "CoreUARTapb_0:PRESETN" "Core_reset_pf_0:FABRIC_RESET_N" "MIV_RV32_C2_0:RESETN" "OAM_IP_top_0:aSyncResetn" "PF_IOD_CDR_CCC_C0_0:ARST_N" "PF_SRAM_AHBL_AXI_C0_0:ARESETN" "PF_SYSTEM_SERVICES_C0_0:RESETN" "PHY_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:B" "PF_IOD_CDR_CCC_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:Y" "CORETSE_0:PRESETN" "CORETSE_1:PRESETN" "PF_IOD_CDR_C0_0:RST_N" "PF_IOD_CDR_C0_1:RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:D" "CORETSE_0:MDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "CORETSE_0:MDOEN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:PAD" "PHY_MDIO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "CORETSE_0:MDI" "CORETSE_1:MDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:ACLK" "CORESPI_0_0:PCLK" "CORETSE_0:MRXCLK" "CORETSE_0:MTXCLK" "CORETSE_0:PCLK" "CORETSE_1:MRXCLK" "CORETSE_1:MTXCLK" "CORETSE_1:PCLK" "CoreUARTapb_0:PCLK" "Core_reset_pf_0:CLK" "MIV_RV32_C2_0:CLK" "OAM_IP_top_0:cpuIfClk" "OAM_IP_top_0:macClk" "OAM_IP_top_0:sysClk" "PF_CCC_0_0:OUT0_FABCLK_0" "PF_SRAM_AHBL_AXI_C0_0:ACLK" "PF_SYSTEM_SERVICES_C0_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_0_0:SPISCLKO" "SPISCLKO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_0_0:SPISDI" "SPISDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_0_0:SPISDO" "SPISDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_0_0:SPISS[0:0]" "SPISS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:ANX_STATE[8:8]" "LINK_OK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MDC" "PHY_MDC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXACPT" "OAM_IP_top_0:carr_mac_rx_rdy_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXEOF" "OAM_IP_top_0:carr_mac_rx_eop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXRDY" "OAM_IP_top_0:carr_mac_rx_dval_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXSOF" "OAM_IP_top_0:carr_mac_rx_sop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXACPT" "OAM_IP_top_0:carr_mac_tx_rdy_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXEOF" "OAM_IP_top_0:carr_mac_tx_eop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXRDY" "OAM_IP_top_0:carr_mac_tx_dval_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXSOF" "OAM_IP_top_0:carr_mac_tx_sop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:RCG_ERROR" "RD_BC_ERROR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:RXCLK" "CORETSE_0:TBI_RX_CLK" "PF_IOD_CDR_C0_0:RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:TBI_TX_CLK" "CORETSE_0:TXCLK" "CORETSE_1:TBI_TX_CLK" "CORETSE_1:TXCLK" "PF_IOD_CDR_CCC_C0_0:TX_CLK_G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXACPT" "OAM_IP_top_0:sys_mac_rx_rdy_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXEOF" "OAM_IP_top_0:sys_mac_rx_eop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXRDY" "OAM_IP_top_0:sys_mac_rx_dval_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXSOF" "OAM_IP_top_0:sys_mac_rx_sop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXACPT" "OAM_IP_top_0:sys_mac_tx_rdy_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXEOF" "OAM_IP_top_0:sys_mac_tx_eop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXRDY" "OAM_IP_top_0:sys_mac_tx_dval_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXSOF" "OAM_IP_top_0:sys_mac_tx_sop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:RXCLK" "CORETSE_1:TBI_RX_CLK" "PF_IOD_CDR_C0_1:RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PENABLES" "OAM_IP_top_0:penable4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PREADYS4" "OAM_IP_top_0:pready4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PSELS4" "OAM_IP_top_0:psel4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PSLVERRS4" "OAM_IP_top_0:pslverr4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PWRITES" "OAM_IP_top_0:pwrite4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:BANK_x_VDDI_STATUS" "Core_reset_pf_0:BANK_y_VDDI_STATUS" "pf_init_monitor_0_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:EXT_RST_N" "REF_CLK_SEL" "RESET_N" "coma_mode" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:FPGA_POR_N" "pf_init_monitor_0_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:INIT_DONE" "pf_init_monitor_0_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:PLL_LOCK" "PF_CCC_0_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_reset_pf_0:PLL_POWERDOWN_B" "PF_CCC_0_0:PLL_POWERDOWN_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:PADN" "REFCLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:PADP" "REFCLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INBUF_DIFF_0:Y" "PF_IOD_CDR_CCC_C0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:JTAG_TCK" "core_jatg_debug_0_0:TGT_TCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:JTAG_TDI" "core_jatg_debug_0_0:TGT_TDI_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:JTAG_TDO" "core_jatg_debug_0_0:TGT_TDO_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:JTAG_TMS" "core_jatg_debug_0_0:TGT_TMS_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:JTAG_TRSTN" "core_jatg_debug_0_0:TGT_TRSTN_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C2_0:MSYS_EI[0:0]" "OAM_IP_top_0:hwInt" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0_0:REF_CLK_0" "REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_0:RX_N" "RX_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_0:RX_P" "RX_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_0:TX_N" "TX_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_0:TX_P" "TX_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_1:RX_N" "RX1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_1:RX_P" "RX1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_1:TX_N" "TX1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_1:TX_P" "TX1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TCK" "core_jatg_debug_0_0:TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TDI" "core_jatg_debug_0_0:TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TDO" "core_jatg_debug_0_0:TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TMS" "core_jatg_debug_0_0:TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TRSTB" "core_jatg_debug_0_0:TRSTB" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXBYTEVALID" "OAM_IP_top_0:carr_mac_rx_mod_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MRXDAT" "OAM_IP_top_0:carr_mac_rx_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXBYTEVALID" "OAM_IP_top_0:carr_mac_tx_mod_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:MTXDAT" "OAM_IP_top_0:carr_mac_tx_data_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:RCG" "PF_IOD_CDR_C0_0:RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:TCG" "PF_IOD_CDR_C0_0:TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXBYTEVALID" "OAM_IP_top_0:sys_mac_rx_mod_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MRXDAT" "OAM_IP_top_0:sys_mac_rx_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXBYTEVALID" "OAM_IP_top_0:sys_mac_tx_mod_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:MTXDAT" "OAM_IP_top_0:sys_mac_tx_data_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:RCG" "PF_IOD_CDR_C0_1:RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:TCG" "PF_IOD_CDR_C0_1:TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PADDRS" "OAM_IP_top_0:paddr4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PRDATAS4" "OAM_IP_top_0:prdata4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:PWDATAS" "OAM_IP_top_0:pwdata4_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:AXI4mmaster0" "MIV_RV32_C2_0:AXI4_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:AXI4mslave0" "PF_SRAM_AHBL_AXI_C0_0:AXI4_Slave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_0_0:APB_bif" "CoreAPB3_0_0:APBmslave2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_0:APBS" "CoreAPB3_0_0:APBmslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORETSE_1:APBS" "CoreAPB3_0_0:APBmslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APB3mmaster" "MIV_RV32_C2_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave3" "CoreUARTapb_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0_0:APBmslave5" "PF_SYSTEM_SERVICES_C0_0:APBSlave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_CDR_C0_0:CDR_CLOCKS" "PF_IOD_CDR_C0_1:CDR_CLOCKS" "PF_IOD_CDR_CCC_C0_0:CDR_CLOCKS" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
