# Import source files
import_files -hdl_source {./src/hdl/apb_if_mem.v}

build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CoreAPB3_0.tcl 
source ./src/components/COREAXI4INTERCONNECT_C0.tcl 
source ./src/components/CORESPI_0.tcl 
source ./src/components/CORETSE_0.tcl 
source ./src/components/CoreUARTapb_0.tcl 
source ./src/components/core_jatg_debug_0.tcl 
source ./src/components/Core_reset_pf.tcl 
source ./src/components/Ethernet_OAM_C0.tcl 
source ./src/components/MIV_RV32_C2.tcl 
source ./src/components/PF_CCC_0.tcl 
source ./src/components/pf_init_monitor_0.tcl 
source ./src/components/PF_IOD_CDR_C0.tcl 
source ./src/components/PF_IOD_CDR_CCC_C0.tcl 
source ./src/components/PF_SRAM_AHBL_AXI_C0.tcl 
source ./src/components/PF_SYSTEM_SERVICES_C0.tcl 
source ./src/components/top.tcl 

#Downgrade the DRC check
#smartdesign -memory_map_drc_change_error_to_warning true \

build_design_hierarchy 

# Set top level module

set_root -module {PF_EVALKIT_TOP::work} 

save_project
puts "Design generated successfully\n"
