# Creating SmartDesign "top"
set sd_name {PF_EVALKIT_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}



# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_2}



# Add APB3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB3} -instance_name {APB3_0}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave0} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave0} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave0} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave0} -pin_names {APB3_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave1} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave1} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave1} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave1} -pin_names {APB3_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave2} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave2} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave2} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave2} -pin_names {APB3_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave3} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave3} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave3} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave3} -pin_names {APB3_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave4} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave4} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave4} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave4} -pin_names {APB3_0:PWDATAS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave5} -pin_names {APB3_0:PADDRS}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave5} -pin_names {APB3_0:PENABLES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave5} -pin_names {APB3_0:PWRITES}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {APB3_0:APBmslave5} -pin_names {APB3_0:PWDATAS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {APB3_0:APBmslave2}



# Add CCC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_0} -instance_name {CCC_0_0}



# Add CORE10GMAC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE10GMAC_C0} -instance_name {CORE10GMAC_C0_0}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE10GMAC_C0_0:APB_0} -pin_names {CORE10GMAC_C0_0:PRDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE10GMAC_C0_0:APB_0} -pin_names {CORE10GMAC_C0_0:PREADY}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE10GMAC_C0_0:APB_0} -pin_names {CORE10GMAC_C0_0:PSLVERR}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_SYS_TX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_ERR_BUS_PROTOCOL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_ERR_FIFO_UNDERRUN}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_LOCAL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_REMOTE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_IDLE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_RS_RX_FAULT_LOCAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_RS_RX_FAULT_REMOTE}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_PCS49_TX_SRESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BLOCK_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_HI_BER}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_STATUS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BER_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_TEST_MODE_ERR_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_ERRORED_BLOCK_CNT_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PMA49_TX_GRBX_HDR_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PMA49_TX_GRBX_DATA_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_STATS_VECTOR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_STATS_VECTOR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_A} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_B} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BER_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_TEST_MODE_ERR_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_PREAMBLE}



# Add CORE10GMAC_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE10GMAC_C1} -instance_name {CORE10GMAC_C1_0}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_SYS_TX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_SYS_MAC_TX_ERR_BUS_PROTOCOL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_SYS_MAC_TX_ERR_FIFO_UNDERRUN}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_RS_TX_FAULT_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_RS_TX_FAULT_LOCAL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_RS_TX_FAULT_REMOTE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_RS_TX_IDLE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_RS_RX_FAULT_LOCAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_RS_RX_FAULT_REMOTE}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_PCS49_TX_SRESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_RX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_RX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_RX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_RX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_RX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_BLOCK_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_HI_BER}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_STATUS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_BER_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_TEST_MODE_ERR_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_ERRORED_BLOCK_CNT_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PMA49_TX_GRBX_HDR_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PMA49_TX_GRBX_DATA_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_SYS_MAC_TX_STATS_VECTOR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_SYS_MAC_RX_STATS_VECTOR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_A} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_B} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_BER_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_PCS49_RX_TEST_MODE_ERR_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C1_0:O_SYS_MAC_RX_PREAMBLE}



# Add CoreAHBLite_metroam_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBLite_metroam} -instance_name {CoreAHBLite_metroam_0}



# Add COREAHBTOAPB3_metroam_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_metroam} -instance_name {COREAHBTOAPB3_metroam_0}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PADDR}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PSEL}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PENABLE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PWRITE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PRDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PWDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PREADY}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {COREAHBTOAPB3_metroam_0:APBmaster} -pin_names {COREAHBTOAPB3_metroam_0:PSLVERR}



# Add COREAXI4INTERCONNECT_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAXI4INTERCONNECT_C0} -instance_name {COREAXI4INTERCONNECT_C0_1}



# Add COREAXITOAHBL_metroam_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAXITOAHBL_metroam} -instance_name {COREAXITOAHBL_metroam_0}



# Add COREJTAGDebug_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDebug_0} -instance_name {COREJTAGDebug_0_0}



# Add INIT_Monitor_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_Monitor} -instance_name {INIT_Monitor_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_Monitor_0:AUTOCALIB_DONE}



# Add MIV_RV32IMA_L1_AXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32IMA_L1_AXI_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_C0_0:MSYS_EI} -pin_slices {[0:0]}
sd_invert_pins -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:MSYS_EI[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_C0_0:MSYS_EI} -pin_slices {[1:1]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:MSYS_EI[1:1]} -value {GND}
#sd_create_pin_group -sd_name ${sd_name} -group_name {IRQ} -instance_name {MIV_RV32IMA_L1_AXI_C0_0} -pin_names {"EXT_IRQ" "MSYS_EI" }
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:JTAG_TDO_DR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:EXT_RESETN}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:EXT_IRQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_C0_0:TIME_COUNT_OUT}



# Add NAND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {NAND2} -instance_name {NAND2_0}



# Add NAND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {NAND2} -instance_name {NAND2_1}



# Add PF_SRAM_AHBL_AXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {PF_SRAM_AHBL_AXI_C0_0}



# Add PF_SYSTEM_SERVICES_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SYSTEM_SERVICES_C0} -instance_name {PF_SYSTEM_SERVICES_C0_0}



# Add PF_TX_PLL_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C1} -instance_name {PF_TX_PLL_C1_0}



# Add PF_XCVR_ERM_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C1} -instance_name {PF_XCVR_ERM_C1_0}
#sd_create_pin_group -sd_name ${sd_name} -group_name {LANE1_IN} -instance_name {PF_XCVR_ERM_C1_0} -pin_names {"LANE1_TX_DATA" "LANE1_CDR_REF_CLK_0" "LANE1_PCS_ARST_N" "LANE1_PMA_ARST_N" "LANE1_TX_SOS" "LANE1_TX_HDR" }
#sd_create_pin_group -sd_name ${sd_name} -group_name {LANE1_OUT} -instance_name {PF_XCVR_ERM_C1_0} -pin_names {"LANE1_RX_DATA" "LANE1_RX_CLK_R" "LANE1_RX_IDLE" "LANE1_TX_CLK_STABLE" "LANE1_RX_BYPASS_DATA" "LANE1_RX_READY" "LANE1_RX_VAL" "LANE1_RX_HDR_VAL" "LANE1_RX_SOS" "LANE1_RX_DATA_VAL" "LANE1_RX_HDR" "LANE1_STATUS_HI_BER" "LANE1_STATUS_LOCK" "LANE1_TX_CLK_R" }
sd_invert_pins -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_PMA_ARST_N} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_BYPASS_DATA}
sd_invert_pins -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_PCS_ARST_N}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_PMA_ARST_N} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_RX_BYPASS_DATA}



# Add PF_XCVR_REF_CLK_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C1} -instance_name {PF_XCVR_REF_CLK_C1_0}



# Add reset_syn_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_syn} -instance_name {reset_syn_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_0:FF_US_RESTORE} -value {GND}



# Add two_port_top_rtl_64_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Ethernet_OAM_C0} -instance_name {two_port_top_rtl_64_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {two_port_top_rtl_64_0:carr_mac_rx_rdy_out}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {two_port_top_rtl_64_0:carr_mac_tx_err_out}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {two_port_top_rtl_64_0:sys_mac_rx_rdy_out}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {two_port_top_rtl_64_0:sys_mac_tx_err_out}



# Add UART_apb_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_apb} -instance_name {UART_apb_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_apb_0:TXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_apb_0:RXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_apb_0:PARITY_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_apb_0:OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_apb_0:FRAMING_ERR}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "PF_XCVR_ERM_C1_0:LANE1_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "AND2_2:B" "CORE10GMAC_C0_0:PRESETN" "CORE10GMAC_C1_0:PRESETN" "COREAHBTOAPB3_metroam_0:HRESETN" "COREAXI4INTERCONNECT_C0_1:ARESETN" "COREAXITOAHBL_metroam_0:ARESETN" "COREAXITOAHBL_metroam_0:HRESETN" "CoreAHBLite_metroam_0:HRESETN" "MIV_RV32IMA_L1_AXI_C0_0:RESETN" "NAND2_0:A" "NAND2_1:A" "PF_SRAM_AHBL_AXI_C0_0:ARESETN" "PF_SYSTEM_SERVICES_C0_0:RESETN" "UART_apb_0:PRESETN" "reset_syn_0:FABRIC_RESET_N" "two_port_top_rtl_64_0:aSyncResetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORE10GMAC_C1_0:I_PCS49_TX_SRESET" "CORE10GMAC_C1_0:I_SYS_TX_SRESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:A" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_2:Y" "CORE10GMAC_C0_0:I_PCS49_TX_SRESET" "CORE10GMAC_C0_0:I_SYS_TX_SRESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT0_FABCLK_0" "CORE10GMAC_C0_0:PCLK" "CORE10GMAC_C1_0:PCLK" "COREAXI4INTERCONNECT_C0_1:ACLK" "COREAXITOAHBL_metroam_0:ACLK" "MIV_RV32IMA_L1_AXI_C0_0:CLK" "PF_SRAM_AHBL_AXI_C0_0:ACLK" "PF_SYSTEM_SERVICES_C0_0:CLK" "UART_apb_0:PCLK" "reset_syn_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT1_FABCLK_0" "CORE10GMAC_C0_0:I_SYS_CLK" "CORE10GMAC_C1_0:I_SYS_CLK" "two_port_top_rtl_64_0:macClk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT2_FABCLK_0" "COREAHBTOAPB3_metroam_0:HCLK" "COREAXITOAHBL_metroam_0:HCLK" "CoreAHBLite_metroam_0:HCLK" "two_port_top_rtl_64_0:cpuIfClk" "two_port_top_rtl_64_0:sysClk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_LOCK_0" "reset_syn_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:REF_CLK_0" "PF_XCVR_REF_CLK_C1_0:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_CORE_RX_CLK" "PF_XCVR_ERM_C1_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_CORE_TX_CLK" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PCS49_RX_SRESET" "CORE10GMAC_C0_0:I_RS_RX_SRESET" "CORE10GMAC_C0_0:I_SYS_RX_SRESET" "NAND2_1:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_DATA_EN" "PF_XCVR_ERM_C1_0:LANE0_RX_DATA_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_HDR_EN" "PF_XCVR_ERM_C1_0:LANE0_RX_HDR_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_LOCK" "PF_XCVR_ERM_C1_0:LANE0_STATUS_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_SOS" "PF_XCVR_ERM_C1_0:LANE0_RX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_EN" "two_port_top_rtl_64_0:carr_mac_tx_dval_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_EOP" "two_port_top_rtl_64_0:carr_mac_tx_eop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_SOP" "two_port_top_rtl_64_0:carr_mac_tx_sop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_CORE_TX_SRESET" "PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_SOS" "PF_XCVR_ERM_C1_0:LANE0_TX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_EN" "two_port_top_rtl_64_0:carr_mac_rx_dval_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_EOP" "two_port_top_rtl_64_0:carr_mac_rx_eop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_ERR" "two_port_top_rtl_64_0:carr_mac_rx_err_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_SOP" "two_port_top_rtl_64_0:carr_mac_rx_sop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_TX_RDY" "two_port_top_rtl_64_0:carr_mac_tx_rdy_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_CORE_RX_CLK" "PF_XCVR_ERM_C1_0:LANE1_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_CORE_TX_CLK" "PF_XCVR_ERM_C1_0:LANE1_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PCS49_RX_SRESET" "CORE10GMAC_C1_0:I_RS_RX_SRESET" "CORE10GMAC_C1_0:I_SYS_RX_SRESET" "NAND2_0:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_DATA_EN" "PF_XCVR_ERM_C1_0:LANE1_RX_DATA_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_HDR_EN" "PF_XCVR_ERM_C1_0:LANE1_RX_HDR_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_LOCK" "PF_XCVR_ERM_C1_0:LANE1_STATUS_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_SOS" "PF_XCVR_ERM_C1_0:LANE1_RX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_SYS_MAC_TX_EN" "two_port_top_rtl_64_0:sys_mac_tx_dval_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_SYS_MAC_TX_EOP" "two_port_top_rtl_64_0:sys_mac_tx_eop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_SYS_MAC_TX_SOP" "two_port_top_rtl_64_0:sys_mac_tx_sop_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_CORE_TX_SRESET" "PF_XCVR_ERM_C1_0:LANE1_PCS_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_PMA49_TX_GRBX_SOS" "PF_XCVR_ERM_C1_0:LANE1_TX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_EN" "two_port_top_rtl_64_0:sys_mac_rx_dval_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_EOP" "two_port_top_rtl_64_0:sys_mac_rx_eop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_ERR" "two_port_top_rtl_64_0:sys_mac_rx_err_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_SOP" "two_port_top_rtl_64_0:sys_mac_rx_sop_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_TX_RDY" "two_port_top_rtl_64_0:sys_mac_tx_rdy_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PENABLE" "two_port_top_rtl_64_0:penable4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PREADY" "two_port_top_rtl_64_0:pready4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PSEL" "two_port_top_rtl_64_0:psel4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PSLVERR" "two_port_top_rtl_64_0:pslverr4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PWRITE" "two_port_top_rtl_64_0:pwrite4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TGT_TCK_0" "MIV_RV32IMA_L1_AXI_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TGT_TDI_0" "MIV_RV32IMA_L1_AXI_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TGT_TDO_0" "MIV_RV32IMA_L1_AXI_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TGT_TMS_0" "MIV_RV32IMA_L1_AXI_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TGT_TRSTN_0" "MIV_RV32IMA_L1_AXI_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDebug_0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:BANK_6_VDDI_STATUS" "reset_syn_0:BANK_x_VDDI_STATUS" "reset_syn_0:BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:DEVICE_INIT_DONE" "reset_syn_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_Monitor_0:FABRIC_POR_N" "reset_syn_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C1_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C1_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_ERM_C1_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_ERM_C1_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N" "PF_XCVR_ERM_C1_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P" "PF_XCVR_ERM_C1_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_N" "PF_XCVR_ERM_C1_0:LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_P" "PF_XCVR_ERM_C1_0:LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AXI_C0_0:MSYS_EI[0:0]" "two_port_top_rtl_64_0:hwInt" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"NAND2_0:B" "PF_XCVR_ERM_C1_0:LANE1_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"NAND2_1:B" "PF_XCVR_ERM_C1_0:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:REF_CLK" "PF_XCVR_ERM_C1_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_ERM_C1_0:LANE1_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_C1_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C1_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C1_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_apb_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_apb_0:TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_syn_0:EXT_RST_N" "resetn" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_DATA" "PF_XCVR_ERM_C1_0:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_HDR" "PF_XCVR_ERM_C1_0:LANE0_RX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_BC" "two_port_top_rtl_64_0:carr_mac_tx_mod_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_DATA" "two_port_top_rtl_64_0:carr_mac_tx_data_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_DATA" "PF_XCVR_ERM_C1_0:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_HDR" "PF_XCVR_ERM_C1_0:LANE0_TX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_BC" "two_port_top_rtl_64_0:carr_mac_rx_mod_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_DATA" "two_port_top_rtl_64_0:carr_mac_rx_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_DATA" "PF_XCVR_ERM_C1_0:LANE1_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_PMA49_RX_GRBX_HDR" "PF_XCVR_ERM_C1_0:LANE1_RX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_SYS_MAC_TX_BC" "two_port_top_rtl_64_0:sys_mac_tx_mod_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:I_SYS_MAC_TX_DATA" "two_port_top_rtl_64_0:sys_mac_tx_data_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_PMA49_TX_GRBX_DATA" "PF_XCVR_ERM_C1_0:LANE1_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_PMA49_TX_GRBX_HDR" "PF_XCVR_ERM_C1_0:LANE1_TX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_BC" "two_port_top_rtl_64_0:sys_mac_rx_mod_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C1_0:O_SYS_MAC_RX_DATA" "two_port_top_rtl_64_0:sys_mac_rx_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PADDR" "two_port_top_rtl_64_0:paddr4_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PRDATA" "two_port_top_rtl_64_0:prdata4_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:PWDATA" "two_port_top_rtl_64_0:pwdata4_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_0:APB3mmaster" "MIV_RV32IMA_L1_AXI_C0_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_0:APBmslave0" "CORE10GMAC_C0_0:APB_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_0:APBmslave1" "CORE10GMAC_C1_0:APB_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_0:APBmslave3" "UART_apb_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_0:APBmslave5" "PF_SYSTEM_SERVICES_C0_0:APBSlave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_metroam_0:AHBslave" "CoreAHBLite_metroam_0:AHBmslave8" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_1:AXI3mslave1" "COREAXITOAHBL_metroam_0:AXISlaveIF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_1:AXI4mmaster0" "MIV_RV32IMA_L1_AXI_C0_0:AXI4_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_1:AXI4mslave0" "PF_SRAM_AHBL_AXI_C0_0:AXI4_Slave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXITOAHBL_metroam_0:AHBMasterIF" "CoreAHBLite_metroam_0:AHBmmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C1_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
