# Import source files
import_files -hdl_source {./src/hdl/retiming_1.v}

build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/APB3.tcl 
source ./src/components/CCC_0.tcl 
source ./src/components/CORE10GMAC_C0.tcl 
source ./src/components/CORE10GMAC_C1.tcl 
source ./src/components/CoreAHBLite_metroam.tcl 
source ./src/components/COREAHBTOAPB3_metroam.tcl 
source ./src/components/COREAXI4INTERCONNECT_C0.tcl 
source ./src/components/COREAXITOAHBL_metroam.tcl 
source ./src/components/COREJTAGDebug_0.tcl 
source ./src/components/Ethernet_OAM_C0.tcl 
source ./src/components/INIT_Monitor.tcl 
source ./src/components/MIV_RV32_C0.tcl 
source ./src/components/PF_SRAM_AHBL_AXI_C0.tcl 
source ./src/components/PF_SYSTEM_SERVICES_C0.tcl 
source ./src/components/PF_TX_PLL_C1.tcl 
source ./src/components/PF_XCVR_ERM_C1.tcl 
source ./src/components/PF_XCVR_REF_CLK_C1.tcl 
source ./src/components/reset_syn.tcl 
source ./src/components/UART_apb.tcl 
source ./src/components/top.tcl 
build_design_hierarchy 

# Set top level module

set_root -module {PF_EVALKIT_TOP::work} 

save_project
puts "Design generated successfully\n"
