###############################################################################################################################################
# © 2024 Microchip Technology Inc. and its subsidiaries
# All rights reserved.
# ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
# ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
# IN ADVANCE IN WRITING
##################################################################################################################################################
# Title        : script.tcl
# Description  : This is the top-level script, which creates the FPGA HW Project. 
#                It invokes all the below TCLs which are required to complete the FPGA design flow.
#         	      -- 1_create_design.tcl: Executes all the required core configuration TCLs with necessary user HDL files to generate the design.
#		          -- 2_constrain_design.tcl: Applies all the necessary constraints for the design.
#      		      -- 3_sim_flow.tcl : Imports the testbench, other required simulation files and simulates the design.
#		          -- 4_implement_design.tcl : Runs synthesis, place & route, and verify timing design flow steps.
#        		  -- 5_program_design.tcl : Creates and exports the programming job file.              
####################################################################################################################################################

# Call common.tcl which contains required cores with the versions numbers to run the TCL scripts
source ./common/common.tcl
set Prjname "mpf_an5522_v2025p1_df"
set PrjLocation "./$Prjname"


#variable used in the design
set SimTime 100us
set Effort_Level true 
set Multi_Pass_Layout false 
set Repair_Min_Delay true

# Remove existing project if present
file delete -force ${PrjLocation}

# Create and configure new project
new_project \
	-name "$Prjname" \
	-location "$PrjLocation" \
	-family "PolarFire" \
	-die $die_eval \
	-package $eval_package \
	-die_voltage "1.0" \
	-speed "STD" \
	-part_range $eval_part_range \
	-hdl "VERILOG"
smartdesign -memory_map_drc_change_error_to_warning 1 -bus_interface_data_width_drc_change_error_to_warning 1 -bus_interface_id_width_drc_change_error_to_warning 1

# Set VHDL language version for this project

select_profile -name $synprofile1

select_profile -name $simuprofile1

puts "Project created successfully"
 # Core Downloads
 download_core -vlnv {Actel:DirectCore:CORE10GMAC:3.0.101} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Actel:DirectCore:COREABC:4.1.111} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:5.1.0} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Microchip:SolutionCore:MIPI_TRAINING_LITE:1.0.0} -location {www.microchip-ip.com/repositories/DirectCore}
 download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.308} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_CCC:2.2.220} -location {www.microchip-ip.com/repositories/SgCore}
  download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.113} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_SYSTEM_SERVICES:3.0.103} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_TX_PLL:2.0.304} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
 download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.206} -location {www.microchip-ip.com/repositories/SgCore}


# Create design
source ./src/1_create_design.tcl

# Constrain design
source ./src/2_constrain_design.tcl

# Implement design
source ./src/4_implement_design.tcl

# Program design
source ./src/5_program_design.tcl

file delete -force mpf_an5522_v2025p1_df_log.txt

save_log -file mpf_an5522_v2025p1_df_log.txt

# Close project
close_project -save 1 
