# Creating SmartDesign "IMX477_IF_TOP"
set sd_name {IMX477_IF_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_TREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_POR_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {sif_clk} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_frame_valid_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_TDATA_O} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_TKEEP_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_TSTRB_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:BIF_1_TVALID_O" \
"TREADY:BIF_1_TREADY_I" \
"TDATA:BIF_1_TDATA_O" \
"TSTRB:BIF_1_TSTRB_O" \
"TKEEP:BIF_1_TKEEP_O" \
"TLAST:BIF_1_TLAST_O" \
"TUSER:BIF_1_TUSER_O" } 

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add buffer_lp_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {buffer_lp} -hdl_file {hdl\buffer.v} -instance_name {buffer_lp_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_E_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_F_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_G_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_H_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_E_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_F_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_G_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {buffer_lp_0:DATA_H_O}



# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}



# Add HSB_AXIS_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {HSB_AXIS} -instance_name {HSB_AXIS_0}
# Exporting Parameters of instance HSB_AXIS_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {HSB_AXIS_0} -params {\
"g_AXI_DWIDTH:64" \
"g_DWIDTH_IN:32" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {HSB_AXIS_0}
sd_update_instance -sd_name ${sd_name} -instance_name {HSB_AXIS_0}



# Add mipicsi2rxdecoderPF_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C0} -instance_name {mipicsi2rxdecoderPF_0}
sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {mipicsi2rxdecoderPF_0} -pin_names {"ACLK_I" "ARESETN_I" }
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:FRAME_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:LINE_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:LINE_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:ECC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:CRC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:MIPI_INTERRUPT_O}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:ACLK_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:ARESETN_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:AWVALID_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:WVALID_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:BREADY_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:ARVALID_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:RREADY_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:VIRTUAL_CHANNEL_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:DATA_TYPE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:WORD_COUNT_O}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:AWADDR_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:WDATA_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:ARADDR_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {mipicsi2rxdecoderPF_0:AXI4Lite_Target_IF}



# Add PF_CCC_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0}



# Add PF_IOD_GENERIC_RX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "PF_CCC_C2_0:PLL_LOCK_0" "mipicsi2rxdecoderPF_0:CAM_PLL_LOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_GENERIC_RX_C0_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "HSB_AXIS_0:CLK_I" "PF_CCC_C2_0:OUT0_FABCLK_0" "mipicsi2rxdecoderPF_0:PARALLEL_CLOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:EXT_RST_N" "PF_IOD_GENERIC_RX_C0_0:training_done_o" "mipicsi2rxdecoderPF_0:TRAINING_DONE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:FABRIC_RESET_N" "HSB_AXIS_0:RESETN_I" "buffer_lp_0:RESETN_I" "mipicsi2rxdecoderPF_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:FPGA_POR_N" "FPGA_POR_N" "PF_IOD_GENERIC_RX_C0_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSB_AXIS_0:ACLK_I" "sif_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSB_AXIS_0:DATA_VALID_I" "mipicsi2rxdecoderPF_0:LINE_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSB_AXIS_0:EOF_I" "mipicsi2rxdecoderPF_0:FRAME_END_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "PF_IOD_GENERIC_RX_C0_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" "RX_CLK_G" "buffer_lp_0:SYS_CLK_I" "mipicsi2rxdecoderPF_0:CAM_CLOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" "buffer_lp_0:DATA_A_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" "buffer_lp_0:DATA_B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" "buffer_lp_0:DATA_C_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" "buffer_lp_0:DATA_D_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"buffer_lp_0:DATA_A_O" "mipicsi2rxdecoderPF_0:L0_LP_DATA_I" "mipicsi2rxdecoderPF_0:L0_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"buffer_lp_0:DATA_B_O" "mipicsi2rxdecoderPF_0:L1_LP_DATA_I" "mipicsi2rxdecoderPF_0:L1_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"buffer_lp_0:DATA_C_O" "mipicsi2rxdecoderPF_0:L2_LP_DATA_I" "mipicsi2rxdecoderPF_0:L2_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"buffer_lp_0:DATA_D_O" "mipicsi2rxdecoderPF_0:L3_LP_DATA_I" "mipicsi2rxdecoderPF_0:L3_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"c1_frame_valid_o" "mipicsi2rxdecoderPF_0:FRAME_VALID_O" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"HSB_AXIS_0:DATA_I" "mipicsi2rxdecoderPF_0:DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" "mipicsi2rxdecoderPF_0:L0_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" "mipicsi2rxdecoderPF_0:L1_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" "mipicsi2rxdecoderPF_0:L2_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" "mipicsi2rxdecoderPF_0:L3_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:RXD" "RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_IOD_GENERIC_RX_C0_0:RXD_N" "RXD_N" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "HSB_AXIS_0:BIF_1" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "IMX477_IF_TOP"
generate_component -component_name ${sd_name}
