# Creating SmartDesign "MAC_BaseR"
set sd_name {MAC_BaseR}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Device_Init_Done} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {I_SYS_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {I_SYS_RX_SRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {I_SYS_TX_SRESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_STABLE} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TKEEP} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_TRGT_AXI4S_DT_TARG_TUSER} -port_direction {IN} -port_range {[2:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TKEEP} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_INITR_AXI4S_DT_INITR_TUSER} -port_direction {OUT} -port_range {[7:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_INITR} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:AXI4S_INITR_AXI4S_DT_INITR_TVALID" \
"TREADY:AXI4S_INITR_AXI4S_DT_INITR_TREADY" \
"TDATA:AXI4S_INITR_AXI4S_DT_INITR_TDATA" \
"TKEEP:AXI4S_INITR_AXI4S_DT_INITR_TKEEP" \
"TLAST:AXI4S_INITR_AXI4S_DT_INITR_TLAST" \
"TUSER:AXI4S_INITR_AXI4S_DT_INITR_TUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_TRGT} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:AXI4S_TRGT_AXI4S_DT_TARG_TVALID" \
"TREADY:AXI4S_TRGT_AXI4S_DT_TARG_TREADY" \
"TDATA:AXI4S_TRGT_AXI4S_DT_TARG_TDATA" \
"TKEEP:AXI4S_TRGT_AXI4S_DT_TARG_TKEEP" \
"TLAST:AXI4S_TRGT_AXI4S_DT_TARG_TLAST" \
"TUSER:AXI4S_TRGT_AXI4S_DT_TARG_TUSER" } 

sd_invert_pins -sd_name ${sd_name} -pin_names {I_SYS_RX_SRESETN}
sd_invert_pins -sd_name ${sd_name} -pin_names {I_SYS_TX_SRESETN}
# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
sd_invert_pins -sd_name ${sd_name} -pin_names {AND2_0:B}



# Add CORE10GMAC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE10GMAC_C0} -instance_name {CORE10GMAC_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC_C0_0:I_SYS_MAC_TX_BC} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC_C0_0:I_SYS_MAC_TX_BC} -pin_slices {[7:3]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_SYS_MAC_TX_BC[7:3]} -value {VCC}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC_C0_0:O_SYS_MAC_RX_BC} -pin_slices {[2:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC_C0_0:O_SYS_MAC_RX_BC} -pin_slices {[7:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_BC[7:3]}
sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {CORE10GMAC_C0_0} -pin_names {"O_SYS_MAC_RX_PREAMBLE" "I_CFG_RS_TX_FAULT_EN" "I_CFG_RS_TX_FAULT_LOCAL" "I_CFG_RS_TX_FAULT_REMOTE" "I_CFG_RS_TX_IDLE" "I_CFG_PCS49_TX_BYPASS_SCRAMBLER" "I_CFG_PCS49_TX_TEST_PRBS31_EN" "I_CFG_PCS49_TX_TEST_PATTERN_EN" "I_CFG_PCS49_TX_TEST_PATTERN_TYPE_SEL" "I_CFG_PCS49_TX_TEST_PATTERN_DATA_SEL" "I_CFG_PCS49_RX_BYPASS_SCRAMBLER" "I_CFG_PCS49_RX_TEST_PRBS31_EN" "I_CFG_PCS49_RX_TEST_PATTERN_EN" "I_CFG_PCS49_RX_TEST_PATTERN_TYPE_SEL" "I_CFG_PCS49_RX_TEST_PATTERN_DATA_SEL" "I_CFG_PCS49_TX_TEST_PATTERN_SEED_A" "I_CFG_PCS49_TX_TEST_PATTERN_SEED_B" "O_CORE_TX_SRESET" "O_CORE_RX_SRESET" "O_SYS_MAC_TX_FAULT" "O_SYS_MAC_TX_ERR_BUS_PROTOCOL" "O_SYS_MAC_TX_ERR_FIFO_OVERFLOW" "O_SYS_MAC_TX_ERR_FIFO_UNDERRUN" "O_SYS_MAC_RX_ERR_FIFO_OVERFLOW" "O_RS_RX_FAULT_LOCAL" "O_RS_RX_FAULT_REMOTE" "O_PCS49_RX_BLOCK_LOCK" "O_PCS49_RX_HI_BER" "O_PCS49_RX_STATUS" "O_PCS49_RX_BER_STRB" "O_PCS49_RX_TEST_MODE_ERR_STRB" "O_PCS49_RX_ERRORED_BLOCK_CNT_STRB" "O_PMA49_TX_GRBX_HDR_EN" "O_PMA49_TX_GRBX_DATA_EN" "O_SYS_MAC_TX_STATS_VECTOR" "O_SYS_MAC_RX_ERR_W" "O_SYS_MAC_RX_STATS_VECTOR" "O_PCS49_RX_BER_CNT" "O_PCS49_RX_TEST_MODE_ERR_CNT" }
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_CORE_TX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_CORE_RX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_FAULT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_ERR_BUS_PROTOCOL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_ERR_FIFO_OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_ERR_FIFO_UNDERRUN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_ERR_FIFO_OVERFLOW}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_LOCAL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_FAULT_REMOTE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_RS_TX_IDLE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_RS_RX_FAULT_LOCAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_RS_RX_FAULT_REMOTE}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_BYPASS_SCRAMBLER} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_RX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BLOCK_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_HI_BER}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_STATUS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BER_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_TEST_MODE_ERR_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_ERRORED_BLOCK_CNT_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PMA49_TX_GRBX_HDR_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PMA49_TX_GRBX_DATA_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_TX_STATS_VECTOR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_ERR_W}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_STATS_VECTOR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_A} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:I_CFG_PCS49_TX_TEST_PATTERN_SEED_B} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_BER_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_PCS49_RX_TEST_MODE_ERR_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC_C0_0:O_SYS_MAC_RX_PREAMBLE}



# Add COREABC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREABC_C0} -instance_name {COREABC_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREABC_C0_0:IO_IN} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREABC_C0_0:IO_OUT}



# Add CoreAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0}



# Add MAC_to_AXIS_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {MAC_to_AXIS} -instance_name {MAC_to_AXIS_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MAC_to_AXIS_0:I_MAC_RX_ERR_W} -value {GND}




# Add PF_TX_PLL_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C0} -instance_name {PF_TX_PLL_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_C0_0:PLL_LOCK}



# Add PF_XCVR_ERM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0} -instance_name {PF_XCVR_ERM_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_JA_CLK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_STATUS_HI_BER}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORE10GMAC_C0_0:O_SYS_MAC_TX_RDY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORE10GMAC_C0_0:O_SYS_MAC_TX_FIFO_AF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "MAC_to_AXIS_0:I_MAC_TX_RDY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_CORE_RX_CLK" "LANE0_RX_CLK_R" "PF_XCVR_ERM_C0_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_CORE_TX_CLK" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PCS49_RX_SRESET" "CORE10GMAC_C0_0:I_RS_RX_SRESET" "CORE10GMAC_C0_0:I_SYS_RX_SRESET" "I_SYS_RX_SRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PCS49_TX_SRESET" "CORE10GMAC_C0_0:I_SYS_TX_SRESET" "I_SYS_TX_SRESETN" "MAC_to_AXIS_0:RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_DATA_EN" "PF_XCVR_ERM_C0_0:LANE0_RX_DATA_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_HDR_EN" "PF_XCVR_ERM_C0_0:LANE0_RX_HDR_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_LOCK" "PF_XCVR_ERM_C0_0:LANE0_STATUS_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_SOS" "PF_XCVR_ERM_C0_0:LANE0_RX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_CLK" "I_SYS_CLK" "MAC_to_AXIS_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_EN" "MAC_to_AXIS_0:O_MAC_TX_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_EOP" "MAC_to_AXIS_0:O_MAC_TX_EOP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_SOP" "MAC_to_AXIS_0:O_MAC_TX_SOP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_SOS" "PF_XCVR_ERM_C0_0:LANE0_TX_SOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_EN" "MAC_to_AXIS_0:I_MAC_RX_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_EOP" "MAC_to_AXIS_0:I_MAC_RX_EOP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_RDY" "COREABC_C0_0:NSYSRESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_SOP" "MAC_to_AXIS_0:I_MAC_RX_SOP" }

sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:PCLK" "COREABC_C0_0:PCLK" "PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:PRESETN" "COREABC_C0_0:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Device_Init_Done" "PF_XCVR_ERM_C0_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C0_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C0_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RX_VAL" "PF_XCVR_ERM_C0_0:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_ERM_C0_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_ERM_C0_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TX_CLK_STABLE" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C0_0:REF_CLK" "PF_XCVR_ERM_C0_0:LANE0_CDR_REF_CLK_0" "REF_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_DATA" "PF_XCVR_ERM_C0_0:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_PMA49_RX_GRBX_HDR" "PF_XCVR_ERM_C0_0:LANE0_RX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_BC[2:0]" "MAC_to_AXIS_0:O_MAC_TX_BC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:I_SYS_MAC_TX_DATA" "MAC_to_AXIS_0:O_MAC_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_DATA" "PF_XCVR_ERM_C0_0:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_PMA49_TX_GRBX_HDR" "PF_XCVR_ERM_C0_0:LANE0_TX_HDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_BC[2:0]" "MAC_to_AXIS_0:I_MAC_RX_BC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:O_SYS_MAC_RX_DATA" "MAC_to_AXIS_0:I_MAC_RX_DATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_INITR" "MAC_to_AXIS_0:AXI4S_INITR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_TRGT" "MAC_to_AXIS_0:AXI4S_TRGT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC_C0_0:APB_0" "CoreAPB3_C0_0:APBmslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREABC_C0_0:APB3Initiator" "CoreAPB3_C0_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C0_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C0_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "MAC_BaseR"
generate_component -component_name ${sd_name}
