   1              		.file	"miv_udma.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.MIV_uDMA_init,"ax",@progbits
  10              		.align	2
  11              		.globl	MIV_uDMA_init
  13              	MIV_uDMA_init:
  14              	.LFB0:
  15              		.file 1 "../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c"
   1:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /*******************************************************************************
   2:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * (c) Copyright 2022-2023 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  *
   4:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  *
   6:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * Mi-V uDMA Soft IP bare-metal driver. This module is delivered as part of
   7:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * Mi-V Extended Sub System(MIV_ESS) 
   8:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
   9:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  10:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** #include "miv_udma_regs.h"
  11:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** #include "miv_udma.h"
  12:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  13:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /***************************************************************************//**
  14:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * MIV_uDMA_init()
  15:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * See "miv_udma.h" for details of how to use this function.
  16:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
  17:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** void
  18:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** MIV_uDMA_init
  19:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** (
  20:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     miv_udma_instance_t* this_udma,
  21:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     addr_t base_addr
  22:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** )
  23:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** {
  16              		.loc 1 23 1
  17              		.cfi_startproc
  18              	.LVL0:
  24:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Assign the Mi-V uDMA base address to the uDMA instance structure */
  25:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     this_udma->base_address = base_addr;
  19              		.loc 1 25 5
  20              		.loc 1 25 29 is_stmt 0
  21 0000 2320B500 		sw	a1,0(a0)
  26:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  22              		.loc 1 26 1
  23 0004 67800000 		ret
  24              		.cfi_endproc
  25              	.LFE0:
  27              		.section	.text.MIV_uDMA_config,"ax",@progbits
  28              		.align	2
  29              		.globl	MIV_uDMA_config
  31              	MIV_uDMA_config:
  32              	.LFB1:
  27:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  28:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /***************************************************************************//**
  29:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * MIV_uDMA_config()
  30:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * See "miv_udma.h" for details of how to use this function.
  31:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
  32:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** void
  33:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** MIV_uDMA_config
  34:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** (
  35:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     miv_udma_instance_t* this_udma,
  36:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     addr_t src_addr,
  37:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     addr_t dest_addr,
  38:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     uint32_t transfer_size,
  39:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     uint32_t irq_config
  40:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** )
  41:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** {
  33              		.loc 1 41 1 is_stmt 1
  34              		.cfi_startproc
  35              	.LVL1:
  42:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Source memory start address */
  43:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg(this_udma->base_address, SRC_START_ADDR, src_addr);
  36              		.loc 1 43 5
  41:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Source memory start address */
  37              		.loc 1 41 1 is_stmt 0
  38 0000 130101FE 		addi	sp,sp,-32
  39              		.cfi_def_cfa_offset 32
  40 0004 232C8100 		sw	s0,24(sp)
  41              		.cfi_offset 8, -8
  42 0008 13040500 		mv	s0,a0
  43              		.loc 1 43 5
  44 000c 03250500 		lw	a0,0(a0)
  45              	.LVL2:
  41:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Source memory start address */
  46              		.loc 1 41 1
  47 0010 232E1100 		sw	ra,28(sp)
  48              		.cfi_offset 1, -4
  41:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Source memory start address */
  49              		.loc 1 41 1
  50 0014 2322E100 		sw	a4,4(sp)
  51              		.loc 1 43 5
  52 0018 1305C500 		addi	a0,a0,12
  41:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Source memory start address */
  53              		.loc 1 41 1
  54 001c 2324D100 		sw	a3,8(sp)
  55 0020 2326C100 		sw	a2,12(sp)
  56              		.loc 1 43 5
  57 0024 97000000 		call	HW_set_32bit_reg
  57      E7800000 
  58              	.LVL3:
  44:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  45:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Destination memory start address */
  46:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg(this_udma->base_address, DEST_START_ADDR, dest_addr);
  59              		.loc 1 46 5 is_stmt 1
  60 002c 0326C100 		lw	a2,12(sp)
  61 0030 03250400 		lw	a0,0(s0)
  62 0034 93050600 		mv	a1,a2
  63 0038 13050501 		addi	a0,a0,16
  64 003c 97000000 		call	HW_set_32bit_reg
  64      E7800000 
  65              	.LVL4:
  47:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  48:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Data transfer size */
  49:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg(this_udma->base_address, BLK_SIZE, transfer_size);
  66              		.loc 1 49 5
  67 0044 03250400 		lw	a0,0(s0)
  68 0048 83268100 		lw	a3,8(sp)
  69 004c 13054501 		addi	a0,a0,20
  70 0050 93850600 		mv	a1,a3
  71 0054 97000000 		call	HW_set_32bit_reg
  71      E7800000 
  72              	.LVL5:
  50:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  51:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Configure the uDMA IRQ */
  52:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg(this_udma->base_address, IRQ_CFG, irq_config);
  73              		.loc 1 52 5
  74 005c 03250400 		lw	a0,0(s0)
  75 0060 03274100 		lw	a4,4(sp)
  53:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  76              		.loc 1 53 1 is_stmt 0
  77 0064 03248101 		lw	s0,24(sp)
  78              		.cfi_restore 8
  79              	.LVL6:
  80 0068 8320C101 		lw	ra,28(sp)
  81              		.cfi_restore 1
  52:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  82              		.loc 1 52 5
  83 006c 93050700 		mv	a1,a4
  84              		.loc 1 53 1
  52:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  85              		.loc 1 52 5
  86 0070 13054500 		addi	a0,a0,4
  87              		.loc 1 53 1
  88 0074 13010102 		addi	sp,sp,32
  89              		.cfi_def_cfa_offset 0
  90              	.LVL7:
  52:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  91              		.loc 1 52 5
  92 0078 17030000 		tail	HW_set_32bit_reg
  92      67000300 
  93              	.LVL8:
  94              		.cfi_endproc
  95              	.LFE1:
  97              		.section	.text.MIV_uDMA_start,"ax",@progbits
  98              		.align	2
  99              		.globl	MIV_uDMA_start
 101              	MIV_uDMA_start:
 102              	.LFB2:
  54:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  55:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /***************************************************************************//**
  56:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * MIV_uDMA_start()
  57:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * See "miv_udma.h" for details of how to use this function.
  58:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
  59:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** void
  60:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** MIV_uDMA_start
  61:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** (
  62:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     miv_udma_instance_t* this_udma
  63:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** )
  64:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** {
 103              		.loc 1 64 1 is_stmt 1
 104              		.cfi_startproc
 105              	.LVL9:
  65:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Start the uDMA transfer */
  66:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg(this_udma->base_address, CONTROL_SR, CTRL_START_TX_MASK);
 106              		.loc 1 66 5
 107 0000 03250500 		lw	a0,0(a0)
 108              	.LVL10:
 109 0004 93051000 		li	a1,1
 110 0008 17030000 		tail	HW_set_32bit_reg
 110      67000300 
 111              	.LVL11:
 112              		.cfi_endproc
 113              	.LFE2:
 115              		.section	.text.MIV_uDMA_reset,"ax",@progbits
 116              		.align	2
 117              		.globl	MIV_uDMA_reset
 119              	MIV_uDMA_reset:
 120              	.LFB3:
  67:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
  68:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  69:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /***************************************************************************//**
  70:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * MIV_uDMA_reset()
  71:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * See "miv_udma.h" for details of how to use this function.
  72:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
  73:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** void
  74:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** MIV_uDMA_reset
  75:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** (
  76:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     miv_udma_instance_t* this_udma
  77:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** )
  78:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** {
 121              		.loc 1 78 1
 122              		.cfi_startproc
 123              	.LVL12:
  79:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Toggle the uDMA_reset bit to reset the uDMA.
  80:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * Resetting the uDMA will clear all the configuration made by
  81:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * MIV_uDMA_config().
  82:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      *
  83:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * This function should be called from the interrupt handler to clear the
  84:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * IRQ.
  85:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      */
  86:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg_field(this_udma->base_address, CTRL_RESET_TX, 0x1u);
 124              		.loc 1 86 5
  78:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Toggle the uDMA_reset bit to reset the uDMA.
 125              		.loc 1 78 1 is_stmt 0
 126 0000 130101FF 		addi	sp,sp,-16
 127              		.cfi_def_cfa_offset 16
 128 0004 23248100 		sw	s0,8(sp)
 129              		.cfi_offset 8, -8
 130 0008 13040500 		mv	s0,a0
 131              		.loc 1 86 5
 132 000c 03250500 		lw	a0,0(a0)
 133              	.LVL13:
 134 0010 93061000 		li	a3,1
 135 0014 13062000 		li	a2,2
 136 0018 93051000 		li	a1,1
  78:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Toggle the uDMA_reset bit to reset the uDMA.
 137              		.loc 1 78 1
 138 001c 23261100 		sw	ra,12(sp)
 139              		.cfi_offset 1, -4
 140              		.loc 1 86 5
 141 0020 97000000 		call	HW_set_32bit_reg_field
 141      E7800000 
 142              	.LVL14:
  87:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg_field(this_udma->base_address, CTRL_RESET_TX, 0x0u);
 143              		.loc 1 87 5 is_stmt 1
 144 0028 03250400 		lw	a0,0(s0)
  88:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** }
 145              		.loc 1 88 1 is_stmt 0
 146 002c 03248100 		lw	s0,8(sp)
 147              		.cfi_restore 8
 148              	.LVL15:
 149 0030 8320C100 		lw	ra,12(sp)
 150              		.cfi_restore 1
  87:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg_field(this_udma->base_address, CTRL_RESET_TX, 0x0u);
 151              		.loc 1 87 5
 152 0034 93060000 		li	a3,0
 153              		.loc 1 88 1
  87:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg_field(this_udma->base_address, CTRL_RESET_TX, 0x0u);
 154              		.loc 1 87 5
 155 0038 13062000 		li	a2,2
 156 003c 93051000 		li	a1,1
 157              		.loc 1 88 1
 158 0040 13010101 		addi	sp,sp,16
 159              		.cfi_def_cfa_offset 0
  87:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     HAL_set_32bit_reg_field(this_udma->base_address, CTRL_RESET_TX, 0x0u);
 160              		.loc 1 87 5
 161 0044 17030000 		tail	HW_set_32bit_reg_field
 161      67000300 
 162              	.LVL16:
 163              		.cfi_endproc
 164              	.LFE3:
 166              		.section	.text.MIV_uDMA_read_status,"ax",@progbits
 167              		.align	2
 168              		.globl	MIV_uDMA_read_status
 170              	MIV_uDMA_read_status:
 171              	.LFB4:
  89:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
  90:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** /***************************************************************************//**
  91:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * MIV_uDMA_read_status()
  92:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  * See "miv_udma.h" for details of how to use this function.
  93:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****  */
  94:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** uint32_t
  95:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** MIV_uDMA_read_status
  96:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** (
  97:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     miv_udma_instance_t* this_udma
  98:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** )
  99:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** {
 172              		.loc 1 99 1 is_stmt 1
 173              		.cfi_startproc
 174              	.LVL17:
 100:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     uint32_t status = 0u;
 175              		.loc 1 100 5
 101:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c **** 
 102:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     /* Read the status of the uDMA transfer.
 103:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * The transfer status register can be Error or Busy depending on the
 104:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      * current uDMA transfer.
 105:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****      */
 106:../src/platform/drivers/fpga_ip/miv_udma/miv_udma.c ****     status = HAL_get_32bit_reg(this_udma->base_address, TX_STATUS);
 176              		.loc 1 106 5
 177              		.loc 1 106 14 is_stmt 0
 178 0000 03250500 		lw	a0,0(a0)
 179              	.LVL18:
 180 0004 13058500 		addi	a0,a0,8
 181 0008 17030000 		tail	HW_get_32bit_reg
 181      67000300 
 182              	.LVL19:
 183              		.cfi_endproc
 184              	.LFE4:
 186              		.text
 187              	.Letext0:
 188              		.file 2 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 189              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 190              		.file 4 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
 191              		.file 5 "../src/platform/drivers/fpga_ip/miv_udma/miv_udma.h"
 192              		.file 6 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
DEFINED SYMBOLS
                            *ABS*:0000000000000000 miv_udma.c
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:13     .text.MIV_uDMA_init:0000000000000000 MIV_uDMA_init
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:17     .text.MIV_uDMA_init:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:19     .text.MIV_uDMA_init:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:20     .text.MIV_uDMA_init:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:21     .text.MIV_uDMA_init:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:23     .text.MIV_uDMA_init:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:24     .text.MIV_uDMA_init:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:31     .text.MIV_uDMA_config:0000000000000000 MIV_uDMA_config
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:34     .text.MIV_uDMA_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:36     .text.MIV_uDMA_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:37     .text.MIV_uDMA_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:38     .text.MIV_uDMA_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:39     .text.MIV_uDMA_config:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:41     .text.MIV_uDMA_config:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:44     .text.MIV_uDMA_config:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:47     .text.MIV_uDMA_config:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:48     .text.MIV_uDMA_config:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:50     .text.MIV_uDMA_config:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:52     .text.MIV_uDMA_config:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:54     .text.MIV_uDMA_config:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:57     .text.MIV_uDMA_config:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:60     .text.MIV_uDMA_config:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:67     .text.MIV_uDMA_config:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:74     .text.MIV_uDMA_config:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:77     .text.MIV_uDMA_config:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:78     .text.MIV_uDMA_config:0000000000000068 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:81     .text.MIV_uDMA_config:000000000000006c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:83     .text.MIV_uDMA_config:000000000000006c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:85     .text.MIV_uDMA_config:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:86     .text.MIV_uDMA_config:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:88     .text.MIV_uDMA_config:0000000000000074 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:89     .text.MIV_uDMA_config:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:92     .text.MIV_uDMA_config:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:94     .text.MIV_uDMA_config:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:101    .text.MIV_uDMA_start:0000000000000000 MIV_uDMA_start
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:104    .text.MIV_uDMA_start:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:106    .text.MIV_uDMA_start:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:107    .text.MIV_uDMA_start:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:112    .text.MIV_uDMA_start:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:119    .text.MIV_uDMA_reset:0000000000000000 MIV_uDMA_reset
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:122    .text.MIV_uDMA_reset:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:124    .text.MIV_uDMA_reset:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:125    .text.MIV_uDMA_reset:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:126    .text.MIV_uDMA_reset:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:127    .text.MIV_uDMA_reset:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:129    .text.MIV_uDMA_reset:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:132    .text.MIV_uDMA_reset:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:138    .text.MIV_uDMA_reset:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:139    .text.MIV_uDMA_reset:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:141    .text.MIV_uDMA_reset:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:144    .text.MIV_uDMA_reset:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:146    .text.MIV_uDMA_reset:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:147    .text.MIV_uDMA_reset:0000000000000030 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:150    .text.MIV_uDMA_reset:0000000000000034 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:152    .text.MIV_uDMA_reset:0000000000000034 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:154    .text.MIV_uDMA_reset:0000000000000038 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:155    .text.MIV_uDMA_reset:0000000000000038 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:158    .text.MIV_uDMA_reset:0000000000000040 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:159    .text.MIV_uDMA_reset:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:161    .text.MIV_uDMA_reset:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:163    .text.MIV_uDMA_reset:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:170    .text.MIV_uDMA_read_status:0000000000000000 MIV_uDMA_read_status
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:173    .text.MIV_uDMA_read_status:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:175    .text.MIV_uDMA_read_status:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:176    .text.MIV_uDMA_read_status:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:177    .text.MIV_uDMA_read_status:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:178    .text.MIV_uDMA_read_status:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:183    .text.MIV_uDMA_read_status:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:27     .text.MIV_uDMA_init:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:97     .text.MIV_uDMA_config:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:115    .text.MIV_uDMA_start:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:166    .text.MIV_uDMA_reset:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:186    .text.MIV_uDMA_read_status:0000000000000010 .L0 
                     .debug_frame:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:542    .debug_abbrev:0000000000000000 .Ldebug_abbrev0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:999    .debug_str:0000000000000088 .LASF26
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1011   .debug_str:000000000000019a .LASF27
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1015   .debug_str:00000000000001dc .LASF28
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:963    .debug_ranges:0000000000000000 .Ldebug_ranges0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:977    .debug_line:0000000000000000 .Ldebug_line0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1043   .debug_str:000000000000030d .LASF0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1003   .debug_str:000000000000015c .LASF1
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1035   .debug_str:00000000000002e3 .LASF2
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1009   .debug_str:0000000000000187 .LASF3
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1039   .debug_str:00000000000002f6 .LASF4
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1017   .debug_str:0000000000000259 .LASF9
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1007   .debug_str:0000000000000175 .LASF5
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1033   .debug_str:00000000000002d5 .LASF6
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1029   .debug_str:00000000000002b4 .LASF7
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1025   .debug_str:0000000000000292 .LASF8
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1037   .debug_str:00000000000002ed .LASF10
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:981    .debug_str:0000000000000012 .LASF11
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:979    .debug_str:0000000000000000 .LASF29
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1023   .debug_str:0000000000000285 .LASF30
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:987    .debug_str:0000000000000033 .LASF12
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1027   .debug_str:000000000000029f .LASF31
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:171    .text.MIV_uDMA_read_status:0000000000000000 .LFB4
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:184    .text.MIV_uDMA_read_status:0000000000000010 .LFE4
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1031   .debug_str:00000000000002cb .LASF13
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:813    .debug_loc:0000000000000000 .LLST7
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:991    .debug_str:0000000000000058 .LASF32
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:182    .text.MIV_uDMA_read_status:0000000000000010 .LVL19
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:995    .debug_str:0000000000000070 .LASF14
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:120    .text.MIV_uDMA_reset:0000000000000000 .LFB3
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:164    .text.MIV_uDMA_reset:000000000000004c .LFE3
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:827    .debug_loc:0000000000000021 .LLST6
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:142    .text.MIV_uDMA_reset:0000000000000028 .LVL14
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:162    .text.MIV_uDMA_reset:000000000000004c .LVL16
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1001   .debug_str:000000000000014d .LASF15
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:102    .text.MIV_uDMA_start:0000000000000000 .LFB2
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:113    .text.MIV_uDMA_start:0000000000000010 .LFE2
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:845    .debug_loc:000000000000004d .LLST5
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:111    .text.MIV_uDMA_start:0000000000000010 .LVL11
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:983    .debug_str:0000000000000019 .LASF16
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:32     .text.MIV_uDMA_config:0000000000000000 .LFB1
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:95     .text.MIV_uDMA_config:0000000000000080 .LFE1
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:859    .debug_loc:000000000000006e .LLST0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:997    .debug_str:000000000000007f .LASF17
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:877    .debug_loc:000000000000009a .LLST1
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:985    .debug_str:0000000000000029 .LASF18
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:891    .debug_loc:00000000000000bb .LLST2
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1041   .debug_str:00000000000002ff .LASF19
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:908    .debug_loc:00000000000000e6 .LLST3
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1005   .debug_str:000000000000016a .LASF20
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:925    .debug_loc:0000000000000111 .LLST4
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:58     .text.MIV_uDMA_config:000000000000002c .LVL3
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:65     .text.MIV_uDMA_config:0000000000000044 .LVL4
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:72     .text.MIV_uDMA_config:000000000000005c .LVL5
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:93     .text.MIV_uDMA_config:0000000000000080 .LVL8
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1013   .debug_str:00000000000001ce .LASF21
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:14     .text.MIV_uDMA_init:0000000000000000 .LFB0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:25     .text.MIV_uDMA_init:0000000000000008 .LFE0
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1021   .debug_str:000000000000027b .LASF22
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:989    .debug_str:0000000000000047 .LASF23
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:1019   .debug_str:0000000000000264 .LASF24
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:993    .debug_str:000000000000005f .LASF25
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:174    .text.MIV_uDMA_read_status:0000000000000000 .LVL17
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:179    .text.MIV_uDMA_read_status:0000000000000004 .LVL18
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:123    .text.MIV_uDMA_reset:0000000000000000 .LVL12
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:133    .text.MIV_uDMA_reset:0000000000000010 .LVL13
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:148    .text.MIV_uDMA_reset:0000000000000030 .LVL15
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:105    .text.MIV_uDMA_start:0000000000000000 .LVL9
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:108    .text.MIV_uDMA_start:0000000000000004 .LVL10
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:35     .text.MIV_uDMA_config:0000000000000000 .LVL1
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:45     .text.MIV_uDMA_config:0000000000000010 .LVL2
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:79     .text.MIV_uDMA_config:0000000000000068 .LVL6
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:90     .text.MIV_uDMA_config:0000000000000078 .LVL7
C:\Users\I71825\AppData\Local\Temp\cc5Yej2S.s:194    .debug_info:0000000000000000 .Ldebug_info0

UNDEFINED SYMBOLS
HW_set_32bit_reg
HW_set_32bit_reg_field
HW_get_32bit_reg
