   1              		.file	"miv_plic.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.Invalid_IRQHandler,"ax",@progbits
  10              		.align	2
  11              		.weak	Invalid_IRQHandler
  13              	Invalid_IRQHandler:
  14              	.LFB24:
  15              		.file 1 "../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c"
   1:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** /*******************************************************************************
   2:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * Copyright 2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  *
   4:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  *
   6:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * MI-V Soft IP fabric bare-metal driver for Mi-V PLIC module. This module is
   7:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * delivered as a part of Mi-V Extended Sub System(MIV_ESS).
   8:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * Please refer to miv_plic.h file for more information.
   9:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  */
  10:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  
  11:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** #include "miv_plic.h"
  12:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
  13:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** /***************************************************************************//**
  14:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * Mi-V PLIC interrupt handler function declaration.
  15:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * These functions are called by the external interrupt handler of the MIV_RV32
  16:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * core base on the PLIC source causing the interrupt.
  17:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  */
  18:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t Invalid_IRQHandler(void);
  19:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT0_IRQHandler(void);
  20:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT1_IRQHandler(void);
  21:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT2_IRQHandler(void);
  22:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT3_IRQHandler(void);
  23:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT4_IRQHandler(void);
  24:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT5_IRQHandler(void);
  25:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT6_IRQHandler(void);
  26:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT7_IRQHandler(void);
  27:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT8_IRQHandler(void);
  28:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT9_IRQHandler(void);
  29:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT10_IRQHandler(void);
  30:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT11_IRQHandler(void);
  31:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT12_IRQHandler(void);
  32:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT13_IRQHandler(void);
  33:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT14_IRQHandler(void);
  34:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT15_IRQHandler(void);
  35:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT16_IRQHandler(void);
  36:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT17_IRQHandler(void);
  37:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT18_IRQHandler(void);
  38:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT19_IRQHandler(void);
  39:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT20_IRQHandler(void);
  40:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT21_IRQHandler(void);
  41:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT22_IRQHandler(void);
  42:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT23_IRQHandler(void);
  43:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT24_IRQHandler(void);
  44:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT25_IRQHandler(void);
  45:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT26_IRQHandler(void);
  46:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT27_IRQHandler(void);
  47:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT28_IRQHandler(void);
  48:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT29_IRQHandler(void);
  49:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t MIV_PLIC_EXT30_IRQHandler(void);
  50:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
  51:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** /***************************************************************************//**
  52:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * MIV_PLIC interrupt handler for external interrupts.
  53:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * The array of the function pointers pointing to the weak handler of the Mi-V
  54:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * PLIC interrupt handlers.
  55:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * These functions are called by the external interrupt handler of the MIV_RV32
  56:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * core base on the PLIC source causing the interrupt.
  57:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  */
  58:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** uint8_t (* const ext_irq_handler_table[32]) (void) =
  59:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
  60:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     Invalid_IRQHandler,
  61:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT0_IRQHandler,
  62:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT1_IRQHandler,
  63:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT2_IRQHandler,
  64:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT3_IRQHandler,
  65:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT4_IRQHandler,
  66:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT5_IRQHandler,
  67:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT6_IRQHandler,
  68:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT7_IRQHandler,
  69:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT8_IRQHandler,
  70:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT9_IRQHandler,
  71:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT10_IRQHandler,
  72:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT11_IRQHandler,
  73:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT12_IRQHandler,
  74:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT13_IRQHandler,
  75:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT14_IRQHandler,
  76:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT15_IRQHandler,
  77:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT16_IRQHandler,
  78:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT17_IRQHandler,
  79:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT18_IRQHandler,
  80:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT19_IRQHandler,
  81:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT20_IRQHandler,
  82:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT21_IRQHandler,
  83:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT22_IRQHandler,
  84:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT23_IRQHandler,
  85:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT24_IRQHandler,
  86:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT25_IRQHandler,
  87:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT26_IRQHandler,
  88:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT27_IRQHandler,
  89:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT28_IRQHandler,
  90:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT29_IRQHandler,
  91:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     MIV_PLIC_EXT30_IRQHandler
  92:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** };
  93:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
  94:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** /* Mi-V PLIC interrupt weak handlers */
  95:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t Invalid_IRQHandler(void)
  96:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
  16              		.loc 1 96 1
  17              		.cfi_startproc
  97:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
  18              		.loc 1 97 5
  98:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
  19              		.loc 1 98 1 is_stmt 0
  20 0000 13050000 		li	a0,0
  21 0004 67800000 		ret
  22              		.cfi_endproc
  23              	.LFE24:
  25              		.section	.text.MIV_PLIC_EXT30_IRQHandler,"ax",@progbits
  26              		.align	2
  27              		.weak	MIV_PLIC_EXT30_IRQHandler
  29              	MIV_PLIC_EXT30_IRQHandler:
  30              	.LFB119:
  31              		.cfi_startproc
  32 0000 13050000 		li	a0,0
  33 0004 67800000 		ret
  34              		.cfi_endproc
  35              	.LFE119:
  37              		.section	.text.MIV_PLIC_EXT0_IRQHandler,"ax",@progbits
  38              		.align	2
  39              		.weak	MIV_PLIC_EXT0_IRQHandler
  41              	MIV_PLIC_EXT0_IRQHandler:
  42              	.LFB59:
  43              		.cfi_startproc
  44 0000 13050000 		li	a0,0
  45 0004 67800000 		ret
  46              		.cfi_endproc
  47              	.LFE59:
  49              		.section	.text.MIV_PLIC_EXT1_IRQHandler,"ax",@progbits
  50              		.align	2
  51              		.weak	MIV_PLIC_EXT1_IRQHandler
  53              	MIV_PLIC_EXT1_IRQHandler:
  54              	.LFB61:
  55              		.cfi_startproc
  56 0000 13050000 		li	a0,0
  57 0004 67800000 		ret
  58              		.cfi_endproc
  59              	.LFE61:
  61              		.section	.text.MIV_PLIC_EXT2_IRQHandler,"ax",@progbits
  62              		.align	2
  63              		.weak	MIV_PLIC_EXT2_IRQHandler
  65              	MIV_PLIC_EXT2_IRQHandler:
  66              	.LFB63:
  67              		.cfi_startproc
  68 0000 13050000 		li	a0,0
  69 0004 67800000 		ret
  70              		.cfi_endproc
  71              	.LFE63:
  73              		.section	.text.MIV_PLIC_EXT3_IRQHandler,"ax",@progbits
  74              		.align	2
  75              		.weak	MIV_PLIC_EXT3_IRQHandler
  77              	MIV_PLIC_EXT3_IRQHandler:
  78              	.LFB65:
  79              		.cfi_startproc
  80 0000 13050000 		li	a0,0
  81 0004 67800000 		ret
  82              		.cfi_endproc
  83              	.LFE65:
  85              		.section	.text.MIV_PLIC_EXT4_IRQHandler,"ax",@progbits
  86              		.align	2
  87              		.weak	MIV_PLIC_EXT4_IRQHandler
  89              	MIV_PLIC_EXT4_IRQHandler:
  90              	.LFB67:
  91              		.cfi_startproc
  92 0000 13050000 		li	a0,0
  93 0004 67800000 		ret
  94              		.cfi_endproc
  95              	.LFE67:
  97              		.section	.text.MIV_PLIC_EXT5_IRQHandler,"ax",@progbits
  98              		.align	2
  99              		.weak	MIV_PLIC_EXT5_IRQHandler
 101              	MIV_PLIC_EXT5_IRQHandler:
 102              	.LFB69:
 103              		.cfi_startproc
 104 0000 13050000 		li	a0,0
 105 0004 67800000 		ret
 106              		.cfi_endproc
 107              	.LFE69:
 109              		.section	.text.MIV_PLIC_EXT6_IRQHandler,"ax",@progbits
 110              		.align	2
 111              		.weak	MIV_PLIC_EXT6_IRQHandler
 113              	MIV_PLIC_EXT6_IRQHandler:
 114              	.LFB71:
 115              		.cfi_startproc
 116 0000 13050000 		li	a0,0
 117 0004 67800000 		ret
 118              		.cfi_endproc
 119              	.LFE71:
 121              		.section	.text.MIV_PLIC_EXT7_IRQHandler,"ax",@progbits
 122              		.align	2
 123              		.weak	MIV_PLIC_EXT7_IRQHandler
 125              	MIV_PLIC_EXT7_IRQHandler:
 126              	.LFB73:
 127              		.cfi_startproc
 128 0000 13050000 		li	a0,0
 129 0004 67800000 		ret
 130              		.cfi_endproc
 131              	.LFE73:
 133              		.section	.text.MIV_PLIC_EXT8_IRQHandler,"ax",@progbits
 134              		.align	2
 135              		.weak	MIV_PLIC_EXT8_IRQHandler
 137              	MIV_PLIC_EXT8_IRQHandler:
 138              	.LFB75:
 139              		.cfi_startproc
 140 0000 13050000 		li	a0,0
 141 0004 67800000 		ret
 142              		.cfi_endproc
 143              	.LFE75:
 145              		.section	.text.MIV_PLIC_EXT9_IRQHandler,"ax",@progbits
 146              		.align	2
 147              		.weak	MIV_PLIC_EXT9_IRQHandler
 149              	MIV_PLIC_EXT9_IRQHandler:
 150              	.LFB77:
 151              		.cfi_startproc
 152 0000 13050000 		li	a0,0
 153 0004 67800000 		ret
 154              		.cfi_endproc
 155              	.LFE77:
 157              		.section	.text.MIV_PLIC_EXT10_IRQHandler,"ax",@progbits
 158              		.align	2
 159              		.weak	MIV_PLIC_EXT10_IRQHandler
 161              	MIV_PLIC_EXT10_IRQHandler:
 162              	.LFB79:
 163              		.cfi_startproc
 164 0000 13050000 		li	a0,0
 165 0004 67800000 		ret
 166              		.cfi_endproc
 167              	.LFE79:
 169              		.section	.text.MIV_PLIC_EXT11_IRQHandler,"ax",@progbits
 170              		.align	2
 171              		.weak	MIV_PLIC_EXT11_IRQHandler
 173              	MIV_PLIC_EXT11_IRQHandler:
 174              	.LFB81:
 175              		.cfi_startproc
 176 0000 13050000 		li	a0,0
 177 0004 67800000 		ret
 178              		.cfi_endproc
 179              	.LFE81:
 181              		.section	.text.MIV_PLIC_EXT12_IRQHandler,"ax",@progbits
 182              		.align	2
 183              		.weak	MIV_PLIC_EXT12_IRQHandler
 185              	MIV_PLIC_EXT12_IRQHandler:
 186              	.LFB83:
 187              		.cfi_startproc
 188 0000 13050000 		li	a0,0
 189 0004 67800000 		ret
 190              		.cfi_endproc
 191              	.LFE83:
 193              		.section	.text.MIV_PLIC_EXT13_IRQHandler,"ax",@progbits
 194              		.align	2
 195              		.weak	MIV_PLIC_EXT13_IRQHandler
 197              	MIV_PLIC_EXT13_IRQHandler:
 198              	.LFB85:
 199              		.cfi_startproc
 200 0000 13050000 		li	a0,0
 201 0004 67800000 		ret
 202              		.cfi_endproc
 203              	.LFE85:
 205              		.section	.text.MIV_PLIC_EXT14_IRQHandler,"ax",@progbits
 206              		.align	2
 207              		.weak	MIV_PLIC_EXT14_IRQHandler
 209              	MIV_PLIC_EXT14_IRQHandler:
 210              	.LFB87:
 211              		.cfi_startproc
 212 0000 13050000 		li	a0,0
 213 0004 67800000 		ret
 214              		.cfi_endproc
 215              	.LFE87:
 217              		.section	.text.MIV_PLIC_EXT15_IRQHandler,"ax",@progbits
 218              		.align	2
 219              		.weak	MIV_PLIC_EXT15_IRQHandler
 221              	MIV_PLIC_EXT15_IRQHandler:
 222              	.LFB89:
 223              		.cfi_startproc
 224 0000 13050000 		li	a0,0
 225 0004 67800000 		ret
 226              		.cfi_endproc
 227              	.LFE89:
 229              		.section	.text.MIV_PLIC_EXT16_IRQHandler,"ax",@progbits
 230              		.align	2
 231              		.weak	MIV_PLIC_EXT16_IRQHandler
 233              	MIV_PLIC_EXT16_IRQHandler:
 234              	.LFB91:
 235              		.cfi_startproc
 236 0000 13050000 		li	a0,0
 237 0004 67800000 		ret
 238              		.cfi_endproc
 239              	.LFE91:
 241              		.section	.text.MIV_PLIC_EXT17_IRQHandler,"ax",@progbits
 242              		.align	2
 243              		.weak	MIV_PLIC_EXT17_IRQHandler
 245              	MIV_PLIC_EXT17_IRQHandler:
 246              	.LFB93:
 247              		.cfi_startproc
 248 0000 13050000 		li	a0,0
 249 0004 67800000 		ret
 250              		.cfi_endproc
 251              	.LFE93:
 253              		.section	.text.MIV_PLIC_EXT18_IRQHandler,"ax",@progbits
 254              		.align	2
 255              		.weak	MIV_PLIC_EXT18_IRQHandler
 257              	MIV_PLIC_EXT18_IRQHandler:
 258              	.LFB95:
 259              		.cfi_startproc
 260 0000 13050000 		li	a0,0
 261 0004 67800000 		ret
 262              		.cfi_endproc
 263              	.LFE95:
 265              		.section	.text.MIV_PLIC_EXT19_IRQHandler,"ax",@progbits
 266              		.align	2
 267              		.weak	MIV_PLIC_EXT19_IRQHandler
 269              	MIV_PLIC_EXT19_IRQHandler:
 270              	.LFB97:
 271              		.cfi_startproc
 272 0000 13050000 		li	a0,0
 273 0004 67800000 		ret
 274              		.cfi_endproc
 275              	.LFE97:
 277              		.section	.text.MIV_PLIC_EXT20_IRQHandler,"ax",@progbits
 278              		.align	2
 279              		.weak	MIV_PLIC_EXT20_IRQHandler
 281              	MIV_PLIC_EXT20_IRQHandler:
 282              	.LFB99:
 283              		.cfi_startproc
 284 0000 13050000 		li	a0,0
 285 0004 67800000 		ret
 286              		.cfi_endproc
 287              	.LFE99:
 289              		.section	.text.MIV_PLIC_EXT21_IRQHandler,"ax",@progbits
 290              		.align	2
 291              		.weak	MIV_PLIC_EXT21_IRQHandler
 293              	MIV_PLIC_EXT21_IRQHandler:
 294              	.LFB101:
 295              		.cfi_startproc
 296 0000 13050000 		li	a0,0
 297 0004 67800000 		ret
 298              		.cfi_endproc
 299              	.LFE101:
 301              		.section	.text.MIV_PLIC_EXT22_IRQHandler,"ax",@progbits
 302              		.align	2
 303              		.weak	MIV_PLIC_EXT22_IRQHandler
 305              	MIV_PLIC_EXT22_IRQHandler:
 306              	.LFB103:
 307              		.cfi_startproc
 308 0000 13050000 		li	a0,0
 309 0004 67800000 		ret
 310              		.cfi_endproc
 311              	.LFE103:
 313              		.section	.text.MIV_PLIC_EXT23_IRQHandler,"ax",@progbits
 314              		.align	2
 315              		.weak	MIV_PLIC_EXT23_IRQHandler
 317              	MIV_PLIC_EXT23_IRQHandler:
 318              	.LFB105:
 319              		.cfi_startproc
 320 0000 13050000 		li	a0,0
 321 0004 67800000 		ret
 322              		.cfi_endproc
 323              	.LFE105:
 325              		.section	.text.MIV_PLIC_EXT24_IRQHandler,"ax",@progbits
 326              		.align	2
 327              		.weak	MIV_PLIC_EXT24_IRQHandler
 329              	MIV_PLIC_EXT24_IRQHandler:
 330              	.LFB107:
 331              		.cfi_startproc
 332 0000 13050000 		li	a0,0
 333 0004 67800000 		ret
 334              		.cfi_endproc
 335              	.LFE107:
 337              		.section	.text.MIV_PLIC_EXT25_IRQHandler,"ax",@progbits
 338              		.align	2
 339              		.weak	MIV_PLIC_EXT25_IRQHandler
 341              	MIV_PLIC_EXT25_IRQHandler:
 342              	.LFB109:
 343              		.cfi_startproc
 344 0000 13050000 		li	a0,0
 345 0004 67800000 		ret
 346              		.cfi_endproc
 347              	.LFE109:
 349              		.section	.text.MIV_PLIC_EXT26_IRQHandler,"ax",@progbits
 350              		.align	2
 351              		.weak	MIV_PLIC_EXT26_IRQHandler
 353              	MIV_PLIC_EXT26_IRQHandler:
 354              	.LFB111:
 355              		.cfi_startproc
 356 0000 13050000 		li	a0,0
 357 0004 67800000 		ret
 358              		.cfi_endproc
 359              	.LFE111:
 361              		.section	.text.MIV_PLIC_EXT27_IRQHandler,"ax",@progbits
 362              		.align	2
 363              		.weak	MIV_PLIC_EXT27_IRQHandler
 365              	MIV_PLIC_EXT27_IRQHandler:
 366              	.LFB113:
 367              		.cfi_startproc
 368 0000 13050000 		li	a0,0
 369 0004 67800000 		ret
 370              		.cfi_endproc
 371              	.LFE113:
 373              		.section	.text.MIV_PLIC_EXT28_IRQHandler,"ax",@progbits
 374              		.align	2
 375              		.weak	MIV_PLIC_EXT28_IRQHandler
 377              	MIV_PLIC_EXT28_IRQHandler:
 378              	.LFB115:
 379              		.cfi_startproc
 380 0000 13050000 		li	a0,0
 381 0004 67800000 		ret
 382              		.cfi_endproc
 383              	.LFE115:
 385              		.section	.text.MIV_PLIC_EXT29_IRQHandler,"ax",@progbits
 386              		.align	2
 387              		.weak	MIV_PLIC_EXT29_IRQHandler
 389              	MIV_PLIC_EXT29_IRQHandler:
 390              	.LFB117:
 391              		.cfi_startproc
 392 0000 13050000 		li	a0,0
 393 0004 67800000 		ret
 394              		.cfi_endproc
 395              	.LFE117:
 397              		.section	.text.MIV_PLIC_isr,"ax",@progbits
 398              		.align	2
 399              		.globl	MIV_PLIC_isr
 401              	MIV_PLIC_isr:
 402              	.LFB56:
  99:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 100:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT0_IRQHandler(void)
 101:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 102:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 103:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 104:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 105:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT1_IRQHandler(void)
 106:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 107:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 108:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 109:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 110:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT2_IRQHandler(void)
 111:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 112:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 113:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 114:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 115:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT3_IRQHandler(void)
 116:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 117:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 118:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 119:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 120:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT4_IRQHandler(void)
 121:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 122:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 123:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 124:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 125:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT5_IRQHandler(void)
 126:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 127:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 128:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 129:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 130:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT6_IRQHandler(void)
 131:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 132:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 133:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 134:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 135:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT7_IRQHandler(void)
 136:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 137:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 138:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 139:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 140:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT8_IRQHandler(void)
 141:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 142:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 143:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 144:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 145:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT9_IRQHandler(void)
 146:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 147:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 148:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 149:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 150:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT10_IRQHandler(void)
 151:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 152:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 153:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 154:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 155:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT11_IRQHandler(void)
 156:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 157:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 158:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 159:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 160:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT12_IRQHandler(void)
 161:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 162:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 163:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 164:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 165:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT13_IRQHandler(void)
 166:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 167:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 168:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 169:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 170:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT14_IRQHandler(void)
 171:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 172:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 173:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 174:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 175:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT15_IRQHandler(void)
 176:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 177:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 178:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 179:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 180:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT16_IRQHandler(void)
 181:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 182:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 183:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 184:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 185:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT17_IRQHandler(void)
 186:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 187:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 188:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 189:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 190:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT18_IRQHandler(void)
 191:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 192:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 193:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 194:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 195:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT19_IRQHandler(void)
 196:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 197:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 198:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 199:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 200:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT20_IRQHandler(void)
 201:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 202:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 203:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 204:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 205:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT21_IRQHandler(void)
 206:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 207:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 208:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 209:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 210:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT22_IRQHandler(void)
 211:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 212:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 213:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 214:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 215:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT23_IRQHandler(void)
 216:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 217:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 218:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 219:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 220:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT24_IRQHandler(void)
 221:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 222:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 223:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 224:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 225:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT25_IRQHandler(void)
 226:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 227:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 228:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 229:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 230:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT26_IRQHandler(void)
 231:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 232:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 233:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 234:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 235:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT27_IRQHandler(void)
 236:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 237:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 238:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 239:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 240:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT28_IRQHandler(void)
 241:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 242:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 243:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 244:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 245:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT29_IRQHandler(void)
 246:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 247:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 248:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 249:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 250:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** __attribute__((weak)) uint8_t MIV_PLIC_EXT30_IRQHandler(void)
 251:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 252:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     return(0U); /* Default handler */
 253:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 254:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 255:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** /*-------------------------------------------------------------------------*//**
 256:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****  * Please refer to miv_plic.h for more information about this function.
 257:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** */
 258:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** void 
 259:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** MIV_PLIC_isr
 260:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** (
 261:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     miv_plic_instance_t *this_plic
 262:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** )
 263:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** {
 403              		.loc 1 263 1 is_stmt 1
 404              		.cfi_startproc
 405              	.LVL0:
 264:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     unsigned long hart_id = read_csr(mhartid);
 406              		.loc 1 264 5
 407              	.LBB7:
 408              		.loc 1 264 29
 409              		.loc 1 264 29
 410              	.LBE7:
 263:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     unsigned long hart_id = read_csr(mhartid);
 411              		.loc 1 263 1 is_stmt 0
 412 0000 130101FE 		addi	sp,sp,-32
 413              		.cfi_def_cfa_offset 32
 414 0004 23263101 		sw	s3,12(sp)
 415 0008 232E1100 		sw	ra,28(sp)
 416 000c 232C8100 		sw	s0,24(sp)
 417 0010 232A9100 		sw	s1,20(sp)
 418 0014 23282101 		sw	s2,16(sp)
 419 0018 23244101 		sw	s4,8(sp)
 420 001c 23225101 		sw	s5,4(sp)
 421              		.cfi_offset 19, -20
 422              		.cfi_offset 1, -4
 423              		.cfi_offset 8, -8
 424              		.cfi_offset 9, -12
 425              		.cfi_offset 18, -16
 426              		.cfi_offset 20, -24
 427              		.cfi_offset 21, -28
 263:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     unsigned long hart_id = read_csr(mhartid);
 428              		.loc 1 263 1
 429 0020 93090500 		mv	s3,a0
 430              	.LBB8:
 431              		.loc 1 264 29
 432              	 #APP
 433              	# 264 "../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c" 1
 265              	
 434              		csrr s0, mhartid
 435              	# 0 "" 2
 436              	.LVL1:
 264:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     unsigned long hart_id = read_csr(mhartid);
 437              		.loc 1 264 29 is_stmt 1
 438              	 #NO_APP
 439              	.LBE8:
 266:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     /* claim the interrupt from PLIC controller */
 267:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 268:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     uint32_t int_num = HAL_get_32bit_reg(this_plic->base_addr +
 440              		.loc 1 268 5
 441              		.loc 1 268 24 is_stmt 0
 442 0028 03250500 		lw	a0,0(a0)
 443              	.LVL2:
 444 002c 37092000 		li	s2,2097152
 445 0030 13094900 		addi	s2,s2,4
 446 0034 1314C400 		slli	s0,s0,12
 447              	.LVL3:
 448 0038 33052501 		add	a0,a0,s2
 449 003c 33058500 		add	a0,a0,s0
 450 0040 97000000 		call	HW_get_32bit_reg
 450      E7800000 
 451              	.LVL4:
 269:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****                                         (0x1000 * hart_id), INT_CLAIM_COMPLETE);
 270:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 271:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     uint8_t disable = EXT_IRQ_KEEP_ENABLED;
 272:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     disable = ext_irq_handler_table[int_num]();
 452              		.loc 1 272 36
 453 0048 13172500 		slli	a4,a0,2
 454 004c 97070000 		lla	a5,.LANCHOR0
 454      93870700 
 455 0054 B387E700 		add	a5,a5,a4
 456              		.loc 1 272 15
 457 0058 83A70700 		lw	a5,0(a5)
 268:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****                                         (0x1000 * hart_id), INT_CLAIM_COMPLETE);
 458              		.loc 1 268 24
 459 005c 130A0500 		mv	s4,a0
 460              	.LVL5:
 271:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     disable = ext_irq_handler_table[int_num]();
 461              		.loc 1 271 5 is_stmt 1
 462              		.loc 1 272 5
 463              		.loc 1 272 15 is_stmt 0
 464 0060 E7800700 		jalr	a5
 465              	.LVL6:
 466 0064 93040500 		mv	s1,a0
 467              	.LVL7:
 273:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 274:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     /* Indicate the PLIC controller that the interrupt is processed and claim is
 275:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****      * complete. */
 276:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     HAL_set_32bit_reg(this_plic->base_addr +
 468              		.loc 1 276 5 is_stmt 1
 469 0068 03A50900 		lw	a0,0(s3)
 470 006c 93050A00 		mv	a1,s4
 471 0070 33052501 		add	a0,a0,s2
 472 0074 33058500 		add	a0,a0,s0
 473 0078 97000000 		call	HW_set_32bit_reg
 473      E7800000 
 474              	.LVL8:
 277:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****                                 (0x1000 * hart_id), INT_CLAIM_COMPLETE, int_num);
 278:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** 
 279:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     if (EXT_IRQ_DISABLE == disable)
 475              		.loc 1 279 5
 476              		.loc 1 279 8 is_stmt 0
 477 0080 93071000 		li	a5,1
 478 0084 6398F406 		bne	s1,a5,.L33
 280:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     {
 281:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****         MIV_PLIC_disable_irq(this_plic, (miv_plic_irq_num_t)int_num);
 479              		.loc 1 281 9 is_stmt 1
 480              	.LVL9:
 481              	.LBB9:
 482              	.LBB10:
 483              		.file 2 "../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h"
   1:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*******************************************************************************
   2:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Copyright 2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
   4:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * SPDX-License-Identifier: MIT
   5:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
   6:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * of this software and associated documentation files (the "Software"), to
   8:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * deal in the Software without restriction, including without limitation the
   9:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
  10:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * sell copies of the Software, and to permit persons to whom the Software is
  11:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * furnished to do so, subject to the following conditions:
  12:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
  13:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The above copyright notice and this permission notice shall be included in
  14:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * all copies or substantial portions of the Software.
  15:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
  16:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * IN THE SOFTWARE.
  23:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
  24:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * This file contains the application programming interface for the MI-V Soft IP
  25:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * PLIC module driver. This module is delivered as a part of Mi-V Extended
  26:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Sub-System(ESS).
  27:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
  28:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  /*=========================================================================*//**
  29:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   @mainpage Mi-V PLIC Bare Metal Driver
  30:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  31:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  32:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Introduction
  33:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  34:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The Mi-V driver provides a set of functions for controlling the Mi-V PLIC
  35:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   (platform level interrupt controller) soft-IP module. This module is delivered
  36:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   as a part of the MIV_ESS. The PLIC multiplexes external interrupt signals into
  37:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   a single interrupt signal that is connected to an external interrupt of the
  38:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   processor.
  39:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  40:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The major features provided by the driver are:
  41:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Support for configuring the PLIC instances.
  42:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Enabling and Disabling interrupts
  43:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Interrupt Handling
  44:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  45:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   This driver can be used as part of a bare metal system where no operating
  46:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   system  is available. The driver can be adapted for use as part of an
  47:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   operating system, but the implementation of the adaptation layer between the
  48:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   driver and  the operating system's driver model is outside the scope of this
  49:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   driver.
  50:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  51:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  52:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Hardware Flow Dependencies
  53:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  54:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The application software should initialize the Mi-V PLIC through the call to
  55:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   the MIV_PLIC_init() function for Mi-V PLIC instance in the design.
  56:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  57:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   No Mi-V PLIC hardware configuration parameters are used by the driver, apart
  58:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   from the Mi-V PLIC base address. Hence, no additional configuration files
  59:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   are required to use the driver.
  60:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  61:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  62:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Theory of Operation
  63:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ==============================================================================
  64:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The operation of Mi-V PLIC driver is divided into following steps:
  65:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Initialization
  66:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Enabling and Disabling interrupts
  67:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****       - Interrupt control
  68:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  69:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   --------------------------------------------
  70:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Initialization
  71:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   --------------------------------------------
  72:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The Mi-V PLIC module is first initialized by the call to MIV_PLIC_init(). This
  73:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   function takes a pointer to the Mi-V PLIC instance data structure and the base
  74:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   address of the Mi-V PLIC instance is defined by the hardware design. The
  75:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   instance data structure is used to store the base address of the Mi-V PLIC
  76:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   module and a pointer to the Mi-V PLIC register data structure. The Mi-V PLIC
  77:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   register data structure maps the address of the Mi-V PLIC registers.
  78:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  79:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ---------------------------------------------
  80:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Enabling and Disabling interrupts
  81:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ---------------------------------------------
  82:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The MIV_PLIC_enable_irq() function enables the specific interrupt provided by
  83:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   user. A call to this function will allow the enabling of each of the global
  84:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   interrupts corresponding to the bit in the interrupt enable register of Mi-V
  85:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   PLIC.
  86:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   The MIV_PLIC_disable_irq() function disables the specific interrupt provided
  87:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   by the user. This function can be used to disable the interrupts from outside
  88:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   of the external interrupt handler.
  89:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
  90:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ----------------------------------------
  91:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   Interrupt Control
  92:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   ----------------------------------------
  93:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   When an interrupt occurs on an enabled interrupt, the PLIC gateway captures
  94:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   the interrupt and asserts the corresponding interrupt pending bit. Once
  95:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   the enable bit and pending bit are asserted, then the PLIC_IRQ signal asserts
  96:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   until the interrupt is claimed by the driver interrupt handler MIV_PLIC_irq()
  97:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   function.
  98:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   When multiple interrupts assert then the lowest interrupt number will be
  99:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   serviced first, for example, if interrupt 1 and 6 assert at the same time,
 100:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   interrupt 1 will be serviced first, followed by interrupt 6.
 101:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 102:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** */
 103:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 104:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #ifndef MIV_PLIC_H_
 105:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #define MIV_PLIC_H_
 106:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 107:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #ifdef __cplusplus
 108:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** extern "C" {
 109:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #endif
 110:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 111:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include <stdint.h>
 112:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include "miv_plic_regs.h"
 113:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 114:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #ifndef LEGACY_DIR_STRUCTURE
 115:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include "hal/hal.h"
 116:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include "miv_rv32_hal/miv_rv32_hal.h"
 117:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #else
 118:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include "hal.h"
 119:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #include "miv_rv32_hal.h"
 120:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** #endif
 121:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 122:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 123:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   This enumeration is used to select a specific Mi-V PLIC interrupt. It is
 124:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   used as a parameter to enable or disable the interrupt.
 125:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** */
 126:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** typedef enum miv_plic_irq_num
 127:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 128:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     NoInterrupt_IRQn = 0,
 129:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT0_IRQn  = 1,
 130:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT1_IRQn  = 2,
 131:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT2_IRQn  = 3,
 132:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT3_IRQn  = 4,
 133:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT4_IRQn  = 5,
 134:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT5_IRQn  = 6,
 135:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT6_IRQn  = 7,
 136:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT7_IRQn  = 8,
 137:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT8_IRQn  = 9,
 138:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT9_IRQn = 10,
 139:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT10_IRQn = 11,
 140:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT11_IRQn = 12,
 141:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT12_IRQn = 13,
 142:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT13_IRQn = 14,
 143:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT14_IRQn = 15,
 144:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT15_IRQn = 16,
 145:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT16_IRQn = 17,
 146:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT17_IRQn = 18,
 147:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT18_IRQn = 19,
 148:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT19_IRQn = 20,
 149:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT20_IRQn = 21,
 150:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT21_IRQn = 22,
 151:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT22_IRQn = 23,
 152:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT23_IRQn = 24,
 153:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT24_IRQn = 25,
 154:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT25_IRQn = 26,
 155:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT26_IRQn = 27,
 156:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT27_IRQn = 28,
 157:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT28_IRQn = 29,
 158:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT29_IRQn = 30,
 159:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     MIV_PLIC_EXT30_IRQn = 31
 160:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** } miv_plic_irq_num_t;
 161:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 162:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*--------------------------------------------------------------------------*//*
 163:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * This structure maps the priority threshold and claim complete register in
 164:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * the memory.
 165:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 166:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** typedef struct
 167:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 168:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     volatile uint32_t PRIORITY_THRESHOLD;
 169:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     volatile uint32_t CLAIM_COMPLETE;
 170:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     volatile uint32_t reserved[1022];
 171:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** } IRQ_Target_Type;
 172:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 173:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*--------------------------------------------------------------------------*//*
 174:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * This structure maps the Interrupt enable sources from 0 - 1023 for one
 175:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * context.
 176:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 177:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** typedef struct
 178:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 179:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     volatile uint32_t ENABLES[32];
 180:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** } Target_Enables_Type;
 181:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 182:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 183:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   This structure holds the base address of the Mi-V PLIC module. This structure
 184:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****   is used by all the functions to access the Mi-V PLIC registers.
 185:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** */
 186:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** typedef struct miv_plic_instance
 187:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 188:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     addr_t base_addr;
 189:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** } miv_plic_instance_t;
 190:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 191:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 192:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The MIV_PLIC_isr is the top level interrupt handler function for the Mi-V PLIC
 193:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * driver. You must call the MIV_PLIC_isr() from the system level interrupt
 194:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * handler(External_IRQHandler).
 195:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * This function must be called from the external interrupt handler function
 196:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * provided by the processor hardware abstraction layer. In case of MIV_RV32
 197:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * soft processor, it must be called from External_IRQHandler() function
 198:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * provided by MIV_RV32 HAL.
 199:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 200:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The MIV_PLIC_isr() function claims the interrupt number
 201:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * that triggered the interrupt and then invokes the appropriate PLIC interrupt
 202:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * handler.
 203:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * After handling the PLIC interrupt, this function will complete the interrupt
 204:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * by clearing the claim complete bit for the particular interrupt source.
 205:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 206:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param this_plic
 207:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  A pointer to the miv_plic_instance_t data structure which
 208:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  will hold all the data related to the Mi-V PLIC instance
 209:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  being used. A pointer to this data structure is passed to
 210:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  rest of Mi-V PLIC driver functions for operation.
 211:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 212:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @return
 213:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  This function does not return any value.
 214:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 215:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Example:
 216:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @code
 217:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         #define MIV_PLIC_BASE_ADDR          0x70000000
 218:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         #define PLIC_EXT_INTR_SOURCES       31
 219:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 220:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         miv_plic_instance_t g_plic;
 221:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         uint8_t MIV_PLIC_EXT0_IRQHandler(void)
 222:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         {
 223:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             ***  ISR operation  ***
 224:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 225:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             return(EXT_IRQ_KEEP_ENABLED);
 226:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         }
 227:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 228:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         void External_IRQHandler(void)
 229:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         {
 230:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             uint32_t reg_val = read_csr(mip);
 231:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_isr(&g_plic);
 232:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         }
 233:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 234:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         void main(void)
 235:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         {
 236:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_init(&g_plic, MIV_PLIC_BASE_ADDR, PLIC_EXT_INTR_SOURCES);
 237:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 238:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT0_IRQn);
 239:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT1_IRQn);
 240:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT2_IRQn);
 241:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *             MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT3_IRQn);
 242:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         }
 243:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @endcode
 244:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 245:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** void MIV_PLIC_isr(miv_plic_instance_t *this_plic);
 246:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 247:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 248:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The MIV_PLIC_init() function initializes the Mi-V PLIC instance with base
 249:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * address. This function resets the PLIC controller by disabling all the PLIC
 250:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * interrupts.
 251:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 252:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Note: This function must be called before calling any other Mi-V PLIC driver
 253:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * function.
 254:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 255:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param this_plic
 256:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  A pointer to the miv_plic_instance_t data structure which
 257:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  will hold all the data related to the Mi-V PLIC instance
 258:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  being used. A pointer to this data structure is passed to
 259:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  rest of Mi-V PLIC driver functions for operation.
 260:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 261:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param base_addr
 262:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  Base address of the Mi-V PLIC instance in the MIV_ESS soft-IP.
 263:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 264:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param ext_intr_sources
 265:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  Number of interrupts initialized in the design.
 266:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 267:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @return
 268:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  This function does not return any value.
 269:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 270:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Example
 271:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @code
 272:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define MIV_PLIC_BASE_ADDR          0x70000000
 273:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define PLIC_EXT_INTR_SOURCES       31
 274:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 275:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          miv_plic_instance_t g_plic;
 276:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 277:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          void main(void)
 278:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          {
 279:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_init(&g_plic, MIV_PLIC_BASE_ADDR, PLIC_EXT_INTR_SOURCES);
 280:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          }
 281:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @endcode
 282:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 283:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** static inline void
 284:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** MIV_PLIC_init
 285:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** (
 286:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     miv_plic_instance_t *this_plic,
 287:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     addr_t base_addr,
 288:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     uint8_t ext_intr_sources
 289:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** )
 290:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 291:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     uint32_t inc;
 292:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     unsigned long hart_id = read_csr(mhartid);
 293:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 294:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     this_plic->base_addr = base_addr;
 295:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 296:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     /* Disable all interrupts for the current hart.
 297:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****      * The PLIC_EXT_INTR_SOURCES should be defined in the hw_platform.h. This 
 298:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****      * macro holds the number of PLIC interrupts enabled in the design.
 299:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****      */
 300:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     for(inc = 0; inc < ((ext_intr_sources + 32u) / 32u); ++inc)
 301:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     {
 302:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****         HAL_set_32bit_reg(
 303:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****                 (this_plic->base_addr + inc + (hart_id * 128)), INT_ENABLE , 0x0u);
 304:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     }
 305:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** }
 306:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 307:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 308:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The MIV_PLIC_enable_irq() function enables the PLIC interrupt provided with
 309:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * IRQn parameter.
 310:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 311:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param this_plic
 312:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  A pointer to the miv_plic_instance_t data structure which
 313:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  will hold all the data related to the Mi-V PLIC instance
 314:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  being used. A pointer to this data structure is passed to
 315:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  rest of Mi-V PLIC driver functions for operation.
 316:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param IRQn
 317:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  Number of PLIC interrupt to enable.
 318:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 319:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @return
 320:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                 This function does not return any value.
 321:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 322:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Example
 323:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @code
 324:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define MIV_PLIC_BASE_ADDR          0x70000000
 325:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define PLIC_EXT_INTR_SOURCES       31
 326:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 327:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          miv_plic_instance_t g_plic;
 328:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 329:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          void main(void)
 330:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          {
 331:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_init(&g_plic, MIV_PLIC_BASE_ADDR, PLIC_EXT_INTR_SOURCES);
 332:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 333:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT0_IRQn);
 334:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT1_IRQn);
 335:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT2_IRQn);
 336:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT3_IRQn);
 337:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         }
 338:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @endcode
 339:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 340:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** static inline void
 341:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** MIV_PLIC_enable_irq
 342:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** (
 343:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****         miv_plic_instance_t *this_plic,
 344:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****         miv_plic_irq_num_t IRQn
 345:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** )
 346:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 347:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     unsigned long hart_id = read_csr(mhartid);
 348:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 349:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     uint32_t current = HAL_get_32bit_reg(
 350:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****             (this_plic->base_addr + (IRQn/32) + (hart_id * 128)) , INT_ENABLE);
 351:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 352:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     current |= (uint32_t)1 << (IRQn % 32);
 353:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 354:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     HAL_set_32bit_reg(
 355:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****             (this_plic->base_addr + (IRQn/32) + (hart_id * 128)), INT_ENABLE, current);
 356:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 357:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** }
 358:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 359:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** /*-------------------------------------------------------------------------*//**
 360:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * The MIV_PLIC_disable_irq() function disables the PLIC interrupt provided with
 361:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * IRQn parameter.
 362:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 363:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * NOTE:
 364:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * This function can be used to disable the PLIC interrupt from outside the
 365:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * external interrupt handler functions.
 366:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * If you wish to disable the PLIC interrupt from the external interrupt handler,
 367:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * you should use the return value of EXT_IRQ_DISABLE. This will disable the
 368:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * selected PLIC interrupt from the Mi-V PLIC driver interrupt handler.
 369:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 370:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param this_plic
 371:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  A pointer to the miv_plic_instance_t data structure which
 372:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  will hold all the data related to the Mi-V PLIC instance
 373:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  being used. A pointer to this data structure is passed to
 374:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  rest of Mi-V PLIC driver functions for operation.
 375:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @param IRQn
 376:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                  Number of PLIC interrupt to disable.
 377:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 378:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @return
 379:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *                 This function does not return any value.
 380:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 381:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * Example
 382:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @code
 383:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define MIV_PLIC_BASE_ADDR          0x70000000
 384:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          #define PLIC_EXT_INTR_SOURCES       31
 385:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 386:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          miv_plic_instance_t g_plic;
 387:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 388:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          void main(void)
 389:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *          {
 390:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_init(&g_plic, MIV_PLIC_BASE_ADDR, PLIC_EXT_INTR_SOURCES);
 391:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 392:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT0_IRQn);
 393:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT1_IRQn);
 394:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT2_IRQn);
 395:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_enable_irq(&g_plic, MIV_PLIC_EXT3_IRQn);
 396:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *
 397:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_disable_irq(&g_plic, MIV_PLIC_EXT0_IRQn);
 398:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_disable_irq(&g_plic, MIV_PLIC_EXT1_IRQn);
 399:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_disable_irq(&g_plic, MIV_PLIC_EXT2_IRQn);
 400:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *              MIV_PLIC_disable_irq(&g_plic, MIV_PLIC_EXT3_IRQn);
 401:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  *         }
 402:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  * @endcode
 403:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****  */
 404:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** static inline void
 405:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** MIV_PLIC_disable_irq
 406:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** (
 407:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****         miv_plic_instance_t *this_plic,
 408:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****         miv_plic_irq_num_t IRQn
 409:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** )
 410:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** {
 411:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     unsigned long hart_id = read_csr(mhartid);
 484              		.loc 2 411 5
 485              	.LBB11:
 486              		.loc 2 411 29
 487              		.loc 2 411 29
 488              	 #APP
 489              	# 411 "../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h" 1
 412              	
 490              		csrr s2, mhartid
 491              	# 0 "" 2
 492              	.LVL10:
 411:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     unsigned long hart_id = read_csr(mhartid);
 493              		.loc 2 411 29
 494              	 #NO_APP
 495              	.LBE11:
 413:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     uint32_t current = HAL_get_32bit_reg((this_plic->base_addr + (IRQn/32) + (hart_id * 128)) , INT
 496              		.loc 2 413 5
 497              		.loc 2 413 24 is_stmt 0
 498 008c 03A50900 		lw	a0,0(s3)
 499 0090 37240000 		li	s0,8192
 500 0094 935A5A00 		srli	s5,s4,5
 501 0098 3305A400 		add	a0,s0,a0
 502 009c 13197900 		slli	s2,s2,7
 503              	.LVL11:
 504 00a0 33055501 		add	a0,a0,s5
 505 00a4 33052501 		add	a0,a0,s2
 506 00a8 97000000 		call	HW_get_32bit_reg
 506      E7800000 
 507              	.LVL12:
 414:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 415:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     current &= ~((uint32_t)1 << (IRQn % 32));
 508              		.loc 2 415 5 is_stmt 1
 416:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 417:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h ****     HAL_set_32bit_reg((this_plic->base_addr + (IRQn/32) + (hart_id * 128)), INT_ENABLE, current);
 509              		.loc 2 417 5
 510 00b0 83A70900 		lw	a5,0(s3)
 415:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 511              		.loc 2 415 30 is_stmt 0
 512 00b4 B3954401 		sll	a1,s1,s4
 415:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h **** 
 513              		.loc 2 415 16
 514 00b8 93C5F5FF 		not	a1,a1
 515              		.loc 2 417 5
 516 00bc 3304F400 		add	s0,s0,a5
 517 00c0 33045401 		add	s0,s0,s5
 518 00c4 B3F5A500 		and	a1,a1,a0
 519 00c8 33052401 		add	a0,s0,s2
 520              	.LVL13:
 521              	.LBE10:
 522              	.LBE9:
 282:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c ****     }
 283:../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c **** }
 523              		.loc 1 283 1
 524 00cc 03248101 		lw	s0,24(sp)
 525              		.cfi_remember_state
 526              		.cfi_restore 8
 527 00d0 8320C101 		lw	ra,28(sp)
 528              		.cfi_restore 1
 529 00d4 83244101 		lw	s1,20(sp)
 530              		.cfi_restore 9
 531              	.LVL14:
 532 00d8 03290101 		lw	s2,16(sp)
 533              		.cfi_restore 18
 534 00dc 8329C100 		lw	s3,12(sp)
 535              		.cfi_restore 19
 536              	.LVL15:
 537 00e0 032A8100 		lw	s4,8(sp)
 538              		.cfi_restore 20
 539              	.LVL16:
 540 00e4 832A4100 		lw	s5,4(sp)
 541              		.cfi_restore 21
 542 00e8 13010102 		addi	sp,sp,32
 543              		.cfi_def_cfa_offset 0
 544              	.LBB13:
 545              	.LBB12:
 546              		.loc 2 417 5
 547 00ec 17030000 		tail	HW_set_32bit_reg
 547      67000300 
 548              	.LVL17:
 549              	.L33:
 550              		.cfi_restore_state
 551              	.LBE12:
 552              	.LBE13:
 553              		.loc 1 283 1
 554 00f4 8320C101 		lw	ra,28(sp)
 555              		.cfi_restore 1
 556 00f8 03248101 		lw	s0,24(sp)
 557              		.cfi_restore 8
 558 00fc 83244101 		lw	s1,20(sp)
 559              		.cfi_restore 9
 560              	.LVL18:
 561 0100 03290101 		lw	s2,16(sp)
 562              		.cfi_restore 18
 563 0104 8329C100 		lw	s3,12(sp)
 564              		.cfi_restore 19
 565              	.LVL19:
 566 0108 032A8100 		lw	s4,8(sp)
 567              		.cfi_restore 20
 568              	.LVL20:
 569 010c 832A4100 		lw	s5,4(sp)
 570              		.cfi_restore 21
 571 0110 13010102 		addi	sp,sp,32
 572              		.cfi_def_cfa_offset 0
 573 0114 67800000 		jr	ra
 574              		.cfi_endproc
 575              	.LFE56:
 577              		.globl	ext_irq_handler_table
 578              		.comm	MRV_LOCAL_IRQn_Type,4,4
 579              		.section	.rodata.ext_irq_handler_table,"a"
 580              		.align	2
 581              		.set	.LANCHOR0,. + 0
 584              	ext_irq_handler_table:
 585 0000 00000000 		.word	Invalid_IRQHandler
 586 0004 00000000 		.word	MIV_PLIC_EXT0_IRQHandler
 587 0008 00000000 		.word	MIV_PLIC_EXT1_IRQHandler
 588 000c 00000000 		.word	MIV_PLIC_EXT2_IRQHandler
 589 0010 00000000 		.word	MIV_PLIC_EXT3_IRQHandler
 590 0014 00000000 		.word	MIV_PLIC_EXT4_IRQHandler
 591 0018 00000000 		.word	MIV_PLIC_EXT5_IRQHandler
 592 001c 00000000 		.word	MIV_PLIC_EXT6_IRQHandler
 593 0020 00000000 		.word	MIV_PLIC_EXT7_IRQHandler
 594 0024 00000000 		.word	MIV_PLIC_EXT8_IRQHandler
 595 0028 00000000 		.word	MIV_PLIC_EXT9_IRQHandler
 596 002c 00000000 		.word	MIV_PLIC_EXT10_IRQHandler
 597 0030 00000000 		.word	MIV_PLIC_EXT11_IRQHandler
 598 0034 00000000 		.word	MIV_PLIC_EXT12_IRQHandler
 599 0038 00000000 		.word	MIV_PLIC_EXT13_IRQHandler
 600 003c 00000000 		.word	MIV_PLIC_EXT14_IRQHandler
 601 0040 00000000 		.word	MIV_PLIC_EXT15_IRQHandler
 602 0044 00000000 		.word	MIV_PLIC_EXT16_IRQHandler
 603 0048 00000000 		.word	MIV_PLIC_EXT17_IRQHandler
 604 004c 00000000 		.word	MIV_PLIC_EXT18_IRQHandler
 605 0050 00000000 		.word	MIV_PLIC_EXT19_IRQHandler
 606 0054 00000000 		.word	MIV_PLIC_EXT20_IRQHandler
 607 0058 00000000 		.word	MIV_PLIC_EXT21_IRQHandler
 608 005c 00000000 		.word	MIV_PLIC_EXT22_IRQHandler
 609 0060 00000000 		.word	MIV_PLIC_EXT23_IRQHandler
 610 0064 00000000 		.word	MIV_PLIC_EXT24_IRQHandler
 611 0068 00000000 		.word	MIV_PLIC_EXT25_IRQHandler
 612 006c 00000000 		.word	MIV_PLIC_EXT26_IRQHandler
 613 0070 00000000 		.word	MIV_PLIC_EXT27_IRQHandler
 614 0074 00000000 		.word	MIV_PLIC_EXT28_IRQHandler
 615 0078 00000000 		.word	MIV_PLIC_EXT29_IRQHandler
 616 007c 00000000 		.word	MIV_PLIC_EXT30_IRQHandler
 617              		.text
 618              	.Letext0:
 619              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 620              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 621              		.file 5 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
 622              		.file 6 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
 623              		.file 7 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
DEFINED SYMBOLS
                            *ABS*:0000000000000000 miv_plic.c
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:13     .text.Invalid_IRQHandler:0000000000000000 Invalid_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:17     .text.Invalid_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:18     .text.Invalid_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:19     .text.Invalid_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:20     .text.Invalid_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:22     .text.Invalid_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:29     .text.MIV_PLIC_EXT30_IRQHandler:0000000000000000 MIV_PLIC_EXT30_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:31     .text.MIV_PLIC_EXT30_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:34     .text.MIV_PLIC_EXT30_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:41     .text.MIV_PLIC_EXT0_IRQHandler:0000000000000000 MIV_PLIC_EXT0_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:43     .text.MIV_PLIC_EXT0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:46     .text.MIV_PLIC_EXT0_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:53     .text.MIV_PLIC_EXT1_IRQHandler:0000000000000000 MIV_PLIC_EXT1_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:55     .text.MIV_PLIC_EXT1_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:58     .text.MIV_PLIC_EXT1_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:65     .text.MIV_PLIC_EXT2_IRQHandler:0000000000000000 MIV_PLIC_EXT2_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:67     .text.MIV_PLIC_EXT2_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:70     .text.MIV_PLIC_EXT2_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:77     .text.MIV_PLIC_EXT3_IRQHandler:0000000000000000 MIV_PLIC_EXT3_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:79     .text.MIV_PLIC_EXT3_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:82     .text.MIV_PLIC_EXT3_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:89     .text.MIV_PLIC_EXT4_IRQHandler:0000000000000000 MIV_PLIC_EXT4_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:91     .text.MIV_PLIC_EXT4_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:94     .text.MIV_PLIC_EXT4_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:101    .text.MIV_PLIC_EXT5_IRQHandler:0000000000000000 MIV_PLIC_EXT5_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:103    .text.MIV_PLIC_EXT5_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:106    .text.MIV_PLIC_EXT5_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:113    .text.MIV_PLIC_EXT6_IRQHandler:0000000000000000 MIV_PLIC_EXT6_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:115    .text.MIV_PLIC_EXT6_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:118    .text.MIV_PLIC_EXT6_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:125    .text.MIV_PLIC_EXT7_IRQHandler:0000000000000000 MIV_PLIC_EXT7_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:127    .text.MIV_PLIC_EXT7_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:130    .text.MIV_PLIC_EXT7_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:137    .text.MIV_PLIC_EXT8_IRQHandler:0000000000000000 MIV_PLIC_EXT8_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:139    .text.MIV_PLIC_EXT8_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:142    .text.MIV_PLIC_EXT8_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:149    .text.MIV_PLIC_EXT9_IRQHandler:0000000000000000 MIV_PLIC_EXT9_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:151    .text.MIV_PLIC_EXT9_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:154    .text.MIV_PLIC_EXT9_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:161    .text.MIV_PLIC_EXT10_IRQHandler:0000000000000000 MIV_PLIC_EXT10_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:163    .text.MIV_PLIC_EXT10_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:166    .text.MIV_PLIC_EXT10_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:173    .text.MIV_PLIC_EXT11_IRQHandler:0000000000000000 MIV_PLIC_EXT11_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:175    .text.MIV_PLIC_EXT11_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:178    .text.MIV_PLIC_EXT11_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:185    .text.MIV_PLIC_EXT12_IRQHandler:0000000000000000 MIV_PLIC_EXT12_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:187    .text.MIV_PLIC_EXT12_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:190    .text.MIV_PLIC_EXT12_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:197    .text.MIV_PLIC_EXT13_IRQHandler:0000000000000000 MIV_PLIC_EXT13_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:199    .text.MIV_PLIC_EXT13_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:202    .text.MIV_PLIC_EXT13_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:209    .text.MIV_PLIC_EXT14_IRQHandler:0000000000000000 MIV_PLIC_EXT14_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:211    .text.MIV_PLIC_EXT14_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:214    .text.MIV_PLIC_EXT14_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:221    .text.MIV_PLIC_EXT15_IRQHandler:0000000000000000 MIV_PLIC_EXT15_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:223    .text.MIV_PLIC_EXT15_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:226    .text.MIV_PLIC_EXT15_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:233    .text.MIV_PLIC_EXT16_IRQHandler:0000000000000000 MIV_PLIC_EXT16_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:235    .text.MIV_PLIC_EXT16_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:238    .text.MIV_PLIC_EXT16_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:245    .text.MIV_PLIC_EXT17_IRQHandler:0000000000000000 MIV_PLIC_EXT17_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:247    .text.MIV_PLIC_EXT17_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:250    .text.MIV_PLIC_EXT17_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:257    .text.MIV_PLIC_EXT18_IRQHandler:0000000000000000 MIV_PLIC_EXT18_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:259    .text.MIV_PLIC_EXT18_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:262    .text.MIV_PLIC_EXT18_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:269    .text.MIV_PLIC_EXT19_IRQHandler:0000000000000000 MIV_PLIC_EXT19_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:271    .text.MIV_PLIC_EXT19_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:274    .text.MIV_PLIC_EXT19_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:281    .text.MIV_PLIC_EXT20_IRQHandler:0000000000000000 MIV_PLIC_EXT20_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:283    .text.MIV_PLIC_EXT20_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:286    .text.MIV_PLIC_EXT20_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:293    .text.MIV_PLIC_EXT21_IRQHandler:0000000000000000 MIV_PLIC_EXT21_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:295    .text.MIV_PLIC_EXT21_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:298    .text.MIV_PLIC_EXT21_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:305    .text.MIV_PLIC_EXT22_IRQHandler:0000000000000000 MIV_PLIC_EXT22_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:307    .text.MIV_PLIC_EXT22_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:310    .text.MIV_PLIC_EXT22_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:317    .text.MIV_PLIC_EXT23_IRQHandler:0000000000000000 MIV_PLIC_EXT23_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:319    .text.MIV_PLIC_EXT23_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:322    .text.MIV_PLIC_EXT23_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:329    .text.MIV_PLIC_EXT24_IRQHandler:0000000000000000 MIV_PLIC_EXT24_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:331    .text.MIV_PLIC_EXT24_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:334    .text.MIV_PLIC_EXT24_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:341    .text.MIV_PLIC_EXT25_IRQHandler:0000000000000000 MIV_PLIC_EXT25_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:343    .text.MIV_PLIC_EXT25_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:346    .text.MIV_PLIC_EXT25_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:353    .text.MIV_PLIC_EXT26_IRQHandler:0000000000000000 MIV_PLIC_EXT26_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:355    .text.MIV_PLIC_EXT26_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:358    .text.MIV_PLIC_EXT26_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:365    .text.MIV_PLIC_EXT27_IRQHandler:0000000000000000 MIV_PLIC_EXT27_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:367    .text.MIV_PLIC_EXT27_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:370    .text.MIV_PLIC_EXT27_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:377    .text.MIV_PLIC_EXT28_IRQHandler:0000000000000000 MIV_PLIC_EXT28_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:379    .text.MIV_PLIC_EXT28_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:382    .text.MIV_PLIC_EXT28_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:389    .text.MIV_PLIC_EXT29_IRQHandler:0000000000000000 MIV_PLIC_EXT29_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:391    .text.MIV_PLIC_EXT29_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:394    .text.MIV_PLIC_EXT29_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:401    .text.MIV_PLIC_isr:0000000000000000 MIV_PLIC_isr
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:404    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:406    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:408    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:409    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:411    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:412    .text.MIV_PLIC_isr:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:413    .text.MIV_PLIC_isr:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:421    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:422    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:423    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:424    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:425    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:426    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:427    .text.MIV_PLIC_isr:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:429    .text.MIV_PLIC_isr:0000000000000020 .L0 
../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c:264    .text.MIV_PLIC_isr:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:440    .text.MIV_PLIC_isr:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:441    .text.MIV_PLIC_isr:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:442    .text.MIV_PLIC_isr:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:453    .text.MIV_PLIC_isr:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:457    .text.MIV_PLIC_isr:0000000000000058 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:459    .text.MIV_PLIC_isr:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:462    .text.MIV_PLIC_isr:0000000000000060 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:463    .text.MIV_PLIC_isr:0000000000000060 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:464    .text.MIV_PLIC_isr:0000000000000060 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:469    .text.MIV_PLIC_isr:0000000000000068 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:476    .text.MIV_PLIC_isr:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:477    .text.MIV_PLIC_isr:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:484    .text.MIV_PLIC_isr:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:486    .text.MIV_PLIC_isr:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:487    .text.MIV_PLIC_isr:0000000000000088 .L0 
../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h:411    .text.MIV_PLIC_isr:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:496    .text.MIV_PLIC_isr:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:497    .text.MIV_PLIC_isr:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:498    .text.MIV_PLIC_isr:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:509    .text.MIV_PLIC_isr:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:510    .text.MIV_PLIC_isr:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:512    .text.MIV_PLIC_isr:00000000000000b4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:514    .text.MIV_PLIC_isr:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:516    .text.MIV_PLIC_isr:00000000000000bc .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:524    .text.MIV_PLIC_isr:00000000000000cc .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:525    .text.MIV_PLIC_isr:00000000000000d0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:526    .text.MIV_PLIC_isr:00000000000000d0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:528    .text.MIV_PLIC_isr:00000000000000d4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:530    .text.MIV_PLIC_isr:00000000000000d8 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:533    .text.MIV_PLIC_isr:00000000000000dc .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:535    .text.MIV_PLIC_isr:00000000000000e0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:538    .text.MIV_PLIC_isr:00000000000000e4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:541    .text.MIV_PLIC_isr:00000000000000e8 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:543    .text.MIV_PLIC_isr:00000000000000ec .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:547    .text.MIV_PLIC_isr:00000000000000ec .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:550    .text.MIV_PLIC_isr:00000000000000f4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:554    .text.MIV_PLIC_isr:00000000000000f4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:555    .text.MIV_PLIC_isr:00000000000000f8 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:557    .text.MIV_PLIC_isr:00000000000000fc .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:559    .text.MIV_PLIC_isr:0000000000000100 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:562    .text.MIV_PLIC_isr:0000000000000104 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:564    .text.MIV_PLIC_isr:0000000000000108 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:567    .text.MIV_PLIC_isr:000000000000010c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:570    .text.MIV_PLIC_isr:0000000000000110 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:572    .text.MIV_PLIC_isr:0000000000000114 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:574    .text.MIV_PLIC_isr:0000000000000118 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:584    .rodata.ext_irq_handler_table:0000000000000000 ext_irq_handler_table
                            *COM*:0000000000000004 MRV_LOCAL_IRQn_Type
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:581    .rodata.ext_irq_handler_table:0000000000000000 .LANCHOR0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:25     .text.Invalid_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:579    .text.MIV_PLIC_isr:0000000000000118 .L0 
                     .debug_frame:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:454    .text.MIV_PLIC_isr:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:549    .text.MIV_PLIC_isr:00000000000000f4 .L33
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1349   .debug_abbrev:0000000000000000 .Ldebug_abbrev0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2216   .debug_str:0000000000000598 .LASF122
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2278   .debug_str:000000000000087b .LASF123
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2296   .debug_str:0000000000000936 .LASF124
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2028   .debug_ranges:0000000000000000 .Ldebug_ranges0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2048   .debug_line:0000000000000000 .Ldebug_line0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2094   .debug_str:0000000000000187 .LASF0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2062   .debug_str:0000000000000079 .LASF5
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2236   .debug_str:000000000000070a .LASF1
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2240   .debug_str:0000000000000732 .LASF2
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2160   .debug_str:00000000000003be .LASF3
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2106   .debug_str:00000000000001e7 .LASF4
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2130   .debug_str:00000000000002cd .LASF6
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2152   .debug_str:0000000000000365 .LASF7
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2092   .debug_str:0000000000000179 .LASF8
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2076   .debug_str:00000000000000e3 .LASF9
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2146   .debug_str:0000000000000341 .LASF10
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2290   .debug_str:000000000000090e .LASF11
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2254   .debug_str:00000000000007b0 .LASF12
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2304   .debug_str:00000000000009f7 .LASF13
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2116   .debug_str:0000000000000244 .LASF14
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2150   .debug_str:000000000000035a .LASF15
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2184   .debug_str:0000000000000494 .LASF16
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2288   .debug_str:0000000000000903 .LASF17
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2054   .debug_str:0000000000000026 .LASF18
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2090   .debug_str:000000000000016e .LASF19
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2206   .debug_str:000000000000054c .LASF20
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2244   .debug_str:0000000000000748 .LASF21
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2268   .debug_str:0000000000000827 .LASF22
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2118   .debug_str:000000000000024f .LASF23
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2220   .debug_str:0000000000000677 .LASF24
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2258   .debug_str:00000000000007cd .LASF25
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2098   .debug_str:00000000000001ad .LASF26
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2132   .debug_str:00000000000002d8 .LASF27
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2164   .debug_str:00000000000003eb .LASF28
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2272   .debug_str:000000000000084b .LASF29
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2176   .debug_str:000000000000044f .LASF30
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2068   .debug_str:00000000000000a2 .LASF31
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2190   .debug_str:00000000000004be .LASF32
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2224   .debug_str:0000000000000697 .LASF33
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2082   .debug_str:000000000000012e .LASF34
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2202   .debug_str:0000000000000538 .LASF35
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2242   .debug_str:000000000000073c .LASF36
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2264   .debug_str:0000000000000807 .LASF37
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2292   .debug_str:0000000000000916 .LASF38
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2148   .debug_str:000000000000034e .LASF39
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2180   .debug_str:0000000000000474 .LASF40
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2212   .debug_str:0000000000000578 .LASF41
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2052   .debug_str:000000000000001a .LASF42
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2086   .debug_str:000000000000014e .LASF43
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2234   .debug_str:00000000000006fe .LASF44
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2066   .debug_str:0000000000000096 .LASF45
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2262   .debug_str:00000000000007f3 .LASF80
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2274   .debug_str:0000000000000857 .LASF125
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2302   .debug_str:00000000000009e6 .LASF46
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2276   .debug_str:0000000000000868 .LASF47
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2308   .debug_str:0000000000000a12 .LASF48
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2170   .debug_str:000000000000041f .LASF49
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2196   .debug_str:00000000000004fd .LASF50
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2230   .debug_str:00000000000006d1 .LASF51
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2064   .debug_str:0000000000000083 .LASF52
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2102   .debug_str:00000000000001c1 .LASF53
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2140   .debug_str:0000000000000317 .LASF54
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2172   .debug_str:0000000000000432 .LASF55
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2280   .debug_str:00000000000008af .LASF56
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2222   .debug_str:0000000000000683 .LASF57
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2256   .debug_str:00000000000007b9 .LASF58
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2282   .debug_str:00000000000008c2 .LASF59
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2134   .debug_str:00000000000002e4 .LASF60
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2166   .debug_str:00000000000003f7 .LASF61
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2198   .debug_str:0000000000000510 .LASF62
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2306   .debug_str:00000000000009fe .LASF63
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2070   .debug_str:00000000000000ae .LASF64
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2168   .debug_str:000000000000040b .LASF65
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2226   .debug_str:00000000000006a3 .LASF66
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2084   .debug_str:000000000000013a .LASF67
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2126   .debug_str:000000000000029f .LASF68
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2158   .debug_str:00000000000003aa .LASF69
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2266   .debug_str:0000000000000813 .LASF70
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2294   .debug_str:0000000000000922 .LASF71
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2058   .debug_str:000000000000004b .LASF72
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2182   .debug_str:0000000000000480 .LASF73
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2214   .debug_str:0000000000000584 .LASF74
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2250   .debug_str:0000000000000783 .LASF75
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2088   .debug_str:000000000000015a .LASF76
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2200   .debug_str:0000000000000524 .LASF77
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2286   .debug_str:00000000000008f0 .LASF78
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2122   .debug_str:0000000000000274 .LASF126
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2174   .debug_str:0000000000000445 .LASF127
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2110   .debug_str:0000000000000205 .LASF79
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2248   .debug_str:000000000000076d .LASF81
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2144   .debug_str:0000000000000334 .LASF128
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:402    .text.MIV_PLIC_isr:0000000000000000 .LFB56
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:575    .text.MIV_PLIC_isr:0000000000000118 .LFE56
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2142   .debug_str:000000000000032a .LASF117
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1893   .debug_loc:0000000000000000 .LLST0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2072   .debug_str:00000000000000c2 .LASF82
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1922   .debug_loc:0000000000000045 .LLST1
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2204   .debug_str:0000000000000544 .LASF83
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1929   .debug_loc:0000000000000058 .LLST2
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2100   .debug_str:00000000000001b9 .LASF84
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1944   .debug_loc:0000000000000081 .LLST3
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2136   .debug_str:00000000000002f8 .LASF85
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:481    .text.MIV_PLIC_isr:0000000000000088 .LBB9
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1960   .debug_loc:00000000000000ab .LLST5
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1974   .debug_loc:00000000000000cc .LLST6
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1981   .debug_loc:00000000000000df .LLST7
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:1988   .debug_loc:00000000000000f2 .LLST8
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:485    .text.MIV_PLIC_isr:0000000000000088 .LBB11
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:495    .text.MIV_PLIC_isr:000000000000008c .LBE11
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:507    .text.MIV_PLIC_isr:00000000000000b0 .LVL12
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:548    .text.MIV_PLIC_isr:00000000000000f4 .LVL17
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:451    .text.MIV_PLIC_isr:0000000000000048 .LVL4
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:465    .text.MIV_PLIC_isr:0000000000000064 .LVL6
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:474    .text.MIV_PLIC_isr:0000000000000080 .LVL8
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2300   .debug_str:00000000000009cc .LASF86
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2156   .debug_str:0000000000000390 .LASF87
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2050   .debug_str:0000000000000000 .LASF88
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2232   .debug_str:00000000000006e4 .LASF89
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2128   .debug_str:00000000000002b3 .LASF90
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2112   .debug_str:0000000000000219 .LASF91
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2228   .debug_str:00000000000006b7 .LASF92
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2186   .debug_str:000000000000049f .LASF93
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2078   .debug_str:00000000000000fa .LASF94
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2060   .debug_str:000000000000005f .LASF95
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2246   .debug_str:0000000000000753 .LASF96
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2080   .debug_str:0000000000000114 .LASF97
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2260   .debug_str:00000000000007d9 .LASF98
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2162   .debug_str:00000000000003d1 .LASF99
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2056   .debug_str:0000000000000031 .LASF100
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2238   .debug_str:0000000000000718 .LASF101
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2218   .debug_str:000000000000065d .LASF102
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2120   .debug_str:000000000000025a .LASF103
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2284   .debug_str:00000000000008d6 .LASF104
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2192   .debug_str:00000000000004ca .LASF105
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2096   .debug_str:0000000000000193 .LASF106
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2124   .debug_str:0000000000000286 .LASF107
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2194   .debug_str:00000000000004e4 .LASF108
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2270   .debug_str:0000000000000832 .LASF109
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2178   .debug_str:000000000000045b .LASF110
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2074   .debug_str:00000000000000ca .LASF111
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2252   .debug_str:0000000000000797 .LASF112
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2154   .debug_str:0000000000000377 .LASF113
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2138   .debug_str:00000000000002fe .LASF114
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2298   .debug_str:00000000000009b3 .LASF115
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2208   .debug_str:0000000000000557 .LASF116
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2104   .debug_str:00000000000001d4 .LASF129
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2108   .debug_str:00000000000001f0 .LASF130
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2188   .debug_str:00000000000004b9 .LASF118
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2210   .debug_str:0000000000000570 .LASF119
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:14     .text.Invalid_IRQHandler:0000000000000000 .LFB24
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:23     .text.Invalid_IRQHandler:0000000000000008 .LFE24
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2114   .debug_str:0000000000000233 .LASF120
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:2310   .debug_str:0000000000000a25 .LASF121
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:405    .text.MIV_PLIC_isr:0000000000000000 .LVL0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:443    .text.MIV_PLIC_isr:000000000000002c .LVL2
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:536    .text.MIV_PLIC_isr:00000000000000e0 .LVL15
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:565    .text.MIV_PLIC_isr:0000000000000108 .LVL19
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:436    .text.MIV_PLIC_isr:0000000000000028 .LVL1
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:447    .text.MIV_PLIC_isr:0000000000000038 .LVL3
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:460    .text.MIV_PLIC_isr:0000000000000060 .LVL5
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:539    .text.MIV_PLIC_isr:00000000000000e4 .LVL16
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:568    .text.MIV_PLIC_isr:000000000000010c .LVL20
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:467    .text.MIV_PLIC_isr:0000000000000068 .LVL7
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:531    .text.MIV_PLIC_isr:00000000000000d8 .LVL14
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:560    .text.MIV_PLIC_isr:0000000000000100 .LVL18
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:480    .text.MIV_PLIC_isr:0000000000000088 .LVL9
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:492    .text.MIV_PLIC_isr:000000000000008c .LVL10
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:503    .text.MIV_PLIC_isr:00000000000000a0 .LVL11
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:520    .text.MIV_PLIC_isr:00000000000000cc .LVL13
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:625    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:407    .text.MIV_PLIC_isr:0000000000000000 .LBB7
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:410    .text.MIV_PLIC_isr:0000000000000000 .LBE7
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:430    .text.MIV_PLIC_isr:0000000000000024 .LBB8
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:439    .text.MIV_PLIC_isr:0000000000000028 .LBE8
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:522    .text.MIV_PLIC_isr:00000000000000cc .LBE9
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:544    .text.MIV_PLIC_isr:00000000000000ec .LBB13
C:\Users\I71825\AppData\Local\Temp\ccdRaI51.s:552    .text.MIV_PLIC_isr:00000000000000f4 .LBE13

UNDEFINED SYMBOLS
HW_get_32bit_reg
HW_set_32bit_reg
