   1              		.file	"miv_rv32_hal.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.MRV_systick_config,"ax",@progbits
  10              		.align	2
  11              		.globl	MRV_systick_config
  13              	MRV_systick_config:
  14              	.LFB21:
  15              		.file 1 "../src/platform/miv_rv32_hal/miv_rv32_hal.c"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @file miv_rv32_hal.c
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @brief Implementation of Hardware Abstraction Layer for Mi-V soft processors
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include <unistd.h>
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include "miv_rv32_hal.h"
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef __cplusplus
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern "C" {
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define SUCCESS                       0U
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define ERROR                         1U
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MASK_32BIT                    0xFFFFFFFFu
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *  Write in a sequence recommended by privileged spec to avoid spurious
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupts
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****    # New comparand is in a1:a0.
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     li t0, -1
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw t0, mtimecmp # No smaller than old value.
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a1, mtimecmp+4 # No smaller than new value.
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a0, mtimecmp # New value.
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMECMP
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)         MTIMECMPH = MASK_32BIT; \
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMP  = value & MASK_32BIT;\
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMPH =  (value >> 32u) & MASK_32BIT;
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMER
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)            MTIME  = value & MASK_32BIT;\
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMEH = (value >> 32u) & MASK_32BIT;
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void Software_IRQHandler(void);
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MTIME_PRESCALER                 100UL
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t Invalid_IRQHandler(void);
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_1_IRQHandler(void);
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_2_IRQHandler(void);
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_3_IRQHandler(void);
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_4_IRQHandler(void);
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_5_IRQHandler(void);
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_6_IRQHandler(void);
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_7_IRQHandler(void);
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_8_IRQHandler(void);
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_9_IRQHandler(void);
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_10_IRQHandler(void);
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_11_IRQHandler(void);
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_12_IRQHandler(void);
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_13_IRQHandler(void);
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_14_IRQHandler(void);
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_15_IRQHandler(void);
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_16_IRQHandler(void);
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_17_IRQHandler(void);
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_18_IRQHandler(void);
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_19_IRQHandler(void);
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_20_IRQHandler(void);
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_21_IRQHandler(void);
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_22_IRQHandler(void);
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_23_IRQHandler(void);
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_24_IRQHandler(void);
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_25_IRQHandler(void);
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_26_IRQHandler(void);
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_27_IRQHandler(void);
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_28_IRQHandler(void);
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_29_IRQHandler(void);
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_30_IRQHandler(void);
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_31_IRQHandler(void);
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for external interrupts.
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t (* const mrv_ext_irq_handler_table[32])(void) =
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Invalid_IRQHandler,
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_1_IRQHandler,
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_2_IRQHandler,
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_3_IRQHandler,
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_4_IRQHandler,
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_5_IRQHandler,
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_6_IRQHandler,
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_7_IRQHandler,
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_8_IRQHandler,
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_9_IRQHandler,
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_10_IRQHandler,
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_11_IRQHandler,
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_12_IRQHandler,
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_13_IRQHandler,
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_14_IRQHandler,
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_15_IRQHandler,
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_16_IRQHandler,
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_17_IRQHandler,
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_18_IRQHandler,
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_19_IRQHandler,
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_20_IRQHandler,
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_21_IRQHandler,
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_22_IRQHandler,
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_23_IRQHandler,
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_24_IRQHandler,
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_25_IRQHandler,
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_26_IRQHandler,
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_27_IRQHandler,
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_28_IRQHandler,
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_29_IRQHandler,
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_30_IRQHandler,
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_31_IRQHandler
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** };
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Interrupt handlers as mapped into the MIE register of the MIV_RV32
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void Reserved_IRQHandler(void);
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void External_IRQHandler(void);
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGEUI_IRQHandler(void);
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGECI_IRQHandler(void);
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI0_IRQHandler(void);
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI1_IRQHandler(void);
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI2_IRQHandler(void);
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI3_IRQHandler(void);
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI4_IRQHandler(void);
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI5_IRQHandler(void);
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void SUBSYS_IRQHandler(void);
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI6_IRQHandler(void);
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI7_IRQHandler(void);
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void SUBSYSR_IRQHandler(void); // @suppress("Unused function declaration")
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /*MIV_RV32_V3_0*/
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif  /* MIV_LEGACY_RV32 */
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Increment value for the mtimecmp register in order to achieve a system tick
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupt as specified through the MRV_systick_config() function.
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_increment = 0U;
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_cmp_value = 0U;
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Configure the machine timer to generate an interrupt.
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint32_t MRV_systick_config(uint64_t ticks)
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  16              		.loc 1 163 1
  17              		.cfi_startproc
  18              	.LVL0:
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t ret_val = ERROR;
  19              		.loc 1 164 5
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
  20              		.loc 1 165 5
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  21              		.loc 1 166 5
  22              		.loc 1 166 25 is_stmt 0
  23 0000 93060000 		li	a3,0
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  24              		.loc 1 167 25
  25 0004 97070000 		lla	a5,.LANCHOR1
  25      93870700 
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  26              		.loc 1 166 25
  27 000c 17070000 		lla	a4,.LANCHOR0
  27      13070700 
  28 0014 13060000 		li	a2,0
  29              		.loc 1 167 25
  30 0018 23A2D700 		sw	a3,4(a5)
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  31              		.loc 1 166 25
  32 001c 2322D700 		sw	a3,4(a4)
  33              		.loc 1 167 5 is_stmt 1
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while (remainder >= MTIME_PRESCALER)
  34              		.loc 1 169 5
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  35              		.loc 1 167 25 is_stmt 0
  36 0020 23A0C700 		sw	a2,0(a5)
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  37              		.loc 1 166 25
  38 0024 2320C700 		sw	a2,0(a4)
  39              		.loc 1 169 11
  40 0028 93070000 		li	a5,0
  41 002c 93060000 		li	a3,0
  42 0030 13080000 		li	a6,0
  43              		.loc 1 169 25
  44 0034 B7580002 		li	a7,33574912
  45              	.LVL1:
  46              	.L2:
  47 0038 13831700 		addi	t1,a5,1
  48 003c 03AE0800 		lw	t3,0(a7)
  49 0040 3336F300 		sltu	a2,t1,a5
  50 0044 3306D600 		add	a2,a2,a3
  51              		.loc 1 169 11
  52 0048 639E0506 		bne	a1,zero,.L3
  53 004c 637CC507 		bleu	t3,a0,.L3
  54 0050 630A0800 		beq	a6,zero,.L5
  55 0054 17060000 		sw	a5,.LANCHOR0,a2
  55      2320F600 
  56 005c 97070000 		sw	a3,.LANCHOR0+4,a5
  56      23A0D700 
  57              	.L5:
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         remainder -= MTIME_PRESCALER;
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = g_systick_increment + MTIME;
  58              		.loc 1 175 5 is_stmt 1
  59              		.loc 1 175 49 is_stmt 0
  60 0064 B7C70002 		li	a5,33603584
  61 0068 83A787FF 		lw	a5,-8(a5)
  62              		.loc 1 175 47
  63 006c 83260700 		lw	a3,0(a4)
  64 0070 03274700 		lw	a4,4(a4)
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
  65              		.loc 1 164 14
  66 0074 13051000 		li	a0,1
  67              	.LVL2:
  68              		.loc 1 175 47
  69 0078 3386D700 		add	a2,a5,a3
  70 007c B337F600 		sltu	a5,a2,a5
  71 0080 B387E700 		add	a5,a5,a4
  72              		.loc 1 175 25
  73 0084 97050000 		sw	a2,.LANCHOR1,a1
  73      23A0C500 
  74 008c 97050000 		sw	a5,.LANCHOR1+4,a1
  74      23A0F500 
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (g_systick_increment > 0U)
  75              		.loc 1 177 5 is_stmt 1
  76              		.loc 1 177 8 is_stmt 0
  77 0094 B3E6E600 		or	a3,a3,a4
  78 0098 63840602 		beq	a3,zero,.L1
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         WRITE_MTIMECMP(g_systick_cmp_value);
  79              		.loc 1 179 9 is_stmt 1
  80 009c 37470002 		li	a4,33570816
  81 00a0 9306F0FF 		li	a3,-1
  82 00a4 2322D700 		sw	a3,4(a4)
  83              		.loc 1 179 9
  84 00a8 2320C700 		sw	a2,0(a4)
  85              		.loc 1 179 9
  86 00ac 2322F700 		sw	a5,4(a4)
  87              		.loc 1 179 44
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
  88              		.loc 1 180 9
  89              	.LBB6:
  90              		.loc 1 180 9
  91              		.loc 1 180 9
  92 00b0 93070008 		li	a5,128
  93              	 #APP
  94              	# 180 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 181              	        MRV_enable_interrupts();
  95              		csrrs a5, mie, a5
  96              	# 0 "" 2
  97              	.LVL3:
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
  98              		.loc 1 180 9
  99              	 #NO_APP
 100              	.LBE6:
 101              		.loc 1 181 9
 102              		.file 2 "../src/platform/miv_rv32_hal/miv_rv32_hal.h"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * 
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*=========================================================================*//**
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Introduction
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, 
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   refer to the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-cor
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIV_RV32 Core as well as this document use the terms defined below:
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32, preprocessor macros have been 
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted.
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The HAL is used to target any of the mentioned platforms by adding the 
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   following macros in the way :
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Project Properties > C/C++ Build > Settings > Preprocessor in Assembler and 
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Compiler settings.
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The table below shows the macros corresponding to the MIV Core being used in 
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   your libero project. By default, the HAL targets v3.1 of the IP core and no 
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   macros need to be set for this configutation.
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-----------------------------|-------------------|
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt Handling
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   configurator.
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the the value stored in the 
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   handler is as an interrupt service routine.
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32.
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****    
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   unchanged.
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Floating Point Interrupt Support
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Softconsole build settings.
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   when the ISR does not used FP insturctions and saving the general purpose 
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   register context is sufficient.
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. This was previously (MIV_RV32 v3.0) 
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   known as OPSRV, which stands for "Offload Processor Subsystem
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   for RISC-V". See the earlier versions of the handbook for more details.
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   In the latest release of the MIV_RV32 IP core v3.1, OPSRV has been renamed to 
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *//*=========================================================================*/
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define RISCV_HAL_H
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 181:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "fpga_design_config/fpga_design_config.h"
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "hw_platform.h"
 185:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef __cplusplus
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** extern "C" {
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 194:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****    
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------------|--------------------------|
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine timer interrupt
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 220:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME and MTIMECMP
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   possible combinations:
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 228:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   core as input.
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt.
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 core design.
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   available internally to the core.
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   External IRQ
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   External Interrupt.
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|--------|----------------|
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_DELTA                     5
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 307:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIMPID Register
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Soft IP core version.
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (0u)
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (0u)
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   RISC-V Specification Interrupts
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   in the MIE/MIP registers.
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, follow the interrupt priority
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   order and register description as mentioned in the RISC-V spec.
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|--------|----------------|
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 365:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 366:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 367:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 368:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 369:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 370:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt numbers:
 371:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 372:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 373:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** enum
 374:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 375:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 376:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 377:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 378:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 379:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 380:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 381:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 382:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 383:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 384:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 385:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 386:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 387:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 388:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 389:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 390:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 391:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 392:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 393:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 394:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 395:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 396:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 397:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 398:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 399:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 400:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 401:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 402:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 403:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 404:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 405:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 406:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 407:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 408:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 409:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 411:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 412:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 414:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 415:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 416:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 417:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 418:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 419:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 420:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 421:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 422:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 423:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 424:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 425:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 426:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 427:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 428:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 429:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 430:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 431:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 432:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 433:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 434:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 435:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 436:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 437:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 438:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 439:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 440:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 441:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 442:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 443:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   */
 444:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 445:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 446:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     uint32_t temp;
 447:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 448:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 449:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "sw x31, %0"
 450:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"=m" (temp));
 451:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 452:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ volatile (
 453:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x1;"
 454:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x1, x31;"
 455:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 456:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x2;"
 457:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x2, x31;"
 458:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 459:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x3;"
 460:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x3, x31;"
 461:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 462:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x4;"
 463:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x4, x31;"
 464:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 465:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x5;"
 466:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x5, x31;"
 467:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 468:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x6;"
 469:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x6, x31;"
 470:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 471:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x7;"
 472:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x7, x31;"
 473:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 474:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x8;"
 475:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x8, x31;"
 476:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 477:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x9;"
 478:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x9, x31;"
 479:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 480:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x10;"
 481:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x10, x31;"
 482:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 483:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x11;"
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x11, x31;"
 485:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 486:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x12;"
 487:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x12, x31;"
 488:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 489:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x13;"
 490:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x13, x31;"
 491:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 492:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x14;"
 493:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x14, x31;"
 494:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 495:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x15;"
 496:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x15, x31;"
 497:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 498:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x16;"
 499:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x16, x31;"
 500:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 501:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x17;"
 502:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x17, x31;"
 503:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 504:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x18;"
 505:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x18, x31;"
 506:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 507:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x19;"
 508:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x19, x31;"
 509:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 510:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x20;"
 511:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x20, x31;"
 512:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 513:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x21;"
 514:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x21, x31;"
 515:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 516:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x22;"
 517:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x22, x31;"
 518:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 519:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x23;"
 520:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x23, x31;"
 521:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 522:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x24;"
 523:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x24, x31;"
 524:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 525:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x25;"
 526:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x25, x31;"
 527:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 528:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x26;"
 529:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x26, x31;"
 530:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 531:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x27;"
 532:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x27, x31;"
 533:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 534:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x28;"
 535:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x28, x31;"
 536:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 537:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x29;"
 538:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x29, x31;"
 539:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 540:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x30;"
 541:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x30, x31;");
 542:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 543:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 544:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "lw x31, %0;"
 545:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :
 546:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"m" (temp));
 547:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 548:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 549:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 550:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 551:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 552:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 553:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   IP configurator.
 554:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 555:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 556:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 557:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 558:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 559:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 560:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 561:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 562:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 563:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 564:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 565:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 566:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   configurator.
 567:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 568:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return 
 569:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 570:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 571:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 572:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 573:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 574:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 575:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 576:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 577:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 578:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 579:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 580:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 581:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 582:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 583:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 584:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 585:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 586:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 587:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, mask);
 588:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 589:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 590:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 591:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_disable_local_irq() function disables the local interrupts. It takes a 
 592:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 593:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt bit in the MIE register is disabled.
 594:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 595:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MRV_disable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 596:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                          MRV32_MSYS_EIE0_IRQn |
 597:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                          MRV32_MSYS_SUBSYS_IRQn);
 598:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 599:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 600:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 601:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mie, mask);
 602:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 603:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /* MIV_LEGACY_RV32 */ 
 604:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 605:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 606:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_enable_interrupts() function enables all interrupts by setting the
 607:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 608:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 609:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 610:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 611:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 612:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 613:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 614:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 615:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_interrupts(void)
 616:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 617:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
 103              		.loc 2 617 5
 104              	.LBB7:
 105              	.LBB8:
 106              		.loc 2 617 5
 107              		.loc 2 617 5
 108              	 #APP
 109              	# 617 "../src/platform/miv_rv32_hal/miv_rv32_hal.h" 1
 618              	}
 110              		csrrs a5, mstatus, 8
 111              	# 0 "" 2
 112              	.LVL4:
 617:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
 113              		.loc 2 617 5
 114              	 #NO_APP
 115              	.LBE8:
 116              	.LBE7:
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         ret_val = SUCCESS;
 117              		.loc 1 182 9
 118              		.loc 1 182 17 is_stmt 0
 119 00bc 13050000 		li	a0,0
 120              	.LVL5:
 121              	.L1:
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 185:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     return ret_val;
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 122              		.loc 1 186 1
 123 00c0 67800000 		ret
 124              	.LVL6:
 125              	.L3:
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 126              		.loc 1 171 9 is_stmt 1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 127              		.loc 1 171 22 is_stmt 0
 128 00c4 83A70800 		lw	a5,0(a7)
 129 00c8 13081000 		li	a6,1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 130              		.loc 1 171 19
 131 00cc B307F540 		sub	a5,a0,a5
 132 00d0 B336F500 		sgtu	a3,a5,a0
 133 00d4 B385D540 		sub	a1,a1,a3
 134              	.LVL7:
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 135              		.loc 1 172 9 is_stmt 1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 136              		.loc 1 171 19 is_stmt 0
 137 00d8 13850700 		mv	a0,a5
 138 00dc 93060600 		mv	a3,a2
 139 00e0 93070300 		mv	a5,t1
 140              	.LVL8:
 141 00e4 6FF05FF5 		j	.L2
 142              		.cfi_endproc
 143              	.LFE21:
 145              		.section	.text.handle_m_timer_interrupt,"ax",@progbits
 146              		.align	2
 147              		.globl	handle_m_timer_interrupt
 149              	handle_m_timer_interrupt:
 150              	.LFB22:
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for machine timer interrupts.
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_timer_interrupt(void)
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 151              		.loc 1 192 1 is_stmt 1
 152              		.cfi_startproc
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 153              		.loc 1 193 5
 154              	.LBB9:
 155              		.loc 1 193 5
 156              		.loc 1 193 5
 157              	.LBE9:
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 158              		.loc 1 192 1 is_stmt 0
 159 0000 130101FF 		addi	sp,sp,-16
 160              		.cfi_def_cfa_offset 16
 161 0004 23261100 		sw	ra,12(sp)
 162              		.cfi_offset 1, -4
 163              	.LBB10:
 164              		.loc 1 193 5
 165 0008 93070008 		li	a5,128
 166              	 #APP
 167              	# 193 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 194              	
 168              		csrrc a5, mie, a5
 169              	# 0 "" 2
 170              	.LVL9:
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 171              		.loc 1 193 5 is_stmt 1
 172              	 #NO_APP
 173              	.LBE10:
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mtime_at_irq = MTIME;
 174              		.loc 1 195 5
 175              		.loc 1 195 29 is_stmt 0
 176 0010 B7C70002 		li	a5,33603584
 177 0014 83A687FF 		lw	a3,-8(a5)
 178              	.LVL10:
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     static volatile uint32_t d_tick = 0u;
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
 179              		.loc 1 201 5 is_stmt 1
 180 0018 97070000 		lla	a5,.LANCHOR1
 180      93870700 
 181 0020 03A70700 		lw	a4,0(a5)
 182 0024 83A74700 		lw	a5,4(a5)
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 183              		.loc 1 202 51 is_stmt 0
 184 0028 17060000 		lla	a2,.LANCHOR0
 184      13060600 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 185              		.loc 1 201 47
 186 0030 93855600 		addi	a1,a3,5
 187              		.loc 1 202 51
 188 0034 03250600 		lw	a0,0(a2)
 189 0038 03284600 		lw	a6,4(a2)
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 190              		.loc 1 201 47
 191 003c B3B6D500 		sltu	a3,a1,a3
 192              	.LVL11:
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 193              		.loc 1 201 10
 194 0040 13060000 		li	a2,0
 195              	.L15:
 196 0044 63E8D704 		bgtu	a3,a5,.L16
 197 0048 6394F600 		bne	a3,a5,.L19
 198 004c 6364B704 		bgtu	a1,a4,.L16
 199              	.L19:
 200 0050 630A0600 		beq	a2,zero,.L18
 201 0054 97060000 		sw	a4,.LANCHOR1,a3
 201      23A0E600 
 202 005c 97060000 		sw	a5,.LANCHOR1+4,a3
 202      23A0F600 
 203              	.L18:
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         d_tick += 1;
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /***************************************************************************//**
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     /*
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Note: If d_tick > 1 it means, that a system timer interrupt has been 
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * missed.
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Please ensure that interrupt handlers are as short as possible to prevent
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * them stopping other interrupts from being handled. For example, if a
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * system timer interrupt occurs during a software interrupt, the system
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * timer interrupt will not be handled until the software interrupt handling
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * is complete. If the software interrupt handling time is more than one 
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * systick interval, it will result in d_tick > 1.
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * If you are running the program using the debugger and halt the CPU at a 
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * breakpoint, MTIME will continue to increment and interrupts will be 
 220:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * missed; resulting in d_tick > 1.
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      */
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     WRITE_MTIMECMP(g_systick_cmp_value);
 204              		.loc 1 223 5 is_stmt 1
 205 0064 B7460002 		li	a3,33570816
 206 0068 1306F0FF 		li	a2,-1
 207 006c 23A2C600 		sw	a2,4(a3)
 208              		.loc 1 223 5
 209 0070 23A0E600 		sw	a4,0(a3)
 210              		.loc 1 223 5
 211 0074 23A2F600 		sw	a5,4(a3)
 212              		.loc 1 223 40
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SysTick_Handler();
 213              		.loc 1 225 5
 214 0078 97000000 		call	SysTick_Handler
 214      E7800000 
 215              	.LVL12:
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 216              		.loc 1 227 5
 217              	.LBB11:
 218              		.loc 1 227 5
 219              		.loc 1 227 5
 220 0080 93070008 		li	a5,128
 221              	 #APP
 222              	# 227 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 228              	}
 223              		csrrs a5, mie, a5
 224              	# 0 "" 2
 225              	.LVL13:
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 226              		.loc 1 227 5
 227              	 #NO_APP
 228              	.LBE11:
 229              		.loc 1 228 1 is_stmt 0
 230 0088 8320C100 		lw	ra,12(sp)
 231              		.cfi_remember_state
 232              		.cfi_restore 1
 233 008c 13010101 		addi	sp,sp,16
 234              		.cfi_def_cfa_offset 0
 235 0090 67800000 		jr	ra
 236              	.LVL14:
 237              	.L16:
 238              		.cfi_restore_state
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 239              		.loc 1 202 9 is_stmt 1
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 240              		.loc 1 202 51 is_stmt 0
 241 0094 3306A700 		add	a2,a4,a0
 242 0098 B338E600 		sltu	a7,a2,a4
 243 009c B3870701 		add	a5,a5,a6
 244 00a0 13070600 		mv	a4,a2
 245 00a4 B387F800 		add	a5,a7,a5
 246 00a8 13061000 		li	a2,1
 247 00ac 6FF09FF9 		j	.L15
 248              		.cfi_endproc
 249              	.LFE22:
 251              		.section	.text.handle_m_soft_interrupt,"ax",@progbits
 252              		.align	2
 253              		.globl	handle_m_soft_interrupt
 255              	handle_m_soft_interrupt:
 256              	.LFB23:
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_soft_interrupt(void)
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 257              		.loc 1 231 1 is_stmt 1
 258              		.cfi_startproc
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 259              		.loc 1 232 5
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 260              		.loc 1 231 1 is_stmt 0
 261 0000 130101FF 		addi	sp,sp,-16
 262              		.cfi_def_cfa_offset 16
 263 0004 23261100 		sw	ra,12(sp)
 264              		.cfi_offset 1, -4
 265              		.loc 1 232 5
 266 0008 97000000 		call	Software_IRQHandler
 266      E7800000 
 267              	.LVL15:
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MRV_clear_soft_irq();
 268              		.loc 1 233 5 is_stmt 1
 269              	.LBB14:
 270              	.LBB15:
 619:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 620:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 621:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_disable_interrupts() function disables all interrupts by clearing the
 622:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 623:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 624:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 625:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 626:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 627:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 628:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 629:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_disable_interrupts(void)
 630:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 631:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MPIE);
 632:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MIE);
 633:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 634:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 635:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 636:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_read_mtvec_base() function reads the mtvec base value, which is the 
 637:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   addr used when an interrupt/trap occurs. In the mtvec register, [31:2] is the 
 638:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   BASE address. NOTE: The BASE address must be aligned on a 4B boundary.
 639:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 640:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 641:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The function does not take any parameters.
 642:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 643:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 644:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The function returns the value of the BASE field [31:2] as an unsigned 32-bit 
 645:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   value.
 646:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 647:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 648:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_LEGACY_RV32
 649:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_v3_0
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline uint32_t MRV_read_mtvec_base (void)
 651:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 652:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     uint32_t mtvec_addr_base = read_csr(mtvec);
 653:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     return mtvec_addr_base & MTVEC_BASE_ADDR_MASK;
 654:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 655:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 656:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 657:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_set_mtvec_base() function takes the mtvec_base address as a unsigned int 
 658:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   and writes the value into the BASE field [31:2] in the mtvec CSR, MODE[1:0] 
 659:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   is Read-only. BASE is 4B aligned, so the lowest 2 bits of mtvec_base are 
 660:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ignored.
 661:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 662:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param mtvec_base
 663:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Any legal value is passed into the function, and it is used as the trap_entry 
 664:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   for interrupts. The PC jumps to this address provided when an interrupt occurs. 
 665:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   In case of vectored interrupts, the address value mentioned in the vector 
 666:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   table under the MIE Register Map is updated to the value passed to this 
 667:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   function parameter.
 668:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 669:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 670:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 671:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 672:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_set_mtvec_base (uint32_t mtvec_base)
 673:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 674:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     mtvec_base = mtvec_base & MTVEC_BASE_ADDR_MASK;
 675:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     write_csr(mtvec, mtvec_base);
 676:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 677:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_RV32_v3_0*/
 678:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_LEGACY_RV32*/
 679:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 680:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 681:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_read_mtime() function returns the current MTIME register value.
 682:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 683:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline uint64_t MRV_read_mtime(void)
 684:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 685:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t hi = 0u;
 686:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t lo = 0u;
 687:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 688:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
 689:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****      * returned value could be wrong. */
 690:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     do {
 691:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****         hi = MTIMEH;
 692:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****         lo = MTIME;
 693:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     } while(hi != MTIMEH);
 694:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 695:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     return((((uint64_t)MTIMEH) << 32u) | lo);
 696:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 697:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 698:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 699:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_raise_soft_irq() function raises a synchronous software interrupt
 700:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   by writing into the MSIP register.
 701:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 702:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 703:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 704:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 705:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 706:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 707:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_raise_soft_irq(void)
 708:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 709:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, MIP_MSIP);       /* Enable software interrupt bit */
 710:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 711:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 712:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* You need to make sure that the global interrupt is enabled */
 713:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x01;   /* raise soft interrupt */
 714:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 715:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Raise soft IRQ on MIV_RV32 processor */
 716:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     SUBSYS->soft_reg |= SUBSYS_SOFT_IRQ;
 717:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 718:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 719:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 720:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 721:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_clear_soft_irq() function clears a synchronous software interrupt
 722:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   by clearing the MSIP register.
 723:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 724:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 725:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 726:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 727:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 728:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 729:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_clear_soft_irq(void)
 730:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 731:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 732:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x00u;   /* clear soft interrupt */
 733:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 734:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Clear soft IRQ on MIV_RV32 processor */
 735:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
 271              		.loc 2 735 5
 272              		.loc 2 735 22 is_stmt 0
 273 0010 37670000 		li	a4,24576
 274 0014 83270702 		lw	a5,32(a4)
 275              	.LBE15:
 276              	.LBE14:
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 277              		.loc 1 234 1
 278 0018 8320C100 		lw	ra,12(sp)
 279              		.cfi_restore 1
 280              	.LBB17:
 281              	.LBB16:
 282              		.loc 2 735 22
 283 001c 93F7D7FF 		andi	a5,a5,-3
 284 0020 2320F702 		sw	a5,32(a4)
 285              	.LBE16:
 286              	.LBE17:
 287              		.loc 1 234 1
 288 0024 13010101 		addi	sp,sp,16
 289              		.cfi_def_cfa_offset 0
 290 0028 67800000 		jr	ra
 291              		.cfi_endproc
 292              	.LFE23:
 294              		.section	.text.handle_local_ei_interrupts,"ax",@progbits
 295              		.align	2
 296              		.globl	handle_local_ei_interrupts
 298              	handle_local_ei_interrupts:
 299              	.LFB24:
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for software interrupts.
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_ext_interrupt(void)
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     unsigned long hart_id = read_csr(mhartid);
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t int_num  = PLIC->TARGET[hart_id].CLAIM_COMPLETE;
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint8_t disable = EXT_IRQ_KEEP_ENABLED;
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (0u !=int_num)
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         disable = mrv_ext_irq_handler_table[int_num]();
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         PLIC->TARGET[hart_id].CLAIM_COMPLETE = int_num;
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if(EXT_IRQ_DISABLE == disable)
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             MRV_PLIC_disable_irq((IRQn_Type)int_num);
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * MSYS local interrupts table
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void (* const local_irq_handler_table[16])(void) =
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_V3_0
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGEUI_IRQHandler,
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGECI_IRQHandler,
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYS_IRQHandler,
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYSR_IRQHandler,
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI0_IRQHandler,
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI1_IRQHandler,
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI2_IRQHandler,
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI3_IRQHandler,
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI4_IRQHandler,
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI5_IRQHandler,
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI6_IRQHandler,
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI7_IRQHandler
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGEUI_IRQHandler,
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGECI_IRQHandler,
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI0_IRQHandler,
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI1_IRQHandler,
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI2_IRQHandler,
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI3_IRQHandler,
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI4_IRQHandler,
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI5_IRQHandler,
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYS_IRQHandler,
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** };
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Jump to interrupt table containing local interrupts
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_local_ei_interrupts(uint8_t irq_no)
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 300              		.loc 1 305 1 is_stmt 1
 301              		.cfi_startproc
 302              	.LVL16:
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mhart_id = read_csr(mhartid);
 303              		.loc 1 306 5
 304              	.LBB18:
 305              		.loc 1 306 25
 306              		.loc 1 306 25
 307              	 #APP
 308              	# 306 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 307              	    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
 309              		csrr a5, mhartid
 310              	# 0 "" 2
 311              	.LVL17:
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mhart_id = read_csr(mhartid);
 312              		.loc 1 306 25
 313              	 #NO_APP
 314              	.LBE18:
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
 315              		.loc 1 310 5
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     (*local_irq_handler_table[ei_no])();
 316              		.loc 1 311 5
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     (*local_irq_handler_table[ei_no])();
 317              		.loc 1 310 13 is_stmt 0
 318 0004 130505FF 		addi	a0,a0,-16
 319              	.LVL18:
 320              		.loc 1 311 6
 321 0008 1375F50F 		andi	a0,a0,0xff
 322 000c 13152500 		slli	a0,a0,2
 323 0010 97070000 		lla	a5,.LANCHOR2
 323      93870700 
 324 0018 3385A700 		add	a0,a5,a0
 325 001c 03230500 		lw	t1,0(a0)
 326 0020 67000300 		jr	t1
 327              	.LVL19:
 328              		.cfi_endproc
 329              	.LFE24:
 331              		.section	.text.handle_trap,"ax",@progbits
 332              		.align	2
 333              		.globl	handle_trap
 335              	handle_trap:
 336              	.LFB25:
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /* MIV_LEGACY_RV32 */
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Trap handler. This function is invoked in the non-vectored mode.
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_trap(uintptr_t mcause, uintptr_t mepc)
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {   
 337              		.loc 1 320 1 is_stmt 1
 338              		.cfi_startproc
 339              	.LVL20:
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 340              		.loc 1 321 5
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (is_interrupt)
 341              		.loc 1 323 5
 342              		.loc 1 323 8 is_stmt 0
 343 0000 63520506 		bge	a0,zero,.L28
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_LEGACY_RV32
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL
 344              		.loc 1 326 9 is_stmt 1
 345              		.loc 1 326 38 is_stmt 0
 346 0004 B7070080 		li	a5,-2147483648
 347 0008 13C707FF 		xori	a4,a5,-16
 348 000c 3377E500 		and	a4,a0,a4
 349              		.loc 1 326 12
 350 0010 630E0700 		beq	a4,zero,.L29
 351              		.loc 1 326 88 discriminator 1
 352 0014 93C707FE 		xori	a5,a5,-32
 353 0018 B377F500 		and	a5,a0,a5
 354              		.loc 1 326 60 discriminator 1
 355 001c 63980700 		bne	a5,zero,.L29
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
 356              		.loc 1 328 13 is_stmt 1
 357 0020 1375F50F 		andi	a0,a0,0xff
 358              	.LVL21:
 359 0024 17030000 		tail	handle_local_ei_interrupts
 359      67000300 
 360              	.LVL22:
 361              	.L29:
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
 362              		.loc 1 330 14
 363              		.loc 1 330 26 is_stmt 0
 364 002c 13151500 		slli	a0,a0,1
 365              	.LVL23:
 366 0030 13551500 		srli	a0,a0,1
 367              		.loc 1 330 17
 368 0034 9307B000 		li	a5,11
 369 0038 6316F500 		bne	a0,a5,.L30
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_LEGACY_RV32
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             External_IRQHandler();
 370              		.loc 1 336 13 is_stmt 1
 371 003c 17030000 		tail	External_IRQHandler
 371      67000300 
 372              	.LVL24:
 373              	.L30:
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_ext_interrupt();
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
 374              		.loc 1 341 14
 375              		.loc 1 341 17 is_stmt 0
 376 0044 93073000 		li	a5,3
 377 0048 6316F500 		bne	a0,a5,.L31
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_soft_interrupt();
 378              		.loc 1 343 13 is_stmt 1
 379 004c 17030000 		tail	handle_m_soft_interrupt
 379      67000300 
 380              	.LVL25:
 381              	.L31:
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
 382              		.loc 1 345 14
 383              		.loc 1 345 17 is_stmt 0
 384 0054 93077000 		li	a5,7
 385 0058 6310F502 		bne	a0,a5,.L27
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_timer_interrupt();
 386              		.loc 1 347 13 is_stmt 1
 387 005c 17030000 		tail	handle_m_timer_interrupt
 387      67000300 
 388              	.LVL26:
 389              	.L28:
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /*
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Arguments supplied to this function are mcause, mepc (exception PC) and
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          stack pointer.
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Based on privileged-isa specification mcause values and meanings are:
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          0 Instruction address misaligned (mtval/mtval is the address)
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          1 Instruction access fault       (mtval/mtval is the address)
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          2 Illegal instruction            (mtval/mtval contains the
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                            offending instruction opcode)
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          3 Breakpoint
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          4 Load address misaligned        (mtval/mtval is the address)
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          5 Load address fault             (mtval/mtval is the address)
 365:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          6 Store/AMO address fault        (mtval/mtval is the address)
 366:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          7 Store/AMO access fault         (mtval/mtval is the address)
 367:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          8 Environment call from U-mode
 368:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          9 Environment call from S-mode
 369:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          A Environment call from M-mode
 370:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          B Instruction page fault
 371:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          C Load page fault                (mtval/mtval is the address)
 372:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          E Store page fault               (mtval/mtval is the address)
 373:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 374:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # Please note: mtval is the newer name for register mbadaddr
 375:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # If you get a compile failure here, use the older name.
 376:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # At this point, both are supported in latest compiler, older compiler
 377:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # versions only support mbadaddr.
 378:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # See: https://github.com/riscv/riscv-gcc/issues/133
 379:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         */
 380:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 381:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* interrupt pending */
 382:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mip      = read_csr(mip);
 383:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 384:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* additional info and meaning depends on mcause */
 385:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtval = read_csr(mtval);
 386:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 387:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* trap vector */
 388:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtvec    = read_csr(mtvec);
 389:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 390:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* temporary, sometimes might hold temporary value of a0 */
 391:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mscratch = read_csr(mscratch);
 392:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 393:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* status contains many smaller fields: */
 394:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mstatus  = read_csr(mstatus);
 395:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 396:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* PC value when the exception was taken*/
 397:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mmepc  = read_csr(mepc);
 398:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 399:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /* breakpoint */
 400:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         __asm__("ebreak");
 401:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 402:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         _exit(1 + mcause);
 390              		.loc 1 402 9
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 391              		.loc 1 320 1 is_stmt 0
 392 0064 130101FF 		addi	sp,sp,-16
 393              		.cfi_def_cfa_offset 16
 394              		.loc 1 402 9
 395 0068 13051500 		addi	a0,a0,1
 396              	.LVL27:
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 397              		.loc 1 320 1
 398 006c 23261100 		sw	ra,12(sp)
 399              		.cfi_offset 1, -4
 400              		.loc 1 402 9
 401 0070 97000000 		call	_exit
 401      E7800000 
 402              	.LVL28:
 403              	.L27:
 404              		.cfi_def_cfa_offset 0
 405              		.cfi_restore 1
 406 0078 67800000 		ret
 407              		.cfi_endproc
 408              	.LFE25:
 410              		.globl	local_irq_handler_table
 411              		.comm	MRV_LOCAL_IRQn_Type,4,4
 412              		.section	.rodata.local_irq_handler_table,"a"
 413              		.align	2
 414              		.set	.LANCHOR2,. + 0
 417              	local_irq_handler_table:
 418 0000 00000000 		.word	MGEUI_IRQHandler
 419 0004 00000000 		.word	MGECI_IRQHandler
 420 0008 00000000 		.word	SUBSYS_IRQHandler
 421 000c 00000000 		.word	SUBSYSR_IRQHandler
 422 0010 00000000 		.word	Reserved_IRQHandler
 423 0014 00000000 		.word	Reserved_IRQHandler
 424 0018 00000000 		.word	Reserved_IRQHandler
 425 001c 00000000 		.word	Reserved_IRQHandler
 426 0020 00000000 		.word	MSYS_EI0_IRQHandler
 427 0024 00000000 		.word	MSYS_EI1_IRQHandler
 428 0028 00000000 		.word	MSYS_EI2_IRQHandler
 429 002c 00000000 		.word	MSYS_EI3_IRQHandler
 430 0030 00000000 		.word	MSYS_EI4_IRQHandler
 431 0034 00000000 		.word	MSYS_EI5_IRQHandler
 432 0038 00000000 		.word	MSYS_EI6_IRQHandler
 433 003c 00000000 		.word	MSYS_EI7_IRQHandler
 434              		.section	.sbss.g_systick_cmp_value,"aw",@nobits
 435              		.align	3
 436              		.set	.LANCHOR1,. + 0
 439              	g_systick_cmp_value:
 440 0000 00000000 		.zero	8
 440      00000000 
 441              		.section	.sbss.g_systick_increment,"aw",@nobits
 442              		.align	3
 443              		.set	.LANCHOR0,. + 0
 446              	g_systick_increment:
 447 0000 00000000 		.zero	8
 447      00000000 
 448              		.text
 449              	.Letext0:
 450              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 451              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 452              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 453              		.file 6 "../src/platform/miv_rv32_hal/miv_rv32_subsys.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 miv_rv32_hal.c
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:13     .text.MRV_systick_config:0000000000000000 MRV_systick_config
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:17     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:19     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:20     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:21     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:22     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:23     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:25     .text.MRV_systick_config:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:27     .text.MRV_systick_config:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:30     .text.MRV_systick_config:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:32     .text.MRV_systick_config:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:34     .text.MRV_systick_config:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:35     .text.MRV_systick_config:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:36     .text.MRV_systick_config:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:38     .text.MRV_systick_config:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:40     .text.MRV_systick_config:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:44     .text.MRV_systick_config:0000000000000034 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:52     .text.MRV_systick_config:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:59     .text.MRV_systick_config:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:60     .text.MRV_systick_config:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:63     .text.MRV_systick_config:000000000000006c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:66     .text.MRV_systick_config:0000000000000074 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:69     .text.MRV_systick_config:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:73     .text.MRV_systick_config:0000000000000084 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:76     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:77     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:80     .text.MRV_systick_config:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:84     .text.MRV_systick_config:00000000000000a8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:86     .text.MRV_systick_config:00000000000000ac .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:88     .text.MRV_systick_config:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:90     .text.MRV_systick_config:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:91     .text.MRV_systick_config:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:92     .text.MRV_systick_config:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:101    .text.MRV_systick_config:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:103    .text.MRV_systick_config:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:106    .text.MRV_systick_config:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:107    .text.MRV_systick_config:00000000000000b8 .L0 
../src/platform/miv_rv32_hal/miv_rv32_hal.h:617    .text.MRV_systick_config:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:117    .text.MRV_systick_config:00000000000000bc .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:118    .text.MRV_systick_config:00000000000000bc .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:119    .text.MRV_systick_config:00000000000000bc .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:123    .text.MRV_systick_config:00000000000000c0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:127    .text.MRV_systick_config:00000000000000c4 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:128    .text.MRV_systick_config:00000000000000c4 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:131    .text.MRV_systick_config:00000000000000cc .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:136    .text.MRV_systick_config:00000000000000d8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:137    .text.MRV_systick_config:00000000000000d8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:142    .text.MRV_systick_config:00000000000000e8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:149    .text.handle_m_timer_interrupt:0000000000000000 handle_m_timer_interrupt
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:152    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:153    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:155    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:156    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:158    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:159    .text.handle_m_timer_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:160    .text.handle_m_timer_interrupt:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:162    .text.handle_m_timer_interrupt:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:165    .text.handle_m_timer_interrupt:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:174    .text.handle_m_timer_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:175    .text.handle_m_timer_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:176    .text.handle_m_timer_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:180    .text.handle_m_timer_interrupt:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:184    .text.handle_m_timer_interrupt:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:186    .text.handle_m_timer_interrupt:0000000000000030 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:188    .text.handle_m_timer_interrupt:0000000000000034 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:191    .text.handle_m_timer_interrupt:000000000000003c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:194    .text.handle_m_timer_interrupt:0000000000000040 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:205    .text.handle_m_timer_interrupt:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:209    .text.handle_m_timer_interrupt:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:211    .text.handle_m_timer_interrupt:0000000000000074 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:213    .text.handle_m_timer_interrupt:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:214    .text.handle_m_timer_interrupt:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:218    .text.handle_m_timer_interrupt:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:219    .text.handle_m_timer_interrupt:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:220    .text.handle_m_timer_interrupt:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:229    .text.handle_m_timer_interrupt:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:230    .text.handle_m_timer_interrupt:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:231    .text.handle_m_timer_interrupt:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:232    .text.handle_m_timer_interrupt:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:234    .text.handle_m_timer_interrupt:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:238    .text.handle_m_timer_interrupt:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:240    .text.handle_m_timer_interrupt:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:241    .text.handle_m_timer_interrupt:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:248    .text.handle_m_timer_interrupt:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:255    .text.handle_m_soft_interrupt:0000000000000000 handle_m_soft_interrupt
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:258    .text.handle_m_soft_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:259    .text.handle_m_soft_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:260    .text.handle_m_soft_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:261    .text.handle_m_soft_interrupt:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:262    .text.handle_m_soft_interrupt:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:264    .text.handle_m_soft_interrupt:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:266    .text.handle_m_soft_interrupt:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:271    .text.handle_m_soft_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:272    .text.handle_m_soft_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:273    .text.handle_m_soft_interrupt:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:278    .text.handle_m_soft_interrupt:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:279    .text.handle_m_soft_interrupt:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:283    .text.handle_m_soft_interrupt:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:288    .text.handle_m_soft_interrupt:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:289    .text.handle_m_soft_interrupt:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:291    .text.handle_m_soft_interrupt:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:298    .text.handle_local_ei_interrupts:0000000000000000 handle_local_ei_interrupts
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:301    .text.handle_local_ei_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:303    .text.handle_local_ei_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:305    .text.handle_local_ei_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:306    .text.handle_local_ei_interrupts:0000000000000000 .L0 
../src/platform/miv_rv32_hal/miv_rv32_hal.c:306    .text.handle_local_ei_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:315    .text.handle_local_ei_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:316    .text.handle_local_ei_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:317    .text.handle_local_ei_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:318    .text.handle_local_ei_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:321    .text.handle_local_ei_interrupts:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:328    .text.handle_local_ei_interrupts:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:335    .text.handle_trap:0000000000000000 handle_trap
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:338    .text.handle_trap:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:340    .text.handle_trap:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:341    .text.handle_trap:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:342    .text.handle_trap:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:343    .text.handle_trap:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:345    .text.handle_trap:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:346    .text.handle_trap:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:350    .text.handle_trap:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:352    .text.handle_trap:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:355    .text.handle_trap:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:357    .text.handle_trap:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:363    .text.handle_trap:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:364    .text.handle_trap:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:368    .text.handle_trap:0000000000000034 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:371    .text.handle_trap:000000000000003c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:375    .text.handle_trap:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:376    .text.handle_trap:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:379    .text.handle_trap:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:383    .text.handle_trap:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:384    .text.handle_trap:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:387    .text.handle_trap:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:391    .text.handle_trap:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:392    .text.handle_trap:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:393    .text.handle_trap:0000000000000068 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:395    .text.handle_trap:0000000000000068 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:398    .text.handle_trap:000000000000006c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:399    .text.handle_trap:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:401    .text.handle_trap:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:404    .text.handle_trap:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:405    .text.handle_trap:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:407    .text.handle_trap:000000000000007c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:417    .rodata.local_irq_handler_table:0000000000000000 local_irq_handler_table
                            *COM*:0000000000000004 MRV_LOCAL_IRQn_Type
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:414    .rodata.local_irq_handler_table:0000000000000000 .LANCHOR2
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:436    .sbss.g_systick_cmp_value:0000000000000000 .LANCHOR1
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:439    .sbss.g_systick_cmp_value:0000000000000000 g_systick_cmp_value
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:443    .sbss.g_systick_increment:0000000000000000 .LANCHOR0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:446    .sbss.g_systick_increment:0000000000000000 g_systick_increment
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:145    .text.MRV_systick_config:00000000000000e8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:251    .text.handle_m_timer_interrupt:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:294    .text.handle_m_soft_interrupt:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:331    .text.handle_local_ei_interrupts:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:412    .text.handle_trap:000000000000007c .L0 
                     .debug_frame:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:25     .text.MRV_systick_config:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:27     .text.MRV_systick_config:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:55     .text.MRV_systick_config:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:56     .text.MRV_systick_config:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:73     .text.MRV_systick_config:0000000000000084 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:74     .text.MRV_systick_config:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:125    .text.MRV_systick_config:00000000000000c4 .L3
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:57     .text.MRV_systick_config:0000000000000064 .L5
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:121    .text.MRV_systick_config:00000000000000c0 .L1
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:46     .text.MRV_systick_config:0000000000000038 .L2
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:180    .text.handle_m_timer_interrupt:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:184    .text.handle_m_timer_interrupt:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:201    .text.handle_m_timer_interrupt:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:202    .text.handle_m_timer_interrupt:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:237    .text.handle_m_timer_interrupt:0000000000000094 .L16
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:199    .text.handle_m_timer_interrupt:0000000000000050 .L19
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:203    .text.handle_m_timer_interrupt:0000000000000064 .L18
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:195    .text.handle_m_timer_interrupt:0000000000000044 .L15
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:323    .text.handle_local_ei_interrupts:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:389    .text.handle_trap:0000000000000064 .L28
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:361    .text.handle_trap:000000000000002c .L29
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:373    .text.handle_trap:0000000000000044 .L30
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:381    .text.handle_trap:0000000000000054 .L31
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:403    .text.handle_trap:0000000000000078 .L27
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:1113   .debug_abbrev:0000000000000000 .Ldebug_abbrev0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2270   .debug_str:000000000000029b .LASF85
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2290   .debug_str:00000000000003c0 .LASF86
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2330   .debug_str:00000000000004ca .LASF87
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2134   .debug_ranges:0000000000000000 .Ldebug_ranges0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2160   .debug_line:0000000000000000 .Ldebug_line0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2184   .debug_str:0000000000000086 .LASF0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2226   .debug_str:00000000000001a2 .LASF1
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2200   .debug_str:0000000000000104 .LASF2
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2176   .debug_str:0000000000000057 .LASF7
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2282   .debug_str:0000000000000391 .LASF3
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2284   .debug_str:000000000000039f .LASF4
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2238   .debug_str:00000000000001f3 .LASF5
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2210   .debug_str:0000000000000145 .LASF6
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2218   .debug_str:0000000000000178 .LASF8
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2234   .debug_str:00000000000001da .LASF9
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2198   .debug_str:00000000000000f6 .LASF10
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2268   .debug_str:0000000000000290 .LASF11
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2292   .debug_str:00000000000003ec .LASF12
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2324   .debug_str:00000000000004ad .LASF13
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2298   .debug_str:0000000000000409 .LASF14
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2172   .debug_str:0000000000000046 .LASF15
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2170   .debug_str:000000000000003c .LASF16
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2304   .debug_str:000000000000042e .LASF17
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2258   .debug_str:000000000000025a .LASF18
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2244   .debug_str:0000000000000219 .LASF19
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2254   .debug_str:000000000000024d .LASF20
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2260   .debug_str:0000000000000266 .LASF21
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2310   .debug_str:0000000000000453 .LASF22
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2296   .debug_str:0000000000000402 .LASF23
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2250   .debug_str:0000000000000238 .LASF24
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2332   .debug_str:0000000000000547 .LASF25
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2242   .debug_str:0000000000000212 .LASF26
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2206   .debug_str:0000000000000121 .LASF27
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2334   .debug_str:0000000000000551 .LASF28
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2326   .debug_str:00000000000004b5 .LASF29
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2186   .debug_str:000000000000009d .LASF30
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2214   .debug_str:0000000000000162 .LASF31
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2232   .debug_str:00000000000001cf .LASF32
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2248   .debug_str:000000000000022d .LASF33
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2322   .debug_str:00000000000004a2 .LASF34
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2166   .debug_str:0000000000000018 .LASF35
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2194   .debug_str:00000000000000d5 .LASF36
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2264   .debug_str:0000000000000279 .LASF37
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2288   .debug_str:00000000000003b5 .LASF38
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2312   .debug_str:000000000000045a .LASF39
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2216   .debug_str:000000000000016d .LASF40
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2274   .debug_str:0000000000000367 .LASF41
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2302   .debug_str:0000000000000422 .LASF42
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2204   .debug_str:0000000000000115 .LASF43
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2220   .debug_str:0000000000000183 .LASF44
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2240   .debug_str:0000000000000206 .LASF45
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2314   .debug_str:0000000000000465 .LASF46
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2336   .debug_str:000000000000055b .LASF47
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2182   .debug_str:000000000000007a .LASF48
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2252   .debug_str:0000000000000241 .LASF49
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2276   .debug_str:0000000000000373 .LASF50
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2190   .debug_str:00000000000000bd .LASF51
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2262   .debug_str:000000000000026d .LASF52
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2286   .debug_str:00000000000003a9 .LASF53
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2308   .debug_str:0000000000000447 .LASF54
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2328   .debug_str:00000000000004be .LASF55
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2230   .debug_str:00000000000001c3 .LASF56
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2246   .debug_str:0000000000000221 .LASF57
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2266   .debug_str:0000000000000284 .LASF58
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2164   .debug_str:000000000000000c .LASF59
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2192   .debug_str:00000000000000c9 .LASF60
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2280   .debug_str:0000000000000385 .LASF61
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2180   .debug_str:000000000000006e .LASF62
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2306   .debug_str:0000000000000433 .LASF63
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2212   .debug_str:000000000000014e .LASF64
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2228   .debug_str:00000000000001af .LASF65
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2344   .debug_str:0000000000000597 .LASF66
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2162   .debug_str:0000000000000000 .LASF74
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:336    .text.handle_trap:0000000000000000 .LFB25
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:408    .text.handle_trap:000000000000007c .LFE25
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2236   .debug_str:00000000000001ec .LASF67
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:1788   .debug_loc:0000000000000000 .LLST5
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2202   .debug_str:0000000000000110 .LASF68
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:1830   .debug_loc:0000000000000060 .LLST6
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2178   .debug_str:0000000000000061 .LASF69
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:1892   .debug_loc:00000000000000f0 .LLST7
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:360    .text.handle_trap:000000000000002c .LVL22
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:372    .text.handle_trap:0000000000000044 .LVL24
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:380    .text.handle_trap:0000000000000054 .LVL25
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:388    .text.handle_trap:0000000000000064 .LVL26
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:402    .text.handle_trap:0000000000000078 .LVL28
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2208   .debug_str:000000000000012a .LASF88
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:299    .text.handle_local_ei_interrupts:0000000000000000 .LFB24
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:329    .text.handle_local_ei_interrupts:0000000000000024 .LFE24
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2272   .debug_str:0000000000000360 .LASF70
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2003   .debug_loc:0000000000000195 .LLST3
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2342   .debug_str:000000000000058e .LASF72
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2318   .debug_str:0000000000000489 .LASF71
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2017   .debug_loc:00000000000001b6 .LLST4
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:304    .text.handle_local_ei_interrupts:0000000000000000 .LBB18
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:314    .text.handle_local_ei_interrupts:0000000000000004 .LBE18
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2222   .debug_str:000000000000018f .LASF73
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2316   .debug_str:0000000000000471 .LASF75
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:256    .text.handle_m_soft_interrupt:0000000000000000 .LFB23
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:292    .text.handle_m_soft_interrupt:000000000000002c .LFE23
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:269    .text.handle_m_soft_interrupt:0000000000000010 .LBB14
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:267    .text.handle_m_soft_interrupt:0000000000000010 .LVL15
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2168   .debug_str:0000000000000023 .LASF76
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:150    .text.handle_m_timer_interrupt:0000000000000000 .LFB22
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:249    .text.handle_m_timer_interrupt:00000000000000b0 .LFE22
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2224   .debug_str:0000000000000195 .LASF77
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:217    .text.handle_m_timer_interrupt:0000000000000080 .LBB11
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:228    .text.handle_m_timer_interrupt:0000000000000088 .LBE11
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:215    .text.handle_m_timer_interrupt:0000000000000080 .LVL12
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2320   .debug_str:000000000000048f .LASF89
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:14     .text.MRV_systick_config:0000000000000000 .LFB21
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:143    .text.MRV_systick_config:00000000000000e8 .LFE21
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2256   .debug_str:0000000000000254 .LASF78
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2035   .debug_loc:00000000000001db .LLST0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2174   .debug_str:000000000000004f .LASF79
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2056   .debug_loc:0000000000000203 .LLST1
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2294   .debug_str:00000000000003f8 .LASF80
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2074   .debug_loc:000000000000022f .LLST2
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:89     .text.MRV_systick_config:00000000000000b0 .LBB6
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:100    .text.MRV_systick_config:00000000000000b8 .LBE6
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:104    .text.MRV_systick_config:00000000000000b8 .LBB7
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:116    .text.MRV_systick_config:00000000000000bc .LBE7
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:105    .text.MRV_systick_config:00000000000000b8 .LBB8
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:115    .text.MRV_systick_config:00000000000000bc .LBE8
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2338   .debug_str:0000000000000567 .LASF90
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2196   .debug_str:00000000000000e0 .LASF91
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2340   .debug_str:000000000000057a .LASF81
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2278   .debug_str:000000000000037f .LASF82
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2188   .debug_str:00000000000000a9 .LASF83
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:2300   .debug_str:0000000000000412 .LASF84
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:339    .text.handle_trap:0000000000000000 .LVL20
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:358    .text.handle_trap:0000000000000024 .LVL21
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:365    .text.handle_trap:0000000000000030 .LVL23
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:396    .text.handle_trap:000000000000006c .LVL27
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:302    .text.handle_local_ei_interrupts:0000000000000000 .LVL16
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:319    .text.handle_local_ei_interrupts:0000000000000008 .LVL18
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:311    .text.handle_local_ei_interrupts:0000000000000004 .LVL17
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:18     .text.MRV_systick_config:0000000000000000 .LVL0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:45     .text.MRV_systick_config:0000000000000038 .LVL1
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:112    .text.MRV_systick_config:00000000000000bc .LVL4
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:120    .text.MRV_systick_config:00000000000000c0 .LVL5
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:124    .text.MRV_systick_config:00000000000000c4 .LVL6
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:67     .text.MRV_systick_config:0000000000000078 .LVL2
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:134    .text.MRV_systick_config:00000000000000d8 .LVL7
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:140    .text.MRV_systick_config:00000000000000e4 .LVL8
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:455    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:154    .text.handle_m_timer_interrupt:0000000000000000 .LBB9
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:157    .text.handle_m_timer_interrupt:0000000000000000 .LBE9
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:163    .text.handle_m_timer_interrupt:0000000000000008 .LBB10
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:173    .text.handle_m_timer_interrupt:0000000000000010 .LBE10
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:276    .text.handle_m_soft_interrupt:0000000000000018 .LBE14
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:280    .text.handle_m_soft_interrupt:000000000000001c .LBB17
C:\Users\I71825\AppData\Local\Temp\cc2h7J5P.s:286    .text.handle_m_soft_interrupt:0000000000000024 .LBE17

UNDEFINED SYMBOLS
SysTick_Handler
Software_IRQHandler
External_IRQHandler
_exit
MGEUI_IRQHandler
MGECI_IRQHandler
SUBSYS_IRQHandler
SUBSYSR_IRQHandler
Reserved_IRQHandler
MSYS_EI0_IRQHandler
MSYS_EI1_IRQHandler
MSYS_EI2_IRQHandler
MSYS_EI3_IRQHandler
MSYS_EI4_IRQHandler
MSYS_EI5_IRQHandler
MSYS_EI6_IRQHandler
MSYS_EI7_IRQHandler
