   1              		.file	"hal_irq.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.HAL_enable_interrupts,"ax",@progbits
  10              		.align	2
  11              		.globl	HAL_enable_interrupts
  13              	HAL_enable_interrupts:
  14              	.LFB21:
  15              		.file 1 "../src/platform/hal/hal_irq.c"
   1:../src/platform/hal/hal_irq.c **** /***************************************************************************//**
   2:../src/platform/hal/hal_irq.c ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/hal/hal_irq.c ****  *
   4:../src/platform/hal/hal_irq.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/hal/hal_irq.c ****  * 
   6:../src/platform/hal/hal_irq.c ****  * @file hal_irq.c
   7:../src/platform/hal/hal_irq.c ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/hal/hal_irq.c ****  * @brief Legacy interrupt control functions for the Microchip driver library 
   9:../src/platform/hal/hal_irq.c ****  * hardware abstraction layer.
  10:../src/platform/hal/hal_irq.c ****  *
  11:../src/platform/hal/hal_irq.c ****  */
  12:../src/platform/hal/hal_irq.c **** #include "hal.h"
  13:../src/platform/hal/hal_irq.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
  14:../src/platform/hal/hal_irq.c **** 
  15:../src/platform/hal/hal_irq.c **** #ifdef __cplusplus
  16:../src/platform/hal/hal_irq.c **** extern "C" {
  17:../src/platform/hal/hal_irq.c **** #endif
  18:../src/platform/hal/hal_irq.c **** 
  19:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  20:../src/platform/hal/hal_irq.c ****  * 
  21:../src/platform/hal/hal_irq.c ****  */
  22:../src/platform/hal/hal_irq.c **** void HAL_enable_interrupts(void) {
  16              		.loc 1 22 34
  17              		.cfi_startproc
  23:../src/platform/hal/hal_irq.c ****     MRV_enable_interrupts();
  18              		.loc 1 23 5
  19              		.file 2 "C:\\Work_Folder_Akhil\\Q3_2024_2025\\Arena_finalizing\\PolarFire\\AN5270_PIP\\New_Softcon
   1:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
   6:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  10:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  11:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  12:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*=========================================================================*//**
  13:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  15:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  16:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Introduction
  17:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  18:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  25:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  30:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  35:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  39:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  40:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  42:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, 
  43:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   refer to the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-cor
  44:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  45:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Core as well as this document use the terms defined below:
  46:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  48:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  58:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  59:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  61:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32, preprocessor macros have been 
  62:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted.
  63:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The HAL is used to target any of the mentioned platforms by adding the 
  64:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   following macros in the way :
  65:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Project Properties > C/C++ Build > Settings > Preprocessor in Assembler and 
  66:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Compiler settings.
  67:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The table below shows the macros corresponding to the MIV Core being used in 
  68:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   your libero project. By default, the HAL targets v3.1 of the IP core and no 
  69:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   macros need to be set for this configutation.
  70:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  71:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  72:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-----------------------------|-------------------|
  73:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  74:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  75:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  76:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  77:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  78:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt Handling
  79:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  80:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  81:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  82:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
  83:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  84:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  85:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  86:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  87:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  88:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  89:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  90:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  91:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  92:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  93:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  94:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  95:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  96:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  97:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  98:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  99:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
 100:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
 101:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 102:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 103:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 104:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 105:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 106:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 107:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 108:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 109:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 110:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 111:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 112:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 113:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 114:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 115:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 116:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the the value stored in the 
 117:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 118:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handler is as an interrupt service routine.
 119:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 120:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 121:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 122:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 123:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 124:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 125:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 126:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 127:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 128:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32.
 129:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 130:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 131:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 132:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 133:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 134:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 135:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 136:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 137:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 138:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 139:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 140:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 141:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 142:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 143:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 144:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 145:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   unchanged.
 146:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 147:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 148:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Floating Point Interrupt Support
 149:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 150:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 151:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 152:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 153:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Softconsole build settings.
 154:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 155:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   when the ISR does not used FP insturctions and saving the general purpose 
 156:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   register context is sufficient.
 157:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 158:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 159:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 160:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 161:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 162:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 163:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 164:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 165:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 166:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. This was previously (MIV_RV32 v3.0) 
 167:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   known as OPSRV, which stands for "Offload Processor Subsystem
 168:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   for RISC-V". See the earlier versions of the handbook for more details.
 169:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   In the latest release of the MIV_RV32 IP core v3.1, OPSRV has been renamed to 
 170:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 171:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 172:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *//*=========================================================================*/
 173:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 174:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
 175:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 176:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 177:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 178:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 179:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 180:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 181:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 182:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "fpga_design_config/fpga_design_config.h"
 183:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 184:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
 185:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 186:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 187:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
 188:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
 189:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 190:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 191:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 192:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 193:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 194:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 195:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 196:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 197:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 198:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 199:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------------|--------------------------|
 200:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 201:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 202:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 203:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 204:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 205:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 206:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 207:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 208:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 209:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 210:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 211:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 212:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 213:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 214:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine timer interrupt
 215:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 216:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 217:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 218:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 219:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 220:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 221:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME and MTIMECMP
 222:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 223:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 224:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 225:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   possible combinations:
 226:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 227:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 228:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 229:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 230:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 231:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 232:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 233:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 234:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 235:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 236:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 237:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 238:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   core as input.
 239:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 240:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 241:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 242:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 243:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt.
 244:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 245:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 246:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 247:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core design.
 248:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 249:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 250:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 251:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 252:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 253:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 254:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   available internally to the core.
 255:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 256:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 257:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 258:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 259:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 260:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 261:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 262:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 263:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 264:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 265:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 266:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 267:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 268:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 269:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 270:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 271:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 272:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 273:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 274:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 275:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 276:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External IRQ
 277:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 278:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 279:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External Interrupt.
 280:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 281:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 282:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 283:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 284:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 285:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 286:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 287:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 288:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 289:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
 290:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 291:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 292:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 293:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 294:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 295:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 296:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 297:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 298:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 299:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 300:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 301:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 302:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 303:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 304:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 305:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 306:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 307:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 308:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 309:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 310:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 311:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 312:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 313:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 314:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 315:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 316:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 317:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 318:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 319:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIMPID Register
 320:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 321:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 322:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 323:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 324:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 325:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 326:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 327:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 328:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 329:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP core version.
 330:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 331:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 332:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 333:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 334:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 335:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 336:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 337:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 338:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 339:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 340:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 341:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 342:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 343:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 344:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 345:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 346:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 347:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   RISC-V Specification Interrupts
 348:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 349:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 350:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   in the MIE/MIP registers.
 351:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 352:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 353:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 354:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
 355:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, follow the interrupt priority
 356:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   order and register description as mentioned in the RISC-V spec.
 357:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 358:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 359:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 360:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 361:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 362:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 363:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 364:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 365:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 366:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 367:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 368:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 369:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 370:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt numbers:
 371:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 372:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 373:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 374:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 375:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 376:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 377:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 378:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 379:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 380:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 381:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 382:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 383:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 384:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 385:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 386:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 387:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 388:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 389:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 390:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 391:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 392:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 393:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 394:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 395:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 396:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 397:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 398:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 399:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 400:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 401:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 402:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 403:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 404:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 405:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 406:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 407:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 408:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 409:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 410:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 411:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 412:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 413:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 414:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 415:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 416:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 417:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 418:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 419:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 420:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 421:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 422:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 423:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 424:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 425:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 426:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 427:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 428:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 429:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 430:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 431:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 432:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 433:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 434:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 435:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 436:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 437:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 438:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 439:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 440:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 441:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 442:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 443:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   */
 444:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 445:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 446:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 447:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 448:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 449:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 450:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 451:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 452:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 453:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 454:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 455:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 456:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 457:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 458:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 459:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 460:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 461:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 462:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 463:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 464:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 465:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 466:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 467:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 468:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 469:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 470:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 471:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 472:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 473:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 474:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 475:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 476:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 477:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 478:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 479:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 480:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 481:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 482:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 483:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 484:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 485:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 486:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 487:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 488:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 489:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 490:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 491:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 492:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 493:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 494:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 495:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 496:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 497:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 498:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 499:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 500:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 501:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 502:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 503:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 504:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 505:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 506:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 507:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 508:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 509:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 510:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 511:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 512:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 513:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 514:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 515:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 516:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 517:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 518:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 519:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 520:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 521:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 522:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 523:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 524:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 525:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 526:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 527:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 528:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 529:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 530:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 531:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 532:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 533:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 534:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 535:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 536:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 537:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 538:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 539:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 540:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 541:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 542:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 543:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 544:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 545:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 546:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 547:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 548:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 549:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 550:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 551:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 552:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 553:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   IP configurator.
 554:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 555:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 556:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 557:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 558:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 559:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 560:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 561:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 562:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 563:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 564:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 565:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 566:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
 567:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 568:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return 
 569:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 570:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 571:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 572:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 573:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 574:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 575:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 576:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 577:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 578:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 579:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 580:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 581:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 582:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 583:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 584:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 585:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 586:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 587:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
 588:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 589:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 590:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 591:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_disable_local_irq() function disables the local interrupts. It takes a 
 592:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 593:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt bit in the MIE register is disabled.
 594:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 595:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_disable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 596:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                          MRV32_MSYS_EIE0_IRQn |
 597:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                          MRV32_MSYS_SUBSYS_IRQn);
 598:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 599:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 600:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 601:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mie, mask);
 602:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 603:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /* MIV_LEGACY_RV32 */ 
 604:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 605:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 606:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_enable_interrupts() function enables all interrupts by setting the
 607:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 608:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 609:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 610:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 611:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 612:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 613:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 614:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 615:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_interrupts(void)
 616:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 617:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
  20              		.loc 2 617 5
  21              	.LBB5:
  22              	.LBB6:
  23              		.loc 2 617 5
  24              		.loc 2 617 5
  25              	 #APP
  26              	# 617 "C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_
   0              	
  27              		csrrs a5, mstatus, 8
  28              	# 0 "" 2
  29              	.LVL0:
  30              		.loc 2 617 5
  31              	 #NO_APP
  32              	.LBE6:
  33              	.LBE5:
  24:../src/platform/hal/hal_irq.c **** }
  34              		.loc 1 24 1 is_stmt 0
  35 0004 67800000 		ret
  36              		.cfi_endproc
  37              	.LFE21:
  39              		.section	.text.HAL_disable_interrupts,"ax",@progbits
  40              		.align	2
  41              		.globl	HAL_disable_interrupts
  43              	HAL_disable_interrupts:
  44              	.LFB22:
  25:../src/platform/hal/hal_irq.c **** 
  26:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  27:../src/platform/hal/hal_irq.c ****  * 
  28:../src/platform/hal/hal_irq.c ****  */
  29:../src/platform/hal/hal_irq.c **** psr_t HAL_disable_interrupts(void) {
  45              		.loc 1 29 36 is_stmt 1
  46              		.cfi_startproc
  30:../src/platform/hal/hal_irq.c ****     psr_t psr;
  47              		.loc 1 30 5
  31:../src/platform/hal/hal_irq.c ****     psr = read_csr(mstatus);
  48              		.loc 1 31 5
  49              	.LBB12:
  50              		.loc 1 31 11
  51              		.loc 1 31 11
  52              	 #APP
  53              	# 31 "../src/platform/hal/hal_irq.c" 1
  32              	    MRV_disable_interrupts();
  54              		csrr a0, mstatus
  55              	# 0 "" 2
  56              	.LVL1:
  31:../src/platform/hal/hal_irq.c ****     psr = read_csr(mstatus);
  57              		.loc 1 31 11
  58              	 #NO_APP
  59              	.LBE12:
  60              		.loc 1 32 5
 618:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 619:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 620:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 621:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_disable_interrupts() function disables all interrupts by clearing the
 622:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 623:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 624:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 625:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 626:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 627:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 628:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 629:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_disable_interrupts(void)
 630:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 631:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MPIE);
  61              		.loc 2 631 5
  62              	.LBB13:
  63              	.LBB14:
  64              		.loc 2 631 5
  65              		.loc 2 631 5
  66 0004 93070008 		li	a5,128
  67              	 #APP
  68              	# 631 "C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_
  69              		csrrc a5, mstatus, a5
  70              	# 0 "" 2
  71              	.LVL2:
  72              		.loc 2 631 5
  73              	 #NO_APP
  74              	.LBE14:
  75              	.LBE13:
 632:C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MIE);
  76              		.loc 2 632 5
  77              	.LBB16:
  78              	.LBB15:
  79              		.loc 2 632 5
  80              		.loc 2 632 5
  81              	 #APP
  82              	# 632 "C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_
  83              		csrrc a5, mstatus, 8
  84              	# 0 "" 2
  85              	.LVL3:
  86              		.loc 2 632 5
  87              	 #NO_APP
  88              	.LBE15:
  89              	.LBE16:
  33:../src/platform/hal/hal_irq.c ****     return(psr);
  90              		.loc 1 33 5
  34:../src/platform/hal/hal_irq.c **** }
  91              		.loc 1 34 1 is_stmt 0
  92 0010 67800000 		ret
  93              		.cfi_endproc
  94              	.LFE22:
  96              		.section	.text.HAL_restore_interrupts,"ax",@progbits
  97              		.align	2
  98              		.globl	HAL_restore_interrupts
 100              	HAL_restore_interrupts:
 101              	.LFB23:
  35:../src/platform/hal/hal_irq.c **** 
  36:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  37:../src/platform/hal/hal_irq.c ****  * 
  38:../src/platform/hal/hal_irq.c ****  */
  39:../src/platform/hal/hal_irq.c **** void HAL_restore_interrupts(psr_t saved_psr) {
 102              		.loc 1 39 46 is_stmt 1
 103              		.cfi_startproc
 104              	.LVL4:
  40:../src/platform/hal/hal_irq.c ****     write_csr(mstatus, saved_psr);
 105              		.loc 1 40 5
 106              	 #APP
 107              	# 40 "../src/platform/hal/hal_irq.c" 1
  41              	}
 108              		csrw mstatus, a0
 109              	# 0 "" 2
 110              		.loc 1 41 1 is_stmt 0
 111              	 #NO_APP
 112 0004 67800000 		ret
 113              		.cfi_endproc
 114              	.LFE23:
 116              		.comm	MRV_LOCAL_IRQn_Type,4,4
 117              		.text
 118              	.Letext0:
 119              		.file 3 "../src/platform/hal/cpu_types.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 hal_irq.c
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:13     .text.HAL_enable_interrupts:0000000000000000 HAL_enable_interrupts
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:17     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:18     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:20     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:23     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:24     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:Work_Folder_AkhilQ3_2024_2025Arena_finalizingPolarFireAN5270_PIPNew_Softconsolempf_an5270_v2025p1_dfsrcplatform/miv_rv32_hal/miv_rv32_hal.h:617    .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:34     .text.HAL_enable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:35     .text.HAL_enable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:36     .text.HAL_enable_interrupts:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:43     .text.HAL_disable_interrupts:0000000000000000 HAL_disable_interrupts
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:46     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:47     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:48     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:50     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:51     .text.HAL_disable_interrupts:0000000000000000 .L0 
../src/platform/hal/hal_irq.c:31     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:60     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:61     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:64     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:65     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:66     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:76     .text.HAL_disable_interrupts:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:79     .text.HAL_disable_interrupts:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:80     .text.HAL_disable_interrupts:000000000000000c .L0 
C:Work_Folder_AkhilQ3_2024_2025Arena_finalizingPolarFireAN5270_PIPNew_Softconsolempf_an5270_v2025p1_dfsrcplatform/miv_rv32_hal/miv_rv32_hal.h:632    .text.HAL_disable_interrupts:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:90     .text.HAL_disable_interrupts:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:91     .text.HAL_disable_interrupts:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:92     .text.HAL_disable_interrupts:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:93     .text.HAL_disable_interrupts:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:100    .text.HAL_restore_interrupts:0000000000000000 HAL_restore_interrupts
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:103    .text.HAL_restore_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:105    .text.HAL_restore_interrupts:0000000000000000 .L0 
../src/platform/hal/hal_irq.c:40     .text.HAL_restore_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:112    .text.HAL_restore_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:113    .text.HAL_restore_interrupts:0000000000000008 .L0 
                            *COM*:0000000000000004 MRV_LOCAL_IRQn_Type
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:39     .text.HAL_enable_interrupts:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:96     .text.HAL_disable_interrupts:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:117    .text.HAL_restore_interrupts:0000000000000008 .L0 
                     .debug_frame:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:437    .debug_abbrev:0000000000000000 .Ldebug_abbrev0
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:941    .debug_str:000000000000031a .LASF44
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:903    .debug_str:000000000000020c .LASF45
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:843    .debug_str:000000000000000b .LASF46
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:823    .debug_ranges:0000000000000000 .Ldebug_ranges0
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:839    .debug_line:0000000000000000 .Ldebug_line0
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C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:101    .text.HAL_restore_interrupts:0000000000000000 .LFB23
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:114    .text.HAL_restore_interrupts:0000000000000008 .LFE23
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:935    .debug_str:00000000000002ed .LASF49
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C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:94     .text.HAL_disable_interrupts:0000000000000014 .LFE22
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:49     .text.HAL_disable_interrupts:0000000000000000 .LBB12
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C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:63     .text.HAL_disable_interrupts:0000000000000004 .LBB14
C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:74     .text.HAL_disable_interrupts:000000000000000c .LBE14
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C:\Users\I71825\AppData\Local\Temp\ccHIJV2i.s:849    .debug_str:0000000000000098 .LASF52
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NO UNDEFINED SYMBOLS
