   1              	# 1 "../src/platform/hal/hw_reg_access.S"
   1              	/***************************************************************************//**
   0              	
   0              	
   0              	
   2              	 * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3              	 *
   4              	 * SPDX-License-Identifier: MIT
   5              	 *
   6              	 * @file hw_reg_access.S
   7              	 * @author Microchip FPGA Embedded Systems Solutions
   8              	 * @brief Hardware registers access functions.
   9              	 * The implementation of these function is platform and toolchain specific.
  10              	 * The functions declared here are implemented using assembler as part of the
  11              	 * processor/toolchain specific HAL. This implementation is for the combination
  12              	 * of the 32 bit RISC-V processors and GNU tool chain.
  13              	 *
  14              	 */
  15              	
  16              	.section .text
  17              	    .globl HW_set_32bit_reg
  18              	    .globl HW_get_32bit_reg
  19              	    .globl HW_set_32bit_reg_field
  20              	    .globl HW_get_32bit_reg_field
  21              	    .globl HW_set_16bit_reg
  22              	    .globl HW_get_16bit_reg
  23              	    .globl HW_set_16bit_reg_field
  24              	    .globl HW_get_16bit_reg_field
  25              	    .globl HW_set_8bit_reg
  26              	    .globl HW_get_8bit_reg
  27              	    .globl HW_set_8bit_reg_field
  28              	    .globl HW_get_8bit_reg_field
  29              	
  30              	
  31              	/***************************************************************************//**
  32              	 * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
  33              	 * register.
  34              	 *
  35              	 * a0:   addr_t reg_addr
  36              	 * a1:   uint32_t value
  37              	 */
  38              	HW_set_32bit_reg:
  39 0000 2320B500 	    sw a1, 0(a0)
  40 0004 67800000 	    ret
  41              	
  42              	/***************************************************************************//**
  43              	 * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
  44              	 * register.
  45              	 *
  46              	 * a0:   addr_t reg_addr
  47              	
  48              	 * @return          32 bits value read from the peripheral register.
  49              	 */
  50              	HW_get_32bit_reg:
  51 0008 03250500 	    lw a0, 0(a0)
  52 000c 67800000 	    ret
  53              	
  54              	/***************************************************************************//**
  55              	 * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
  56              	 * wide peripheral register.
  57              	 *
  58              	 * a0:   addr_t reg_addr
  59              	 * a1:   int_fast8_t shift
  60              	 * a2:   uint32_t mask
  61              	 * a3:   uint32_t value
  62              	 */
  63              	HW_set_32bit_reg_field:
  64 0010 138E0600 	    mv t3, a3
  65 0014 331EBE00 	    sll t3, t3, a1
  66 0018 337ECE00 	    and  t3, t3, a2
  67 001c 03230500 	    lw t1, 0(a0)
  68 0020 93030600 	    mv t2, a2
  69 0024 93C3F3FF 	    not t2, t2
  70 0028 33737300 	    and t1, t1, t2
  71 002c 3363C301 	    or t1, t1, t3
  72 0030 23206500 	    sw t1, 0(a0)
  73 0034 67800000 	    ret
  74              	
  75              	/***************************************************************************//**
  76              	 * HW_get_32bit_reg_field is used to read the content of a field out of a
  77              	 * 32 bits wide peripheral register.
  78              	 *
  79              	 * a0:   addr_t reg_addr
  80              	 * a1:   int_fast8_t shift
  81              	 * a2:   uint32_t mask
  82              	 *
  83              	 * @return          32 bits value containing the register field value specified
  84              	 *                  as parameter.
  85              	 */
  86              	HW_get_32bit_reg_field:
  87 0038 03250500 	    lw a0, 0(a0)
  88 003c 3375C500 	    and a0, a0, a2
  89 0040 3355B500 	    srl a0, a0, a1
  90 0044 67800000 	    ret
  91              	
  92              	/***************************************************************************//**
  93              	 * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
  94              	 * register.
  95              	 *
  96              	 * a0:   addr_t reg_addr
  97              	 * a1:   uint_fast16_t value
  98              	 */
  99              	HW_set_16bit_reg:
 100 0048 2310B500 	    sh a1, 0(a0)
 101 004c 67800000 	    ret
 102              	
 103              	/***************************************************************************//**
 104              	 * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
 105              	 * register.
 106              	 *
 107              	 * a0:   addr_t reg_addr
 108              	
 109              	 * @return          16 bits value read from the peripheral register.
 110              	 */
 111              	HW_get_16bit_reg:
 112 0050 03150500 	    lh a0, (a0)
 113 0054 67800000 	    ret
 114              	
 115              	/***************************************************************************//**
 116              	 * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
 117              	 * wide peripheral register.
 118              	 *
 119              	 * a0:   addr_t reg_addr
 120              	 * a1:   int_fast8_t shift
 121              	 * a2:   uint_fast16_t mask
 122              	 * a3:   uint_fast16_t value
 123              	 * @param value     Value to be written in the specified field.
 124              	 */
 125              	HW_set_16bit_reg_field:
 126 0058 138E0600 	    mv t3, a3
 127 005c 331EBE00 	    sll t3, t3, a1
 128 0060 337ECE00 	    and  t3, t3, a2
 129 0064 03130500 	    lh t1, 0(a0)
 130 0068 93030600 	    mv t2, a2
 131 006c 93C3F3FF 	    not t2, t2
 132 0070 33737300 	    and t1, t1, t2
 133 0074 3363C301 	    or t1, t1, t3
 134 0078 23106500 	    sh t1, 0(a0)
 135 007c 67800000 	    ret
 136              	
 137              	/***************************************************************************//**
 138              	 * HW_get_16bit_reg_field is used to read the content of a field from a
 139              	 * 16 bits wide peripheral register.
 140              	 *
 141              	 * a0:   addr_t reg_addr
 142              	 * a1:   int_fast8_t shift
 143              	 * a2:   uint_fast16_t mask
 144              	 *
 145              	 * @return          16 bits value containing the register field value specified
 146              	 *                  as parameter.
 147              	 */
 148              	HW_get_16bit_reg_field:
 149 0080 03150500 	    lh a0, 0(a0)
 150 0084 3375C500 	    and a0, a0, a2
 151 0088 3355B500 	    srl a0, a0, a1
 152 008c 67800000 	    ret
 153              	
 154              	/***************************************************************************//**
 155              	 * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
 156              	 * register.
 157              	 *
 158              	 * a0:   addr_t reg_addr
 159              	 * a1:   uint_fast8_t value
 160              	 */
 161              	HW_set_8bit_reg:
 162 0090 2300B500 	    sb a1, 0(a0)
 163 0094 67800000 	    ret
 164              	
 165              	/***************************************************************************//**
 166              	 * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
 167              	 * register.
 168              	 *
 169              	 * a0:   addr_t reg_addr
 170              	
 171              	 * @return          8 bits value read from the peripheral register.
 172              	 */
 173              	HW_get_8bit_reg:
 174 0098 03050500 	    lb a0, 0(a0)
 175 009c 67800000 	    ret
 176              	
 177              	/***************************************************************************//**
 178              	 * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
 179              	 * wide peripheral register.
 180              	 *
 181              	 * a0:   addr_t reg_addr,
 182              	 * a1:   int_fast8_t shift
 183              	 * a2:   uint_fast8_t mask
 184              	 * a3:   uint_fast8_t value
 185              	 */
 186              	HW_set_8bit_reg_field:
 187 00a0 138E0600 	    mv t3, a3
 188 00a4 331EBE00 	    sll t3, t3, a1
 189 00a8 337ECE00 	    and  t3, t3, a2
 190 00ac 03030500 	    lb t1, 0(a0)
 191 00b0 93030600 	    mv t2, a2
 192 00b4 93C3F3FF 	    not t2, t2
 193 00b8 33737300 	    and t1, t1, t2
 194 00bc 3363C301 	    or t1, t1, t3
 195 00c0 23006500 	    sb t1, 0(a0)
 196 00c4 67800000 	    ret
 197              	
 198              	/***************************************************************************//**
 199              	 * HW_get_8bit_reg_field is used to read the content of a field from a
 200              	 * 8 bits wide peripheral register.
 201              	 *
 202              	 * a0:   addr_t reg_addr
 203              	 * a1:   int_fast8_t shift
 204              	 * a2:   uint_fast8_t mask
 205              	 *
 206              	 * @return          8 bits value containing the register field value specified
 207              	 *                  as parameter.
 208              	 */
 209              	HW_get_8bit_reg_field:
 210 00c8 03050500 	    lb a0, 0(a0)
 211 00cc 3375C500 	    and a0, a0, a2
 212 00d0 3355B500 	    srl a0, a0, a1
 213 00d4 67800000 	    ret
 214              	
 215              	.end
DEFINED SYMBOLS
../src/platform/hal/hw_reg_access.S:38     .text:0000000000000000 HW_set_32bit_reg
../src/platform/hal/hw_reg_access.S:50     .text:0000000000000008 HW_get_32bit_reg
../src/platform/hal/hw_reg_access.S:63     .text:0000000000000010 HW_set_32bit_reg_field
../src/platform/hal/hw_reg_access.S:86     .text:0000000000000038 HW_get_32bit_reg_field
../src/platform/hal/hw_reg_access.S:99     .text:0000000000000048 HW_set_16bit_reg
../src/platform/hal/hw_reg_access.S:111    .text:0000000000000050 HW_get_16bit_reg
../src/platform/hal/hw_reg_access.S:125    .text:0000000000000058 HW_set_16bit_reg_field
../src/platform/hal/hw_reg_access.S:148    .text:0000000000000080 HW_get_16bit_reg_field
../src/platform/hal/hw_reg_access.S:161    .text:0000000000000090 HW_set_8bit_reg
../src/platform/hal/hw_reg_access.S:173    .text:0000000000000098 HW_get_8bit_reg
../src/platform/hal/hw_reg_access.S:186    .text:00000000000000a0 HW_set_8bit_reg_field
../src/platform/hal/hw_reg_access.S:209    .text:00000000000000c8 HW_get_8bit_reg_field
../src/platform/hal/hw_reg_access.S:39     .text:0000000000000000 .L0 
../src/platform/hal/hw_reg_access.S:40     .text:0000000000000004 .L0 
../src/platform/hal/hw_reg_access.S:51     .text:0000000000000008 .L0 
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../src/platform/hal/hw_reg_access.S:215    .text:00000000000000d8 .L0 
                            .text:0000000000000000 .L0 
../src/platform/hal/hw_reg_access.S:215    .text:00000000000000d8 .L0 
                       .debug_str:0000000000000000 .L0 
                       .debug_str:0000000000000024 .L0 
                       .debug_str:00000000000000a1 .L0 

NO UNDEFINED SYMBOLS
