
mpf_an5270_v2025p1_df.elf:     file format elf32-littleriscv
mpf_an5270_v2025p1_df.elf
architecture: riscv:rv32, flags 0x00000112:
EXEC_P, HAS_SYMS, D_PAGED
start address 0x40000000

Program Header:
    LOAD off    0x00001000 vaddr 0x40000000 paddr 0x40000000 align 2**12
         filesz 0x00002df0 memsz 0x00003830 flags rwx

Sections:
Idx Name              Size      VMA       LMA       File off  Algn  Flags
  0 .entry            000009a0  40000000  40000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .text             00002440  400009a0  400009a0  000019a0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .sdata            00000010  40002de0  40002de0  00003de0  2**4  CONTENTS, ALLOC, LOAD, DATA
  3 .data             00000000  40002df0  40002df0  00003df0  2**4  CONTENTS, ALLOC, LOAD, DATA
  4 .sbss             00000020  40002df0  40002df0  00003df0  2**4  ALLOC
  5 .bss              00000220  40002e10  40002e10  00003df0  2**4  ALLOC
  6 .heap             00000000  40003030  40003030  00003df0  2**4  CONTENTS
  7 .stack            00000800  40003030  40003030  00003df0  2**4  ALLOC
  8 .riscv.attributes 0000001c  00000000  00000000  00003df0  2**0  CONTENTS, READONLY
  9 .comment          00000051  00000000  00000000  00003e0c  2**0  CONTENTS, READONLY
 10 .debug_line       00006bf6  00000000  00000000  00003e5d  2**0  CONTENTS, READONLY, DEBUGGING
 11 .debug_info       0000a3e1  00000000  00000000  0000aa53  2**0  CONTENTS, READONLY, DEBUGGING
 12 .debug_abbrev     00001c1e  00000000  00000000  00014e34  2**0  CONTENTS, READONLY, DEBUGGING
 13 .debug_aranges    00000458  00000000  00000000  00016a58  2**3  CONTENTS, READONLY, DEBUGGING
 14 .debug_str        00001eba  00000000  00000000  00016eb0  2**0  CONTENTS, READONLY, DEBUGGING
 15 .debug_ranges     00000568  00000000  00000000  00018d70  2**3  CONTENTS, READONLY, DEBUGGING
 16 .debug_loc        000025fb  00000000  00000000  000192d8  2**0  CONTENTS, READONLY, DEBUGGING
 17 .debug_frame      00000d78  00000000  00000000  0001b8d4  2**2  CONTENTS, READONLY, DEBUGGING
SYMBOL TABLE:
40000000 l    d  .entry	00000000 .entry
400009a0 l    d  .text	00000000 .text
40002de0 l    d  .sdata	00000000 .sdata
40002df0 l    d  .data	00000000 .data
40002df0 l    d  .sbss	00000000 .sbss
40002e10 l    d  .bss	00000000 .bss
40003030 l    d  .heap	00000000 .heap
40003030 l    d  .stack	00000000 .stack
00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
00000000 l    d  .comment	00000000 .comment
00000000 l    d  .debug_line	00000000 .debug_line
00000000 l    d  .debug_info	00000000 .debug_info
00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
00000000 l    d  .debug_aranges	00000000 .debug_aranges
00000000 l    d  .debug_str	00000000 .debug_str
00000000 l    d  .debug_ranges	00000000 .debug_ranges
00000000 l    d  .debug_loc	00000000 .debug_loc
00000000 l    d  .debug_frame	00000000 .debug_frame
00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
400009a0 l       .text	00000000 handle_reset
40000004 l       .entry	00000000 trap_entry
40000090 l       .entry	00000000 generic_trap_handler
40000010 l       .entry	00000000 sw_trap_entry
40000120 l       .entry	00000000 vector_sw_trap_handler
40000020 l       .entry	00000000 tmr_trap_entry
400001a8 l       .entry	00000000 vector_tmr_trap_handler
40000030 l       .entry	00000000 ext_trap_entry
40000230 l       .entry	00000000 vector_ext_trap_handler
40000044 l       .entry	00000000 MGEUI_trap_entry
400002b8 l       .entry	00000000 vector_MGEUI_trap_handler
40000048 l       .entry	00000000 MGECI_trap_entry
40000340 l       .entry	00000000 vector_MGECI_trap_handler
4000005c l       .entry	00000000 MSYS_MIE22_trap_entry
40000890 l       .entry	00000000 vector_SUBSYSR_IRQHandler
40000060 l       .entry	00000000 MSYS_MIE23_trap_entry
400006f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
40000064 l       .entry	00000000 MSYS_MIE24_trap_entry
400003c8 l       .entry	00000000 vector_MSYS_EI0_trap_handler
40000068 l       .entry	00000000 MSYS_MIE25_trap_entry
40000450 l       .entry	00000000 vector_MSYS_EI1_trap_handler
4000006c l       .entry	00000000 MSYS_MIE26_trap_entry
400004d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
40000070 l       .entry	00000000 MSYS_MIE27_trap_entry
40000560 l       .entry	00000000 vector_MSYS_EI3_trap_handler
40000074 l       .entry	00000000 MSYS_MIE28_trap_entry
400005e8 l       .entry	00000000 vector_MSYS_EI4_trap_handler
40000078 l       .entry	00000000 MSYS_MIE29_trap_entry
40000670 l       .entry	00000000 vector_MSYS_EI5_trap_handler
4000007c l       .entry	00000000 MSYS_MIE30_trap_entry
40000780 l       .entry	00000000 vector_MSYS_EI6_trap_handler
40000080 l       .entry	00000000 MSYS_MIE31_trap_entry
40000808 l       .entry	00000000 vector_MSYS_EI7_trap_handler
40000918 l       .entry	00000000 generic_restore
400009f0 l       .text	00000000 ima_cores_setup
40000a38 l       .text	00000000 vector_address_not_matching
400009fc l       .text	00000000 generic_reset_handling
40000ab0 l       .text	00000000 block_copy
40000a3c l       .text	00000000 initializations
40000a90 l       .text	00000000 zeroize_block
40000ad8 l       .text	00000000 block_copy_error
40000aa0 l       .text	00000000 zeroize_loop
40000ac0 l       .text	00000000 block_copy_loop
40000adc l       .text	00000000 block_copy_exit
00000000 l    df *ABS*	00000000 miv_rv32_hal.c
40002df0 l     O .sbss	00000008 g_systick_cmp_value
40002df8 l     O .sbss	00000008 g_systick_increment
00000000 l    df *ABS*	00000000 miv_rv32_init.c
00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
40000d08 l     F .text	00000010 Software_IRQHandler.localalias.0
00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
00000000 l    df *ABS*	00000000 hal_irq.c
00000000 l    df *ABS*	00000000 core_i2c.c
40000e44 l     F .text	00000020 enable_slave_if_required
00000000 l    df *ABS*	00000000 i2c_interrupt.c
00000000 l    df *ABS*	00000000 core_gpio.c
00000000 l    df *ABS*	00000000 AXI4-Lite.c
00000000 l    df *ABS*	00000000 imx334_corei2c.c
40001b18 l     F .text	00000098 sensor_i2c_write_gain
40001bb0 l     F .text	000000ac sensor_i2c_write.isra.0
40002e10 l     O .bss	00000040 tx_buffer
40002e00 l     O .sbss	00000004 status
00000000 l    df *ABS*	00000000 hdmi_tx.c
40002e50 l     O .bss	00000010 tx_buffer
40002d80 l     O .text	00000052 iic_hdmi_out_config
00000000 l    df *ABS*	00000000 msdelay.c
00000000 l    df *ABS*	00000000 main.c
40002de0 l     O .sdata	00000002 in_gain
40002de2 l     O .sdata	00000002 in_gain1
40002e60 g     O .bss	00000002 bayer1
40002e62 g     O .bss	00000002 det_thr2_cam1_4k
40002e64 g     O .bss	00000002 b_gain
00000800 g       *ABS*	00000000 STACK_SIZE
40001cfc g     F .text	000007b0 imx334_cam_reginit
40002e66 g     O .bss	00000002 det_thr2
400035e0 g       .sdata	00000000 __global_pointer$
40002e68 g     O .bss	00000004 contrast_scl
40002df0 g       *ABS*	00000000 __data_load
400025fc g     F .text	00000038 SysTick_Handler
40000e34 g       .text	00000000 HW_get_8bit_reg_field
40002e6c g     O .bss	00000002 r_gain
40001058 g     F .text	00000140 I2C_write_read
40002e70 g     O .bss	00000004 second_const
40002df0 g       .sbss	00000000 __sbss_start
40000c74 g     F .text	00000024 handle_local_ei_interrupts
40000d6c g       .text	00000000 HW_set_32bit_reg
40002e74 g     O .bss	00000008 g_gpio_out
40000d50 g     F .text	00000014 HAL_disable_interrupts
400024ac g     F .text	00000044 gain_setting
40002e7c g     O .bss	00000004 rx_ms_count1
40002e80 g     O .bss	00000002 dpc_bayer_cam1_4k
40002de0 g       .sdata	00000000 __sdata_start
40000d2c  w    F .text	00000004 MSYS_EI4_IRQHandler
40000d64 g     F .text	00000008 HAL_restore_interrupts
40002e82 g     O .bss	00000002 b_const
40002e84 g     O .bss	00000002 dpc_bayer_cam1
40000e0c g       .text	00000000 HW_set_8bit_reg_field
400024f0 g     F .text	000000ec HDMI_tx_init
40002c70 g     F .text	00000048 .hidden __udivsi3
40000d24  w    F .text	00000004 SUBSYS_IRQHandler
40000c98 g     F .text	00000068 handle_trap
40002e86 g     O .bss	00000002 det_thr1_cam2_scale
40000d38  w    F .text	00000004 MSYS_EI6_IRQHandler
40000d40  w    F .text	00000004 SUBSYSR_IRQHandler
40000ae0 g     F .text	000000d0 MRV_systick_config
40000d1c  w    F .text	00000004 MGECI_IRQHandler
400011d8 g     F .text	0000061c I2C_isr
40003030 g       .heap	00000000 _heap_end
40002d40 g     O .text	00000040 local_irq_handler_table
40000d3c  w    F .text	00000004 MSYS_EI7_IRQHandler
40003030 g       .bss	00000000 __bss_end
40002e88 g     O .bss	00000004 cam_4K_IE_IA_Constant
40002e8c g     O .bss	00000002 dpc_sel
40000d00 g     F .text	00000004 _init
40000dfc g       .text	00000000 HW_set_8bit_reg
40000e04 g       .text	00000000 HW_get_8bit_reg
40002e8e g     O .bss	00000002 det_thr1_cam1_4k
40002654 g     F .text	00000020 MSYS_EI1_IRQHandler
40002e10 g       .sbss	00000000 __sbss_end
40002e90 g     O .bss	00000002 bayer0
40000d7c g       .text	00000000 HW_set_32bit_reg_field
40002e04 g     O .sbss	00000004 timerdone
40002e94 g     O .bss	00000004 g_ms_count
40002e98 g     O .bss	00000004 rx_ms_count
40002e9c g     O .bss	0000006c g_i2c_instance_hdmi
40002f08 g     O .bss	00000002 r_const
40002f0c g     O .bss	00000004 cam_IE_IA_Constant
40003830 g       .stack	00000000 __stack_top
40002cb8 g     F .text	00000010 .hidden __umodsi3
40002f10 g     O .bss	00000002 det_thr2_cam1
40001b08 g     F .text	00000008 axi4literead
40002f14 g     O .bss	00000004 ie_ver
00000000 g       *ABS*	00000000 HEAP_SIZE
40002f18 g     O .bss	00000002 contrast
40002f1c g     O .bss	00000004 total_sum
40000000 g       .entry	00000000 _start
40000bb0 g     F .text	0000009c handle_m_timer_interrupt
40002f20 g     O .bss	00000002 g_const
40002694 g     F .text	0000031c set_bgr_gain
40002de0 g       *ABS*	00000000 __sdata_load
40002df0 g       .data	00000000 __data_end
40002c44 g     F .text	00000024 .hidden __mulsi3
40000da4 g       .text	00000000 HW_get_32bit_reg_field
40002f22 g     O .bss	00000002 det_thr1_cam1
4000185c g     F .text	0000011c GPIO_init
40002f24 g     O .bss	00000004 g_10ms_count
40002e10 g       .bss	00000000 __bss_start
40000d48 g     F .text	00000008 HAL_enable_interrupts
40002d1c g     F .text	0000001c memset
400029b0 g     F .text	00000294 main
40000d30  w    F .text	00000004 MSYS_EI5_IRQHandler
40002f28 g     O .bss	00000002 g_gain
400017f4 g     F .text	00000034 I2C_enable_irq
40002f2c g     O .bss	00000004 scale_IE_IA_Constant
40000d20  w    F .text	00000004 MGEUI_IRQHandler
400025dc g     F .text	00000020 msdelay
40002f30 g     O .bss	00000002 det_thr1
40000dbc g       .text	00000000 HW_get_16bit_reg
40002c68 g     F .text	00000084 .hidden __divsi3
40002df0 g       .sdata	00000000 __sdata_end
40001c5c g     F .text	000000a0 imx334_cam_init
40003030 g       .heap	00000000 __heap_end
40000d04 g     F .text	00000004 _fini
40000dc4 g       .text	00000000 HW_set_16bit_reg_field
40002674 g     F .text	00000020 MSYS_EI2_IRQHandler
40003030 g       .stack	00000000 __stack_bottom
40000d08  w    F .text	00000010 Software_IRQHandler
40002f34 g     O .bss	0000006c g_i2c_instance_cam2
40003030 g       .heap	00000000 __heap_start
40000e64 g     F .text	00000100 I2C_init
40001198 g     F .text	00000040 I2C_wait_complete
40001b10 g     F .text	00000008 axi4litewrite
40003030 g       .bss	00000000 _end
40000d34  w    F .text	00000004 Reserved_IRQHandler
40002fa0 g     O .bss	00000002 det_thr2_cam2_scale
40002fa2 g     O .bss	00000002 dpc_bayer
40002fa4 g     O .bss	00000002 brightness
40002fa6 g     O .bss	00000002 dpc_bayer_cam2_scale
40001828 g     F .text	00000034 I2C_disable_irq
40002fa8 g     O .bss	00000004 a
40002cec g     F .text	00000030 .hidden __modsi3
40000d74 g       .text	00000000 HW_get_32bit_reg
40000d44 g     F .text	00000004 _exit
40000db4 g       .text	00000000 HW_set_16bit_reg
40000d28  w    F .text	00000004 MSYS_EI3_IRQHandler
40002fac g     O .bss	00000002 bayer4k
40002fb0 g     O .bss	00000004 g_100ms_count1
40000d18  w    F .text	00000004 External_IRQHandler
40002df0 g       .data	00000000 __data_start
40002fb4 g     O .bss	00000002 alpha
40002fb8 g     O .bss	0000006c g_i2c_instance_cam1
40000c4c g     F .text	00000028 handle_m_soft_interrupt
40000dec g       .text	00000000 HW_get_16bit_reg_field
40001978 g     F .text	00000190 GPIO_set_output
40000f64 g     F .text	000000f4 I2C_write
40002634 g     F .text	00000020 MSYS_EI0_IRQHandler



Disassembly of section .entry:

40000000 <_start>:
_start():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:113

  .section      .entry, "ax"
  .globl _start

_start:
  j handle_reset
40000000:	1a10006f          	j	400009a0 <handle_reset>

40000004 <trap_entry>:
trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:124
   at the jump and you can at least look at mcause, mepc and get some hints
   about the crash. */
trap_entry:
.option push
.option norvc
j generic_trap_handler
40000004:	08c0006f          	j	40000090 <generic_trap_handler>
	...

40000010 <sw_trap_entry>:
sw_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:130
.option pop
  .word 0
  .word 0

sw_trap_entry:
  j vector_sw_trap_handler
40000010:	1100006f          	j	40000120 <vector_sw_trap_handler>
	...

40000020 <tmr_trap_entry>:
tmr_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:139
  .word 0
  .word 0
  .word 0

tmr_trap_entry:
  j vector_tmr_trap_handler
40000020:	1880006f          	j	400001a8 <vector_tmr_trap_handler>
	...

40000030 <ext_trap_entry>:
ext_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:148
  .word 0
  .word 0
  .word 0

ext_trap_entry:
  j vector_ext_trap_handler
40000030:	2000006f          	j	40000230 <vector_ext_trap_handler>
	...

40000044 <MGEUI_trap_entry>:
MGEUI_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:159
  .word 0
  .word 0

#ifndef MIV_LEGACY_RV32
MGEUI_trap_entry:
  j vector_MGEUI_trap_handler
40000044:	2740006f          	j	400002b8 <vector_MGEUI_trap_handler>

40000048 <MGECI_trap_entry>:
MGECI_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:165
#ifdef __riscv_compressed
  .2byte 0
#endif

MGECI_trap_entry:
  j vector_MGECI_trap_handler
40000048:	2f80006f          	j	40000340 <vector_MGECI_trap_handler>
	...

4000005c <MSYS_MIE22_trap_entry>:
MSYS_MIE22_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:177
  .word 0

#ifndef MIV_RV32_V3_0
MSYS_MIE22_trap_entry:
#ifndef MIV_RV32_V3_0 
  j vector_SUBSYSR_IRQHandler
4000005c:	0350006f          	j	40000890 <vector_SUBSYSR_IRQHandler>

40000060 <MSYS_MIE23_trap_entry>:
MSYS_MIE23_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:184
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE23_trap_entry:
  j vector_SUBSYS_IRQHandler
40000060:	6980006f          	j	400006f8 <vector_SUBSYS_IRQHandler>

40000064 <MSYS_MIE24_trap_entry>:
MSYS_MIE24_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:191
  .2byte 0
#endif
#endif /*MIV_RV32_V3_0*/

MSYS_MIE24_trap_entry:
  j vector_MSYS_EI0_trap_handler
40000064:	3640006f          	j	400003c8 <vector_MSYS_EI0_trap_handler>

40000068 <MSYS_MIE25_trap_entry>:
MSYS_MIE25_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:197
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE25_trap_entry:
  j vector_MSYS_EI1_trap_handler
40000068:	3e80006f          	j	40000450 <vector_MSYS_EI1_trap_handler>

4000006c <MSYS_MIE26_trap_entry>:
MSYS_MIE26_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:203
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE26_trap_entry:
  j vector_MSYS_EI2_trap_handler
4000006c:	46c0006f          	j	400004d8 <vector_MSYS_EI2_trap_handler>

40000070 <MSYS_MIE27_trap_entry>:
MSYS_MIE27_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:209
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE27_trap_entry:
  j vector_MSYS_EI3_trap_handler
40000070:	4f00006f          	j	40000560 <vector_MSYS_EI3_trap_handler>

40000074 <MSYS_MIE28_trap_entry>:
MSYS_MIE28_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:215
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE28_trap_entry:
  j vector_MSYS_EI4_trap_handler
40000074:	5740006f          	j	400005e8 <vector_MSYS_EI4_trap_handler>

40000078 <MSYS_MIE29_trap_entry>:
MSYS_MIE29_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:221
#ifdef __riscv_compressed
  .2byte 0
#endif

MSYS_MIE29_trap_entry:
  j vector_MSYS_EI5_trap_handler
40000078:	5f80006f          	j	40000670 <vector_MSYS_EI5_trap_handler>

4000007c <MSYS_MIE30_trap_entry>:
MSYS_MIE30_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:228
  .2byte 0
#endif

MSYS_MIE30_trap_entry:
#ifndef MIV_RV32_V3_0
  j vector_MSYS_EI6_trap_handler
4000007c:	7040006f          	j	40000780 <vector_MSYS_EI6_trap_handler>

40000080 <MSYS_MIE31_trap_entry>:
MSYS_MIE31_trap_entry():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:238
  .2byte 0
#endif

#ifndef MIV_RV32_V3_0
MSYS_MIE31_trap_entry:
  j vector_MSYS_EI7_trap_handler
40000080:	7880006f          	j	40000808 <vector_MSYS_EI7_trap_handler>
40000084:	00000013          	nop
40000088:	00000013          	nop
4000008c:	00000013          	nop

40000090 <generic_trap_handler>:
generic_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:247
#endif /* MIV_RV32_V3_0 */
#endif /* MIV_LEGACY_RV32 */

.align 4
generic_trap_handler:
  STORE_CONTEXT
40000090:	f8010113          	addi	sp,sp,-128
40000094:	00112023          	sw	ra,0(sp)
40000098:	00212223          	sw	sp,4(sp)
4000009c:	00312423          	sw	gp,8(sp)
400000a0:	00412623          	sw	tp,12(sp)
400000a4:	00512823          	sw	t0,16(sp)
400000a8:	00612a23          	sw	t1,20(sp)
400000ac:	00712c23          	sw	t2,24(sp)
400000b0:	00812e23          	sw	s0,28(sp)
400000b4:	02912023          	sw	s1,32(sp)
400000b8:	02a12223          	sw	a0,36(sp)
400000bc:	02b12423          	sw	a1,40(sp)
400000c0:	02c12623          	sw	a2,44(sp)
400000c4:	02d12823          	sw	a3,48(sp)
400000c8:	02e12a23          	sw	a4,52(sp)
400000cc:	02f12c23          	sw	a5,56(sp)
400000d0:	03012e23          	sw	a6,60(sp)
400000d4:	05112023          	sw	a7,64(sp)
400000d8:	05212223          	sw	s2,68(sp)
400000dc:	05312423          	sw	s3,72(sp)
400000e0:	05412623          	sw	s4,76(sp)
400000e4:	05512823          	sw	s5,80(sp)
400000e8:	05612a23          	sw	s6,84(sp)
400000ec:	05712c23          	sw	s7,88(sp)
400000f0:	05812e23          	sw	s8,92(sp)
400000f4:	07912023          	sw	s9,96(sp)
400000f8:	07a12223          	sw	s10,100(sp)
400000fc:	07b12423          	sw	s11,104(sp)
40000100:	07c12623          	sw	t3,108(sp)
40000104:	07d12823          	sw	t4,112(sp)
40000108:	07e12a23          	sw	t5,116(sp)
4000010c:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
  csrr a0, mcause
40000110:	34202573          	csrr	a0,mcause
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
  csrr a1, mepc
40000114:	341025f3          	csrr	a1,mepc
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
  jal handle_trap
40000118:	381000ef          	jal	ra,40000c98 <handle_trap>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
  j generic_restore
4000011c:	7fc0006f          	j	40000918 <generic_restore>

40000120 <vector_sw_trap_handler>:
vector_sw_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:254

vector_sw_trap_handler:
  STORE_CONTEXT
40000120:	f8010113          	addi	sp,sp,-128
40000124:	00112023          	sw	ra,0(sp)
40000128:	00212223          	sw	sp,4(sp)
4000012c:	00312423          	sw	gp,8(sp)
40000130:	00412623          	sw	tp,12(sp)
40000134:	00512823          	sw	t0,16(sp)
40000138:	00612a23          	sw	t1,20(sp)
4000013c:	00712c23          	sw	t2,24(sp)
40000140:	00812e23          	sw	s0,28(sp)
40000144:	02912023          	sw	s1,32(sp)
40000148:	02a12223          	sw	a0,36(sp)
4000014c:	02b12423          	sw	a1,40(sp)
40000150:	02c12623          	sw	a2,44(sp)
40000154:	02d12823          	sw	a3,48(sp)
40000158:	02e12a23          	sw	a4,52(sp)
4000015c:	02f12c23          	sw	a5,56(sp)
40000160:	03012e23          	sw	a6,60(sp)
40000164:	05112023          	sw	a7,64(sp)
40000168:	05212223          	sw	s2,68(sp)
4000016c:	05312423          	sw	s3,72(sp)
40000170:	05412623          	sw	s4,76(sp)
40000174:	05512823          	sw	s5,80(sp)
40000178:	05612a23          	sw	s6,84(sp)
4000017c:	05712c23          	sw	s7,88(sp)
40000180:	05812e23          	sw	s8,92(sp)
40000184:	07912023          	sw	s9,96(sp)
40000188:	07a12223          	sw	s10,100(sp)
4000018c:	07b12423          	sw	s11,104(sp)
40000190:	07c12623          	sw	t3,108(sp)
40000194:	07d12823          	sw	t4,112(sp)
40000198:	07e12a23          	sw	t5,116(sp)
4000019c:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
  jal handle_m_soft_interrupt
400001a0:	2ad000ef          	jal	ra,40000c4c <handle_m_soft_interrupt>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
  j generic_restore
400001a4:	7740006f          	j	40000918 <generic_restore>

400001a8 <vector_tmr_trap_handler>:
vector_tmr_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:259

vector_tmr_trap_handler:
  STORE_CONTEXT
400001a8:	f8010113          	addi	sp,sp,-128
400001ac:	00112023          	sw	ra,0(sp)
400001b0:	00212223          	sw	sp,4(sp)
400001b4:	00312423          	sw	gp,8(sp)
400001b8:	00412623          	sw	tp,12(sp)
400001bc:	00512823          	sw	t0,16(sp)
400001c0:	00612a23          	sw	t1,20(sp)
400001c4:	00712c23          	sw	t2,24(sp)
400001c8:	00812e23          	sw	s0,28(sp)
400001cc:	02912023          	sw	s1,32(sp)
400001d0:	02a12223          	sw	a0,36(sp)
400001d4:	02b12423          	sw	a1,40(sp)
400001d8:	02c12623          	sw	a2,44(sp)
400001dc:	02d12823          	sw	a3,48(sp)
400001e0:	02e12a23          	sw	a4,52(sp)
400001e4:	02f12c23          	sw	a5,56(sp)
400001e8:	03012e23          	sw	a6,60(sp)
400001ec:	05112023          	sw	a7,64(sp)
400001f0:	05212223          	sw	s2,68(sp)
400001f4:	05312423          	sw	s3,72(sp)
400001f8:	05412623          	sw	s4,76(sp)
400001fc:	05512823          	sw	s5,80(sp)
40000200:	05612a23          	sw	s6,84(sp)
40000204:	05712c23          	sw	s7,88(sp)
40000208:	05812e23          	sw	s8,92(sp)
4000020c:	07912023          	sw	s9,96(sp)
40000210:	07a12223          	sw	s10,100(sp)
40000214:	07b12423          	sw	s11,104(sp)
40000218:	07c12623          	sw	t3,108(sp)
4000021c:	07d12823          	sw	t4,112(sp)
40000220:	07e12a23          	sw	t5,116(sp)
40000224:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
  jal handle_m_timer_interrupt
40000228:	189000ef          	jal	ra,40000bb0 <handle_m_timer_interrupt>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
  j generic_restore
4000022c:	6ec0006f          	j	40000918 <generic_restore>

40000230 <vector_ext_trap_handler>:
vector_ext_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:264

vector_ext_trap_handler:
  STORE_CONTEXT
40000230:	f8010113          	addi	sp,sp,-128
40000234:	00112023          	sw	ra,0(sp)
40000238:	00212223          	sw	sp,4(sp)
4000023c:	00312423          	sw	gp,8(sp)
40000240:	00412623          	sw	tp,12(sp)
40000244:	00512823          	sw	t0,16(sp)
40000248:	00612a23          	sw	t1,20(sp)
4000024c:	00712c23          	sw	t2,24(sp)
40000250:	00812e23          	sw	s0,28(sp)
40000254:	02912023          	sw	s1,32(sp)
40000258:	02a12223          	sw	a0,36(sp)
4000025c:	02b12423          	sw	a1,40(sp)
40000260:	02c12623          	sw	a2,44(sp)
40000264:	02d12823          	sw	a3,48(sp)
40000268:	02e12a23          	sw	a4,52(sp)
4000026c:	02f12c23          	sw	a5,56(sp)
40000270:	03012e23          	sw	a6,60(sp)
40000274:	05112023          	sw	a7,64(sp)
40000278:	05212223          	sw	s2,68(sp)
4000027c:	05312423          	sw	s3,72(sp)
40000280:	05412623          	sw	s4,76(sp)
40000284:	05512823          	sw	s5,80(sp)
40000288:	05612a23          	sw	s6,84(sp)
4000028c:	05712c23          	sw	s7,88(sp)
40000290:	05812e23          	sw	s8,92(sp)
40000294:	07912023          	sw	s9,96(sp)
40000298:	07a12223          	sw	s10,100(sp)
4000029c:	07b12423          	sw	s11,104(sp)
400002a0:	07c12623          	sw	t3,108(sp)
400002a4:	07d12823          	sw	t4,112(sp)
400002a8:	07e12a23          	sw	t5,116(sp)
400002ac:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:268
#ifdef MIV_LEGACY_RV32
  jal handle_m_ext_interrupt
#else
  jal External_IRQHandler
400002b0:	269000ef          	jal	ra,40000d18 <External_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:270
#endif /* MIV_LEGACY_RV32 */
  j generic_restore
400002b4:	6640006f          	j	40000918 <generic_restore>

400002b8 <vector_MGEUI_trap_handler>:
vector_MGEUI_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:274

#ifndef MIV_LEGACY_RV32
vector_MGEUI_trap_handler:
  STORE_CONTEXT
400002b8:	f8010113          	addi	sp,sp,-128
400002bc:	00112023          	sw	ra,0(sp)
400002c0:	00212223          	sw	sp,4(sp)
400002c4:	00312423          	sw	gp,8(sp)
400002c8:	00412623          	sw	tp,12(sp)
400002cc:	00512823          	sw	t0,16(sp)
400002d0:	00612a23          	sw	t1,20(sp)
400002d4:	00712c23          	sw	t2,24(sp)
400002d8:	00812e23          	sw	s0,28(sp)
400002dc:	02912023          	sw	s1,32(sp)
400002e0:	02a12223          	sw	a0,36(sp)
400002e4:	02b12423          	sw	a1,40(sp)
400002e8:	02c12623          	sw	a2,44(sp)
400002ec:	02d12823          	sw	a3,48(sp)
400002f0:	02e12a23          	sw	a4,52(sp)
400002f4:	02f12c23          	sw	a5,56(sp)
400002f8:	03012e23          	sw	a6,60(sp)
400002fc:	05112023          	sw	a7,64(sp)
40000300:	05212223          	sw	s2,68(sp)
40000304:	05312423          	sw	s3,72(sp)
40000308:	05412623          	sw	s4,76(sp)
4000030c:	05512823          	sw	s5,80(sp)
40000310:	05612a23          	sw	s6,84(sp)
40000314:	05712c23          	sw	s7,88(sp)
40000318:	05812e23          	sw	s8,92(sp)
4000031c:	07912023          	sw	s9,96(sp)
40000320:	07a12223          	sw	s10,100(sp)
40000324:	07b12423          	sw	s11,104(sp)
40000328:	07c12623          	sw	t3,108(sp)
4000032c:	07d12823          	sw	t4,112(sp)
40000330:	07e12a23          	sw	t5,116(sp)
40000334:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
  jal MGEUI_IRQHandler
40000338:	1e9000ef          	jal	ra,40000d20 <MGEUI_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
  j generic_restore
4000033c:	5dc0006f          	j	40000918 <generic_restore>

40000340 <vector_MGECI_trap_handler>:
vector_MGECI_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:279

vector_MGECI_trap_handler:
  STORE_CONTEXT
40000340:	f8010113          	addi	sp,sp,-128
40000344:	00112023          	sw	ra,0(sp)
40000348:	00212223          	sw	sp,4(sp)
4000034c:	00312423          	sw	gp,8(sp)
40000350:	00412623          	sw	tp,12(sp)
40000354:	00512823          	sw	t0,16(sp)
40000358:	00612a23          	sw	t1,20(sp)
4000035c:	00712c23          	sw	t2,24(sp)
40000360:	00812e23          	sw	s0,28(sp)
40000364:	02912023          	sw	s1,32(sp)
40000368:	02a12223          	sw	a0,36(sp)
4000036c:	02b12423          	sw	a1,40(sp)
40000370:	02c12623          	sw	a2,44(sp)
40000374:	02d12823          	sw	a3,48(sp)
40000378:	02e12a23          	sw	a4,52(sp)
4000037c:	02f12c23          	sw	a5,56(sp)
40000380:	03012e23          	sw	a6,60(sp)
40000384:	05112023          	sw	a7,64(sp)
40000388:	05212223          	sw	s2,68(sp)
4000038c:	05312423          	sw	s3,72(sp)
40000390:	05412623          	sw	s4,76(sp)
40000394:	05512823          	sw	s5,80(sp)
40000398:	05612a23          	sw	s6,84(sp)
4000039c:	05712c23          	sw	s7,88(sp)
400003a0:	05812e23          	sw	s8,92(sp)
400003a4:	07912023          	sw	s9,96(sp)
400003a8:	07a12223          	sw	s10,100(sp)
400003ac:	07b12423          	sw	s11,104(sp)
400003b0:	07c12623          	sw	t3,108(sp)
400003b4:	07d12823          	sw	t4,112(sp)
400003b8:	07e12a23          	sw	t5,116(sp)
400003bc:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
  jal MGECI_IRQHandler
400003c0:	15d000ef          	jal	ra,40000d1c <MGECI_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
  j generic_restore
400003c4:	5540006f          	j	40000918 <generic_restore>

400003c8 <vector_MSYS_EI0_trap_handler>:
vector_MSYS_EI0_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:284

vector_MSYS_EI0_trap_handler:
  STORE_CONTEXT
400003c8:	f8010113          	addi	sp,sp,-128
400003cc:	00112023          	sw	ra,0(sp)
400003d0:	00212223          	sw	sp,4(sp)
400003d4:	00312423          	sw	gp,8(sp)
400003d8:	00412623          	sw	tp,12(sp)
400003dc:	00512823          	sw	t0,16(sp)
400003e0:	00612a23          	sw	t1,20(sp)
400003e4:	00712c23          	sw	t2,24(sp)
400003e8:	00812e23          	sw	s0,28(sp)
400003ec:	02912023          	sw	s1,32(sp)
400003f0:	02a12223          	sw	a0,36(sp)
400003f4:	02b12423          	sw	a1,40(sp)
400003f8:	02c12623          	sw	a2,44(sp)
400003fc:	02d12823          	sw	a3,48(sp)
40000400:	02e12a23          	sw	a4,52(sp)
40000404:	02f12c23          	sw	a5,56(sp)
40000408:	03012e23          	sw	a6,60(sp)
4000040c:	05112023          	sw	a7,64(sp)
40000410:	05212223          	sw	s2,68(sp)
40000414:	05312423          	sw	s3,72(sp)
40000418:	05412623          	sw	s4,76(sp)
4000041c:	05512823          	sw	s5,80(sp)
40000420:	05612a23          	sw	s6,84(sp)
40000424:	05712c23          	sw	s7,88(sp)
40000428:	05812e23          	sw	s8,92(sp)
4000042c:	07912023          	sw	s9,96(sp)
40000430:	07a12223          	sw	s10,100(sp)
40000434:	07b12423          	sw	s11,104(sp)
40000438:	07c12623          	sw	t3,108(sp)
4000043c:	07d12823          	sw	t4,112(sp)
40000440:	07e12a23          	sw	t5,116(sp)
40000444:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
  jal MSYS_EI0_IRQHandler
40000448:	1ec020ef          	jal	ra,40002634 <MSYS_EI0_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
  j generic_restore
4000044c:	4cc0006f          	j	40000918 <generic_restore>

40000450 <vector_MSYS_EI1_trap_handler>:
vector_MSYS_EI1_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:289

vector_MSYS_EI1_trap_handler:
  STORE_CONTEXT
40000450:	f8010113          	addi	sp,sp,-128
40000454:	00112023          	sw	ra,0(sp)
40000458:	00212223          	sw	sp,4(sp)
4000045c:	00312423          	sw	gp,8(sp)
40000460:	00412623          	sw	tp,12(sp)
40000464:	00512823          	sw	t0,16(sp)
40000468:	00612a23          	sw	t1,20(sp)
4000046c:	00712c23          	sw	t2,24(sp)
40000470:	00812e23          	sw	s0,28(sp)
40000474:	02912023          	sw	s1,32(sp)
40000478:	02a12223          	sw	a0,36(sp)
4000047c:	02b12423          	sw	a1,40(sp)
40000480:	02c12623          	sw	a2,44(sp)
40000484:	02d12823          	sw	a3,48(sp)
40000488:	02e12a23          	sw	a4,52(sp)
4000048c:	02f12c23          	sw	a5,56(sp)
40000490:	03012e23          	sw	a6,60(sp)
40000494:	05112023          	sw	a7,64(sp)
40000498:	05212223          	sw	s2,68(sp)
4000049c:	05312423          	sw	s3,72(sp)
400004a0:	05412623          	sw	s4,76(sp)
400004a4:	05512823          	sw	s5,80(sp)
400004a8:	05612a23          	sw	s6,84(sp)
400004ac:	05712c23          	sw	s7,88(sp)
400004b0:	05812e23          	sw	s8,92(sp)
400004b4:	07912023          	sw	s9,96(sp)
400004b8:	07a12223          	sw	s10,100(sp)
400004bc:	07b12423          	sw	s11,104(sp)
400004c0:	07c12623          	sw	t3,108(sp)
400004c4:	07d12823          	sw	t4,112(sp)
400004c8:	07e12a23          	sw	t5,116(sp)
400004cc:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
  jal MSYS_EI1_IRQHandler
400004d0:	184020ef          	jal	ra,40002654 <MSYS_EI1_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
  j generic_restore
400004d4:	4440006f          	j	40000918 <generic_restore>

400004d8 <vector_MSYS_EI2_trap_handler>:
vector_MSYS_EI2_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:294

vector_MSYS_EI2_trap_handler:
  STORE_CONTEXT
400004d8:	f8010113          	addi	sp,sp,-128
400004dc:	00112023          	sw	ra,0(sp)
400004e0:	00212223          	sw	sp,4(sp)
400004e4:	00312423          	sw	gp,8(sp)
400004e8:	00412623          	sw	tp,12(sp)
400004ec:	00512823          	sw	t0,16(sp)
400004f0:	00612a23          	sw	t1,20(sp)
400004f4:	00712c23          	sw	t2,24(sp)
400004f8:	00812e23          	sw	s0,28(sp)
400004fc:	02912023          	sw	s1,32(sp)
40000500:	02a12223          	sw	a0,36(sp)
40000504:	02b12423          	sw	a1,40(sp)
40000508:	02c12623          	sw	a2,44(sp)
4000050c:	02d12823          	sw	a3,48(sp)
40000510:	02e12a23          	sw	a4,52(sp)
40000514:	02f12c23          	sw	a5,56(sp)
40000518:	03012e23          	sw	a6,60(sp)
4000051c:	05112023          	sw	a7,64(sp)
40000520:	05212223          	sw	s2,68(sp)
40000524:	05312423          	sw	s3,72(sp)
40000528:	05412623          	sw	s4,76(sp)
4000052c:	05512823          	sw	s5,80(sp)
40000530:	05612a23          	sw	s6,84(sp)
40000534:	05712c23          	sw	s7,88(sp)
40000538:	05812e23          	sw	s8,92(sp)
4000053c:	07912023          	sw	s9,96(sp)
40000540:	07a12223          	sw	s10,100(sp)
40000544:	07b12423          	sw	s11,104(sp)
40000548:	07c12623          	sw	t3,108(sp)
4000054c:	07d12823          	sw	t4,112(sp)
40000550:	07e12a23          	sw	t5,116(sp)
40000554:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
  jal MSYS_EI2_IRQHandler
40000558:	11c020ef          	jal	ra,40002674 <MSYS_EI2_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
  j generic_restore
4000055c:	3bc0006f          	j	40000918 <generic_restore>

40000560 <vector_MSYS_EI3_trap_handler>:
vector_MSYS_EI3_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:299

vector_MSYS_EI3_trap_handler:
  STORE_CONTEXT
40000560:	f8010113          	addi	sp,sp,-128
40000564:	00112023          	sw	ra,0(sp)
40000568:	00212223          	sw	sp,4(sp)
4000056c:	00312423          	sw	gp,8(sp)
40000570:	00412623          	sw	tp,12(sp)
40000574:	00512823          	sw	t0,16(sp)
40000578:	00612a23          	sw	t1,20(sp)
4000057c:	00712c23          	sw	t2,24(sp)
40000580:	00812e23          	sw	s0,28(sp)
40000584:	02912023          	sw	s1,32(sp)
40000588:	02a12223          	sw	a0,36(sp)
4000058c:	02b12423          	sw	a1,40(sp)
40000590:	02c12623          	sw	a2,44(sp)
40000594:	02d12823          	sw	a3,48(sp)
40000598:	02e12a23          	sw	a4,52(sp)
4000059c:	02f12c23          	sw	a5,56(sp)
400005a0:	03012e23          	sw	a6,60(sp)
400005a4:	05112023          	sw	a7,64(sp)
400005a8:	05212223          	sw	s2,68(sp)
400005ac:	05312423          	sw	s3,72(sp)
400005b0:	05412623          	sw	s4,76(sp)
400005b4:	05512823          	sw	s5,80(sp)
400005b8:	05612a23          	sw	s6,84(sp)
400005bc:	05712c23          	sw	s7,88(sp)
400005c0:	05812e23          	sw	s8,92(sp)
400005c4:	07912023          	sw	s9,96(sp)
400005c8:	07a12223          	sw	s10,100(sp)
400005cc:	07b12423          	sw	s11,104(sp)
400005d0:	07c12623          	sw	t3,108(sp)
400005d4:	07d12823          	sw	t4,112(sp)
400005d8:	07e12a23          	sw	t5,116(sp)
400005dc:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
  jal MSYS_EI3_IRQHandler
400005e0:	748000ef          	jal	ra,40000d28 <MSYS_EI3_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
  j generic_restore
400005e4:	3340006f          	j	40000918 <generic_restore>

400005e8 <vector_MSYS_EI4_trap_handler>:
vector_MSYS_EI4_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:304

vector_MSYS_EI4_trap_handler:
  STORE_CONTEXT
400005e8:	f8010113          	addi	sp,sp,-128
400005ec:	00112023          	sw	ra,0(sp)
400005f0:	00212223          	sw	sp,4(sp)
400005f4:	00312423          	sw	gp,8(sp)
400005f8:	00412623          	sw	tp,12(sp)
400005fc:	00512823          	sw	t0,16(sp)
40000600:	00612a23          	sw	t1,20(sp)
40000604:	00712c23          	sw	t2,24(sp)
40000608:	00812e23          	sw	s0,28(sp)
4000060c:	02912023          	sw	s1,32(sp)
40000610:	02a12223          	sw	a0,36(sp)
40000614:	02b12423          	sw	a1,40(sp)
40000618:	02c12623          	sw	a2,44(sp)
4000061c:	02d12823          	sw	a3,48(sp)
40000620:	02e12a23          	sw	a4,52(sp)
40000624:	02f12c23          	sw	a5,56(sp)
40000628:	03012e23          	sw	a6,60(sp)
4000062c:	05112023          	sw	a7,64(sp)
40000630:	05212223          	sw	s2,68(sp)
40000634:	05312423          	sw	s3,72(sp)
40000638:	05412623          	sw	s4,76(sp)
4000063c:	05512823          	sw	s5,80(sp)
40000640:	05612a23          	sw	s6,84(sp)
40000644:	05712c23          	sw	s7,88(sp)
40000648:	05812e23          	sw	s8,92(sp)
4000064c:	07912023          	sw	s9,96(sp)
40000650:	07a12223          	sw	s10,100(sp)
40000654:	07b12423          	sw	s11,104(sp)
40000658:	07c12623          	sw	t3,108(sp)
4000065c:	07d12823          	sw	t4,112(sp)
40000660:	07e12a23          	sw	t5,116(sp)
40000664:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
  jal MSYS_EI4_IRQHandler
40000668:	6c4000ef          	jal	ra,40000d2c <MSYS_EI4_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
  j generic_restore
4000066c:	2ac0006f          	j	40000918 <generic_restore>

40000670 <vector_MSYS_EI5_trap_handler>:
vector_MSYS_EI5_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:309

vector_MSYS_EI5_trap_handler:
  STORE_CONTEXT
40000670:	f8010113          	addi	sp,sp,-128
40000674:	00112023          	sw	ra,0(sp)
40000678:	00212223          	sw	sp,4(sp)
4000067c:	00312423          	sw	gp,8(sp)
40000680:	00412623          	sw	tp,12(sp)
40000684:	00512823          	sw	t0,16(sp)
40000688:	00612a23          	sw	t1,20(sp)
4000068c:	00712c23          	sw	t2,24(sp)
40000690:	00812e23          	sw	s0,28(sp)
40000694:	02912023          	sw	s1,32(sp)
40000698:	02a12223          	sw	a0,36(sp)
4000069c:	02b12423          	sw	a1,40(sp)
400006a0:	02c12623          	sw	a2,44(sp)
400006a4:	02d12823          	sw	a3,48(sp)
400006a8:	02e12a23          	sw	a4,52(sp)
400006ac:	02f12c23          	sw	a5,56(sp)
400006b0:	03012e23          	sw	a6,60(sp)
400006b4:	05112023          	sw	a7,64(sp)
400006b8:	05212223          	sw	s2,68(sp)
400006bc:	05312423          	sw	s3,72(sp)
400006c0:	05412623          	sw	s4,76(sp)
400006c4:	05512823          	sw	s5,80(sp)
400006c8:	05612a23          	sw	s6,84(sp)
400006cc:	05712c23          	sw	s7,88(sp)
400006d0:	05812e23          	sw	s8,92(sp)
400006d4:	07912023          	sw	s9,96(sp)
400006d8:	07a12223          	sw	s10,100(sp)
400006dc:	07b12423          	sw	s11,104(sp)
400006e0:	07c12623          	sw	t3,108(sp)
400006e4:	07d12823          	sw	t4,112(sp)
400006e8:	07e12a23          	sw	t5,116(sp)
400006ec:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
  jal MSYS_EI5_IRQHandler
400006f0:	640000ef          	jal	ra,40000d30 <MSYS_EI5_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
  j generic_restore
400006f4:	2240006f          	j	40000918 <generic_restore>

400006f8 <vector_SUBSYS_IRQHandler>:
vector_SUBSYS_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:314

vector_SUBSYS_IRQHandler:
  STORE_CONTEXT
400006f8:	f8010113          	addi	sp,sp,-128
400006fc:	00112023          	sw	ra,0(sp)
40000700:	00212223          	sw	sp,4(sp)
40000704:	00312423          	sw	gp,8(sp)
40000708:	00412623          	sw	tp,12(sp)
4000070c:	00512823          	sw	t0,16(sp)
40000710:	00612a23          	sw	t1,20(sp)
40000714:	00712c23          	sw	t2,24(sp)
40000718:	00812e23          	sw	s0,28(sp)
4000071c:	02912023          	sw	s1,32(sp)
40000720:	02a12223          	sw	a0,36(sp)
40000724:	02b12423          	sw	a1,40(sp)
40000728:	02c12623          	sw	a2,44(sp)
4000072c:	02d12823          	sw	a3,48(sp)
40000730:	02e12a23          	sw	a4,52(sp)
40000734:	02f12c23          	sw	a5,56(sp)
40000738:	03012e23          	sw	a6,60(sp)
4000073c:	05112023          	sw	a7,64(sp)
40000740:	05212223          	sw	s2,68(sp)
40000744:	05312423          	sw	s3,72(sp)
40000748:	05412623          	sw	s4,76(sp)
4000074c:	05512823          	sw	s5,80(sp)
40000750:	05612a23          	sw	s6,84(sp)
40000754:	05712c23          	sw	s7,88(sp)
40000758:	05812e23          	sw	s8,92(sp)
4000075c:	07912023          	sw	s9,96(sp)
40000760:	07a12223          	sw	s10,100(sp)
40000764:	07b12423          	sw	s11,104(sp)
40000768:	07c12623          	sw	t3,108(sp)
4000076c:	07d12823          	sw	t4,112(sp)
40000770:	07e12a23          	sw	t5,116(sp)
40000774:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
  jal SUBSYS_IRQHandler
40000778:	5ac000ef          	jal	ra,40000d24 <SUBSYS_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
  j generic_restore
4000077c:	19c0006f          	j	40000918 <generic_restore>

40000780 <vector_MSYS_EI6_trap_handler>:
vector_MSYS_EI6_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:320

#ifndef MIV_RV32_V3_0
vector_MSYS_EI6_trap_handler:
  STORE_CONTEXT
40000780:	f8010113          	addi	sp,sp,-128
40000784:	00112023          	sw	ra,0(sp)
40000788:	00212223          	sw	sp,4(sp)
4000078c:	00312423          	sw	gp,8(sp)
40000790:	00412623          	sw	tp,12(sp)
40000794:	00512823          	sw	t0,16(sp)
40000798:	00612a23          	sw	t1,20(sp)
4000079c:	00712c23          	sw	t2,24(sp)
400007a0:	00812e23          	sw	s0,28(sp)
400007a4:	02912023          	sw	s1,32(sp)
400007a8:	02a12223          	sw	a0,36(sp)
400007ac:	02b12423          	sw	a1,40(sp)
400007b0:	02c12623          	sw	a2,44(sp)
400007b4:	02d12823          	sw	a3,48(sp)
400007b8:	02e12a23          	sw	a4,52(sp)
400007bc:	02f12c23          	sw	a5,56(sp)
400007c0:	03012e23          	sw	a6,60(sp)
400007c4:	05112023          	sw	a7,64(sp)
400007c8:	05212223          	sw	s2,68(sp)
400007cc:	05312423          	sw	s3,72(sp)
400007d0:	05412623          	sw	s4,76(sp)
400007d4:	05512823          	sw	s5,80(sp)
400007d8:	05612a23          	sw	s6,84(sp)
400007dc:	05712c23          	sw	s7,88(sp)
400007e0:	05812e23          	sw	s8,92(sp)
400007e4:	07912023          	sw	s9,96(sp)
400007e8:	07a12223          	sw	s10,100(sp)
400007ec:	07b12423          	sw	s11,104(sp)
400007f0:	07c12623          	sw	t3,108(sp)
400007f4:	07d12823          	sw	t4,112(sp)
400007f8:	07e12a23          	sw	t5,116(sp)
400007fc:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
  jal MSYS_EI6_IRQHandler
40000800:	538000ef          	jal	ra,40000d38 <MSYS_EI6_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
  j generic_restore
40000804:	1140006f          	j	40000918 <generic_restore>

40000808 <vector_MSYS_EI7_trap_handler>:
vector_MSYS_EI7_trap_handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:325

vector_MSYS_EI7_trap_handler:
  STORE_CONTEXT
40000808:	f8010113          	addi	sp,sp,-128
4000080c:	00112023          	sw	ra,0(sp)
40000810:	00212223          	sw	sp,4(sp)
40000814:	00312423          	sw	gp,8(sp)
40000818:	00412623          	sw	tp,12(sp)
4000081c:	00512823          	sw	t0,16(sp)
40000820:	00612a23          	sw	t1,20(sp)
40000824:	00712c23          	sw	t2,24(sp)
40000828:	00812e23          	sw	s0,28(sp)
4000082c:	02912023          	sw	s1,32(sp)
40000830:	02a12223          	sw	a0,36(sp)
40000834:	02b12423          	sw	a1,40(sp)
40000838:	02c12623          	sw	a2,44(sp)
4000083c:	02d12823          	sw	a3,48(sp)
40000840:	02e12a23          	sw	a4,52(sp)
40000844:	02f12c23          	sw	a5,56(sp)
40000848:	03012e23          	sw	a6,60(sp)
4000084c:	05112023          	sw	a7,64(sp)
40000850:	05212223          	sw	s2,68(sp)
40000854:	05312423          	sw	s3,72(sp)
40000858:	05412623          	sw	s4,76(sp)
4000085c:	05512823          	sw	s5,80(sp)
40000860:	05612a23          	sw	s6,84(sp)
40000864:	05712c23          	sw	s7,88(sp)
40000868:	05812e23          	sw	s8,92(sp)
4000086c:	07912023          	sw	s9,96(sp)
40000870:	07a12223          	sw	s10,100(sp)
40000874:	07b12423          	sw	s11,104(sp)
40000878:	07c12623          	sw	t3,108(sp)
4000087c:	07d12823          	sw	t4,112(sp)
40000880:	07e12a23          	sw	t5,116(sp)
40000884:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
  jal MSYS_EI7_IRQHandler
40000888:	4b4000ef          	jal	ra,40000d3c <MSYS_EI7_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
  j generic_restore
4000088c:	08c0006f          	j	40000918 <generic_restore>

40000890 <vector_SUBSYSR_IRQHandler>:
vector_SUBSYSR_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:331


vector_SUBSYSR_IRQHandler:
  STORE_CONTEXT
40000890:	f8010113          	addi	sp,sp,-128
40000894:	00112023          	sw	ra,0(sp)
40000898:	00212223          	sw	sp,4(sp)
4000089c:	00312423          	sw	gp,8(sp)
400008a0:	00412623          	sw	tp,12(sp)
400008a4:	00512823          	sw	t0,16(sp)
400008a8:	00612a23          	sw	t1,20(sp)
400008ac:	00712c23          	sw	t2,24(sp)
400008b0:	00812e23          	sw	s0,28(sp)
400008b4:	02912023          	sw	s1,32(sp)
400008b8:	02a12223          	sw	a0,36(sp)
400008bc:	02b12423          	sw	a1,40(sp)
400008c0:	02c12623          	sw	a2,44(sp)
400008c4:	02d12823          	sw	a3,48(sp)
400008c8:	02e12a23          	sw	a4,52(sp)
400008cc:	02f12c23          	sw	a5,56(sp)
400008d0:	03012e23          	sw	a6,60(sp)
400008d4:	05112023          	sw	a7,64(sp)
400008d8:	05212223          	sw	s2,68(sp)
400008dc:	05312423          	sw	s3,72(sp)
400008e0:	05412623          	sw	s4,76(sp)
400008e4:	05512823          	sw	s5,80(sp)
400008e8:	05612a23          	sw	s6,84(sp)
400008ec:	05712c23          	sw	s7,88(sp)
400008f0:	05812e23          	sw	s8,92(sp)
400008f4:	07912023          	sw	s9,96(sp)
400008f8:	07a12223          	sw	s10,100(sp)
400008fc:	07b12423          	sw	s11,104(sp)
40000900:	07c12623          	sw	t3,108(sp)
40000904:	07d12823          	sw	t4,112(sp)
40000908:	07e12a23          	sw	t5,116(sp)
4000090c:	07f12c23          	sw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
  jal SUBSYSR_IRQHandler
40000910:	430000ef          	jal	ra,40000d40 <SUBSYSR_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
  j generic_restore
40000914:	0040006f          	j	40000918 <generic_restore>

40000918 <generic_restore>:
generic_restore():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:339

#endif /*MIV_RV32_V3_0*/
#endif /* MIV_LEGACY_RV32 */

generic_restore:
  LREG x1, 0 * REGBYTES(sp)
40000918:	00012083          	lw	ra,0(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
  LREG x2, 1 * REGBYTES(sp)
4000091c:	00412103          	lw	sp,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
  LREG x3, 2 * REGBYTES(sp)
40000920:	00812183          	lw	gp,8(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
  LREG x4, 3 * REGBYTES(sp)
40000924:	00c12203          	lw	tp,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
  LREG x5, 4 * REGBYTES(sp)
40000928:	01012283          	lw	t0,16(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
  LREG x6, 5 * REGBYTES(sp)
4000092c:	01412303          	lw	t1,20(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
  LREG x7, 6 * REGBYTES(sp)
40000930:	01812383          	lw	t2,24(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
  LREG x8, 7 * REGBYTES(sp)
40000934:	01c12403          	lw	s0,28(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
  LREG x9, 8 * REGBYTES(sp)
40000938:	02012483          	lw	s1,32(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
  LREG x10, 9 * REGBYTES(sp)
4000093c:	02412503          	lw	a0,36(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
  LREG x11, 10 * REGBYTES(sp)
40000940:	02812583          	lw	a1,40(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
  LREG x12, 11 * REGBYTES(sp)
40000944:	02c12603          	lw	a2,44(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
  LREG x13, 12 * REGBYTES(sp)
40000948:	03012683          	lw	a3,48(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
  LREG x14, 13 * REGBYTES(sp)
4000094c:	03412703          	lw	a4,52(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
  LREG x15, 14 * REGBYTES(sp)
40000950:	03812783          	lw	a5,56(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
  LREG x16, 15 * REGBYTES(sp)
40000954:	03c12803          	lw	a6,60(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
  LREG x17, 16 * REGBYTES(sp)
40000958:	04012883          	lw	a7,64(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
  LREG x18, 17 * REGBYTES(sp)
4000095c:	04412903          	lw	s2,68(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
  LREG x19, 18 * REGBYTES(sp)
40000960:	04812983          	lw	s3,72(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
  LREG x20, 19 * REGBYTES(sp)
40000964:	04c12a03          	lw	s4,76(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
  LREG x21, 20 * REGBYTES(sp)
40000968:	05012a83          	lw	s5,80(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
  LREG x22, 21 * REGBYTES(sp)
4000096c:	05412b03          	lw	s6,84(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
  LREG x23, 22 * REGBYTES(sp)
40000970:	05812b83          	lw	s7,88(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
  LREG x24, 23 * REGBYTES(sp)
40000974:	05c12c03          	lw	s8,92(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
  LREG x25, 24 * REGBYTES(sp)
40000978:	06012c83          	lw	s9,96(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
  LREG x26, 25 * REGBYTES(sp)
4000097c:	06412d03          	lw	s10,100(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
  LREG x27, 26 * REGBYTES(sp)
40000980:	06812d83          	lw	s11,104(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
  LREG x28, 27 * REGBYTES(sp)
40000984:	06c12e03          	lw	t3,108(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
  LREG x29, 28 * REGBYTES(sp)
40000988:	07012e83          	lw	t4,112(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
  LREG x30, 29 * REGBYTES(sp)
4000098c:	07412f03          	lw	t5,116(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
  LREG x31, 30 * REGBYTES(sp)
40000990:	07812f83          	lw	t6,120(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:408
  flw	f30, 30 * REGBYTES(sp)
  flw	f31, 31 * REGBYTES(sp)
  #endif /* __riscv_flen */
  #endif /* MIV_FP_CONTEXT_SAVE */

  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
40000994:	08010113          	addi	sp,sp,128
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
  mret
40000998:	30200073          	mret
4000099c:	0000                	unimp
	...

Disassembly of section .text:

400009a0 <handle_reset>:
handle_reset():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:418
/* Ensure instructions are not relaxed, since gp is not yet set */
.option push
.option norelax

#ifndef MIV_RV32_V3_0
  csrwi mstatus, 0
400009a0:	30005073          	csrwi	mstatus,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
  csrwi mie, 0
400009a4:	30405073          	csrwi	mie,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
  la ra, _start
400009a8:	fffff097          	auipc	ra,0xfffff
400009ac:	65808093          	addi	ra,ra,1624 # 40000000 <_start>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:424

/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
#ifndef MIV_LEGACY_RV32
  li t0, MTIMEH_ADDR
400009b0:	0200c2b7          	lui	t0,0x200c
400009b4:	ffc28293          	addi	t0,t0,-4 # 200bffc <STACK_SIZE+0x200b7fc>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
  sw x0, 0(t0)
400009b8:	0002a023          	sw	zero,0(t0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:428
#endif

  csrr t0, misa
400009bc:	301022f3          	csrr	t0,misa
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
  andi t0, t0, A_EXTENSION_MASK
400009c0:	0012f293          	andi	t0,t0,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
400009c4:	02029663          	bnez	t0,400009f0 <ima_cores_setup>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:438
/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
   address + 0x4. Check the mode bits. */
/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
   configured by the user at runtime */

  csrr t0, mtvec
400009c8:	305022f3          	csrr	t0,mtvec
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
  andi t0, t0, MTVEC_MODE_BIT_MASK
400009cc:	0032f293          	andi	t0,t0,3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
  li t1, MTVEC_VECTORED_MODE_VAL
400009d0:	00100313          	li	t1,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
400009d4:	00629e63          	bne	t0,t1,400009f0 <ima_cores_setup>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:445

  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
     Verify that the trap_handler address matches the configuration in MTVEC */
  csrr t0, mtvec
400009d8:	305022f3          	csrr	t0,mtvec
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
  andi t0, t0, 0xFFFFFFFC
400009dc:	ffc2f293          	andi	t0,t0,-4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
  la t1, trap_entry
400009e0:	fffff317          	auipc	t1,0xfffff
400009e4:	62430313          	addi	t1,t1,1572 # 40000004 <trap_entry>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
  bne t0, t1, vector_address_not_matching
400009e8:	04629863          	bne	t0,t1,40000a38 <vector_address_not_matching>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
  j generic_reset_handling
400009ec:	0100006f          	j	400009fc <generic_reset_handling>

400009f0 <ima_cores_setup>:
ima_cores_setup():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:476
  bne t0, t1, vector_address_not_matching
  j generic_reset_handling
#endif /*MIV_RV32_V3_0*/

ima_cores_setup:
  la t0, trap_entry
400009f0:	fffff297          	auipc	t0,0xfffff
400009f4:	61428293          	addi	t0,t0,1556 # 40000004 <trap_entry>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:482

#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
#endif
  csrw mtvec, t0
400009f8:	30529073          	csrw	mtvec,t0

400009fc <generic_reset_handling>:
generic_reset_handling():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:487

generic_reset_handling:
/* Copy sdata section first so that the gp is set and linker relaxation can be
   used */
    la a4, __sdata_load
400009fc:	00002717          	auipc	a4,0x2
40000a00:	3e470713          	addi	a4,a4,996 # 40002de0 <__sdata_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
    la a5, __sdata_start
40000a04:	00002797          	auipc	a5,0x2
40000a08:	3dc78793          	addi	a5,a5,988 # 40002de0 <__sdata_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
    la a6, __sdata_end
40000a0c:	00002817          	auipc	a6,0x2
40000a10:	3e480813          	addi	a6,a6,996 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
    beq a4, a5, 1f     /* Exit if source and dest are same */
40000a14:	00f70863          	beq	a4,a5,40000a24 <generic_reset_handling+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
40000a18:	01078663          	beq	a5,a6,40000a24 <generic_reset_handling+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
    call block_copy
40000a1c:	00000097          	auipc	ra,0x0
40000a20:	094080e7          	jalr	148(ra) # 40000ab0 <block_copy>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:496

1:
  /* initialize global pointer */
  la gp, __global_pointer$
40000a24:	00003197          	auipc	gp,0x3
40000a28:	bbc18193          	addi	gp,gp,-1092 # 400035e0 <__global_pointer$>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:513
  csrw mstatus, t1

  lui t0, 0x0
  fscsr t0
#endif
  call initializations
40000a2c:	010000ef          	jal	ra,40000a3c <initializations>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:515
  /* Initialize stack pointer */
  la sp, __stack_top
40000a30:	25018113          	addi	sp,gp,592 # 40003830 <__stack_top>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:518

  /* Jump into C code */
  j _init
40000a34:	2cc0006f          	j	40000d00 <_init>

40000a38 <vector_address_not_matching>:
vector_address_not_matching():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:523

/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
   as configured in the MIV_RV32 core vectored mode */
vector_address_not_matching:
  ebreak
40000a38:	00100073          	ebreak

40000a3c <initializations>:
initializations():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:527

initializations:
/* Initialize the .bss section */
    mv t0, ra           /* Store ra for future use */
40000a3c:	00008293          	mv	t0,ra
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
    la  a5, __bss_start
40000a40:	83018793          	addi	a5,gp,-2000 # 40002e10 <__sbss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
    la  a6, __bss_end
40000a44:	a5018813          	addi	a6,gp,-1456 # 40003030 <__bss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
    beq a5, a6, 1f     /* Section start and end address are the same */
40000a48:	01078463          	beq	a5,a6,40000a50 <initializations+0x14>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
    call zeroize_block
40000a4c:	044000ef          	jal	ra,40000a90 <zeroize_block>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:535

1:
/* Initialize the .sbss section */
    la  a5, __sbss_start
40000a50:	81018793          	addi	a5,gp,-2032 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
    la  a6, __sbss_end
40000a54:	83018813          	addi	a6,gp,-2000 # 40002e10 <__sbss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
    beq a5, a6, 1f     /* Section start and end address are the same */
40000a58:	01078c63          	beq	a5,a6,40000a70 <initializations+0x34>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
    call zeroize_block
40000a5c:	034000ef          	jal	ra,40000a90 <zeroize_block>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:541

/* Clear heap */
    la  a5, __heap_start
40000a60:	a5018793          	addi	a5,gp,-1456 # 40003030 <__bss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
    la  a6, __heap_end
40000a64:	a5018813          	addi	a6,gp,-1456 # 40003030 <__bss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
    beq a5, a6, 1f     /* Section start and end address are the same */
40000a68:	01078463          	beq	a5,a6,40000a70 <initializations+0x34>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
    call zeroize_block
40000a6c:	024000ef          	jal	ra,40000a90 <zeroize_block>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:548

1:
/* Copy data section */
    la  a4, __data_load
40000a70:	81018713          	addi	a4,gp,-2032 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
    la  a5, __data_start
40000a74:	81018793          	addi	a5,gp,-2032 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
    la  a6, __data_end
40000a78:	81018813          	addi	a6,gp,-2032 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
    beq a4, a5, 1f     /* Exit early if source and dest are same */
40000a7c:	00f70663          	beq	a4,a5,40000a88 <initializations+0x4c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
    beq a5, a6, 1f     /* Section start and end addresses are the same */
40000a80:	01078463          	beq	a5,a6,40000a88 <initializations+0x4c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
    call block_copy
40000a84:	02c000ef          	jal	ra,40000ab0 <block_copy>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:556

1:
    mv ra, t0           /* Retrieve ra */
40000a88:	00028093          	mv	ra,t0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
    ret
40000a8c:	00008067          	ret

40000a90 <zeroize_block>:
zeroize_block():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:560

zeroize_block:
    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
40000a90:	04f86463          	bltu	a6,a5,40000ad8 <block_copy_error>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
    or a7, a6, a5                   /* Check if start or end is unalined */
40000a94:	00f868b3          	or	a7,a6,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
    andi a7, a7, 0x03u
40000a98:	0038f893          	andi	a7,a7,3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
    bgtz a7, block_copy_error       /* Unaligned addresses error*/
40000a9c:	03104e63          	bgtz	a7,40000ad8 <block_copy_error>

40000aa0 <zeroize_loop>:
zeroize_loop():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:565
zeroize_loop:
    sw x0, 0(a5)
40000aa0:	0007a023          	sw	zero,0(a5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
    add a5, a5, __SIZEOF_POINTER__
40000aa4:	00478793          	addi	a5,a5,4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
    blt a5, a6, zeroize_loop
40000aa8:	ff07cce3          	blt	a5,a6,40000aa0 <zeroize_loop>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
    ret
40000aac:	00008067          	ret

40000ab0 <block_copy>:
block_copy():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:571

block_copy:
    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
40000ab0:	02f86463          	bltu	a6,a5,40000ad8 <block_copy_error>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
    or a7, a6, a5                   /* Check if start or end is unalined */
40000ab4:	00f868b3          	or	a7,a6,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
    andi a7, a7, 0x03u
40000ab8:	0038f893          	andi	a7,a7,3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
    bgtz a7, block_copy_error       /* Unaligned addresses error*/
40000abc:	01104e63          	bgtz	a7,40000ad8 <block_copy_error>

40000ac0 <block_copy_loop>:
block_copy_loop():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:576
block_copy_loop:
    lw a7, 0(a4)
40000ac0:	00072883          	lw	a7,0(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
    sw a7, 0(a5)
40000ac4:	0117a023          	sw	a7,0(a5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
    addi a5, a5, 0x04
40000ac8:	00478793          	addi	a5,a5,4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
    addi a4, a4, 0x04
40000acc:	00470713          	addi	a4,a4,4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
    blt a5, a6, block_copy_loop
40000ad0:	ff07c8e3          	blt	a5,a6,40000ac0 <block_copy_loop>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
    j block_copy_exit
40000ad4:	0080006f          	j	40000adc <block_copy_exit>

40000ad8 <block_copy_error>:
block_copy_error():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:584

block_copy_error:
    j block_copy_error
40000ad8:	0000006f          	j	40000ad8 <block_copy_error>

40000adc <block_copy_exit>:
block_copy_exit():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:587

block_copy_exit:
    ret
40000adc:	00008067          	ret

40000ae0 <MRV_systick_config>:
MRV_systick_config():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
 */
uint32_t MRV_systick_config(uint64_t ticks)
{
    uint32_t ret_val = ERROR;
    uint64_t remainder = ticks;
    g_systick_increment = 0U;
40000ae0:	00000693          	li	a3,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
    g_systick_cmp_value = 0U;
40000ae4:	81018793          	addi	a5,gp,-2032 # 40002df0 <__data_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
    g_systick_increment = 0U;
40000ae8:	81818713          	addi	a4,gp,-2024 # 40002df8 <g_systick_increment>
40000aec:	00000613          	li	a2,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
    g_systick_cmp_value = 0U;
40000af0:	00d7a223          	sw	a3,4(a5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
    g_systick_increment = 0U;
40000af4:	00d72223          	sw	a3,4(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
    g_systick_cmp_value = 0U;
40000af8:	00c7a023          	sw	a2,0(a5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
    g_systick_increment = 0U;
40000afc:	00c72023          	sw	a2,0(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:169

    while (remainder >= MTIME_PRESCALER)
40000b00:	00000793          	li	a5,0
40000b04:	00000693          	li	a3,0
40000b08:	00000813          	li	a6,0
40000b0c:	020058b7          	lui	a7,0x2005
40000b10:	00178313          	addi	t1,a5,1
40000b14:	0008ae03          	lw	t3,0(a7) # 2005000 <STACK_SIZE+0x2004800>
40000b18:	00f33633          	sltu	a2,t1,a5
40000b1c:	00d60633          	add	a2,a2,a3
40000b20:	06059663          	bnez	a1,40000b8c <MRV_systick_config+0xac>
40000b24:	07c57463          	bgeu	a0,t3,40000b8c <MRV_systick_config+0xac>
40000b28:	00080663          	beqz	a6,40000b34 <MRV_systick_config+0x54>
40000b2c:	80f1ac23          	sw	a5,-2024(gp) # 40002df8 <g_systick_increment>
40000b30:	80d1ae23          	sw	a3,-2020(gp) # 40002dfc <g_systick_increment+0x4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:175
    {
        remainder -= MTIME_PRESCALER;
        g_systick_increment++;
    }

    g_systick_cmp_value = g_systick_increment + MTIME;
40000b34:	0200c7b7          	lui	a5,0x200c
40000b38:	ff87a783          	lw	a5,-8(a5) # 200bff8 <STACK_SIZE+0x200b7f8>
40000b3c:	00072683          	lw	a3,0(a4)
40000b40:	00472703          	lw	a4,4(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:164
    uint32_t ret_val = ERROR;
40000b44:	00100513          	li	a0,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:175
    g_systick_cmp_value = g_systick_increment + MTIME;
40000b48:	00d78633          	add	a2,a5,a3
40000b4c:	00f637b3          	sltu	a5,a2,a5
40000b50:	00e787b3          	add	a5,a5,a4
40000b54:	80c1a823          	sw	a2,-2032(gp) # 40002df0 <__data_load>
40000b58:	80f1aa23          	sw	a5,-2028(gp) # 40002df4 <__data_load+0x4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177

    if (g_systick_increment > 0U)
40000b5c:	00e6e6b3          	or	a3,a3,a4
40000b60:	02068463          	beqz	a3,40000b88 <MRV_systick_config+0xa8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:179
    {
        WRITE_MTIMECMP(g_systick_cmp_value);
40000b64:	02004737          	lui	a4,0x2004
40000b68:	fff00693          	li	a3,-1
40000b6c:	00d72223          	sw	a3,4(a4) # 2004004 <STACK_SIZE+0x2003804>
40000b70:	00c72023          	sw	a2,0(a4)
40000b74:	00f72223          	sw	a5,4(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:180
        set_csr(mie, MIP_MTIP);
40000b78:	08000793          	li	a5,128
40000b7c:	3047a7f3          	csrrs	a5,mie,a5
MRV_enable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:617
  @return
  This functions returns the CORE_GPR_DED_RESET_REG bit value.
 */
static inline void MRV_enable_interrupts(void)
{
    set_csr(mstatus, MSTATUS_MIE);
40000b80:	300467f3          	csrrsi	a5,mstatus,8
MRV_systick_config():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:182
        MRV_enable_interrupts();
        ret_val = SUCCESS;
40000b84:	00000513          	li	a0,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:186
    }

    return ret_val;
}
40000b88:	00008067          	ret
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:171
        remainder -= MTIME_PRESCALER;
40000b8c:	0008a783          	lw	a5,0(a7)
40000b90:	00100813          	li	a6,1
40000b94:	40f507b3          	sub	a5,a0,a5
40000b98:	00f536b3          	sltu	a3,a0,a5
40000b9c:	40d585b3          	sub	a1,a1,a3
40000ba0:	00078513          	mv	a0,a5
40000ba4:	00060693          	mv	a3,a2
40000ba8:	00030793          	mv	a5,t1
40000bac:	f65ff06f          	j	40000b10 <MRV_systick_config+0x30>

40000bb0 <handle_m_timer_interrupt>:
handle_m_timer_interrupt():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192

/*------------------------------------------------------------------------------
 * RISC-V interrupt handler for machine timer interrupts.
 */
void handle_m_timer_interrupt(void)
{
40000bb0:	ff010113          	addi	sp,sp,-16
40000bb4:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
    clear_csr(mie, MIP_MTIP);
40000bb8:	08000793          	li	a5,128
40000bbc:	3047b7f3          	csrrc	a5,mie,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195

    uint64_t mtime_at_irq = MTIME;
40000bc0:	0200c7b7          	lui	a5,0x200c
40000bc4:	ff87a683          	lw	a3,-8(a5) # 200bff8 <STACK_SIZE+0x200b7f8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201

#ifndef NDEBUG
    static volatile uint32_t d_tick = 0u;
#endif

    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
40000bc8:	81018793          	addi	a5,gp,-2032 # 40002df0 <__data_load>
40000bcc:	0007a703          	lw	a4,0(a5)
40000bd0:	0047a783          	lw	a5,4(a5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
40000bd4:	81818613          	addi	a2,gp,-2024 # 40002df8 <g_systick_increment>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
40000bd8:	00568593          	addi	a1,a3,5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
40000bdc:	00062503          	lw	a0,0(a2)
40000be0:	00462803          	lw	a6,4(a2)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
40000be4:	00d5b6b3          	sltu	a3,a1,a3
40000be8:	00000613          	li	a2,0
40000bec:	04d7e263          	bltu	a5,a3,40000c30 <handle_m_timer_interrupt+0x80>
40000bf0:	00f69463          	bne	a3,a5,40000bf8 <handle_m_timer_interrupt+0x48>
40000bf4:	02b76e63          	bltu	a4,a1,40000c30 <handle_m_timer_interrupt+0x80>
40000bf8:	00060663          	beqz	a2,40000c04 <handle_m_timer_interrupt+0x54>
40000bfc:	80e1a823          	sw	a4,-2032(gp) # 40002df0 <__data_load>
40000c00:	80f1aa23          	sw	a5,-2028(gp) # 40002df4 <__data_load+0x4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
     * If you are running the program using the debugger and halt the CPU at a 
     * breakpoint, MTIME will continue to increment and interrupts will be 
     * missed; resulting in d_tick > 1.
     */

    WRITE_MTIMECMP(g_systick_cmp_value);
40000c04:	020046b7          	lui	a3,0x2004
40000c08:	fff00613          	li	a2,-1
40000c0c:	00c6a223          	sw	a2,4(a3) # 2004004 <STACK_SIZE+0x2003804>
40000c10:	00e6a023          	sw	a4,0(a3)
40000c14:	00f6a223          	sw	a5,4(a3)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225

    SysTick_Handler();
40000c18:	1e5010ef          	jal	ra,400025fc <SysTick_Handler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227

    set_csr(mie, MIP_MTIP);
40000c1c:	08000793          	li	a5,128
40000c20:	3047a7f3          	csrrs	a5,mie,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
}
40000c24:	00c12083          	lw	ra,12(sp)
40000c28:	01010113          	addi	sp,sp,16
40000c2c:	00008067          	ret
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
40000c30:	00a70633          	add	a2,a4,a0
40000c34:	00e638b3          	sltu	a7,a2,a4
40000c38:	010787b3          	add	a5,a5,a6
40000c3c:	00060713          	mv	a4,a2
40000c40:	00f887b3          	add	a5,a7,a5
40000c44:	00100613          	li	a2,1
40000c48:	fa5ff06f          	j	40000bec <handle_m_timer_interrupt+0x3c>

40000c4c <handle_m_soft_interrupt>:
handle_m_soft_interrupt():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231

void handle_m_soft_interrupt(void)
{
40000c4c:	ff010113          	addi	sp,sp,-16
40000c50:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
    Software_IRQHandler();
40000c54:	0b4000ef          	jal	ra,40000d08 <Software_IRQHandler>
MRV_clear_soft_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
{
#ifdef MIV_LEGACY_RV32
    MSIP = 0x00u;   /* clear soft interrupt */
#else
    /* Clear soft IRQ on MIV_RV32 processor */
    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
40000c58:	00006737          	lui	a4,0x6
40000c5c:	02072783          	lw	a5,32(a4) # 6020 <STACK_SIZE+0x5820>
handle_m_soft_interrupt():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
    MRV_clear_soft_irq();
}
40000c60:	00c12083          	lw	ra,12(sp)
MRV_clear_soft_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
40000c64:	ffd7f793          	andi	a5,a5,-3
40000c68:	02f72023          	sw	a5,32(a4)
handle_m_soft_interrupt():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
40000c6c:	01010113          	addi	sp,sp,16
40000c70:	00008067          	ret

40000c74 <handle_local_ei_interrupts>:
handle_local_ei_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
/*------------------------------------------------------------------------------
 * Jump to interrupt table containing local interrupts
 */
void handle_local_ei_interrupts(uint8_t irq_no)
{
    uint64_t mhart_id = read_csr(mhartid);
40000c74:	f14027f3          	csrr	a5,mhartid
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)

    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
40000c78:	ff050513          	addi	a0,a0,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
    (*local_irq_handler_table[ei_no])();
40000c7c:	0ff57513          	andi	a0,a0,255
40000c80:	00251513          	slli	a0,a0,0x2
40000c84:	00002797          	auipc	a5,0x2
40000c88:	0bc78793          	addi	a5,a5,188 # 40002d40 <local_irq_handler_table>
40000c8c:	00a78533          	add	a0,a5,a0
40000c90:	00052303          	lw	t1,0(a0)
40000c94:	00030067          	jr	t1

40000c98 <handle_trap>:
handle_trap():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
 */
void handle_trap(uintptr_t mcause, uintptr_t mepc)
{   
    uint64_t is_interrupt = mcause & MCAUSE_INT;

    if (is_interrupt)
40000c98:	04055a63          	bgez	a0,40000cec <handle_trap+0x54>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
    {
#ifndef MIV_LEGACY_RV32
        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
40000c9c:	800007b7          	lui	a5,0x80000
40000ca0:	ff07c713          	xori	a4,a5,-16
40000ca4:	00e57733          	and	a4,a0,a4
40000ca8:	00070c63          	beqz	a4,40000cc0 <handle_trap+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
40000cac:	fe07c793          	xori	a5,a5,-32
40000cb0:	00f577b3          	and	a5,a0,a5
40000cb4:	00079663          	bnez	a5,40000cc0 <handle_trap+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
        {
            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
40000cb8:	0ff57513          	andi	a0,a0,255
40000cbc:	fb9ff06f          	j	40000c74 <handle_local_ei_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
        }
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
40000cc0:	00151513          	slli	a0,a0,0x1
40000cc4:	00155513          	srli	a0,a0,0x1
40000cc8:	00b00793          	li	a5,11
40000ccc:	00f51463          	bne	a0,a5,40000cd4 <handle_trap+0x3c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
#else
        if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
#endif
        {
#ifndef MIV_LEGACY_RV32
            External_IRQHandler();
40000cd0:	0480006f          	j	40000d18 <External_IRQHandler>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
#else
            handle_m_ext_interrupt();
#endif
        }
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
40000cd4:	00300793          	li	a5,3
40000cd8:	00f51463          	bne	a0,a5,40000ce0 <handle_trap+0x48>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
        {
            handle_m_soft_interrupt();
40000cdc:	f71ff06f          	j	40000c4c <handle_m_soft_interrupt>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
        }
        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
40000ce0:	00700793          	li	a5,7
40000ce4:	00f51c63          	bne	a0,a5,40000cfc <handle_trap+0x64>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
        {
            handle_m_timer_interrupt();
40000ce8:	ec9ff06f          	j	40000bb0 <handle_m_timer_interrupt>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
{   
40000cec:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
         uintptr_t mmepc  = read_csr(mepc);

        /* breakpoint */
        __asm__("ebreak");
#else
        _exit(1 + mcause);
40000cf0:	00150513          	addi	a0,a0,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
{   
40000cf4:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
        _exit(1 + mcause);
40000cf8:	04c000ef          	jal	ra,40000d44 <_exit>
40000cfc:	00008067          	ret

40000d00 <_init>:
_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
    /* This function is a placeholder for the case where some more hardware
     * specific initializations are required before jumping into the application
     * code. You can implement it here. */

    /* Jump to the application code after all initializations are completed */
    main();
40000d00:	4b10106f          	j	400029b0 <main>

40000d04 <_fini>:
_fini():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:34

/* Function called after main() finishes */
void
_fini(void)
{
}
40000d04:	00008067          	ret

40000d08 <Software_IRQHandler>:
Software_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
#ifdef __cplusplus
extern "C" {
#endif

__attribute__((weak)) void Software_IRQHandler(void)
{
40000d08:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
    _exit(10);
40000d0c:	00a00513          	li	a0,10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
{
40000d10:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
    _exit(10);
40000d14:	030000ef          	jal	ra,40000d44 <_exit>

40000d18 <External_IRQHandler>:
External_IRQHandler():
40000d18:	00008067          	ret

40000d1c <MGECI_IRQHandler>:
MGECI_IRQHandler():
40000d1c:	00008067          	ret

40000d20 <MGEUI_IRQHandler>:
MGEUI_IRQHandler():
40000d20:	00008067          	ret

40000d24 <SUBSYS_IRQHandler>:
SUBSYS_IRQHandler():
40000d24:	00008067          	ret

40000d28 <MSYS_EI3_IRQHandler>:
MSYS_EI3_IRQHandler():
40000d28:	00008067          	ret

40000d2c <MSYS_EI4_IRQHandler>:
MSYS_EI4_IRQHandler():
40000d2c:	00008067          	ret

40000d30 <MSYS_EI5_IRQHandler>:
MSYS_EI5_IRQHandler():
40000d30:	00008067          	ret

40000d34 <Reserved_IRQHandler>:
Reserved_IRQHandler():
40000d34:	fd5ff06f          	j	40000d08 <Software_IRQHandler>

40000d38 <MSYS_EI6_IRQHandler>:
MSYS_EI6_IRQHandler():
40000d38:	00008067          	ret

40000d3c <MSYS_EI7_IRQHandler>:
MSYS_EI7_IRQHandler():
40000d3c:	00008067          	ret

40000d40 <SUBSYSR_IRQHandler>:
SUBSYSR_IRQHandler():
40000d40:	00008067          	ret

40000d44 <_exit>:
_exit():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)

    write(STDERR_FILENO, message, strlen(message));
    write_hex(STDERR_FILENO, code);
#endif

    while (1){};
40000d44:	0000006f          	j	40000d44 <_exit>

40000d48 <HAL_enable_interrupts>:
MRV_enable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
  @return
  This functions returns the CORE_GPR_DED_RESET_REG bit value.
 */
static inline void MRV_enable_interrupts(void)
{
    set_csr(mstatus, MSTATUS_MIE);
40000d48:	300467f3          	csrrsi	a5,mstatus,8
HAL_enable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hal_irq.c:24
/*------------------------------------------------------------------------------
 * 
 */
void HAL_enable_interrupts(void) {
    MRV_enable_interrupts();
}
40000d4c:	00008067          	ret

40000d50 <HAL_disable_interrupts>:
HAL_disable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hal_irq.c:31
/*------------------------------------------------------------------------------
 * 
 */
psr_t HAL_disable_interrupts(void) {
    psr_t psr;
    psr = read_csr(mstatus);
40000d50:	30002573          	csrr	a0,mstatus
MRV_disable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:631
  @return
  This functions returns the CORE_GPR_DED_RESET_REG bit value.
 */
static inline void MRV_disable_interrupts(void)
{
    clear_csr(mstatus, MSTATUS_MPIE);
40000d54:	08000793          	li	a5,128
40000d58:	3007b7f3          	csrrc	a5,mstatus,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:632
    clear_csr(mstatus, MSTATUS_MIE);
40000d5c:	300477f3          	csrrci	a5,mstatus,8
HAL_disable_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hal_irq.c:34
    MRV_disable_interrupts();
    return(psr);
}
40000d60:	00008067          	ret

40000d64 <HAL_restore_interrupts>:
HAL_restore_interrupts():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hal_irq.c:40

/*------------------------------------------------------------------------------
 * 
 */
void HAL_restore_interrupts(psr_t saved_psr) {
    write_csr(mstatus, saved_psr);
40000d64:	30051073          	csrw	mstatus,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hal_irq.c:41
}
40000d68:	00008067          	ret

40000d6c <HW_set_32bit_reg>:
HW_set_32bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:39
 *
 * a0:   addr_t reg_addr
 * a1:   uint32_t value
 */
HW_set_32bit_reg:
    sw a1, 0(a0)
40000d6c:	00b52023          	sw	a1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:40
    ret
40000d70:	00008067          	ret

40000d74 <HW_get_32bit_reg>:
HW_get_32bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:51
 * a0:   addr_t reg_addr

 * @return          32 bits value read from the peripheral register.
 */
HW_get_32bit_reg:
    lw a0, 0(a0)
40000d74:	00052503          	lw	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:52
    ret
40000d78:	00008067          	ret

40000d7c <HW_set_32bit_reg_field>:
HW_set_32bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:64
 * a1:   int_fast8_t shift
 * a2:   uint32_t mask
 * a3:   uint32_t value
 */
HW_set_32bit_reg_field:
    mv t3, a3
40000d7c:	00068e13          	mv	t3,a3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:65
    sll t3, t3, a1
40000d80:	00be1e33          	sll	t3,t3,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:66
    and  t3, t3, a2
40000d84:	00ce7e33          	and	t3,t3,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:67
    lw t1, 0(a0)
40000d88:	00052303          	lw	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:68
    mv t2, a2
40000d8c:	00060393          	mv	t2,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:69
    not t2, t2
40000d90:	fff3c393          	not	t2,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:70
    and t1, t1, t2
40000d94:	00737333          	and	t1,t1,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:71
    or t1, t1, t3
40000d98:	01c36333          	or	t1,t1,t3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:72
    sw t1, 0(a0)
40000d9c:	00652023          	sw	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:73
    ret
40000da0:	00008067          	ret

40000da4 <HW_get_32bit_reg_field>:
HW_get_32bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:87
 *
 * @return          32 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_32bit_reg_field:
    lw a0, 0(a0)
40000da4:	00052503          	lw	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:88
    and a0, a0, a2
40000da8:	00c57533          	and	a0,a0,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:89
    srl a0, a0, a1
40000dac:	00b55533          	srl	a0,a0,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:90
    ret
40000db0:	00008067          	ret

40000db4 <HW_set_16bit_reg>:
HW_set_16bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:100
 *
 * a0:   addr_t reg_addr
 * a1:   uint_fast16_t value
 */
HW_set_16bit_reg:
    sh a1, 0(a0)
40000db4:	00b51023          	sh	a1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:101
    ret
40000db8:	00008067          	ret

40000dbc <HW_get_16bit_reg>:
HW_get_16bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:112
 * a0:   addr_t reg_addr

 * @return          16 bits value read from the peripheral register.
 */
HW_get_16bit_reg:
    lh a0, (a0)
40000dbc:	00051503          	lh	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:113
    ret
40000dc0:	00008067          	ret

40000dc4 <HW_set_16bit_reg_field>:
HW_set_16bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:126
 * a2:   uint_fast16_t mask
 * a3:   uint_fast16_t value
 * @param value     Value to be written in the specified field.
 */
HW_set_16bit_reg_field:
    mv t3, a3
40000dc4:	00068e13          	mv	t3,a3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:127
    sll t3, t3, a1
40000dc8:	00be1e33          	sll	t3,t3,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:128
    and  t3, t3, a2
40000dcc:	00ce7e33          	and	t3,t3,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:129
    lh t1, 0(a0)
40000dd0:	00051303          	lh	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:130
    mv t2, a2
40000dd4:	00060393          	mv	t2,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:131
    not t2, t2
40000dd8:	fff3c393          	not	t2,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:132
    and t1, t1, t2
40000ddc:	00737333          	and	t1,t1,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:133
    or t1, t1, t3
40000de0:	01c36333          	or	t1,t1,t3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:134
    sh t1, 0(a0)
40000de4:	00651023          	sh	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:135
    ret
40000de8:	00008067          	ret

40000dec <HW_get_16bit_reg_field>:
HW_get_16bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:149
 *
 * @return          16 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_16bit_reg_field:
    lh a0, 0(a0)
40000dec:	00051503          	lh	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:150
    and a0, a0, a2
40000df0:	00c57533          	and	a0,a0,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:151
    srl a0, a0, a1
40000df4:	00b55533          	srl	a0,a0,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:152
    ret
40000df8:	00008067          	ret

40000dfc <HW_set_8bit_reg>:
HW_set_8bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:162
 *
 * a0:   addr_t reg_addr
 * a1:   uint_fast8_t value
 */
HW_set_8bit_reg:
    sb a1, 0(a0)
40000dfc:	00b50023          	sb	a1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:163
    ret
40000e00:	00008067          	ret

40000e04 <HW_get_8bit_reg>:
HW_get_8bit_reg():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:174
 * a0:   addr_t reg_addr

 * @return          8 bits value read from the peripheral register.
 */
HW_get_8bit_reg:
    lb a0, 0(a0)
40000e04:	00050503          	lb	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:175
    ret
40000e08:	00008067          	ret

40000e0c <HW_set_8bit_reg_field>:
HW_set_8bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:187
 * a1:   int_fast8_t shift
 * a2:   uint_fast8_t mask
 * a3:   uint_fast8_t value
 */
HW_set_8bit_reg_field:
    mv t3, a3
40000e0c:	00068e13          	mv	t3,a3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:188
    sll t3, t3, a1
40000e10:	00be1e33          	sll	t3,t3,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:189
    and  t3, t3, a2
40000e14:	00ce7e33          	and	t3,t3,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:190
    lb t1, 0(a0)
40000e18:	00050303          	lb	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:191
    mv t2, a2
40000e1c:	00060393          	mv	t2,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:192
    not t2, t2
40000e20:	fff3c393          	not	t2,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:193
    and t1, t1, t2
40000e24:	00737333          	and	t1,t1,t2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:194
    or t1, t1, t3
40000e28:	01c36333          	or	t1,t1,t3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:195
    sb t1, 0(a0)
40000e2c:	00650023          	sb	t1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:196
    ret
40000e30:	00008067          	ret

40000e34 <HW_get_8bit_reg_field>:
HW_get_8bit_reg_field():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:210
 *
 * @return          8 bits value containing the register field value specified
 *                  as parameter.
 */
HW_get_8bit_reg_field:
    lb a0, 0(a0)
40000e34:	00050503          	lb	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:211
    and a0, a0, a2
40000e38:	00c57533          	and	a0,a0,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:212
    srl a0, a0, a1
40000e3c:	00b55533          	srl	a0,a0,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/hal/hw_reg_access.S:213
    ret
40000e40:	00008067          	ret

40000e44 <enable_slave_if_required>:
enable_slave_if_required():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:673
{
    /*
     * This function is only called from within the ISR and so does not need
     * guarding on the register access.
     */
    if( 0 != this_i2c->is_slave_enabled )
40000e44:	06054783          	lbu	a5,96(a0)
40000e48:	00078c63          	beqz	a5,40000e60 <enable_slave_if_required+0x1c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:675
    {
        HAL_set_8bit_reg_field( this_i2c->base_address, AA, 0x01u );
40000e4c:	00052503          	lw	a0,0(a0)
40000e50:	00100693          	li	a3,1
40000e54:	00400613          	li	a2,4
40000e58:	00200593          	li	a1,2
40000e5c:	fb1ff06f          	j	40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:677
    }
}
40000e60:	00008067          	ret

40000e64 <I2C_init>:
I2C_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:100
{
40000e64:	fe010113          	addi	sp,sp,-32
40000e68:	00112e23          	sw	ra,28(sp)
40000e6c:	00812c23          	sw	s0,24(sp)
40000e70:	00912a23          	sw	s1,20(sp)
40000e74:	00050413          	mv	s0,a0
40000e78:	01212823          	sw	s2,16(sp)
40000e7c:	01312623          	sw	s3,12(sp)
40000e80:	01412423          	sw	s4,8(sp)
40000e84:	00068493          	mv	s1,a3
40000e88:	00058993          	mv	s3,a1
40000e8c:	00060913          	mv	s2,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:108
    saved_psr = HAL_disable_interrupts();
40000e90:	ec1ff0ef          	jal	ra,40000d50 <HAL_disable_interrupts>
40000e94:	00050a13          	mv	s4,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:116
    memset(this_i2c, 0, sizeof(i2c_instance_t));
40000e98:	06400613          	li	a2,100
40000e9c:	00000593          	li	a1,0
40000ea0:	00840513          	addi	a0,s0,8
40000ea4:	679010ef          	jal	ra,40002d1c <memset>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:126
    this_i2c->ser_address = ((uint_fast8_t)ser_address << 1u);
40000ea8:	00191913          	slli	s2,s2,0x1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:121
    this_i2c->base_address = base_address;
40000eac:	01342023          	sw	s3,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:126
    this_i2c->ser_address = ((uint_fast8_t)ser_address << 1u);
40000eb0:	01242223          	sw	s2,4(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:131
    HAL_set_8bit_reg_field(this_i2c->base_address, ENS1, 0x00); /* Reset I2C hardware. */
40000eb4:	00098513          	mv	a0,s3
40000eb8:	00000693          	li	a3,0
40000ebc:	04000613          	li	a2,64
40000ec0:	00600593          	li	a1,6
40000ec4:	f49ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:132
    HAL_set_8bit_reg_field(this_i2c->base_address, ENS1, 0x01); /* set enable bit */
40000ec8:	00042503          	lw	a0,0(s0)
40000ecc:	00100693          	li	a3,1
40000ed0:	04000613          	li	a2,64
40000ed4:	00600593          	li	a1,6
40000ed8:	f35ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:133
    HAL_set_8bit_reg_field(this_i2c->base_address, CR2, ( (clock_speed >> 2) & 0x01) );
40000edc:	00042503          	lw	a0,0(s0)
40000ee0:	0024d693          	srli	a3,s1,0x2
40000ee4:	0016f693          	andi	a3,a3,1
40000ee8:	08000613          	li	a2,128
40000eec:	00700593          	li	a1,7
40000ef0:	f1dff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:134
    HAL_set_8bit_reg_field(this_i2c->base_address, CR1, ( (clock_speed >> 1) & 0x01) );
40000ef4:	00042503          	lw	a0,0(s0)
40000ef8:	0014d693          	srli	a3,s1,0x1
40000efc:	0016f693          	andi	a3,a3,1
40000f00:	00200613          	li	a2,2
40000f04:	00100593          	li	a1,1
40000f08:	f05ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:135
    HAL_set_8bit_reg_field(this_i2c->base_address, CR0, ( clock_speed & 0x01) );
40000f0c:	00042503          	lw	a0,0(s0)
40000f10:	0014f693          	andi	a3,s1,1
40000f14:	00100613          	li	a2,1
40000f18:	00000593          	li	a1,0
40000f1c:	ef1ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:137
    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS, this_i2c->ser_address);
40000f20:	00042503          	lw	a0,0(s0)
40000f24:	00442583          	lw	a1,4(s0)
40000f28:	00c50513          	addi	a0,a0,12
40000f2c:	ed1ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:138
    HAL_set_8bit_reg(this_i2c->base_address, ADDRESS1, this_i2c->ser_address);
40000f30:	00042503          	lw	a0,0(s0)
40000f34:	00442583          	lw	a1,4(s0)
40000f38:	01c50513          	addi	a0,a0,28
40000f3c:	ec1ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:144
}
40000f40:	01812403          	lw	s0,24(sp)
40000f44:	01c12083          	lw	ra,28(sp)
40000f48:	01412483          	lw	s1,20(sp)
40000f4c:	01012903          	lw	s2,16(sp)
40000f50:	00c12983          	lw	s3,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:143
    HAL_restore_interrupts( saved_psr );
40000f54:	000a0513          	mv	a0,s4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:144
}
40000f58:	00812a03          	lw	s4,8(sp)
40000f5c:	02010113          	addi	sp,sp,32
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:143
    HAL_restore_interrupts( saved_psr );
40000f60:	e05ff06f          	j	40000d64 <HAL_restore_interrupts>

40000f64 <I2C_write>:
I2C_write():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:211
{
40000f64:	fd010113          	addi	sp,sp,-48
40000f68:	02812423          	sw	s0,40(sp)
40000f6c:	02912223          	sw	s1,36(sp)
40000f70:	00050413          	mv	s0,a0
40000f74:	00b12623          	sw	a1,12(sp)
40000f78:	00c12423          	sw	a2,8(sp)
40000f7c:	00d12223          	sw	a3,4(sp)
40000f80:	00e12023          	sw	a4,0(sp)
40000f84:	02112623          	sw	ra,44(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:215
    saved_psr = HAL_disable_interrupts();
40000f88:	dc9ff0ef          	jal	ra,40000d50 <HAL_disable_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:218
    if( this_i2c->transaction == NO_TRANSACTION)
40000f8c:	00c44783          	lbu	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:215
    saved_psr = HAL_disable_interrupts();
40000f90:	00050493          	mv	s1,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:218
    if( this_i2c->transaction == NO_TRANSACTION)
40000f94:	00012703          	lw	a4,0(sp)
40000f98:	00412683          	lw	a3,4(sp)
40000f9c:	00812603          	lw	a2,8(sp)
40000fa0:	00c12583          	lw	a1,12(sp)
40000fa4:	00079663          	bnez	a5,40000fb0 <I2C_write+0x4c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:220
      this_i2c->transaction = MASTER_WRITE_TRANSACTION;
40000fa8:	00100793          	li	a5,1
40000fac:	00f40623          	sb	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:224
    this_i2c->pending_transaction = MASTER_WRITE_TRANSACTION ;
40000fb0:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:234
    this_i2c->master_status = I2C_IN_PROGRESS;
40000fb4:	02f42a23          	sw	a5,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:235
    this_i2c->options = options;
40000fb8:	00e40a23          	sb	a4,20(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:237
    if(I2C_IN_PROGRESS == this_i2c->slave_status)
40000fbc:	05442703          	lw	a4,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:227
    this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
40000fc0:	00159593          	slli	a1,a1,0x1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:224
    this_i2c->pending_transaction = MASTER_WRITE_TRANSACTION ;
40000fc4:	06f40523          	sb	a5,106(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:227
    this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
40000fc8:	00b42423          	sw	a1,8(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:228
    this_i2c->dir = WRITE_DIR;
40000fcc:	02042223          	sw	zero,36(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:229
    this_i2c->master_tx_buffer = write_buffer;
40000fd0:	00c42c23          	sw	a2,24(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:230
    this_i2c->master_tx_size = write_size;
40000fd4:	00d42e23          	sw	a3,28(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:231
    this_i2c->master_tx_idx = 0u;
40000fd8:	02042023          	sw	zero,32(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:237
    if(I2C_IN_PROGRESS == this_i2c->slave_status)
40000fdc:	06f71263          	bne	a4,a5,40001040 <I2C_write+0xdc>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:239
        this_i2c->is_transaction_pending = 1u;
40000fe0:	06e404a3          	sb	a4,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:251
    if ( I2C_HOLD_BUS == this_i2c->bus_status )
40000fe4:	06844703          	lbu	a4,104(s0)
40000fe8:	00100793          	li	a5,1
40000fec:	00f71c63          	bne	a4,a5,40001004 <I2C_write+0xa0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:253
        HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
40000ff0:	00042503          	lw	a0,0(s0)
40000ff4:	00000693          	li	a3,0
40000ff8:	00800613          	li	a2,8
40000ffc:	00300593          	li	a1,3
40001000:	e0dff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:256
    stat_ctrl = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
40001004:	00042503          	lw	a0,0(s0)
40001008:	00450513          	addi	a0,a0,4
4000100c:	df9ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
40001010:	00a10fa3          	sb	a0,31(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:257
    stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
40001014:	01f14783          	lbu	a5,31(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:260
    I2C_enable_irq( this_i2c );
40001018:	00040513          	mv	a0,s0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:257
    stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
4000101c:	0ff7f793          	andi	a5,a5,255
40001020:	00f10fa3          	sb	a5,31(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:260
    I2C_enable_irq( this_i2c );
40001024:	7d0000ef          	jal	ra,400017f4 <I2C_enable_irq>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:263
}
40001028:	02812403          	lw	s0,40(sp)
4000102c:	02c12083          	lw	ra,44(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:262
    HAL_restore_interrupts( saved_psr );
40001030:	00048513          	mv	a0,s1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:263
}
40001034:	02412483          	lw	s1,36(sp)
40001038:	03010113          	addi	sp,sp,48
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:262
    HAL_restore_interrupts( saved_psr );
4000103c:	d29ff06f          	j	40000d64 <HAL_restore_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:243
        HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
40001040:	00042503          	lw	a0,0(s0)
40001044:	00100693          	li	a3,1
40001048:	02000613          	li	a2,32
4000104c:	00500593          	li	a1,5
40001050:	dbdff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
40001054:	f91ff06f          	j	40000fe4 <I2C_write+0x80>

40001058 <I2C_write_read>:
I2C_write_read():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:353
    this_i2c->master_status = I2C_FAILED;
40001058:	00200893          	li	a7,2
4000105c:	03152a23          	sw	a7,52(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:355
    if((read_size > 0u) && (offset_size > 0u))
40001060:	12078a63          	beqz	a5,40001194 <I2C_write_read+0x13c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:355 (discriminator 1)
40001064:	12068863          	beqz	a3,40001194 <I2C_write_read+0x13c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:347
{
40001068:	fc010113          	addi	sp,sp,-64
4000106c:	02812c23          	sw	s0,56(sp)
40001070:	02912a23          	sw	s1,52(sp)
40001074:	03212823          	sw	s2,48(sp)
40001078:	03312623          	sw	s3,44(sp)
4000107c:	03412423          	sw	s4,40(sp)
40001080:	03512223          	sw	s5,36(sp)
40001084:	03612023          	sw	s6,32(sp)
40001088:	01712e23          	sw	s7,28(sp)
4000108c:	00078913          	mv	s2,a5
40001090:	00050413          	mv	s0,a0
40001094:	02112e23          	sw	ra,60(sp)
40001098:	00080a13          	mv	s4,a6
4000109c:	00070a93          	mv	s5,a4
400010a0:	00068993          	mv	s3,a3
400010a4:	00060b13          	mv	s6,a2
400010a8:	00058493          	mv	s1,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:360
        saved_psr = HAL_disable_interrupts();
400010ac:	ca5ff0ef          	jal	ra,40000d50 <HAL_disable_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:363
        if( this_i2c->transaction == NO_TRANSACTION)
400010b0:	00c44783          	lbu	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:360
        saved_psr = HAL_disable_interrupts();
400010b4:	00050b93          	mv	s7,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:363
        if( this_i2c->transaction == NO_TRANSACTION)
400010b8:	00079663          	bnez	a5,400010c4 <I2C_write_read+0x6c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:365
            this_i2c->transaction = MASTER_RANDOM_READ_TRANSACTION;
400010bc:	00300793          	li	a5,3
400010c0:	00f40623          	sb	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:385
        this_i2c->master_status = I2C_IN_PROGRESS;
400010c4:	00100713          	li	a4,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:369
        this_i2c->pending_transaction = MASTER_RANDOM_READ_TRANSACTION ;
400010c8:	00300793          	li	a5,3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:385
        this_i2c->master_status = I2C_IN_PROGRESS;
400010cc:	02e42a23          	sw	a4,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:369
        this_i2c->pending_transaction = MASTER_RANDOM_READ_TRANSACTION ;
400010d0:	06f40523          	sb	a5,106(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:388
        if(I2C_IN_PROGRESS == this_i2c->slave_status)
400010d4:	05442783          	lw	a5,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:372
        this_i2c->target_addr = (uint_fast8_t)serial_addr << 1u;
400010d8:	00149593          	slli	a1,s1,0x1
400010dc:	00b42423          	sw	a1,8(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:374
        this_i2c->dir = WRITE_DIR;
400010e0:	02042223          	sw	zero,36(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:376
        this_i2c->master_tx_buffer = addr_offset;
400010e4:	01642c23          	sw	s6,24(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:377
        this_i2c->master_tx_size = offset_size;
400010e8:	01342e23          	sw	s3,28(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:378
        this_i2c->master_tx_idx = 0u;
400010ec:	02042023          	sw	zero,32(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:380
        this_i2c->master_rx_buffer = read_buffer;
400010f0:	03542423          	sw	s5,40(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:381
        this_i2c->master_rx_size = read_size;
400010f4:	03242623          	sw	s2,44(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:382
        this_i2c->master_rx_idx = 0u;
400010f8:	02042823          	sw	zero,48(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:386
        this_i2c->options = options;
400010fc:	01440a23          	sb	s4,20(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:388
        if(I2C_IN_PROGRESS == this_i2c->slave_status)
40001100:	06e79e63          	bne	a5,a4,4000117c <I2C_write_read+0x124>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:390
            this_i2c->is_transaction_pending = 1u;
40001104:	06f404a3          	sb	a5,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:402
        if ( I2C_HOLD_BUS == this_i2c->bus_status )
40001108:	06844703          	lbu	a4,104(s0)
4000110c:	00100793          	li	a5,1
40001110:	00f71c63          	bne	a4,a5,40001128 <I2C_write_read+0xd0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:404
            HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
40001114:	00042503          	lw	a0,0(s0)
40001118:	00000693          	li	a3,0
4000111c:	00800613          	li	a2,8
40001120:	00300593          	li	a1,3
40001124:	ce9ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:407
        stat_ctrl = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
40001128:	00042503          	lw	a0,0(s0)
4000112c:	00450513          	addi	a0,a0,4
40001130:	cd5ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
40001134:	00a107a3          	sb	a0,15(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:408
        stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
40001138:	00f14783          	lbu	a5,15(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:411
        I2C_enable_irq( this_i2c );
4000113c:	00040513          	mv	a0,s0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:408
        stat_ctrl = stat_ctrl;  /* Avoids lint warning. */
40001140:	0ff7f793          	andi	a5,a5,255
40001144:	00f107a3          	sb	a5,15(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:411
        I2C_enable_irq( this_i2c );
40001148:	6ac000ef          	jal	ra,400017f4 <I2C_enable_irq>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:415
}
4000114c:	03812403          	lw	s0,56(sp)
40001150:	03c12083          	lw	ra,60(sp)
40001154:	03412483          	lw	s1,52(sp)
40001158:	03012903          	lw	s2,48(sp)
4000115c:	02c12983          	lw	s3,44(sp)
40001160:	02812a03          	lw	s4,40(sp)
40001164:	02412a83          	lw	s5,36(sp)
40001168:	02012b03          	lw	s6,32(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:413
        HAL_restore_interrupts( saved_psr );
4000116c:	000b8513          	mv	a0,s7
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:415
}
40001170:	01c12b83          	lw	s7,28(sp)
40001174:	04010113          	addi	sp,sp,64
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:413
        HAL_restore_interrupts( saved_psr );
40001178:	bedff06f          	j	40000d64 <HAL_restore_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:394
            HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
4000117c:	00042503          	lw	a0,0(s0)
40001180:	00100693          	li	a3,1
40001184:	02000613          	li	a2,32
40001188:	00500593          	li	a1,5
4000118c:	c81ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
40001190:	f79ff06f          	j	40001108 <I2C_write_read+0xb0>
40001194:	00008067          	ret

40001198 <I2C_wait_complete>:
I2C_wait_complete():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:442
{
40001198:	fe010113          	addi	sp,sp,-32
4000119c:	00112e23          	sw	ra,28(sp)
400011a0:	00812c23          	sw	s0,24(sp)
400011a4:	00b12623          	sw	a1,12(sp)
400011a8:	00050413          	mv	s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:451
    saved_psr = HAL_disable_interrupts();
400011ac:	ba5ff0ef          	jal	ra,40000d50 <HAL_disable_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:452
    this_i2c->master_timeout_ms = timeout_ms;
400011b0:	00c12583          	lw	a1,12(sp)
400011b4:	02b42c23          	sw	a1,56(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:453
    HAL_restore_interrupts( saved_psr );
400011b8:	badff0ef          	jal	ra,40000d64 <HAL_restore_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:458
    } while(I2C_IN_PROGRESS == i2c_status);
400011bc:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:457 (discriminator 1)
        i2c_status = this_i2c->master_status;
400011c0:	03442503          	lw	a0,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:458 (discriminator 1)
    } while(I2C_IN_PROGRESS == i2c_status);
400011c4:	fef50ee3          	beq	a0,a5,400011c0 <I2C_wait_complete+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:460
}
400011c8:	01c12083          	lw	ra,28(sp)
400011cc:	01812403          	lw	s0,24(sp)
400011d0:	02010113          	addi	sp,sp,32
400011d4:	00008067          	ret

400011d8 <I2C_isr>:
I2C_isr():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:772
 */
void I2C_isr
(
    i2c_instance_t * this_i2c
)
{
400011d8:	fe010113          	addi	sp,sp,-32
400011dc:	00812c23          	sw	s0,24(sp)
400011e0:	00050413          	mv	s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:778
    volatile uint8_t status;
    uint8_t data;
    uint8_t hold_bus;
    uint8_t clear_irq = 1u;

    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
400011e4:	00052503          	lw	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:772
{
400011e8:	00112e23          	sw	ra,28(sp)
400011ec:	00912a23          	sw	s1,20(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:778
    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
400011f0:	00450513          	addi	a0,a0,4
400011f4:	c11ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
400011f8:	00a107a3          	sb	a0,15(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    
    switch( status )
400011fc:	00f14783          	lbu	a5,15(sp)
40001200:	07000713          	li	a4,112
40001204:	0ff7f793          	andi	a5,a5,255
40001208:	4ae78863          	beq	a5,a4,400016b8 <I2C_isr+0x4e0>
4000120c:	14f76263          	bltu	a4,a5,40001350 <I2C_isr+0x178>
40001210:	03800713          	li	a4,56
40001214:	34e78e63          	beq	a5,a4,40001570 <I2C_isr+0x398>
40001218:	0af76463          	bltu	a4,a5,400012c0 <I2C_isr+0xe8>
4000121c:	01800713          	li	a4,24
40001220:	30e78663          	beq	a5,a4,4000152c <I2C_isr+0x354>
40001224:	04f76c63          	bltu	a4,a5,4000127c <I2C_isr+0xa4>
40001228:	00800713          	li	a4,8
4000122c:	26e78e63          	beq	a5,a4,400014a8 <I2C_isr+0x2d0>
40001230:	01000713          	li	a4,16
40001234:	26e78a63          	beq	a5,a4,400014a8 <I2C_isr+0x2d0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1205
        case ST_RESET_ACTIVATED:
        case ST_BUS_ERROR: /* Bus error during MST or selected slave modes */
        default:
            /* Some undefined state has encountered. Clear Start bit to make
             * sure, next good transaction happen */
            HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
40001238:	00042503          	lw	a0,0(s0)
4000123c:	00000693          	li	a3,0
40001240:	02000613          	li	a2,32
40001244:	00500593          	li	a1,5
40001248:	bc5ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1219
             */
            this_i2c->slave_tx_idx = 0u;
            /*
             * Clear statuses to I2C_FAILED only if there was an operation in progress.
             */
            if(I2C_IN_PROGRESS == this_i2c->master_status)
4000124c:	03442703          	lw	a4,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1210
            this_i2c->transaction = NO_TRANSACTION;
40001250:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1215
            this_i2c->slave_tx_idx = 0u;
40001254:	04042223          	sw	zero,68(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1219
            if(I2C_IN_PROGRESS == this_i2c->master_status)
40001258:	00100793          	li	a5,1
4000125c:	00f71663          	bne	a4,a5,40001268 <I2C_isr+0x90>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1221
            {
                this_i2c->master_status = I2C_FAILED;
40001260:	00200793          	li	a5,2
40001264:	02f42a23          	sw	a5,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1224
            }

            if(I2C_IN_PROGRESS == this_i2c->slave_status)
40001268:	05442703          	lw	a4,84(s0)
4000126c:	00100793          	li	a5,1
40001270:	28f71e63          	bne	a4,a5,4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1226
            {
                this_i2c->slave_status = I2C_FAILED;
40001274:	00200793          	li	a5,2
40001278:	4840006f          	j	400016fc <I2C_isr+0x524>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    switch( status )
4000127c:	02800713          	li	a4,40
40001280:	2ae78663          	beq	a5,a4,4000152c <I2C_isr+0x354>
40001284:	03000713          	li	a4,48
40001288:	00042503          	lw	a0,0(s0)
4000128c:	00e78663          	beq	a5,a4,40001298 <I2C_isr+0xc0>
40001290:	02000713          	li	a4,32
40001294:	fae792e3          	bne	a5,a4,40001238 <I2C_isr+0x60>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:917
            HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);
40001298:	00100693          	li	a3,1
4000129c:	01000613          	li	a2,16
400012a0:	00400593          	li	a1,4
400012a4:	b69ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:918
            this_i2c->master_status = I2C_FAILED;
400012a8:	00200793          	li	a5,2
400012ac:	02f42a23          	sw	a5,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:924
            this_i2c->transaction = NO_TRANSACTION;
400012b0:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1132
            enable_slave_if_required(this_i2c); /* Make sure AA is set correctly */
400012b4:	00040513          	mv	a0,s0
400012b8:	b8dff0ef          	jal	ra,40000e44 <enable_slave_if_required>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
            }

            break;
    }
    
    if ( clear_irq )
400012bc:	2500006f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    switch( status )
400012c0:	05000713          	li	a4,80
400012c4:	00042503          	lw	a0,0(s0)
400012c8:	36e78e63          	beq	a5,a4,40001644 <I2C_isr+0x46c>
400012cc:	00f76a63          	bltu	a4,a5,400012e0 <I2C_isr+0x108>
400012d0:	04000713          	li	a4,64
400012d4:	30e78e63          	beq	a5,a4,400015f0 <I2C_isr+0x418>
400012d8:	04800713          	li	a4,72
400012dc:	fb9ff06f          	j	40001294 <I2C_isr+0xbc>
400012e0:	06000713          	li	a4,96
400012e4:	3ce78a63          	beq	a5,a4,400016b8 <I2C_isr+0x4e0>
400012e8:	06800713          	li	a4,104
400012ec:	3ce78263          	beq	a5,a4,400016b0 <I2C_isr+0x4d8>
400012f0:	05800713          	li	a4,88
400012f4:	f4e792e3          	bne	a5,a4,40001238 <I2C_isr+0x60>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:941
            this_i2c->master_rx_buffer[this_i2c->master_rx_idx] = HAL_get_8bit_reg(this_i2c->base_address, DATA);
400012f8:	03042783          	lw	a5,48(s0)
400012fc:	02842483          	lw	s1,40(s0)
40001300:	00850513          	addi	a0,a0,8
40001304:	00f484b3          	add	s1,s1,a5
40001308:	afdff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
4000130c:	00a48023          	sb	a0,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:943
            hold_bus = this_i2c->options & I2C_HOLD_BUS; 
40001310:	01444783          	lbu	a5,20(s0)
40001314:	0017f793          	andi	a5,a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:946
            this_i2c->bus_status  = hold_bus;
40001318:	06f40423          	sb	a5,104(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:947
            if ( hold_bus == 0u )
4000131c:	34079e63          	bnez	a5,40001678 <I2C_isr+0x4a0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:949
                HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);  /*xmt stop condition */
40001320:	00042503          	lw	a0,0(s0)
40001324:	00100693          	li	a3,1
40001328:	01000613          	li	a2,16
4000132c:	00400593          	li	a1,4
40001330:	addff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:952
                   enable_slave_if_required(this_i2c);
40001334:	00040513          	mv	a0,s0
40001338:	b0dff0ef          	jal	ra,40000e44 <enable_slave_if_required>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:776
    uint8_t clear_irq = 1u;
4000133c:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:963
            this_i2c->transaction = NO_TRANSACTION;
40001340:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:964
            this_i2c->master_status = I2C_SUCCESS;
40001344:	02042a23          	sw	zero,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001348:	1c079263          	bnez	a5,4000150c <I2C_isr+0x334>
4000134c:	2800006f          	j	400015cc <I2C_isr+0x3f4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    switch( status )
40001350:	0a800713          	li	a4,168
40001354:	06e78e63          	beq	a5,a4,400013d0 <I2C_isr+0x1f8>
40001358:	04f76e63          	bltu	a4,a5,400013b4 <I2C_isr+0x1dc>
4000135c:	08800713          	li	a4,136
40001360:	32e78463          	beq	a5,a4,40001688 <I2C_isr+0x4b0>
40001364:	02f76c63          	bltu	a4,a5,4000139c <I2C_isr+0x1c4>
40001368:	07800713          	li	a4,120
4000136c:	34e78263          	beq	a5,a4,400016b0 <I2C_isr+0x4d8>
40001370:	08000713          	li	a4,128
40001374:	ece792e3          	bne	a5,a4,40001238 <I2C_isr+0x60>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1015
            if((this_i2c->slave_rx_buffer != (uint8_t *)0)
40001378:	04842783          	lw	a5,72(s0)
4000137c:	3a078e63          	beqz	a5,40001738 <I2C_isr+0x560>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1016
               && (this_i2c->slave_rx_idx < this_i2c->slave_rx_size))
40001380:	05042703          	lw	a4,80(s0)
40001384:	04c42783          	lw	a5,76(s0)
40001388:	36f76e63          	bltu	a4,a5,40001704 <I2C_isr+0x52c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1037
                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u); 
4000138c:	00000693          	li	a3,0
40001390:	00400613          	li	a2,4
40001394:	00200593          	li	a1,2
40001398:	1e40006f          	j	4000157c <I2C_isr+0x3a4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    switch( status )
4000139c:	09800713          	li	a4,152
400013a0:	2ee78463          	beq	a5,a4,40001688 <I2C_isr+0x4b0>
400013a4:	0a000713          	li	a4,160
400013a8:	38e78e63          	beq	a5,a4,40001744 <I2C_isr+0x56c>
400013ac:	09000713          	li	a4,144
400013b0:	fc5ff06f          	j	40001374 <I2C_isr+0x19c>
400013b4:	0c000713          	li	a4,192
400013b8:	0ce78a63          	beq	a5,a4,4000148c <I2C_isr+0x2b4>
400013bc:	0af76c63          	bltu	a4,a5,40001474 <I2C_isr+0x29c>
400013c0:	0b000713          	li	a4,176
400013c4:	00e78663          	beq	a5,a4,400013d0 <I2C_isr+0x1f8>
400013c8:	0b800713          	li	a4,184
400013cc:	e6e796e3          	bne	a5,a4,40001238 <I2C_isr+0x60>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1140
            if ( status == ST_SLAVE_SLAR_ACK )
400013d0:	00f14783          	lbu	a5,15(sp)
400013d4:	0a800713          	li	a4,168
400013d8:	04f71263          	bne	a4,a5,4000141c <I2C_isr+0x244>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1148
                if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
400013dc:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1142
                this_i2c->transaction = READ_SLAVE_TRANSACTION;
400013e0:	00500793          	li	a5,5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1144
                this_i2c->slave_status = I2C_IN_PROGRESS;
400013e4:	00100493          	li	s1,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1142
                this_i2c->transaction = READ_SLAVE_TRANSACTION;
400013e8:	00f40623          	sb	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1143
                this_i2c->random_read_addr = 0u;
400013ec:	00042823          	sw	zero,16(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1144
                this_i2c->slave_status = I2C_IN_PROGRESS;
400013f0:	04942a23          	sw	s1,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1148
                if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
400013f4:	02000613          	li	a2,32
400013f8:	00500593          	li	a1,5
400013fc:	a39ff0ef          	jal	ra,40000e34 <HW_get_8bit_reg_field>
40001400:	00050e63          	beqz	a0,4000141c <I2C_isr+0x244>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1150
                    HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
40001404:	00042503          	lw	a0,0(s0)
40001408:	00000693          	li	a3,0
4000140c:	02000613          	li	a2,32
40001410:	00500593          	li	a1,5
40001414:	9f9ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1151
                    this_i2c->is_transaction_pending = 1u;
40001418:	069404a3          	sb	s1,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1154
            if (this_i2c->slave_tx_idx >= this_i2c->slave_tx_size)
4000141c:	00042503          	lw	a0,0(s0)
40001420:	04442703          	lw	a4,68(s0)
40001424:	04042783          	lw	a5,64(s0)
40001428:	00850513          	addi	a0,a0,8
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1158
                HAL_set_8bit_reg(this_i2c->base_address, DATA, 0xFFu);
4000142c:	0ff00593          	li	a1,255
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1154
            if (this_i2c->slave_tx_idx >= this_i2c->slave_tx_size)
40001430:	00f77c63          	bgeu	a4,a5,40001448 <I2C_isr+0x270>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1163
                HAL_set_8bit_reg(this_i2c->base_address, DATA, (uint_fast8_t)this_i2c->slave_tx_buffer[this_i2c->slave_tx_idx++]);
40001434:	03c42783          	lw	a5,60(s0)
40001438:	00170693          	addi	a3,a4,1
4000143c:	04d42223          	sw	a3,68(s0)
40001440:	00e787b3          	add	a5,a5,a4
40001444:	0007c583          	lbu	a1,0(a5) # 80000000 <__stack_top+0x3fffc7d0>
40001448:	9b5ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1166
            if (this_i2c->slave_tx_idx >= this_i2c->slave_tx_size) /* last byte? */
4000144c:	04442703          	lw	a4,68(s0)
40001450:	04042783          	lw	a5,64(s0)
40001454:	0af76c63          	bltu	a4,a5,4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1168
                 HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u); 
40001458:	00042503          	lw	a0,0(s0)
4000145c:	00000693          	li	a3,0
40001460:	00400613          	li	a2,4
40001464:	00200593          	li	a1,2
40001468:	9a5ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1171
                this_i2c->slave_tx_idx = 0u;
4000146c:	04042223          	sw	zero,68(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001470:	09c0006f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:780
    switch( status )
40001474:	0d800713          	li	a4,216
40001478:	34e78e63          	beq	a5,a4,400017d4 <I2C_isr+0x5fc>
4000147c:	0e000713          	li	a4,224
40001480:	08e78663          	beq	a5,a4,4000150c <I2C_isr+0x334>
40001484:	0c800713          	li	a4,200
40001488:	dae798e3          	bne	a5,a4,40001238 <I2C_isr+0x60>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1180
            this_i2c->slave_tx_idx = 0u;
4000148c:	04042223          	sw	zero,68(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1181
            HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u); 
40001490:	00042503          	lw	a0,0(s0)
40001494:	00100693          	li	a3,1
40001498:	00400613          	li	a2,4
4000149c:	00200593          	li	a1,2
400014a0:	96dff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1184
            this_i2c->slave_status = I2C_SUCCESS;
400014a4:	3040006f          	j	400017a8 <I2C_isr+0x5d0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:786
            HAL_set_8bit_reg_field( this_i2c->base_address, STA, 0x00u);
400014a8:	00042503          	lw	a0,0(s0)
400014ac:	00000693          	li	a3,0
400014b0:	02000613          	li	a2,32
400014b4:	00500593          	li	a1,5
400014b8:	955ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:787
            HAL_set_8bit_reg( this_i2c->base_address, DATA, this_i2c->target_addr); /* write call address */
400014bc:	00042503          	lw	a0,0(s0)
400014c0:	00842583          	lw	a1,8(s0)
400014c4:	00850513          	addi	a0,a0,8
400014c8:	935ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:788
            HAL_set_8bit_reg_field( this_i2c->base_address, DIR, this_i2c->dir); /* set direction bit */
400014cc:	00042503          	lw	a0,0(s0)
400014d0:	02442683          	lw	a3,36(s0)
400014d4:	00100613          	li	a2,1
400014d8:	00000593          	li	a1,0
400014dc:	00850513          	addi	a0,a0,8
400014e0:	92dff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:789
            if(this_i2c->dir == WRITE_DIR)
400014e4:	02442783          	lw	a5,36(s0)
400014e8:	02079e63          	bnez	a5,40001524 <I2C_isr+0x34c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:791
                 this_i2c->master_tx_idx = 0u;
400014ec:	02042023          	sw	zero,32(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:803
            if(this_i2c->is_transaction_pending)
400014f0:	06944783          	lbu	a5,105(s0)
400014f4:	00078463          	beqz	a5,400014fc <I2C_isr+0x324>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:805
                this_i2c->is_transaction_pending = 0u;
400014f8:	060404a3          	sb	zero,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:812
            if(this_i2c->transaction != this_i2c->pending_transaction)
400014fc:	06a44783          	lbu	a5,106(s0)
40001500:	00c44703          	lbu	a4,12(s0)
40001504:	00f70463          	beq	a4,a5,4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:814
                this_i2c->transaction = this_i2c->pending_transaction;
40001508:	00f40623          	sb	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1235
    {
        /* clear interrupt. */
        HAL_set_8bit_reg_field(this_i2c->base_address, SI, 0x00u);
4000150c:	00042503          	lw	a0,0(s0)
40001510:	00000693          	li	a3,0
40001514:	00800613          	li	a2,8
40001518:	00300593          	li	a1,3
4000151c:	8f1ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
40001520:	0ac0006f          	j	400015cc <I2C_isr+0x3f4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:795
                 this_i2c->master_rx_idx = 0u;
40001524:	02042823          	sw	zero,48(s0)
40001528:	fc9ff06f          	j	400014f0 <I2C_isr+0x318>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:839
            if (this_i2c->master_tx_idx < this_i2c->master_tx_size)
4000152c:	02042703          	lw	a4,32(s0)
40001530:	01c42783          	lw	a5,28(s0)
40001534:	02f77463          	bgeu	a4,a5,4000155c <I2C_isr+0x384>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:841
                HAL_set_8bit_reg(this_i2c->base_address, DATA, (uint_fast8_t)this_i2c->master_tx_buffer[this_i2c->master_tx_idx++]);
40001538:	01842783          	lw	a5,24(s0)
4000153c:	00170693          	addi	a3,a4,1
40001540:	00042503          	lw	a0,0(s0)
40001544:	02d42023          	sw	a3,32(s0)
40001548:	00e787b3          	add	a5,a5,a4
4000154c:	0007c583          	lbu	a1,0(a5)
40001550:	00850513          	addi	a0,a0,8
40001554:	8a9ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001558:	fb5ff06f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:843
            else if ( this_i2c->transaction == MASTER_RANDOM_READ_TRANSACTION )
4000155c:	00c44703          	lbu	a4,12(s0)
40001560:	00300793          	li	a5,3
40001564:	02f71263          	bne	a4,a5,40001588 <I2C_isr+0x3b0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:847
                 this_i2c->dir = READ_DIR;
40001568:	00100793          	li	a5,1
4000156c:	02f42223          	sw	a5,36(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:848
                 HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
40001570:	00100693          	li	a3,1
40001574:	02000613          	li	a2,32
40001578:	00500593          	li	a1,5
4000157c:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:905
                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u);
40001580:	88dff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001584:	f89ff06f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:857
                hold_bus = this_i2c->options & I2C_HOLD_BUS;
40001588:	01444783          	lbu	a5,20(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:856
                this_i2c->transaction = NO_TRANSACTION;
4000158c:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:857
                hold_bus = this_i2c->options & I2C_HOLD_BUS;
40001590:	0017f793          	andi	a5,a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:860
                this_i2c->bus_status  = hold_bus;
40001594:	06f40423          	sb	a5,104(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:861
                if ( hold_bus == 0u )
40001598:	02079463          	bnez	a5,400015c0 <I2C_isr+0x3e8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:863
                    HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);  /*xmt stop condition */
4000159c:	00042503          	lw	a0,0(s0)
400015a0:	00100693          	li	a3,1
400015a4:	01000613          	li	a2,16
400015a8:	00400593          	li	a1,4
400015ac:	861ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:864
                    enable_slave_if_required(this_i2c);
400015b0:	00040513          	mv	a0,s0
400015b4:	891ff0ef          	jal	ra,40000e44 <enable_slave_if_required>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:871
                this_i2c->master_status = I2C_SUCCESS;
400015b8:	02042a23          	sw	zero,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
400015bc:	f51ff06f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:868
                    I2C_disable_irq( this_i2c );
400015c0:	00040513          	mv	a0,s0
400015c4:	264000ef          	jal	ra,40001828 <I2C_disable_irq>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:871
                this_i2c->master_status = I2C_SUCCESS;
400015c8:	02042a23          	sw	zero,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1240
    }
    
    /* Read the status register to ensure the last I2C registers write took place
     * in a system built around a bus making use of posted writes. */
    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
400015cc:	00042503          	lw	a0,0(s0)
400015d0:	00450513          	addi	a0,a0,4
400015d4:	831ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1241
}
400015d8:	01c12083          	lw	ra,28(sp)
400015dc:	01812403          	lw	s0,24(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1240
    status = HAL_get_8bit_reg( this_i2c->base_address, STATUS);
400015e0:	00a107a3          	sb	a0,15(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1241
}
400015e4:	01412483          	lw	s1,20(sp)
400015e8:	02010113          	addi	sp,sp,32
400015ec:	00008067          	ret
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:899
            if(this_i2c->master_rx_size > 1u)
400015f0:	02c42703          	lw	a4,44(s0)
400015f4:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:901
                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
400015f8:	00100693          	li	a3,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:899
            if(this_i2c->master_rx_size > 1u)
400015fc:	00e7e663          	bltu	a5,a4,40001608 <I2C_isr+0x430>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:903
            else if(1u == this_i2c->master_rx_size)
40001600:	00f71a63          	bne	a4,a5,40001614 <I2C_isr+0x43c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:905
                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x00u);
40001604:	00000693          	li	a3,0
40001608:	00400613          	li	a2,4
4000160c:	00200593          	li	a1,2
40001610:	f71ff06f          	j	40001580 <I2C_isr+0x3a8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:909
                HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
40001614:	00100693          	li	a3,1
40001618:	00400613          	li	a2,4
4000161c:	00200593          	li	a1,2
40001620:	fecff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:910
                HAL_set_8bit_reg_field(this_i2c->base_address, STO, 0x01u);
40001624:	00042503          	lw	a0,0(s0)
40001628:	00100693          	li	a3,1
4000162c:	01000613          	li	a2,16
40001630:	00400593          	li	a1,4
40001634:	fd8ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:911
                this_i2c->master_status = I2C_SUCCESS;
40001638:	02042a23          	sw	zero,52(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1109
            this_i2c->transaction = NO_TRANSACTION;
4000163c:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001640:	ecdff06f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:930
            this_i2c->master_rx_buffer[this_i2c->master_rx_idx++] = HAL_get_8bit_reg(this_i2c->base_address, DATA);
40001644:	03042783          	lw	a5,48(s0)
40001648:	02842483          	lw	s1,40(s0)
4000164c:	00850513          	addi	a0,a0,8
40001650:	00178713          	addi	a4,a5,1
40001654:	02e42823          	sw	a4,48(s0)
40001658:	00f484b3          	add	s1,s1,a5
4000165c:	fa8ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
40001660:	00a48023          	sb	a0,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:931
            if( this_i2c->master_rx_idx >= (this_i2c->master_rx_size - 1u))
40001664:	02c42783          	lw	a5,44(s0)
40001668:	03042703          	lw	a4,48(s0)
4000166c:	fff78793          	addi	a5,a5,-1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1034
            if(this_i2c->slave_rx_idx >= this_i2c->slave_rx_size)
40001670:	e8f76ee3          	bltu	a4,a5,4000150c <I2C_isr+0x334>
40001674:	d19ff06f          	j	4000138c <I2C_isr+0x1b4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:956
                I2C_disable_irq( this_i2c );
40001678:	00040513          	mv	a0,s0
4000167c:	1ac000ef          	jal	ra,40001828 <I2C_disable_irq>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:957
                clear_irq = 0u;
40001680:	00000793          	li	a5,0
40001684:	cbdff06f          	j	40001340 <I2C_isr+0x168>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:970
            HAL_set_8bit_reg_field(this_i2c->base_address, AA, 0x01u);
40001688:	00042503          	lw	a0,0(s0)
4000168c:	00100693          	li	a3,1
40001690:	00400613          	li	a2,4
40001694:	00200593          	li	a1,2
40001698:	f74ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:976
            if(this_i2c->is_transaction_pending)
4000169c:	06944783          	lbu	a5,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:972
            this_i2c->transaction = NO_TRANSACTION;
400016a0:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:973
            this_i2c->slave_status = I2C_SUCCESS;
400016a4:	04042a23          	sw	zero,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:976
            if(this_i2c->is_transaction_pending)
400016a8:	e60782e3          	beqz	a5,4000150c <I2C_isr+0x334>
400016ac:	ec5ff06f          	j	40001570 <I2C_isr+0x398>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:988
            this_i2c->is_transaction_pending = 1u;
400016b0:	00100793          	li	a5,1
400016b4:	06f404a3          	sb	a5,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1000
            if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
400016b8:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:993
            this_i2c->transaction = WRITE_SLAVE_TRANSACTION;
400016bc:	00400793          	li	a5,4
400016c0:	00f40623          	sb	a5,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:994
            this_i2c->slave_rx_idx = 0u;
400016c4:	04042823          	sw	zero,80(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:995
            this_i2c->random_read_addr = 0u;
400016c8:	00042823          	sw	zero,16(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1000
            if(HAL_get_8bit_reg_field(this_i2c->base_address, STA))
400016cc:	02000613          	li	a2,32
400016d0:	00500593          	li	a1,5
400016d4:	f60ff0ef          	jal	ra,40000e34 <HW_get_8bit_reg_field>
400016d8:	02050063          	beqz	a0,400016f8 <I2C_isr+0x520>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1002
                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x00u);
400016dc:	00042503          	lw	a0,0(s0)
400016e0:	00000693          	li	a3,0
400016e4:	02000613          	li	a2,32
400016e8:	00500593          	li	a1,5
400016ec:	f20ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1003
                this_i2c->is_transaction_pending = 1u;
400016f0:	00100793          	li	a5,1
400016f4:	06f404a3          	sb	a5,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1005
            this_i2c->slave_status = I2C_IN_PROGRESS;
400016f8:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1226
                this_i2c->slave_status = I2C_FAILED;
400016fc:	04f42a23          	sw	a5,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1232
    if ( clear_irq )
40001700:	e0dff06f          	j	4000150c <I2C_isr+0x334>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1018
                data = HAL_get_8bit_reg(this_i2c->base_address, DATA);
40001704:	00042503          	lw	a0,0(s0)
40001708:	00850513          	addi	a0,a0,8
4000170c:	ef8ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1019
                this_i2c->slave_rx_buffer[this_i2c->slave_rx_idx++] = data;
40001710:	05042783          	lw	a5,80(s0)
40001714:	04842703          	lw	a4,72(s0)
40001718:	00178693          	addi	a3,a5,1
4000171c:	00f70733          	add	a4,a4,a5
40001720:	04d42823          	sw	a3,80(s0)
40001724:	00a70023          	sb	a0,0(a4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1028
                    this_i2c->random_read_addr = (this_i2c->random_read_addr << 8) + data;
40001728:	01042783          	lw	a5,16(s0)
4000172c:	00879793          	slli	a5,a5,0x8
40001730:	00a787b3          	add	a5,a5,a0
40001734:	00f42823          	sw	a5,16(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1034
            if(this_i2c->slave_rx_idx >= this_i2c->slave_rx_size)
40001738:	05042703          	lw	a4,80(s0)
4000173c:	04c42783          	lw	a5,76(s0)
40001740:	f31ff06f          	j	40001670 <I2C_isr+0x498>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1047
            if ( this_i2c->transaction == WRITE_SLAVE_TRANSACTION )
40001744:	00c44703          	lbu	a4,12(s0)
40001748:	00400793          	li	a5,4
4000174c:	08f71063          	bne	a4,a5,400017cc <I2C_isr+0x5f4>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1049
                if ( this_i2c->slave_rx_idx == this_i2c->slave_mem_offset_length )
40001750:	05042603          	lw	a2,80(s0)
40001754:	05842783          	lw	a5,88(s0)
40001758:	00f61663          	bne	a2,a5,40001764 <I2C_isr+0x58c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1051
                    this_i2c->slave_tx_idx = this_i2c->random_read_addr;
4000175c:	01042783          	lw	a5,16(s0)
40001760:	04f42223          	sw	a5,68(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1054
                if ( this_i2c->slave_write_handler != 0u )
40001764:	05c42783          	lw	a5,92(s0)
40001768:	d20784e3          	beqz	a5,40001490 <I2C_isr+0x2b8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1057
                    h_ret = this_i2c->slave_write_handler( this_i2c, this_i2c->slave_rx_buffer, (uint16_t)this_i2c->slave_rx_idx );
4000176c:	04842583          	lw	a1,72(s0)
40001770:	01061613          	slli	a2,a2,0x10
40001774:	01065613          	srli	a2,a2,0x10
40001778:	00040513          	mv	a0,s0
4000177c:	000780e7          	jalr	a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1058
                    if ( I2C_REENABLE_SLAVE_RX == h_ret )
40001780:	00051863          	bnez	a0,40001790 <I2C_isr+0x5b8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1093
                enable_slave_if_required(this_i2c);
40001784:	00040513          	mv	a0,s0
40001788:	ebcff0ef          	jal	ra,40000e44 <enable_slave_if_required>
4000178c:	01c0006f          	j	400017a8 <I2C_isr+0x5d0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1068
                        HAL_set_8bit_reg_field( this_i2c->base_address, AA, 0x0u );
40001790:	00042503          	lw	a0,0(s0)
40001794:	00000693          	li	a3,0
40001798:	00400613          	li	a2,4
4000179c:	00200593          	li	a1,2
400017a0:	e6cff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1072
                        this_i2c->is_slave_enabled = 0u;
400017a4:	06040023          	sb	zero,96(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1100
            if(this_i2c->is_transaction_pending)
400017a8:	06944783          	lbu	a5,105(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1097
            this_i2c->slave_status = I2C_SUCCESS;
400017ac:	04042a23          	sw	zero,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1100
            if(this_i2c->is_transaction_pending)
400017b0:	e80786e3          	beqz	a5,4000163c <I2C_isr+0x464>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1102
                HAL_set_8bit_reg_field(this_i2c->base_address, STA, 0x01u);
400017b4:	00042503          	lw	a0,0(s0)
400017b8:	00100693          	li	a3,1
400017bc:	02000613          	li	a2,32
400017c0:	00500593          	li	a1,5
400017c4:	e48ff0ef          	jal	ra,40000e0c <HW_set_8bit_reg_field>
400017c8:	e75ff06f          	j	4000163c <I2C_isr+0x464>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1087
                this_i2c->slave_tx_idx = 0u;
400017cc:	04042223          	sw	zero,68(s0)
400017d0:	fb5ff06f          	j	40001784 <I2C_isr+0x5ac>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1127
            if(I2C_IN_PROGRESS == this_i2c->slave_status)
400017d4:	05442703          	lw	a4,84(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1118
            this_i2c->transaction = NO_TRANSACTION;
400017d8:	00040623          	sb	zero,12(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1123
            this_i2c->slave_tx_idx = 0u;
400017dc:	04042223          	sw	zero,68(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1127
            if(I2C_IN_PROGRESS == this_i2c->slave_status)
400017e0:	00100793          	li	a5,1
400017e4:	acf718e3          	bne	a4,a5,400012b4 <I2C_isr+0xdc>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.c:1129
                this_i2c->slave_status = I2C_FAILED;
400017e8:	00200793          	li	a5,2
400017ec:	04f42a23          	sw	a5,84(s0)
400017f0:	ac5ff06f          	j	400012b4 <I2C_isr+0xdc>

400017f4 <I2C_enable_irq>:
I2C_enable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:23
 * This function must be modified to enable interrupts generated from the
 * CoreI2C instance identified as parameter.
 */
void I2C_enable_irq( i2c_instance_t * this_i2c )
{
    if(this_i2c == &g_i2c_instance_cam2)
400017f4:	95418793          	addi	a5,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
400017f8:	00f51663          	bne	a0,a5,40001804 <I2C_enable_irq+0x10>
MRV_enable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
    set_csr(mie, mask);
400017fc:	010007b7          	lui	a5,0x1000
40001800:	3047a7f3          	csrrs	a5,mie,a5
I2C_enable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:28
    {
        MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
    }

    if(this_i2c == &g_i2c_instance_hdmi)
40001804:	8bc18793          	addi	a5,gp,-1860 # 40002e9c <g_i2c_instance_hdmi>
40001808:	00f51663          	bne	a0,a5,40001814 <I2C_enable_irq+0x20>
MRV_enable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
4000180c:	020007b7          	lui	a5,0x2000
40001810:	3047a7f3          	csrrs	a5,mie,a5
I2C_enable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:33
    {
        MRV_enable_local_irq(MRV32_MSYS_EIE1_IRQn);
    }

    if(this_i2c == &g_i2c_instance_cam1)
40001814:	9d818793          	addi	a5,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
40001818:	00f51663          	bne	a0,a5,40001824 <I2C_enable_irq+0x30>
MRV_enable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
4000181c:	040007b7          	lui	a5,0x4000
40001820:	3047a7f3          	csrrs	a5,mie,a5
I2C_enable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:37
       {
           MRV_enable_local_irq(MRV32_MSYS_EIE2_IRQn);
       }
}
40001824:	00008067          	ret

40001828 <I2C_disable_irq>:
I2C_disable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:45
 * This function must be modified to disable interrupts generated from the
 * CoreI2C instance identified as parameter.
 */
void I2C_disable_irq( i2c_instance_t * this_i2c )
{
    if(this_i2c == &g_i2c_instance_cam2)
40001828:	95418793          	addi	a5,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
4000182c:	00f51663          	bne	a0,a5,40001838 <I2C_disable_irq+0x10>
MRV_disable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:601
    clear_csr(mie, mask);
40001830:	010007b7          	lui	a5,0x1000
40001834:	3047b7f3          	csrrc	a5,mie,a5
I2C_disable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:50
    {
        MRV_disable_local_irq(MRV32_MSYS_EIE0_IRQn);
    }

    if(this_i2c == &g_i2c_instance_hdmi)
40001838:	8bc18793          	addi	a5,gp,-1860 # 40002e9c <g_i2c_instance_hdmi>
4000183c:	00f51663          	bne	a0,a5,40001848 <I2C_disable_irq+0x20>
MRV_disable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:601
40001840:	020007b7          	lui	a5,0x2000
40001844:	3047b7f3          	csrrc	a5,mie,a5
I2C_disable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:55
    {
        MRV_disable_local_irq(MRV32_MSYS_EIE1_IRQn);
    }

    if(this_i2c == &g_i2c_instance_cam1)
40001848:	9d818793          	addi	a5,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
4000184c:	00f51663          	bne	a0,a5,40001858 <I2C_disable_irq+0x30>
MRV_disable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:601
40001850:	040007b7          	lui	a5,0x4000
40001854:	3047b7f3          	csrrc	a5,mie,a5
I2C_disable_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c:60
    {
        MRV_disable_local_irq(MRV32_MSYS_EIE2_IRQn);
    }

}
40001858:	00008067          	ret

4000185c <GPIO_init>:
GPIO_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
(
    gpio_instance_t *   this_gpio,
    addr_t              base_addr,
    gpio_apb_width_t    bus_width
)
{
4000185c:	ff010113          	addi	sp,sp,-16
40001860:	00812423          	sw	s0,8(sp)
40001864:	00050413          	mv	s0,a0
40001868:	00912223          	sw	s1,4(sp)
4000186c:	01212023          	sw	s2,0(sp)
40001870:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
    uint8_t i = 0;
    addr_t cfg_reg_addr = base_addr;
    
    this_gpio->base_addr = base_addr;
40001874:	00b42023          	sw	a1,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
{
40001878:	00058493          	mv	s1,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
    this_gpio->apb_bus_width = bus_width;
4000187c:	00c52223          	sw	a2,4(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
    
    /* Clear configuration. */
    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
40001880:	08058913          	addi	s2,a1,128
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
    {
        HW_set_8bit_reg( cfg_reg_addr, 0 );
40001884:	00048513          	mv	a0,s1
40001888:	00000593          	li	a1,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
        cfg_reg_addr += 4;
4000188c:	00448493          	addi	s1,s1,4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
        HW_set_8bit_reg( cfg_reg_addr, 0 );
40001890:	d6cff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
40001894:	ff2498e3          	bne	s1,s2,40001884 <GPIO_init+0x28>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
    }
    /* Clear any pending interrupts */
    switch( this_gpio->apb_bus_width )
40001898:	00442783          	lw	a5,4(s0)
4000189c:	00100713          	li	a4,1
400018a0:	02e78a63          	beq	a5,a4,400018d4 <GPIO_init+0x78>
400018a4:	06078463          	beqz	a5,4000190c <GPIO_init+0xb0>
400018a8:	00200713          	li	a4,2
400018ac:	0ae79a63          	bne	a5,a4,40001960 <GPIO_init+0x104>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
    {
        case GPIO_APB_32_BITS_BUS:
            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
400018b0:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
            
        default:
            HAL_ASSERT(0);
            break;
    }
}
400018b4:	00812403          	lw	s0,8(sp)
400018b8:	00c12083          	lw	ra,12(sp)
400018bc:	00412483          	lw	s1,4(sp)
400018c0:	00012903          	lw	s2,0(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
400018c4:	fff00593          	li	a1,-1
400018c8:	08050513          	addi	a0,a0,128
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
400018cc:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
400018d0:	c9cff06f          	j	40000d6c <HW_set_32bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
400018d4:	00042503          	lw	a0,0(s0)
400018d8:	000104b7          	lui	s1,0x10
400018dc:	fff48593          	addi	a1,s1,-1 # ffff <STACK_SIZE+0xf7ff>
400018e0:	08050513          	addi	a0,a0,128
400018e4:	cd0ff0ef          	jal	ra,40000db4 <HW_set_16bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
400018e8:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
400018ec:	00812403          	lw	s0,8(sp)
400018f0:	00c12083          	lw	ra,12(sp)
400018f4:	00012903          	lw	s2,0(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
400018f8:	fff48593          	addi	a1,s1,-1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
400018fc:	00412483          	lw	s1,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
40001900:	08450513          	addi	a0,a0,132
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
40001904:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
40001908:	cacff06f          	j	40000db4 <HW_set_16bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
4000190c:	00042503          	lw	a0,0(s0)
40001910:	0ff00593          	li	a1,255
40001914:	08050513          	addi	a0,a0,128
40001918:	ce4ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
4000191c:	00042503          	lw	a0,0(s0)
40001920:	0ff00593          	li	a1,255
40001924:	08450513          	addi	a0,a0,132
40001928:	cd4ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
4000192c:	00042503          	lw	a0,0(s0)
40001930:	0ff00593          	li	a1,255
40001934:	08850513          	addi	a0,a0,136
40001938:	cc4ff0ef          	jal	ra,40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
4000193c:	00042503          	lw	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
40001940:	00812403          	lw	s0,8(sp)
40001944:	00c12083          	lw	ra,12(sp)
40001948:	00412483          	lw	s1,4(sp)
4000194c:	00012903          	lw	s2,0(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
40001950:	0ff00593          	li	a1,255
40001954:	08c50513          	addi	a0,a0,140
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
40001958:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
4000195c:	ca0ff06f          	j	40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
}
40001960:	00c12083          	lw	ra,12(sp)
40001964:	00812403          	lw	s0,8(sp)
40001968:	00412483          	lw	s1,4(sp)
4000196c:	00012903          	lw	s2,0(sp)
40001970:	01010113          	addi	sp,sp,16
40001974:	00008067          	ret

40001978 <GPIO_set_output>:
GPIO_set_output():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:232
(
    gpio_instance_t *   this_gpio,
    gpio_id_t           port_id,
    uint8_t             value
)
{
40001978:	fe010113          	addi	sp,sp,-32
4000197c:	00912a23          	sw	s1,20(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:236
    HAL_ASSERT( port_id < NB_OF_GPIO );
    
            
    switch( this_gpio->apb_bus_width )
40001980:	00452483          	lw	s1,4(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:232
{
40001984:	00812c23          	sw	s0,24(sp)
40001988:	01212823          	sw	s2,16(sp)
4000198c:	01312623          	sw	s3,12(sp)
40001990:	01512223          	sw	s5,4(sp)
40001994:	00112e23          	sw	ra,28(sp)
40001998:	01412423          	sw	s4,8(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:236
    switch( this_gpio->apb_bus_width )
4000199c:	00100413          	li	s0,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:232
{
400019a0:	00050a93          	mv	s5,a0
400019a4:	00058913          	mv	s2,a1
400019a8:	00060993          	mv	s3,a2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:236
    switch( this_gpio->apb_bus_width )
400019ac:	04848e63          	beq	s1,s0,40001a08 <GPIO_set_output+0x90>
400019b0:	0c048463          	beqz	s1,40001a78 <GPIO_set_output+0x100>
400019b4:	00200793          	li	a5,2
400019b8:	12f49663          	bne	s1,a5,40001ae4 <GPIO_set_output+0x16c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:242
    {
        case GPIO_APB_32_BITS_BUS:
            {
                uint32_t outputs_state;
                
                outputs_state = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
400019bc:	00052503          	lw	a0,0(a0)
400019c0:	01241433          	sll	s0,s0,s2
400019c4:	0a050513          	addi	a0,a0,160
400019c8:	bacff0ef          	jal	ra,40000d74 <HW_get_32bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:249
                {
                    outputs_state &= ~(1 << port_id);
                }
                else
                {
                    outputs_state |= 1 << port_id;
400019cc:	00a465b3          	or	a1,s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:243
                if ( 0 == value )
400019d0:	00099663          	bnez	s3,400019dc <GPIO_set_output+0x64>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:245
                    outputs_state &= ~(1 << port_id);
400019d4:	fff44413          	not	s0,s0
400019d8:	00a475b3          	and	a1,s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:251
                }
                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
400019dc:	000aa503          	lw	a0,0(s5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
            
        default:
            HAL_ASSERT(0);
            break;
    }
}
400019e0:	01812403          	lw	s0,24(sp)
400019e4:	01c12083          	lw	ra,28(sp)
400019e8:	01412483          	lw	s1,20(sp)
400019ec:	01012903          	lw	s2,16(sp)
400019f0:	00c12983          	lw	s3,12(sp)
400019f4:	00812a03          	lw	s4,8(sp)
400019f8:	00412a83          	lw	s5,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:251
                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
400019fc:	0a050513          	addi	a0,a0,160
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001a00:	02010113          	addi	sp,sp,32
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:251
                HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, outputs_state );
40001a04:	b68ff06f          	j	40000d6c <HW_set_32bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:267
                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 4) * 4);
40001a08:	00052783          	lw	a5,0(a0)
40001a0c:	0045da13          	srli	s4,a1,0x4
40001a10:	002a1a13          	slli	s4,s4,0x2
40001a14:	0a0a0a13          	addi	s4,s4,160
40001a18:	00f97413          	andi	s0,s2,15
40001a1c:	00fa0a33          	add	s4,s4,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:269
                outputs_state = HW_get_16bit_reg( gpio_out_reg_addr );
40001a20:	008494b3          	sll	s1,s1,s0
40001a24:	000a0513          	mv	a0,s4
40001a28:	01049493          	slli	s1,s1,0x10
40001a2c:	b90ff0ef          	jal	ra,40000dbc <HW_get_16bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:270
                if ( 0 == value )
40001a30:	4104d493          	srai	s1,s1,0x10
40001a34:	02099e63          	bnez	s3,40001a70 <GPIO_set_output+0xf8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:272
                    outputs_state &= ~(1 << (port_id & 0x0F));
40001a38:	fff4c493          	not	s1,s1
40001a3c:	00a4f4b3          	and	s1,s1,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001a40:	01812403          	lw	s0,24(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:276
                    outputs_state |= 1 << (port_id & 0x0F);
40001a44:	01049593          	slli	a1,s1,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001a48:	01c12083          	lw	ra,28(sp)
40001a4c:	01412483          	lw	s1,20(sp)
40001a50:	01012903          	lw	s2,16(sp)
40001a54:	00c12983          	lw	s3,12(sp)
40001a58:	00412a83          	lw	s5,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:278
                HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
40001a5c:	000a0513          	mv	a0,s4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001a60:	00812a03          	lw	s4,8(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:276
                    outputs_state |= 1 << (port_id & 0x0F);
40001a64:	0105d593          	srli	a1,a1,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001a68:	02010113          	addi	sp,sp,32
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:278
                HW_set_16bit_reg( gpio_out_reg_addr, outputs_state );
40001a6c:	b48ff06f          	j	40000db4 <HW_set_16bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:276
                    outputs_state |= 1 << (port_id & 0x0F);
40001a70:	00a4e4b3          	or	s1,s1,a0
40001a74:	fcdff06f          	j	40001a40 <GPIO_set_output+0xc8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:294
                uint32_t gpio_out_reg_addr = this_gpio->base_addr + GPIO_OUT_REG_OFFSET + ((port_id >> 3) * 4);
40001a78:	00052783          	lw	a5,0(a0)
40001a7c:	0035d493          	srli	s1,a1,0x3
40001a80:	00249493          	slli	s1,s1,0x2
40001a84:	0a048493          	addi	s1,s1,160
40001a88:	00797913          	andi	s2,s2,7
40001a8c:	00f484b3          	add	s1,s1,a5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:296
                outputs_state = HW_get_8bit_reg( gpio_out_reg_addr );
40001a90:	01241433          	sll	s0,s0,s2
40001a94:	00048513          	mv	a0,s1
40001a98:	01841413          	slli	s0,s0,0x18
40001a9c:	b68ff0ef          	jal	ra,40000e04 <HW_get_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:297
                if ( 0 == value )
40001aa0:	41845413          	srai	s0,s0,0x18
40001aa4:	02099c63          	bnez	s3,40001adc <GPIO_set_output+0x164>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:299
                    outputs_state &= ~(1 << (port_id & 0x07));
40001aa8:	fff44413          	not	s0,s0
40001aac:	00a47433          	and	s0,s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:303
                    outputs_state |= 1 << (port_id & 0x07);
40001ab0:	0ff47593          	andi	a1,s0,255
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001ab4:	01812403          	lw	s0,24(sp)
40001ab8:	01c12083          	lw	ra,28(sp)
40001abc:	01012903          	lw	s2,16(sp)
40001ac0:	00c12983          	lw	s3,12(sp)
40001ac4:	00812a03          	lw	s4,8(sp)
40001ac8:	00412a83          	lw	s5,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:305
                HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
40001acc:	00048513          	mv	a0,s1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001ad0:	01412483          	lw	s1,20(sp)
40001ad4:	02010113          	addi	sp,sp,32
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:305
                HW_set_8bit_reg( gpio_out_reg_addr, outputs_state );
40001ad8:	b24ff06f          	j	40000dfc <HW_set_8bit_reg>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:303
                    outputs_state |= 1 << (port_id & 0x07);
40001adc:	00a46433          	or	s0,s0,a0
40001ae0:	fd1ff06f          	j	40001ab0 <GPIO_set_output+0x138>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:322
}
40001ae4:	01c12083          	lw	ra,28(sp)
40001ae8:	01812403          	lw	s0,24(sp)
40001aec:	01412483          	lw	s1,20(sp)
40001af0:	01012903          	lw	s2,16(sp)
40001af4:	00c12983          	lw	s3,12(sp)
40001af8:	00812a03          	lw	s4,8(sp)
40001afc:	00412a83          	lw	s5,4(sp)
40001b00:	02010113          	addi	sp,sp,32
40001b04:	00008067          	ret

40001b08 <axi4literead>:
axi4literead():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.c:16
 volatile uint32_t axi4literead(uint32_t address)
{

	uint32_t data;

	data = (uint32_t)(*(volatile int*) address);
40001b08:	00052503          	lw	a0,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.c:19
	//data = (uint32_t)(*(volatile int*) address);
return data;
}
40001b0c:	00008067          	ret

40001b10 <axi4litewrite>:
axi4litewrite():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.c:24

 volatile void axi4litewrite(uint32_t address,uint32_t data)
 {

 	*(volatile int*) address = data;
40001b10:	00b52023          	sw	a1,0(a0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.c:26

 }
40001b14:	00008067          	ret

40001b18 <sensor_i2c_write_gain>:
sensor_i2c_write_gain():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:36
					write_length, I2C_RELEASE_BUS );
			status = I2C_wait_complete(sensor2_i2c, I2C_NO_TIMEOUT );

	return status;
}
static i2c_status_t sensor_i2c_write_gain(uint8_t i2c_ch_sel, uint16_t data_reg, uint8_t data) {
40001b18:	ff010113          	addi	sp,sp,-16
40001b1c:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:37
	if (i2c_ch_sel==1){
40001b20:	00100793          	li	a5,1
40001b24:	04f51863          	bne	a0,a5,40001b74 <sensor_i2c_write_gain+0x5c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:39

	tx_buffer[0] = data_reg >> 8;
40001b28:	03000793          	li	a5,48
40001b2c:	82f18823          	sb	a5,-2000(gp) # 40002e10 <__sbss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:44
	tx_buffer[1] = data_reg & 0xff;
	tx_buffer[2] = data;// >> 8;
	write_length = sizeof(data_reg) + sizeof(data);

	I2C_write(sensor1_i2c, IMX334_1_DEV_REG, (const uint8_t *) tx_buffer,write_length, I2C_RELEASE_BUS );
40001b30:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:40
	tx_buffer[1] = data_reg & 0xff;
40001b34:	82b188a3          	sb	a1,-1999(gp) # 40002e11 <__sbss_end+0x1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:41
	tx_buffer[2] = data;// >> 8;
40001b38:	82c18923          	sb	a2,-1998(gp) # 40002e12 <__sbss_end+0x2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:44
	I2C_write(sensor1_i2c, IMX334_1_DEV_REG, (const uint8_t *) tx_buffer,write_length, I2C_RELEASE_BUS );
40001b3c:	01a00593          	li	a1,26
40001b40:	00000713          	li	a4,0
40001b44:	00300693          	li	a3,3
40001b48:	83018613          	addi	a2,gp,-2000 # 40002e10 <__sbss_end>
40001b4c:	c18ff0ef          	jal	ra,40000f64 <I2C_write>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:45
    status = I2C_wait_complete(sensor1_i2c, I2C_NO_TIMEOUT );
40001b50:	00000593          	li	a1,0
40001b54:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:56
	tx_buffer[0] = data_reg >> 8;
	tx_buffer[1] = data_reg & 0xff;
	tx_buffer[2] = data;
	write_length = sizeof(data_reg) + sizeof(data);
	I2C_write(sensor2_i2c, IMX334_2_DEV_REG, (const uint8_t *) tx_buffer,write_length, I2C_RELEASE_BUS );
	status = I2C_wait_complete(sensor2_i2c, I2C_NO_TIMEOUT );
40001b58:	e40ff0ef          	jal	ra,40001198 <I2C_wait_complete>
40001b5c:	82a1a023          	sw	a0,-2016(gp) # 40002e00 <status>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:59
	}
	return status;
}
40001b60:	00c12083          	lw	ra,12(sp)
40001b64:	82018793          	addi	a5,gp,-2016 # 40002e00 <status>
40001b68:	0007a503          	lw	a0,0(a5) # 4000000 <STACK_SIZE+0x3fff800>
40001b6c:	01010113          	addi	sp,sp,16
40001b70:	00008067          	ret
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:49
	(i2c_ch_sel==2){
40001b74:	00200793          	li	a5,2
40001b78:	fef514e3          	bne	a0,a5,40001b60 <sensor_i2c_write_gain+0x48>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:51
	tx_buffer[0] = data_reg >> 8;
40001b7c:	03000793          	li	a5,48
40001b80:	82f18823          	sb	a5,-2000(gp) # 40002e10 <__sbss_end>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:55
	I2C_write(sensor2_i2c, IMX334_2_DEV_REG, (const uint8_t *) tx_buffer,write_length, I2C_RELEASE_BUS );
40001b84:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:52
	tx_buffer[1] = data_reg & 0xff;
40001b88:	82b188a3          	sb	a1,-1999(gp) # 40002e11 <__sbss_end+0x1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:53
	tx_buffer[2] = data;
40001b8c:	82c18923          	sb	a2,-1998(gp) # 40002e12 <__sbss_end+0x2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:55
	I2C_write(sensor2_i2c, IMX334_2_DEV_REG, (const uint8_t *) tx_buffer,write_length, I2C_RELEASE_BUS );
40001b90:	01000593          	li	a1,16
40001b94:	00000713          	li	a4,0
40001b98:	00300693          	li	a3,3
40001b9c:	83018613          	addi	a2,gp,-2000 # 40002e10 <__sbss_end>
40001ba0:	bc4ff0ef          	jal	ra,40000f64 <I2C_write>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:56
	status = I2C_wait_complete(sensor2_i2c, I2C_NO_TIMEOUT );
40001ba4:	00000593          	li	a1,0
40001ba8:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
40001bac:	fadff06f          	j	40001b58 <sensor_i2c_write_gain+0x40>

40001bb0 <sensor_i2c_write.isra.0>:
sensor_i2c_write():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:15
static i2c_status_t sensor_i2c_write(uint8_t i2c_ch_sel, uint16_t data_reg, uint8_t data) {
40001bb0:	fe010113          	addi	sp,sp,-32
40001bb4:	00812c23          	sw	s0,24(sp)
40001bb8:	00912a23          	sw	s1,20(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:16
	tx_buffer[0] = data_reg >> 8;
40001bbc:	83018413          	addi	s0,gp,-2000 # 40002e10 <__sbss_end>
40001bc0:	00851493          	slli	s1,a0,0x8
40001bc4:	00855513          	srli	a0,a0,0x8
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:15
static i2c_status_t sensor_i2c_write(uint8_t i2c_ch_sel, uint16_t data_reg, uint8_t data) {
40001bc8:	01312623          	sw	s3,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:16
	tx_buffer[0] = data_reg >> 8;
40001bcc:	00a4e4b3          	or	s1,s1,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:22
		I2C_write(sensor1_i2c, IMX334_1_DEV_REG, (const uint8_t *) tx_buffer,
40001bd0:	00040613          	mv	a2,s0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:15
static i2c_status_t sensor_i2c_write(uint8_t i2c_ch_sel, uint16_t data_reg, uint8_t data) {
40001bd4:	00058993          	mv	s3,a1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:18
	tx_buffer[2] = data;// >> 8;
40001bd8:	00b40123          	sb	a1,2(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:22
		I2C_write(sensor1_i2c, IMX334_1_DEV_REG, (const uint8_t *) tx_buffer,
40001bdc:	00000713          	li	a4,0
40001be0:	00300693          	li	a3,3
40001be4:	01a00593          	li	a1,26
40001be8:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:15
static i2c_status_t sensor_i2c_write(uint8_t i2c_ch_sel, uint16_t data_reg, uint8_t data) {
40001bec:	00112e23          	sw	ra,28(sp)
40001bf0:	01212823          	sw	s2,16(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:16
	tx_buffer[0] = data_reg >> 8;
40001bf4:	00941023          	sh	s1,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:22
		I2C_write(sensor1_i2c, IMX334_1_DEV_REG, (const uint8_t *) tx_buffer,
40001bf8:	b6cff0ef          	jal	ra,40000f64 <I2C_write>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:24
			status = I2C_wait_complete(sensor1_i2c, I2C_NO_TIMEOUT );
40001bfc:	00000593          	li	a1,0
40001c00:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
40001c04:	d94ff0ef          	jal	ra,40001198 <I2C_wait_complete>
40001c08:	82018913          	addi	s2,gp,-2016 # 40002e00 <status>
40001c0c:	00a92023          	sw	a0,0(s2)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:30
		I2C_write(sensor2_i2c, IMX334_2_DEV_REG, (const uint8_t *) tx_buffer,
40001c10:	00040613          	mv	a2,s0
40001c14:	00000713          	li	a4,0
40001c18:	00300693          	li	a3,3
40001c1c:	01000593          	li	a1,16
40001c20:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:26
			tx_buffer[0] = data_reg >> 8;
40001c24:	00941023          	sh	s1,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:28
			tx_buffer[2] = data;
40001c28:	01340123          	sb	s3,2(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:30
		I2C_write(sensor2_i2c, IMX334_2_DEV_REG, (const uint8_t *) tx_buffer,
40001c2c:	b38ff0ef          	jal	ra,40000f64 <I2C_write>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:32
			status = I2C_wait_complete(sensor2_i2c, I2C_NO_TIMEOUT );
40001c30:	00000593          	li	a1,0
40001c34:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
40001c38:	d60ff0ef          	jal	ra,40001198 <I2C_wait_complete>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:35
}
40001c3c:	01c12083          	lw	ra,28(sp)
40001c40:	01812403          	lw	s0,24(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:32
			status = I2C_wait_complete(sensor2_i2c, I2C_NO_TIMEOUT );
40001c44:	00a92023          	sw	a0,0(s2)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:35
}
40001c48:	01412483          	lw	s1,20(sp)
40001c4c:	01012903          	lw	s2,16(sp)
40001c50:	00c12983          	lw	s3,12(sp)
40001c54:	02010113          	addi	sp,sp,32
40001c58:	00008067          	ret

40001c5c <imx334_cam_init>:
imx334_cam_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:62

void imx334_cam_init()
{
40001c5c:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:63
	I2C_init( sensor1_i2c, COREI2C_IMX1_BASE_ADDR, IMX334_1_DEV_REG, I2C_PCLK_DIV_256 );
40001c60:	00000693          	li	a3,0
40001c64:	01a00613          	li	a2,26
40001c68:	700075b7          	lui	a1,0x70007
40001c6c:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:62
{
40001c70:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:63
	I2C_init( sensor1_i2c, COREI2C_IMX1_BASE_ADDR, IMX334_1_DEV_REG, I2C_PCLK_DIV_256 );
40001c74:	9f0ff0ef          	jal	ra,40000e64 <I2C_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:64
	I2C_init( sensor2_i2c, COREI2C_IMX2_BASE_ADDR, IMX334_2_DEV_REG, I2C_PCLK_DIV_256 );
40001c78:	00000693          	li	a3,0
40001c7c:	01000613          	li	a2,16
40001c80:	700045b7          	lui	a1,0x70004
40001c84:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
40001c88:	9dcff0ef          	jal	ra,40000e64 <I2C_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:65
	GPIO_set_output(&g_gpio_out, CAM1_RST, 0u);
40001c8c:	00000613          	li	a2,0
40001c90:	00800593          	li	a1,8
40001c94:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40001c98:	ce1ff0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:66
	GPIO_set_output(&g_gpio_out, CAM2_RST, 0u);
40001c9c:	00000613          	li	a2,0
40001ca0:	00700593          	li	a1,7
40001ca4:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40001ca8:	cd1ff0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:67
	msdelay(100);
40001cac:	06400513          	li	a0,100
40001cb0:	12d000ef          	jal	ra,400025dc <msdelay>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:68
	GPIO_set_output(&g_gpio_out, CAM1_RST, 1u); // Bring camera out of reset
40001cb4:	00100613          	li	a2,1
40001cb8:	00800593          	li	a1,8
40001cbc:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40001cc0:	cb9ff0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:69
	GPIO_set_output(&g_gpio_out, CAM2_RST, 1u); // Bring camera out of reset
40001cc4:	00100613          	li	a2,1
40001cc8:	00700593          	li	a1,7
40001ccc:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40001cd0:	ca9ff0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:70
	msdelay(100);
40001cd4:	06400513          	li	a0,100
40001cd8:	105000ef          	jal	ra,400025dc <msdelay>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:71
	GPIO_set_output(&g_gpio_out, CAM_CLK_EN, 1u); //Enable Cam clock from FPGA
40001cdc:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40001ce0:	00100613          	li	a2,1
40001ce4:	00900593          	li	a1,9
40001ce8:	c91ff0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:73
	msdelay(100);
}
40001cec:	00c12083          	lw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:72
	msdelay(100);
40001cf0:	06400513          	li	a0,100
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:73
}
40001cf4:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:72
	msdelay(100);
40001cf8:	0e50006f          	j	400025dc <msdelay>

40001cfc <imx334_cam_reginit>:
imx334_cam_reginit():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:76

void imx334_cam_reginit( uint8_t i2c_ch_sel)
{
40001cfc:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:79
	uint32_t i;

	sensor_i2c_write(i2c_ch_sel, 0x3000, 0x01);// STANDBY MODE enabled
40001d00:	00100593          	li	a1,1
40001d04:	00003537          	lui	a0,0x3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:76
{
40001d08:	00112623          	sw	ra,12(sp)
40001d0c:	00812423          	sw	s0,8(sp)
40001d10:	00912223          	sw	s1,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:80
	sensor_i2c_write(i2c_ch_sel, 0x3018, 0x04);//WINMODE
40001d14:	00003437          	lui	s0,0x3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:79
	sensor_i2c_write(i2c_ch_sel, 0x3000, 0x01);// STANDBY MODE enabled
40001d18:	e99ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:80
	sensor_i2c_write(i2c_ch_sel, 0x3018, 0x04);//WINMODE
40001d1c:	00400593          	li	a1,4
40001d20:	01840513          	addi	a0,s0,24 # 3018 <STACK_SIZE+0x2818>
40001d24:	e8dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:81
	sensor_i2c_write(i2c_ch_sel, 0x3030, 0xCA);//VMAX
40001d28:	0ca00593          	li	a1,202
40001d2c:	03040513          	addi	a0,s0,48
40001d30:	e81ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:82
	sensor_i2c_write(i2c_ch_sel, 0x3031, 0x08);//VMAX
40001d34:	00800593          	li	a1,8
40001d38:	03140513          	addi	a0,s0,49
40001d3c:	e75ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:83
	sensor_i2c_write(i2c_ch_sel, 0x3032, 0x00);//VMAX
40001d40:	00000593          	li	a1,0
40001d44:	03240513          	addi	a0,s0,50
40001d48:	e69ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:84
	sensor_i2c_write(i2c_ch_sel, 0x3034, 0x4C);//HMAX
40001d4c:	04c00593          	li	a1,76
40001d50:	03440513          	addi	a0,s0,52
40001d54:	e5dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:85
	sensor_i2c_write(i2c_ch_sel, 0x3035, 0x04);//HMAX
40001d58:	00400593          	li	a1,4
40001d5c:	03540513          	addi	a0,s0,53
40001d60:	e51ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:87
#if CAM_CONFIG_4K_1_2M
	sensor_i2c_write(i2c_ch_sel, 0x302C, 0x30);//TRIM_START
40001d64:	03000593          	li	a1,48
40001d68:	02c40513          	addi	a0,s0,44
40001d6c:	e45ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:88
	sensor_i2c_write(i2c_ch_sel, 0x302D, 0x00);//TRIM_START
40001d70:	00000593          	li	a1,0
40001d74:	02d40513          	addi	a0,s0,45
40001d78:	e39ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:89
	sensor_i2c_write(i2c_ch_sel, 0x302E, 0x00);//HNUM
40001d7c:	00000593          	li	a1,0
40001d80:	02e40513          	addi	a0,s0,46
40001d84:	e2dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:90
	sensor_i2c_write(i2c_ch_sel, 0x302F, 0x0F);//HNUM
40001d88:	00f00593          	li	a1,15
40001d8c:	02f40513          	addi	a0,s0,47
40001d90:	e21ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:91
	sensor_i2c_write(i2c_ch_sel, 0x3074, 0xB0);//AREA3_ST_ADR_1
40001d94:	0b000593          	li	a1,176
40001d98:	07440513          	addi	a0,s0,116
40001d9c:	e15ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:92
	sensor_i2c_write(i2c_ch_sel, 0x3075, 0x00);//AREA3_ST_ADR_1
40001da0:	00000593          	li	a1,0
40001da4:	07540513          	addi	a0,s0,117
40001da8:	e09ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:93
	sensor_i2c_write(i2c_ch_sel, 0x308E, 0xB1);//AREA3_ST_ADR_2
40001dac:	0b100593          	li	a1,177
40001db0:	08e40513          	addi	a0,s0,142
40001db4:	dfdff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:94
	sensor_i2c_write(i2c_ch_sel, 0x308F, 0x00);//AREA3_ST_ADR_2
40001db8:	00000593          	li	a1,0
40001dbc:	08f40513          	addi	a0,s0,143
40001dc0:	df1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:95
	sensor_i2c_write(i2c_ch_sel, 0x3076, 0x70);//AREA3_WIDTH_1
40001dc4:	07000593          	li	a1,112
40001dc8:	07640513          	addi	a0,s0,118
40001dcc:	de5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:96
	sensor_i2c_write(i2c_ch_sel, 0x3077, 0x08);//AREA3_WIDTH_1
40001dd0:	00800593          	li	a1,8
40001dd4:	07740513          	addi	a0,s0,119
40001dd8:	dd9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:97
	sensor_i2c_write(i2c_ch_sel, 0x3090, 0x70);//AREA3_WIDTH_2
40001ddc:	07000593          	li	a1,112
40001de0:	09040513          	addi	a0,s0,144
40001de4:	dcdff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:98
	sensor_i2c_write(i2c_ch_sel, 0x3091, 0x08);//AREA3_WIDTH_2
40001de8:	00800593          	li	a1,8
40001dec:	09140513          	addi	a0,s0,145
40001df0:	dc1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:99
	sensor_i2c_write(i2c_ch_sel, 0x3308, 0x70);//Y_OUT_SIZE
40001df4:	07000593          	li	a1,112
40001df8:	30840513          	addi	a0,s0,776
40001dfc:	db5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:100
	sensor_i2c_write(i2c_ch_sel, 0x3309, 0x08);//Y_OUT_SIZE
40001e00:	00800593          	li	a1,8
40001e04:	30940513          	addi	a0,s0,777
40001e08:	da9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:101
	sensor_i2c_write(i2c_ch_sel, 0x30C6, 0x00);//BLACK_OFSET_ADR
40001e0c:	00000593          	li	a1,0
40001e10:	0c640513          	addi	a0,s0,198
40001e14:	d9dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:102
	sensor_i2c_write(i2c_ch_sel, 0x30C7, 0x00);//BLACK_OFSET_ADR
40001e18:	00000593          	li	a1,0
40001e1c:	0c740513          	addi	a0,s0,199
40001e20:	d91ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:103
	sensor_i2c_write(i2c_ch_sel, 0x30CE, 0x00);//UNRD_LINE_MAX
40001e24:	00000593          	li	a1,0
40001e28:	0ce40513          	addi	a0,s0,206
40001e2c:	d85ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:104
	sensor_i2c_write(i2c_ch_sel, 0x30CF, 0x00);//UNRD_LINE_MAX
40001e30:	00000593          	li	a1,0
40001e34:	0cf40513          	addi	a0,s0,207
40001e38:	d79ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:105
	sensor_i2c_write(i2c_ch_sel, 0x30D8, 0x20);//UNREAD_ED_ADR
40001e3c:	02000593          	li	a1,32
40001e40:	0d840513          	addi	a0,s0,216
40001e44:	d6dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:106
	sensor_i2c_write(i2c_ch_sel, 0x30D9, 0x12);//UNREAD_ED_ADR
40001e48:	01200593          	li	a1,18
40001e4c:	0d940513          	addi	a0,s0,217
40001e50:	d61ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:107
	sensor_i2c_write(i2c_ch_sel, 0x304C, 0x00);//OPB_SIZE_V-OPTICAL BLACK
40001e54:	00000593          	li	a1,0
40001e58:	04c40513          	addi	a0,s0,76
40001e5c:	d55ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:132
	sensor_i2c_write(i2c_ch_sel, 0x30D8, 0x18);//UNREAD_ED_ADR
	sensor_i2c_write(i2c_ch_sel, 0x30D9, 0x0A);//UNREAD_ED_ADR
	sensor_i2c_write(i2c_ch_sel, 0x304C, 0x00);//OPB_SIZE_V-OPTICAL BLACK
#endif

	sensor_i2c_write(i2c_ch_sel, 0x304E, 0x00);//H_REVERSE
40001e60:	00000593          	li	a1,0
40001e64:	04e40513          	addi	a0,s0,78
40001e68:	d49ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:133
	sensor_i2c_write(i2c_ch_sel, 0x304F, 0x00);//V_REVERSE
40001e6c:	00000593          	li	a1,0
40001e70:	04f40513          	addi	a0,s0,79
40001e74:	d3dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:134
	sensor_i2c_write(i2c_ch_sel, 0x3050, 0x0);//ADBIT-0-10BIT/ 1-12BIT
40001e78:	00000593          	li	a1,0
40001e7c:	05040513          	addi	a0,s0,80
40001e80:	d31ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:136

	sensor_i2c_write(i2c_ch_sel, 0x30B6, 0x00);//UNREAD_PARAM5
40001e84:	00000593          	li	a1,0
40001e88:	0b640513          	addi	a0,s0,182
40001e8c:	d25ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:137
	sensor_i2c_write(i2c_ch_sel, 0x30B7, 0x00);//UNREAD_PARAM5
40001e90:	00000593          	li	a1,0
40001e94:	0b740513          	addi	a0,s0,183
40001e98:	d19ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:138
	sensor_i2c_write(i2c_ch_sel, 0x3116, 0x08);//UNREAD_PARAM6
40001e9c:	00800593          	li	a1,8
40001ea0:	11640513          	addi	a0,s0,278
40001ea4:	d0dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:139
	sensor_i2c_write(i2c_ch_sel, 0x3117, 0x00);//UNREAD_PARAM6
40001ea8:	00000593          	li	a1,0
40001eac:	11740513          	addi	a0,s0,279
40001eb0:	d01ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:142

	/*Change this if slave mode is used*/
	sensor_i2c_write(i2c_ch_sel, 0x31A0, 0x20);//XVS,XHS output tied to ground
40001eb4:	02000593          	li	a1,32
40001eb8:	1a040513          	addi	a0,s0,416
40001ebc:	cf5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:143
	sensor_i2c_write(i2c_ch_sel, 0x31A1, 0x0F);//XVS,XHS output tied to ground
40001ec0:	00f00593          	li	a1,15
40001ec4:	1a140513          	addi	a0,s0,417
40001ec8:	ce9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:146
#if CAM_CONFIG_4K_1_2M
	/*1188 Mbps*/
	sensor_i2c_write(i2c_ch_sel, 0x300C, 0x42);//BC_WAIT_TIME
40001ecc:	04200593          	li	a1,66
40001ed0:	00c40513          	addi	a0,s0,12
40001ed4:	cddff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:147
	sensor_i2c_write(i2c_ch_sel, 0x300D, 0x2E);//CP_WAIT_TIME
40001ed8:	02e00593          	li	a1,46
40001edc:	00d40513          	addi	a0,s0,13
40001ee0:	cd1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:148
	sensor_i2c_write(i2c_ch_sel, 0x314C, 0xB0);//INCKSEL1
40001ee4:	0b000593          	li	a1,176
40001ee8:	14c40513          	addi	a0,s0,332
40001eec:	cc5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:149
	sensor_i2c_write(i2c_ch_sel, 0x314D, 0x00);//INCKSEL1
40001ef0:	00000593          	li	a1,0
40001ef4:	14d40513          	addi	a0,s0,333
40001ef8:	cb9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:150
	sensor_i2c_write(i2c_ch_sel, 0x315A, 0x02);//INCKSEL2
40001efc:	00200593          	li	a1,2
40001f00:	15a40513          	addi	a0,s0,346
40001f04:	cadff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:151
	sensor_i2c_write(i2c_ch_sel, 0x3168, 0x8F);//INCKSEL3
40001f08:	08f00593          	li	a1,143
40001f0c:	16840513          	addi	a0,s0,360
40001f10:	ca1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:152
	sensor_i2c_write(i2c_ch_sel, 0x316A, 0x7E);//INCKSEL4
40001f14:	07e00593          	li	a1,126
40001f18:	16a40513          	addi	a0,s0,362
40001f1c:	c95ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:153
	sensor_i2c_write(i2c_ch_sel, 0x319E, 0x01);//SYS_MODE
40001f20:	00100593          	li	a1,1
40001f24:	19e40513          	addi	a0,s0,414
40001f28:	c89ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:165
	sensor_i2c_write(i2c_ch_sel, 0x315A, 0x0A);//INCKSEL2
	sensor_i2c_write(i2c_ch_sel, 0x3168, 0xA0);//INCKSEL3
	sensor_i2c_write(i2c_ch_sel, 0x316A, 0x7E);//INCKSEL4
	sensor_i2c_write(i2c_ch_sel, 0x319E, 0x02);//SYS_MODE
#endif
	sensor_i2c_write(i2c_ch_sel, 0x3199, 0x00);//HADD,VADD - 0 All pix scan, 3-2/2binning
40001f2c:	00000593          	li	a1,0
40001f30:	19940513          	addi	a0,s0,409
40001f34:	c7dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:166
	sensor_i2c_write(i2c_ch_sel, 0x319D, 0x00);//MDBIT-0-10bit,1-12bit
40001f38:	00000593          	li	a1,0
40001f3c:	19d40513          	addi	a0,s0,413
40001f40:	c71ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:168

	sensor_i2c_write(i2c_ch_sel, 0x31DD, 0x03);//VALID_EXPAND
40001f44:	00300593          	li	a1,3
40001f48:	1dd40513          	addi	a0,s0,477
40001f4c:	c65ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:169
	sensor_i2c_write(i2c_ch_sel, 0x3300, 0x00);//TCYCLE
40001f50:	00000593          	li	a1,0
40001f54:	30040513          	addi	a0,s0,768
40001f58:	c59ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:171

	sensor_i2c_write(i2c_ch_sel, 0x341C, 0xFF);//ADBIT1 FFh-10bit, 47h-12bit
40001f5c:	0ff00593          	li	a1,255
40001f60:	41c40513          	addi	a0,s0,1052
40001f64:	c4dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:172
	sensor_i2c_write(i2c_ch_sel, 0x341D, 0x01);//ADBIT1 01h-10bit, 00h-12bit
40001f68:	00100593          	li	a1,1
40001f6c:	41d40513          	addi	a0,s0,1053
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:175

#if CAM_CONFIG_lane
	sensor_i2c_write(i2c_ch_sel, 0x3A01, 0x03);//4 LANE_MODE
40001f70:	000044b7          	lui	s1,0x4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:172
	sensor_i2c_write(i2c_ch_sel, 0x341D, 0x01);//ADBIT1 01h-10bit, 00h-12bit
40001f74:	c3dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:175
	sensor_i2c_write(i2c_ch_sel, 0x3A01, 0x03);//4 LANE_MODE
40001f78:	00300593          	li	a1,3
40001f7c:	a0148513          	addi	a0,s1,-1535 # 3a01 <STACK_SIZE+0x3201>
40001f80:	c31ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:179
#else
	sensor_i2c_write(i2c_ch_sel, 0x3A01, 0x07);//8 LANE_MODE
#endif
	sensor_i2c_write(i2c_ch_sel, 0x3A18, 0x7F);//TCLKPOST
40001f84:	07f00593          	li	a1,127
40001f88:	a1848513          	addi	a0,s1,-1512
40001f8c:	c25ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:180
	sensor_i2c_write(i2c_ch_sel, 0x3A19, 0x00);//TCLKPOST
40001f90:	00000593          	li	a1,0
40001f94:	a1948513          	addi	a0,s1,-1511
40001f98:	c19ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:181
	sensor_i2c_write(i2c_ch_sel, 0x3A1A, 0x37);//TCLKPPREPARE
40001f9c:	03700593          	li	a1,55
40001fa0:	a1a48513          	addi	a0,s1,-1510
40001fa4:	c0dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:182
	sensor_i2c_write(i2c_ch_sel, 0x3A1B, 0x00);//TCLKPREPARE
40001fa8:	00000593          	li	a1,0
40001fac:	a1b48513          	addi	a0,s1,-1509
40001fb0:	c01ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:183
	sensor_i2c_write(i2c_ch_sel, 0x3A1C, 0x37);//TCLKTRAIL
40001fb4:	03700593          	li	a1,55
40001fb8:	a1c48513          	addi	a0,s1,-1508
40001fbc:	bf5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:184
	sensor_i2c_write(i2c_ch_sel, 0x3A1D, 0x00);//TCLKTRAIL
40001fc0:	00000593          	li	a1,0
40001fc4:	a1d48513          	addi	a0,s1,-1507
40001fc8:	be9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:185
	sensor_i2c_write(i2c_ch_sel, 0x3A1E, 0xF7);//TCLKZERO
40001fcc:	0f700593          	li	a1,247
40001fd0:	a1e48513          	addi	a0,s1,-1506
40001fd4:	bddff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:186
	sensor_i2c_write(i2c_ch_sel, 0x3A1F, 0x00);//TCLKZERO
40001fd8:	00000593          	li	a1,0
40001fdc:	a1f48513          	addi	a0,s1,-1505
40001fe0:	bd1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:187
	sensor_i2c_write(i2c_ch_sel, 0x3A20, 0x3F);//THSPREPARE
40001fe4:	03f00593          	li	a1,63
40001fe8:	a2048513          	addi	a0,s1,-1504
40001fec:	bc5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:188
	sensor_i2c_write(i2c_ch_sel, 0x3A21, 0x00);//THSPREPARE
40001ff0:	00000593          	li	a1,0
40001ff4:	a2148513          	addi	a0,s1,-1503
40001ff8:	bb9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:189
	sensor_i2c_write(i2c_ch_sel, 0x3A20, 0x6F);//THSZERO
40001ffc:	06f00593          	li	a1,111
40002000:	a2048513          	addi	a0,s1,-1504
40002004:	badff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:190
	sensor_i2c_write(i2c_ch_sel, 0x3A21, 0x00);//THSZERO
40002008:	00000593          	li	a1,0
4000200c:	a2148513          	addi	a0,s1,-1503
40002010:	ba1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:191
	sensor_i2c_write(i2c_ch_sel, 0x3A20, 0x3F);//THSTRAIL
40002014:	03f00593          	li	a1,63
40002018:	a2048513          	addi	a0,s1,-1504
4000201c:	b95ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:192
	sensor_i2c_write(i2c_ch_sel, 0x3A21, 0x00);//THSTRAIL
40002020:	00000593          	li	a1,0
40002024:	a2148513          	addi	a0,s1,-1503
40002028:	b89ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:193
	sensor_i2c_write(i2c_ch_sel, 0x3A20, 0x5F);//THSEXIT
4000202c:	05f00593          	li	a1,95
40002030:	a2048513          	addi	a0,s1,-1504
40002034:	b7dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:194
	sensor_i2c_write(i2c_ch_sel, 0x3A21, 0x00);//THSEXIT
40002038:	00000593          	li	a1,0
4000203c:	a2148513          	addi	a0,s1,-1503
40002040:	b71ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:195
	sensor_i2c_write(i2c_ch_sel, 0x3A20, 0x2F);//TLPX
40002044:	02f00593          	li	a1,47
40002048:	a2048513          	addi	a0,s1,-1504
4000204c:	b65ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:196
	sensor_i2c_write(i2c_ch_sel, 0x3A21, 0x00);//TLPX
40002050:	00000593          	li	a1,0
40002054:	a2148513          	addi	a0,s1,-1503
40002058:	b59ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:212
	sensor_i2c_write(i2c_ch_sel, 0x3303, 0x00);// Black level LSB
	sensor_i2c_write(i2c_ch_sel, 0x336C, 0x01);// WRJ_OPEN
#endif

	/*Additional settings for All scan mode */
	sensor_i2c_write(i2c_ch_sel, 0x3078, 0x02);
4000205c:	00200593          	li	a1,2
40002060:	07840513          	addi	a0,s0,120
40002064:	b4dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:213
	sensor_i2c_write(i2c_ch_sel, 0x3079, 0x00);
40002068:	00000593          	li	a1,0
4000206c:	07940513          	addi	a0,s0,121
40002070:	b41ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:214
	sensor_i2c_write(i2c_ch_sel, 0x307A, 0x00);
40002074:	00000593          	li	a1,0
40002078:	07a40513          	addi	a0,s0,122
4000207c:	b35ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:215
	sensor_i2c_write(i2c_ch_sel, 0x307B, 0x00);
40002080:	00000593          	li	a1,0
40002084:	07b40513          	addi	a0,s0,123
40002088:	b29ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:216
	sensor_i2c_write(i2c_ch_sel, 0x3080, 0x02);//0xFE if inverted vertical readout
4000208c:	00200593          	li	a1,2
40002090:	08040513          	addi	a0,s0,128
40002094:	b1dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:217
	sensor_i2c_write(i2c_ch_sel, 0x3081, 0x00);
40002098:	00000593          	li	a1,0
4000209c:	08140513          	addi	a0,s0,129
400020a0:	b11ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:218
	sensor_i2c_write(i2c_ch_sel, 0x3082, 0x00);
400020a4:	00000593          	li	a1,0
400020a8:	08240513          	addi	a0,s0,130
400020ac:	b05ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:219
	sensor_i2c_write(i2c_ch_sel, 0x3083, 0x00);
400020b0:	00000593          	li	a1,0
400020b4:	08340513          	addi	a0,s0,131
400020b8:	af9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:220
	sensor_i2c_write(i2c_ch_sel, 0x3088, 0x02);
400020bc:	00200593          	li	a1,2
400020c0:	08840513          	addi	a0,s0,136
400020c4:	aedff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:221
	sensor_i2c_write(i2c_ch_sel, 0x3094, 0x00);
400020c8:	00000593          	li	a1,0
400020cc:	09440513          	addi	a0,s0,148
400020d0:	ae1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:222
	sensor_i2c_write(i2c_ch_sel, 0x3095, 0x00);
400020d4:	00000593          	li	a1,0
400020d8:	09540513          	addi	a0,s0,149
400020dc:	ad5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:223
	sensor_i2c_write(i2c_ch_sel, 0x3096, 0x00);
400020e0:	00000593          	li	a1,0
400020e4:	09640513          	addi	a0,s0,150
400020e8:	ac9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:224
	sensor_i2c_write(i2c_ch_sel, 0x309B, 0x02);//0xFE if inverted vertical readout
400020ec:	00200593          	li	a1,2
400020f0:	09b40513          	addi	a0,s0,155
400020f4:	abdff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:225
	sensor_i2c_write(i2c_ch_sel, 0x309C, 0x00);
400020f8:	00000593          	li	a1,0
400020fc:	09c40513          	addi	a0,s0,156
40002100:	ab1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:226
	sensor_i2c_write(i2c_ch_sel, 0x309D, 0x00);
40002104:	00000593          	li	a1,0
40002108:	09d40513          	addi	a0,s0,157
4000210c:	aa5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:227
	sensor_i2c_write(i2c_ch_sel, 0x309E, 0x00);
40002110:	00000593          	li	a1,0
40002114:	09e40513          	addi	a0,s0,158
40002118:	a99ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:228
	sensor_i2c_write(i2c_ch_sel, 0x30A4, 0x00);
4000211c:	00000593          	li	a1,0
40002120:	0a440513          	addi	a0,s0,164
40002124:	a8dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:229
	sensor_i2c_write(i2c_ch_sel, 0x30A5, 0x00);
40002128:	00000593          	li	a1,0
4000212c:	0a540513          	addi	a0,s0,165
40002130:	a81ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:234
	/*End of additional settings for all scan mode*/


	/*Additional Mandatory Settings*/
	sensor_i2c_write(i2c_ch_sel, 0x3288, 0x21);
40002134:	02100593          	li	a1,33
40002138:	28840513          	addi	a0,s0,648
4000213c:	a75ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:235
	sensor_i2c_write(i2c_ch_sel, 0x328A, 0x02);
40002140:	00200593          	li	a1,2
40002144:	28a40513          	addi	a0,s0,650
40002148:	a69ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:236
	sensor_i2c_write(i2c_ch_sel, 0x3414, 0x05);
4000214c:	00500593          	li	a1,5
40002150:	41440513          	addi	a0,s0,1044
40002154:	a5dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:237
	sensor_i2c_write(i2c_ch_sel, 0x3416, 0x18);
40002158:	01800593          	li	a1,24
4000215c:	41640513          	addi	a0,s0,1046
40002160:	a51ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:238
	sensor_i2c_write(i2c_ch_sel, 0x35AC, 0x0E);
40002164:	00e00593          	li	a1,14
40002168:	5ac40513          	addi	a0,s0,1452
4000216c:	a45ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:239
	sensor_i2c_write(i2c_ch_sel, 0x3648, 0x01);
40002170:	00100593          	li	a1,1
40002174:	64840513          	addi	a0,s0,1608
40002178:	a39ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:240
	sensor_i2c_write(i2c_ch_sel, 0x364A, 0x04);
4000217c:	00400593          	li	a1,4
40002180:	64a40513          	addi	a0,s0,1610
40002184:	a2dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:241
	sensor_i2c_write(i2c_ch_sel, 0x364C, 0x04);
40002188:	00400593          	li	a1,4
4000218c:	64c40513          	addi	a0,s0,1612
40002190:	a21ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:242
	sensor_i2c_write(i2c_ch_sel, 0x3678, 0x01);
40002194:	00100593          	li	a1,1
40002198:	67840513          	addi	a0,s0,1656
4000219c:	a15ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:243
	sensor_i2c_write(i2c_ch_sel, 0x367C, 0x31);
400021a0:	03100593          	li	a1,49
400021a4:	67c40513          	addi	a0,s0,1660
400021a8:	a09ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:244
	sensor_i2c_write(i2c_ch_sel, 0x367E, 0x31);
400021ac:	03100593          	li	a1,49
400021b0:	67e40513          	addi	a0,s0,1662
400021b4:	9fdff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:245
	sensor_i2c_write(i2c_ch_sel, 0x3708, 0x02);
400021b8:	00200593          	li	a1,2
400021bc:	70840513          	addi	a0,s0,1800
400021c0:	9f1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:246
	sensor_i2c_write(i2c_ch_sel, 0x3714, 0x01);
400021c4:	00100593          	li	a1,1
400021c8:	71440513          	addi	a0,s0,1812
400021cc:	9e5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:247
	sensor_i2c_write(i2c_ch_sel, 0x3715, 0x02);
400021d0:	00200593          	li	a1,2
400021d4:	71540513          	addi	a0,s0,1813
400021d8:	9d9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:248
	sensor_i2c_write(i2c_ch_sel, 0x3716, 0x02);
400021dc:	00200593          	li	a1,2
400021e0:	71640513          	addi	a0,s0,1814
400021e4:	9cdff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:249
	sensor_i2c_write(i2c_ch_sel, 0x3717, 0x02);
400021e8:	00200593          	li	a1,2
400021ec:	71740513          	addi	a0,s0,1815
400021f0:	9c1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:250
	sensor_i2c_write(i2c_ch_sel, 0x371C, 0x3D);
400021f4:	03d00593          	li	a1,61
400021f8:	71c40513          	addi	a0,s0,1820
400021fc:	9b5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:251
	sensor_i2c_write(i2c_ch_sel, 0x371D, 0x3F);
40002200:	03f00593          	li	a1,63
40002204:	71d40513          	addi	a0,s0,1821
40002208:	9a9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:252
	sensor_i2c_write(i2c_ch_sel, 0x372C, 0x00);
4000220c:	00000593          	li	a1,0
40002210:	72c40513          	addi	a0,s0,1836
40002214:	99dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:253
	sensor_i2c_write(i2c_ch_sel, 0x372D, 0x00);
40002218:	00000593          	li	a1,0
4000221c:	72d40513          	addi	a0,s0,1837
40002220:	991ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:254
	sensor_i2c_write(i2c_ch_sel, 0x372E, 0x46);
40002224:	04600593          	li	a1,70
40002228:	72e40513          	addi	a0,s0,1838
4000222c:	985ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:255
	sensor_i2c_write(i2c_ch_sel, 0x372F, 0x00);
40002230:	00000593          	li	a1,0
40002234:	72f40513          	addi	a0,s0,1839
40002238:	979ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:256
	sensor_i2c_write(i2c_ch_sel, 0x3730, 0x89);
4000223c:	08900593          	li	a1,137
40002240:	73040513          	addi	a0,s0,1840
40002244:	96dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:257
	sensor_i2c_write(i2c_ch_sel, 0x3731, 0x00);
40002248:	00000593          	li	a1,0
4000224c:	73140513          	addi	a0,s0,1841
40002250:	961ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:258
	sensor_i2c_write(i2c_ch_sel, 0x3732, 0x08);
40002254:	00800593          	li	a1,8
40002258:	73240513          	addi	a0,s0,1842
4000225c:	955ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:259
	sensor_i2c_write(i2c_ch_sel, 0x3733, 0x01);
40002260:	00100593          	li	a1,1
40002264:	73340513          	addi	a0,s0,1843
40002268:	949ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:260
	sensor_i2c_write(i2c_ch_sel, 0x3734, 0xFE);
4000226c:	0fe00593          	li	a1,254
40002270:	73440513          	addi	a0,s0,1844
40002274:	93dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:261
	sensor_i2c_write(i2c_ch_sel, 0x3735, 0x05);
40002278:	00500593          	li	a1,5
4000227c:	73540513          	addi	a0,s0,1845
40002280:	931ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:262
	sensor_i2c_write(i2c_ch_sel, 0x375D, 0x00);
40002284:	00000593          	li	a1,0
40002288:	75d40513          	addi	a0,s0,1885
4000228c:	925ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:263
	sensor_i2c_write(i2c_ch_sel, 0x375E, 0x00);
40002290:	00000593          	li	a1,0
40002294:	75e40513          	addi	a0,s0,1886
40002298:	919ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:264
	sensor_i2c_write(i2c_ch_sel, 0x375F, 0x61);
4000229c:	06100593          	li	a1,97
400022a0:	75f40513          	addi	a0,s0,1887
400022a4:	90dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:265
	sensor_i2c_write(i2c_ch_sel, 0x3760, 0x06);
400022a8:	00600593          	li	a1,6
400022ac:	76040513          	addi	a0,s0,1888
400022b0:	901ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:266
	sensor_i2c_write(i2c_ch_sel, 0x3768, 0x1B);
400022b4:	01b00593          	li	a1,27
400022b8:	76840513          	addi	a0,s0,1896
400022bc:	8f5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:267
	sensor_i2c_write(i2c_ch_sel, 0x3769, 0x1B);
400022c0:	01b00593          	li	a1,27
400022c4:	76940513          	addi	a0,s0,1897
400022c8:	8e9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:268
	sensor_i2c_write(i2c_ch_sel, 0x376A, 0x1A);
400022cc:	01a00593          	li	a1,26
400022d0:	76a40513          	addi	a0,s0,1898
400022d4:	8ddff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:269
	sensor_i2c_write(i2c_ch_sel, 0x376B, 0x19);
400022d8:	01900593          	li	a1,25
400022dc:	76b40513          	addi	a0,s0,1899
400022e0:	8d1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:270
	sensor_i2c_write(i2c_ch_sel, 0x376C, 0x18);
400022e4:	01800593          	li	a1,24
400022e8:	76c40513          	addi	a0,s0,1900
400022ec:	8c5ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:271
	sensor_i2c_write(i2c_ch_sel, 0x376D, 0x14);
400022f0:	01400593          	li	a1,20
400022f4:	76d40513          	addi	a0,s0,1901
400022f8:	8b9ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:272
	sensor_i2c_write(i2c_ch_sel, 0x376E, 0x0F);
400022fc:	00f00593          	li	a1,15
40002300:	76e40513          	addi	a0,s0,1902
40002304:	8adff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:273
	sensor_i2c_write(i2c_ch_sel, 0x3776, 0x00);
40002308:	00000593          	li	a1,0
4000230c:	77640513          	addi	a0,s0,1910
40002310:	8a1ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:274
	sensor_i2c_write(i2c_ch_sel, 0x3777, 0x00);
40002314:	00000593          	li	a1,0
40002318:	77740513          	addi	a0,s0,1911
4000231c:	895ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:275
	sensor_i2c_write(i2c_ch_sel, 0x3778, 0x46);
40002320:	04600593          	li	a1,70
40002324:	77840513          	addi	a0,s0,1912
40002328:	889ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:276
	sensor_i2c_write(i2c_ch_sel, 0x3779, 0x00);
4000232c:	00000593          	li	a1,0
40002330:	77940513          	addi	a0,s0,1913
40002334:	87dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:277
	sensor_i2c_write(i2c_ch_sel, 0x377A, 0x08);
40002338:	00800593          	li	a1,8
4000233c:	77a40513          	addi	a0,s0,1914
40002340:	871ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:278
	sensor_i2c_write(i2c_ch_sel, 0x377B, 0x01);
40002344:	00100593          	li	a1,1
40002348:	77b40513          	addi	a0,s0,1915
4000234c:	865ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:279
	sensor_i2c_write(i2c_ch_sel, 0x377C, 0x45);
40002350:	04500593          	li	a1,69
40002354:	77c40513          	addi	a0,s0,1916
40002358:	859ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:280
	sensor_i2c_write(i2c_ch_sel, 0x377D, 0x01);
4000235c:	00100593          	li	a1,1
40002360:	77d40513          	addi	a0,s0,1917
40002364:	84dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:281
	sensor_i2c_write(i2c_ch_sel, 0x377E, 0x23);
40002368:	02300593          	li	a1,35
4000236c:	77e40513          	addi	a0,s0,1918
40002370:	841ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:282
	sensor_i2c_write(i2c_ch_sel, 0x377F, 0x02);
40002374:	00200593          	li	a1,2
40002378:	77f40513          	addi	a0,s0,1919
4000237c:	835ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:283
	sensor_i2c_write(i2c_ch_sel, 0x3780, 0xD9);
40002380:	0d900593          	li	a1,217
40002384:	78040513          	addi	a0,s0,1920
40002388:	829ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:284
	sensor_i2c_write(i2c_ch_sel, 0x3781, 0x03);
4000238c:	00300593          	li	a1,3
40002390:	78140513          	addi	a0,s0,1921
40002394:	81dff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:285
	sensor_i2c_write(i2c_ch_sel, 0x3782, 0xF5);
40002398:	0f500593          	li	a1,245
4000239c:	78240513          	addi	a0,s0,1922
400023a0:	811ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:286
	sensor_i2c_write(i2c_ch_sel, 0x3783, 0x06);
400023a4:	00600593          	li	a1,6
400023a8:	78340513          	addi	a0,s0,1923
400023ac:	805ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:287
	sensor_i2c_write(i2c_ch_sel, 0x3784, 0xA5);
400023b0:	0a500593          	li	a1,165
400023b4:	78440513          	addi	a0,s0,1924
400023b8:	ff8ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:288
	sensor_i2c_write(i2c_ch_sel, 0x3788, 0x0F);
400023bc:	00f00593          	li	a1,15
400023c0:	78840513          	addi	a0,s0,1928
400023c4:	fecff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:289
	sensor_i2c_write(i2c_ch_sel, 0x378A, 0xD9);
400023c8:	0d900593          	li	a1,217
400023cc:	78a40513          	addi	a0,s0,1930
400023d0:	fe0ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:290
	sensor_i2c_write(i2c_ch_sel, 0x378B, 0x03);
400023d4:	00300593          	li	a1,3
400023d8:	78b40513          	addi	a0,s0,1931
400023dc:	fd4ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:291
	sensor_i2c_write(i2c_ch_sel, 0x378C, 0xEB);
400023e0:	0eb00593          	li	a1,235
400023e4:	78c40513          	addi	a0,s0,1932
400023e8:	fc8ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:292
	sensor_i2c_write(i2c_ch_sel, 0x378D, 0x05);
400023ec:	00500593          	li	a1,5
400023f0:	78d40513          	addi	a0,s0,1933
400023f4:	fbcff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:293
	sensor_i2c_write(i2c_ch_sel, 0x378E, 0x87);
400023f8:	08700593          	li	a1,135
400023fc:	78e40513          	addi	a0,s0,1934
40002400:	fb0ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:294
	sensor_i2c_write(i2c_ch_sel, 0x378F, 0x06);
40002404:	00600593          	li	a1,6
40002408:	78f40513          	addi	a0,s0,1935
4000240c:	fa4ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:295
	sensor_i2c_write(i2c_ch_sel, 0x3790, 0xF5);
40002410:	0f500593          	li	a1,245
40002414:	79040513          	addi	a0,s0,1936
40002418:	f98ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:296
	sensor_i2c_write(i2c_ch_sel, 0x3792, 0x43);
4000241c:	04300593          	li	a1,67
40002420:	79240513          	addi	a0,s0,1938
40002424:	f8cff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:297
	sensor_i2c_write(i2c_ch_sel, 0x3794, 0x7A);
40002428:	07a00593          	li	a1,122
4000242c:	79440513          	addi	a0,s0,1940
40002430:	f80ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:298
	sensor_i2c_write(i2c_ch_sel, 0x3796, 0xA1);
40002434:	0a100593          	li	a1,161
40002438:	79640513          	addi	a0,s0,1942
4000243c:	f74ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:299
	sensor_i2c_write(i2c_ch_sel, 0x37B0, 0x37);// Xmaster pin high = 37h, else 36h
40002440:	03700593          	li	a1,55
40002444:	7b040513          	addi	a0,s0,1968
40002448:	f68ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:300
	sensor_i2c_write(i2c_ch_sel, 0x3E04, 0x0E);
4000244c:	00e00593          	li	a1,14
40002450:	e0448513          	addi	a0,s1,-508
40002454:	f5cff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:303
	/*End of additional mandatory settings */

	sensor_i2c_write(i2c_ch_sel, 0x30E8, 0x30);// Gain setting LSB
40002458:	03000593          	li	a1,48
4000245c:	0e840513          	addi	a0,s0,232
40002460:	f50ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:304
	sensor_i2c_write(i2c_ch_sel, 0x30E9, 0x00);// Gain setting MSB
40002464:	00000593          	li	a1,0
40002468:	0e940513          	addi	a0,s0,233
4000246c:	f44ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:305
	sensor_i2c_write(i2c_ch_sel, 0x3E04, 0x0E);// Mandatory value as per data sheet
40002470:	00e00593          	li	a1,14
40002474:	e0448513          	addi	a0,s1,-508
40002478:	f38ff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:306
	sensor_i2c_write(i2c_ch_sel, 0x3002, 0x00);// Master mode
4000247c:	00000593          	li	a1,0
40002480:	00240513          	addi	a0,s0,2
40002484:	f2cff0ef          	jal	ra,40001bb0 <sensor_i2c_write.isra.0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:307
	msdelay(1000);
40002488:	3e800513          	li	a0,1000
4000248c:	150000ef          	jal	ra,400025dc <msdelay>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:312

	sensor_i2c_write(i2c_ch_sel, 0x3000, 0x00);// STANDBY mode disabled
	//sensor_i2c_write_bits(0x301A, 0x0004, 1);  	//Enable Streaming
	for(i = 0; i < 50000; i++);
}
40002490:	00812403          	lw	s0,8(sp)
40002494:	00c12083          	lw	ra,12(sp)
40002498:	00412483          	lw	s1,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:309
	sensor_i2c_write(i2c_ch_sel, 0x3000, 0x00);// STANDBY mode disabled
4000249c:	00000593          	li	a1,0
400024a0:	00003537          	lui	a0,0x3
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:312
}
400024a4:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:309
	sensor_i2c_write(i2c_ch_sel, 0x3000, 0x00);// STANDBY mode disabled
400024a8:	f08ff06f          	j	40001bb0 <sensor_i2c_write.isra.0>

400024ac <gain_setting>:
gain_setting():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:316


void gain_setting( uint8_t i2c_ch_sel,uint16_t in_gain)
{
400024ac:	ff010113          	addi	sp,sp,-16
400024b0:	00812423          	sw	s0,8(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:317
sensor_i2c_write_gain(i2c_ch_sel, 0x30E8, in_gain);// Gain setting LSB
400024b4:	00003437          	lui	s0,0x3
400024b8:	0ff5f613          	andi	a2,a1,255
400024bc:	0e840593          	addi	a1,s0,232 # 30e8 <STACK_SIZE+0x28e8>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:316
{
400024c0:	00912223          	sw	s1,4(sp)
400024c4:	00112623          	sw	ra,12(sp)
400024c8:	00050493          	mv	s1,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:317
sensor_i2c_write_gain(i2c_ch_sel, 0x30E8, in_gain);// Gain setting LSB
400024cc:	e4cff0ef          	jal	ra,40001b18 <sensor_i2c_write_gain>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:318
sensor_i2c_write_gain(i2c_ch_sel, 0x30E9, 0);// Gain setting MSB
400024d0:	0e940593          	addi	a1,s0,233
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:320

}
400024d4:	00812403          	lw	s0,8(sp)
400024d8:	00c12083          	lw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:318
sensor_i2c_write_gain(i2c_ch_sel, 0x30E9, 0);// Gain setting MSB
400024dc:	00048513          	mv	a0,s1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:320
}
400024e0:	00412483          	lw	s1,4(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:318
sensor_i2c_write_gain(i2c_ch_sel, 0x30E9, 0);// Gain setting MSB
400024e4:	00000613          	li	a2,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:320
}
400024e8:	01010113          	addi	sp,sp,16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/imx334_corei2c/imx334_corei2c.c:318
sensor_i2c_write_gain(i2c_ch_sel, 0x30E9, 0);// Gain setting MSB
400024ec:	e2cff06f          	j	40001b18 <sensor_i2c_write_gain>

400024f0 <HDMI_tx_init>:
HDMI_tx_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:126
    status = I2C_wait_complete( this_i2c, I2C_NO_TIMEOUT );
	return status;
}

void HDMI_tx_init()
{
400024f0:	fd010113          	addi	sp,sp,-48
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:131
	uint8_t read_buffer[IIC_HDMI_OUT_CONFIG_LEN][2];
    uint32_t inc, i;
	uint8_t read_data;

	I2C_init( this_i2c, COREI2C_BASE_ADDR, 0x01, I2C_PCLK_DIV_256 );
400024f4:	00000693          	li	a3,0
400024f8:	00100613          	li	a2,1
400024fc:	700085b7          	lui	a1,0x70008
40002500:	8bc18513          	addi	a0,gp,-1860 # 40002e9c <g_i2c_instance_hdmi>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:126
{
40002504:	02112623          	sw	ra,44(sp)
40002508:	02812423          	sw	s0,40(sp)
4000250c:	02912223          	sw	s1,36(sp)
40002510:	01312e23          	sw	s3,28(sp)
40002514:	01412c23          	sw	s4,24(sp)
40002518:	03212023          	sw	s2,32(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:131
	I2C_init( this_i2c, COREI2C_BASE_ADDR, 0x01, I2C_PCLK_DIV_256 );
4000251c:	949fe0ef          	jal	ra,40000e64 <I2C_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:137

/*	GPIO_set_output(&g_gpio_out, GPIO_9, 0u);
	msdelay(5);
	GPIO_set_output(&g_gpio_out, GPIO_9, 1u); // hdmi reset*/

    msdelay(1);
40002520:	00100513          	li	a0,1
40002524:	0b8000ef          	jal	ra,400025dc <msdelay>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:145
    {
      //printf("transaction successful\n");
    }*/

   	//Configure ADV7511 Core Registers
   	for(inc = 0; inc < IIC_HDMI_OUT_CONFIG_LEN; ++inc)
40002528:	00001417          	auipc	s0,0x1
4000252c:	85840413          	addi	s0,s0,-1960 # 40002d80 <iic_hdmi_out_config>
40002530:	00001997          	auipc	s3,0x1
40002534:	8a298993          	addi	s3,s3,-1886 # 40002dd2 <iic_hdmi_out_config+0x52>
hdmi_i2c_tx_write():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:111
    I2C_write(this_i2c, i2c_div_address, (const uint8_t *)tx_buffer, write_length, I2C_RELEASE_BUS );
40002538:	87018a13          	addi	s4,gp,-1936 # 40002e50 <tx_buffer>
4000253c:	8bc18493          	addi	s1,gp,-1860 # 40002e9c <g_i2c_instance_hdmi>
HDMI_tx_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:147
   	{
		if(hdmi_i2c_tx_write(I2C_HDMI_OUT_ADDR, iic_hdmi_out_config[inc][0], iic_hdmi_out_config[inc][1]) == I2C_SUCCESS)
40002540:	00044903          	lbu	s2,0(s0)
40002544:	00144783          	lbu	a5,1(s0)
hdmi_i2c_tx_write():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:102
	if(data_reg){
40002548:	08090463          	beqz	s2,400025d0 <HDMI_tx_init+0xe0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:103
		tx_buffer[0] = data_reg;
4000254c:	87218823          	sb	s2,-1936(gp) # 40002e50 <tx_buffer>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:104
		tx_buffer[1] = data;
40002550:	86f188a3          	sb	a5,-1935(gp) # 40002e51 <tx_buffer+0x1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:105
		write_length = sizeof(data_reg) + sizeof(data);
40002554:	00200693          	li	a3,2
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:111
    I2C_write(this_i2c, i2c_div_address, (const uint8_t *)tx_buffer, write_length, I2C_RELEASE_BUS );
40002558:	00000713          	li	a4,0
4000255c:	000a0613          	mv	a2,s4
40002560:	03900593          	li	a1,57
40002564:	00048513          	mv	a0,s1
40002568:	9fdfe0ef          	jal	ra,40000f64 <I2C_write>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:113
    status = I2C_wait_complete( this_i2c, I2C_NO_TIMEOUT );
4000256c:	00000593          	li	a1,0
40002570:	00048513          	mv	a0,s1
40002574:	c25fe0ef          	jal	ra,40001198 <I2C_wait_complete>
hdmi_i2c_tx_read():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:120
	I2C_write_read( this_i2c, i2c_div_address, &data_reg, 1, readdata, readlen, I2C_RELEASE_BUS);
40002578:	00000813          	li	a6,0
4000257c:	00100793          	li	a5,1
40002580:	00e10713          	addi	a4,sp,14
40002584:	00100693          	li	a3,1
40002588:	00f10613          	addi	a2,sp,15
4000258c:	03900593          	li	a1,57
40002590:	00048513          	mv	a0,s1
40002594:	012107a3          	sb	s2,15(sp)
40002598:	ac1fe0ef          	jal	ra,40001058 <I2C_write_read>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:121
    status = I2C_wait_complete( this_i2c, I2C_NO_TIMEOUT );
4000259c:	00000593          	li	a1,0
400025a0:	00048513          	mv	a0,s1
400025a4:	00240413          	addi	s0,s0,2
400025a8:	bf1fe0ef          	jal	ra,40001198 <I2C_wait_complete>
HDMI_tx_init():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:145
   	for(inc = 0; inc < IIC_HDMI_OUT_CONFIG_LEN; ++inc)
400025ac:	f8899ae3          	bne	s3,s0,40002540 <HDMI_tx_init+0x50>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:161
   	    	//printf("transaction successful\n");
   		}

	}

}
400025b0:	02c12083          	lw	ra,44(sp)
400025b4:	02812403          	lw	s0,40(sp)
400025b8:	02412483          	lw	s1,36(sp)
400025bc:	02012903          	lw	s2,32(sp)
400025c0:	01c12983          	lw	s3,28(sp)
400025c4:	01812a03          	lw	s4,24(sp)
400025c8:	03010113          	addi	sp,sp,48
400025cc:	00008067          	ret
hdmi_i2c_tx_write():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:107
	tx_buffer[0] = data;
400025d0:	86f18823          	sb	a5,-1936(gp) # 40002e50 <tx_buffer>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/hdmi_config/hdmi_tx.c:108
	write_length = sizeof(data);
400025d4:	00100693          	li	a3,1
400025d8:	f81ff06f          	j	40002558 <HDMI_tx_init+0x68>

400025dc <msdelay>:
msdelay():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:19
extern volatile uint32_t g_100ms_count1;
extern volatile uint32_t g_ms_count;

void msdelay(uint32_t tms)
{
    g_ms_count = tms;
400025dc:	8aa1aa23          	sw	a0,-1868(gp) # 40002e94 <g_ms_count>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:20
    g_100ms_count1 = 0;
400025e0:	9c01a823          	sw	zero,-1584(gp) # 40002fb0 <g_100ms_count1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:21
    timerdone = 1;
400025e4:	00100793          	li	a5,1
400025e8:	82f1a223          	sw	a5,-2012(gp) # 40002e04 <timerdone>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:22
    while(timerdone != 0)
400025ec:	82418713          	addi	a4,gp,-2012 # 40002e04 <timerdone>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:22 (discriminator 1)
400025f0:	00072783          	lw	a5,0(a4)
400025f4:	fe079ee3          	bnez	a5,400025f0 <msdelay+0x14>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/delay/msdelay.c:27
	{
		//busy wait loop
	}

}
400025f8:	00008067          	ret

400025fc <SysTick_Handler>:
SysTick_Handler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:161
 */
void SysTick_Handler(void) {

//  g_state = (~g_state) & 0x01;

    if(timerdone == 1)
400025fc:	82418793          	addi	a5,gp,-2012 # 40002e04 <timerdone>
40002600:	0007a703          	lw	a4,0(a5)
40002604:	00100793          	li	a5,1
40002608:	02f71463          	bne	a4,a5,40002630 <SysTick_Handler+0x34>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:163
    {
        g_100ms_count1 += 1;
4000260c:	9d018713          	addi	a4,gp,-1584 # 40002fb0 <g_100ms_count1>
40002610:	00072783          	lw	a5,0(a4)
40002614:	00178793          	addi	a5,a5,1
40002618:	9cf1a823          	sw	a5,-1584(gp) # 40002fb0 <g_100ms_count1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:164
        if(g_ms_count <= g_100ms_count1)
4000261c:	8b418793          	addi	a5,gp,-1868 # 40002e94 <g_ms_count>
40002620:	0007a683          	lw	a3,0(a5)
40002624:	00072783          	lw	a5,0(a4)
40002628:	00d7e463          	bltu	a5,a3,40002630 <SysTick_Handler+0x34>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:165
            timerdone = 0;
4000262c:	8201a223          	sw	zero,-2012(gp) # 40002e04 <timerdone>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:168
    }

}
40002630:	00008067          	ret

40002634 <MSYS_EI0_IRQHandler>:
MSYS_EI0_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:186

//    I2C_isr(&g_i2c_instance_hdmi);
//}

uint8_t MSYS_EI0_IRQHandler(void)
{
40002634:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:187
    I2C_isr(&g_i2c_instance_cam2);
40002638:	95418513          	addi	a0,gp,-1708 # 40002f34 <g_i2c_instance_cam2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:186
{
4000263c:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:187
    I2C_isr(&g_i2c_instance_cam2);
40002640:	b99fe0ef          	jal	ra,400011d8 <I2C_isr>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:189
    return (EXT_IRQ_KEEP_ENABLED);
}
40002644:	00c12083          	lw	ra,12(sp)
40002648:	00000513          	li	a0,0
4000264c:	01010113          	addi	sp,sp,16
40002650:	00008067          	ret

40002654 <MSYS_EI1_IRQHandler>:
MSYS_EI1_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:192

uint8_t MSYS_EI1_IRQHandler(void)
{
40002654:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:193
    I2C_isr(&g_i2c_instance_hdmi);
40002658:	8bc18513          	addi	a0,gp,-1860 # 40002e9c <g_i2c_instance_hdmi>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:192
{
4000265c:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:193
    I2C_isr(&g_i2c_instance_hdmi);
40002660:	b79fe0ef          	jal	ra,400011d8 <I2C_isr>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:195
    return (EXT_IRQ_KEEP_ENABLED);
}
40002664:	00c12083          	lw	ra,12(sp)
40002668:	00000513          	li	a0,0
4000266c:	01010113          	addi	sp,sp,16
40002670:	00008067          	ret

40002674 <MSYS_EI2_IRQHandler>:
MSYS_EI2_IRQHandler():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:198

uint8_t MSYS_EI2_IRQHandler(void)
{
40002674:	ff010113          	addi	sp,sp,-16
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:199
    I2C_isr(&g_i2c_instance_cam1);
40002678:	9d818513          	addi	a0,gp,-1576 # 40002fb8 <g_i2c_instance_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:198
{
4000267c:	00112623          	sw	ra,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:199
    I2C_isr(&g_i2c_instance_cam1);
40002680:	b59fe0ef          	jal	ra,400011d8 <I2C_isr>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:201
    return (EXT_IRQ_KEEP_ENABLED);
}
40002684:	00c12083          	lw	ra,12(sp)
40002688:	00000513          	li	a0,0
4000268c:	01010113          	addi	sp,sp,16
40002690:	00008067          	ret

40002694 <set_bgr_gain>:
set_bgr_gain():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:289



void set_bgr_gain()
{
    contrast_scl = (325*(contrast+128) / (387 - contrast))>>5u;
40002694:	9381d503          	lhu	a0,-1736(gp) # 40002f18 <contrast>
40002698:	08050513          	addi	a0,a0,128 # 3080 <STACK_SIZE+0x2880>
4000269c:	00251793          	slli	a5,a0,0x2
400026a0:	00a787b3          	add	a5,a5,a0
400026a4:	9381d703          	lhu	a4,-1736(gp) # 40002f18 <contrast>
400026a8:	00679513          	slli	a0,a5,0x6
400026ac:	18300593          	li	a1,387
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:288
{
400026b0:	fd010113          	addi	sp,sp,-48
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:289
    contrast_scl = (325*(contrast+128) / (387 - contrast))>>5u;
400026b4:	00a78533          	add	a0,a5,a0
400026b8:	40e585b3          	sub	a1,a1,a4
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:288
{
400026bc:	02112623          	sw	ra,44(sp)
400026c0:	02812423          	sw	s0,40(sp)
400026c4:	02912223          	sw	s1,36(sp)
400026c8:	03212023          	sw	s2,32(sp)
400026cc:	01312e23          	sw	s3,28(sp)
400026d0:	01412c23          	sw	s4,24(sp)
400026d4:	01512a23          	sw	s5,20(sp)
400026d8:	01612823          	sw	s6,16(sp)
400026dc:	01712623          	sw	s7,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:289
    contrast_scl = (325*(contrast+128) / (387 - contrast))>>5u;
400026e0:	588000ef          	jal	ra,40002c68 <__divsi3>
400026e4:	88818493          	addi	s1,gp,-1912 # 40002e68 <contrast_scl>
400026e8:	40555513          	srai	a0,a0,0x5
400026ec:	00a4a023          	sw	a0,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:290
    r_const = (r_gain * contrast_scl)/10;
400026f0:	88c1d503          	lhu	a0,-1908(gp) # 40002e6c <r_gain>
400026f4:	0004a583          	lw	a1,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    g_const = (g_gain * contrast_scl/10);
    b_const = (b_gain * contrast_scl)/10;
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
400026f8:	89018913          	addi	s2,gp,-1904 # 40002e70 <second_const>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:295

    bayer0 = 0x00;      // BI1
400026fc:	8b018b93          	addi	s7,gp,-1872 # 40002e90 <bayer0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:290
    r_const = (r_gain * contrast_scl)/10;
40002700:	544000ef          	jal	ra,40002c44 <__mulsi3>
40002704:	00a00593          	li	a1,10
40002708:	568000ef          	jal	ra,40002c70 <__udivsi3>
4000270c:	92a19423          	sh	a0,-1752(gp) # 40002f08 <r_const>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:291
    g_const = (g_gain * contrast_scl/10);
40002710:	9481d503          	lhu	a0,-1720(gp) # 40002f28 <g_gain>
40002714:	0004a583          	lw	a1,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:298
    bayer1 = 0x00;      // BI2
    bayer4k = 0x00;     // 4k BI
    ie_ver = 0x00;
40002718:	93418b13          	addi	s6,gp,-1740 # 40002f14 <ie_ver>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:300

    cam_IE_IA_Constant  = 0x00;
4000271c:	92c18a93          	addi	s5,gp,-1748 # 40002f0c <cam_IE_IA_Constant>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:291
    g_const = (g_gain * contrast_scl/10);
40002720:	524000ef          	jal	ra,40002c44 <__mulsi3>
40002724:	00a00593          	li	a1,10
40002728:	548000ef          	jal	ra,40002c70 <__udivsi3>
4000272c:	94a19023          	sh	a0,-1728(gp) # 40002f20 <g_const>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:292
    b_const = (b_gain * contrast_scl)/10;
40002730:	8841d503          	lhu	a0,-1916(gp) # 40002e64 <b_gain>
40002734:	0004a583          	lw	a1,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:302

    scale_IE_IA_Constant  = 0x00;
40002738:	94c18a13          	addi	s4,gp,-1716 # 40002f2c <scale_IE_IA_Constant>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:304

    cam_4K_IE_IA_Constant  = 0x00;
4000273c:	8a818993          	addi	s3,gp,-1880 # 40002e88 <cam_4K_IE_IA_Constant>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:292
    b_const = (b_gain * contrast_scl)/10;
40002740:	504000ef          	jal	ra,40002c44 <__mulsi3>
40002744:	00a00593          	li	a1,10
40002748:	528000ef          	jal	ra,40002c70 <__udivsi3>
4000274c:	8aa19123          	sh	a0,-1886(gp) # 40002e82 <b_const>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
40002750:	9c41d403          	lhu	s0,-1596(gp) # 40002fa4 <brightness>
40002754:	0004a503          	lw	a0,0(s1)
40002758:	00a00593          	li	a1,10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:296
    bayer1 = 0x00;      // BI2
4000275c:	88018493          	addi	s1,gp,-1920 # 40002e60 <bayer1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
40002760:	00751513          	slli	a0,a0,0x7
40002764:	50c000ef          	jal	ra,40002c70 <__udivsi3>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:306

    dpc_bayer_cam1 = 0x01;
40002768:	00100693          	li	a3,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:307
    det_thr1_cam1 = 0x1E;
4000276c:	01e00713          	li	a4,30
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:306
    dpc_bayer_cam1 = 0x01;
40002770:	8ad19223          	sh	a3,-1884(gp) # 40002e84 <dpc_bayer_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:307
    det_thr1_cam1 = 0x1E;
40002774:	94e19123          	sh	a4,-1726(gp) # 40002f22 <det_thr1_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
40002778:	40a40533          	sub	a0,s0,a0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:308
    det_thr2_cam1 = 0x0A;
4000277c:	00a00793          	li	a5,10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:297
    bayer4k = 0x00;     // 4k BI
40002780:	9cc18413          	addi	s0,gp,-1588 # 40002fac <bayer4k>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
40002784:	00751513          	slli	a0,a0,0x7
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:308
    det_thr2_cam1 = 0x0A;
40002788:	92f19823          	sh	a5,-1744(gp) # 40002f10 <det_thr2_cam1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:310

    dpc_bayer_cam2_scale = 0x01;
4000278c:	9cd19323          	sh	a3,-1594(gp) # 40002fa6 <dpc_bayer_cam2_scale>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:311
    det_thr1_cam2_scale = 0x1E;
40002790:	8ae19323          	sh	a4,-1882(gp) # 40002e86 <det_thr1_cam2_scale>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:312
    det_thr2_cam2_scale = 0x0A;
40002794:	9cf19023          	sh	a5,-1600(gp) # 40002fa0 <det_thr2_cam2_scale>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:293
    second_const = 128 * (brightness - ((128*contrast_scl)/10));
40002798:	00a92023          	sw	a0,0(s2)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:318

    dpc_bayer_cam1_4k = 0x01;
    det_thr1_cam1_4k = 0x1E;
    det_thr2_cam1_4k = 0x0A; 

    axi4litewrite(BAYER_ADDR_0,bayer0);
4000279c:	00000593          	li	a1,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:295
    bayer0 = 0x00;      // BI1
400027a0:	000b9023          	sh	zero,0(s7)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:296
    bayer1 = 0x00;      // BI2
400027a4:	00049023          	sh	zero,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:297
    bayer4k = 0x00;     // 4k BI
400027a8:	00041023          	sh	zero,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:298
    ie_ver = 0x00;
400027ac:	000b2023          	sw	zero,0(s6)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:300
    cam_IE_IA_Constant  = 0x00;
400027b0:	000aa023          	sw	zero,0(s5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:302
    scale_IE_IA_Constant  = 0x00;
400027b4:	000a2023          	sw	zero,0(s4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:304
    cam_4K_IE_IA_Constant  = 0x00;
400027b8:	0009a023          	sw	zero,0(s3)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:318
    axi4litewrite(BAYER_ADDR_0,bayer0);
400027bc:	60010537          	lui	a0,0x60010
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:314
    dpc_bayer_cam1_4k = 0x01;
400027c0:	8ad19023          	sh	a3,-1888(gp) # 40002e80 <dpc_bayer_cam1_4k>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:315
    det_thr1_cam1_4k = 0x1E;
400027c4:	8ae19723          	sh	a4,-1874(gp) # 40002e8e <det_thr1_cam1_4k>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:316
    det_thr2_cam1_4k = 0x0A; 
400027c8:	88f19123          	sh	a5,-1918(gp) # 40002e62 <det_thr2_cam1_4k>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:318
    axi4litewrite(BAYER_ADDR_0,bayer0);
400027cc:	b44ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:319
            bayer0 = (uint16_t)axi4literead(BAYER_ADDR_0);
400027d0:	60010537          	lui	a0,0x60010
400027d4:	b34ff0ef          	jal	ra,40001b08 <axi4literead>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:320
    axi4litewrite(BAYER_ADDR_1,bayer1);
400027d8:	0004d583          	lhu	a1,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:319
            bayer0 = (uint16_t)axi4literead(BAYER_ADDR_0);
400027dc:	00ab9023          	sh	a0,0(s7)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:320
    axi4litewrite(BAYER_ADDR_1,bayer1);
400027e0:	60020537          	lui	a0,0x60020
400027e4:	b2cff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:321
            bayer1 = (uint16_t)axi4literead(BAYER_ADDR_1);
400027e8:	60020537          	lui	a0,0x60020
400027ec:	b1cff0ef          	jal	ra,40001b08 <axi4literead>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:322
    axi4litewrite(BAYER_ADDR_4k,bayer4k);
400027f0:	00045583          	lhu	a1,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:321
            bayer1 = (uint16_t)axi4literead(BAYER_ADDR_1);
400027f4:	00a49023          	sh	a0,0(s1)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:322
    axi4litewrite(BAYER_ADDR_4k,bayer4k);
400027f8:	60030537          	lui	a0,0x60030
400027fc:	b14ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:323
            bayer4k = (uint16_t)axi4literead(BAYER_ADDR_4k);
40002800:	60030537          	lui	a0,0x60030
40002804:	b04ff0ef          	jal	ra,40001b08 <axi4literead>
40002808:	00a41023          	sh	a0,0(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:326

            //IE1 AXI4-Lite write operation
                    axi4litewrite(R_CONST_ADDR,r_const);
4000280c:	60050437          	lui	s0,0x60050
40002810:	00840513          	addi	a0,s0,8 # 60050008 <__stack_top+0x2004c7d8>
40002814:	9281d583          	lhu	a1,-1752(gp) # 40002f08 <r_const>
40002818:	af8ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:327
                    axi4litewrite(G_CONST_ADDR,g_const);
4000281c:	00c40513          	addi	a0,s0,12
40002820:	9401d583          	lhu	a1,-1728(gp) # 40002f20 <g_const>
40002824:	aecff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:328
                    axi4litewrite(B_CONST_ADDR,b_const);
40002828:	01040513          	addi	a0,s0,16
4000282c:	8a21d583          	lhu	a1,-1886(gp) # 40002e82 <b_const>
40002830:	ae0ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:329
                    axi4litewrite(SECOND_CONST_ADDR,second_const);
40002834:	00092583          	lw	a1,0(s2)
40002838:	01440513          	addi	a0,s0,20
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:341
            ie_ver = (uint32_t)axi4literead(R_CONST_ADDR);

                    cam_IE_IA_Constant = (uint32_t)axi4literead(RGB_SUM_ADDR);

                //IE2 AXI4-Lite write operation
                    axi4litewrite(R_CONST_ADDR_0,r_const);
4000283c:	600604b7          	lui	s1,0x60060
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:329
                    axi4litewrite(SECOND_CONST_ADDR,second_const);
40002840:	ad0ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:336
            ie_ver = (uint32_t)axi4literead(R_CONST_ADDR);
40002844:	00840513          	addi	a0,s0,8
40002848:	ac0ff0ef          	jal	ra,40001b08 <axi4literead>
4000284c:	00ab2023          	sw	a0,0(s6)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:338
                    cam_IE_IA_Constant = (uint32_t)axi4literead(RGB_SUM_ADDR);
40002850:	70009537          	lui	a0,0x70009
40002854:	03850513          	addi	a0,a0,56 # 70009038 <__stack_top+0x30005808>
40002858:	ab0ff0ef          	jal	ra,40001b08 <axi4literead>
4000285c:	00aaa023          	sw	a0,0(s5)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:341
                    axi4litewrite(R_CONST_ADDR_0,r_const);
40002860:	9281d583          	lhu	a1,-1752(gp) # 40002f08 <r_const>
40002864:	00848513          	addi	a0,s1,8 # 60060008 <__stack_top+0x2005c7d8>
40002868:	aa8ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:342
                    axi4litewrite(G_CONST_ADDR_0,g_const);
4000286c:	00c48513          	addi	a0,s1,12
40002870:	9401d583          	lhu	a1,-1728(gp) # 40002f20 <g_const>
40002874:	a9cff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:343
                    axi4litewrite(B_CONST_ADDR_0,b_const);
40002878:	01048513          	addi	a0,s1,16
4000287c:	8a21d583          	lhu	a1,-1886(gp) # 40002e82 <b_const>
40002880:	a90ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:344
                    axi4litewrite(SECOND_CONST_ADDR_0,second_const);
40002884:	00092583          	lw	a1,0(s2)
40002888:	01448513          	addi	a0,s1,20
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:349

                    scale_IE_IA_Constant = (uint32_t)axi4literead(INTENSITY_AVARAGE_0);

                //4k IE3 AXI4-Lite write operation
                    axi4litewrite(R_CONST_ADDR_1,r_const);
4000288c:	600704b7          	lui	s1,0x60070
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:344
                    axi4litewrite(SECOND_CONST_ADDR_0,second_const);
40002890:	a80ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:346
                    scale_IE_IA_Constant = (uint32_t)axi4literead(INTENSITY_AVARAGE_0);
40002894:	01840513          	addi	a0,s0,24
40002898:	a70ff0ef          	jal	ra,40001b08 <axi4literead>
4000289c:	00aa2023          	sw	a0,0(s4)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:349
                    axi4litewrite(R_CONST_ADDR_1,r_const);
400028a0:	9281d583          	lhu	a1,-1752(gp) # 40002f08 <r_const>
400028a4:	00848513          	addi	a0,s1,8 # 60070008 <__stack_top+0x2006c7d8>
400028a8:	a68ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:350
                    axi4litewrite(G_CONST_ADDR_1,g_const);
400028ac:	00c48513          	addi	a0,s1,12
400028b0:	9401d583          	lhu	a1,-1728(gp) # 40002f20 <g_const>
400028b4:	a5cff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:351
                    axi4litewrite(B_CONST_ADDR_1,b_const);
400028b8:	01048513          	addi	a0,s1,16
400028bc:	8a21d583          	lhu	a1,-1886(gp) # 40002e82 <b_const>
400028c0:	a50ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:352
                    axi4litewrite(SECOND_CONST_ADDR_1,second_const);
400028c4:	00092583          	lw	a1,0(s2)
400028c8:	01448513          	addi	a0,s1,20
400028cc:	a44ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:354

                    cam_4K_IE_IA_Constant = (uint32_t)axi4literead(INTENSITY_AVARAGE_1);
400028d0:	01840513          	addi	a0,s0,24
400028d4:	a34ff0ef          	jal	ra,40001b08 <axi4literead>
400028d8:	00a9a023          	sw	a0,0(s3)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:356

                    axi4litewrite(ALPHA_ADDR,alpha);
400028dc:	60040537          	lui	a0,0x60040
400028e0:	9d41d583          	lhu	a1,-1580(gp) # 40002fb4 <alpha>
400028e4:	01450513          	addi	a0,a0,20 # 60040014 <__stack_top+0x2003c7e4>
400028e8:	a28ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:359

                    //---- DPC CAM1
                    axi4litewrite(DPC_enable_CAM1,dpc_sel);
400028ec:	60080437          	lui	s0,0x60080
400028f0:	00c40513          	addi	a0,s0,12 # 6008000c <__stack_top+0x2007c7dc>
400028f4:	8ac1d583          	lhu	a1,-1876(gp) # 40002e8c <dpc_sel>
400028f8:	a18ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:360
                    axi4litewrite(DPC_bayer_CAM1,dpc_bayer);
400028fc:	9c21d583          	lhu	a1,-1598(gp) # 40002fa2 <dpc_bayer>
40002900:	60080537          	lui	a0,0x60080
40002904:	a0cff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:361
                    axi4litewrite(DET_THR1_ADDR_CAM1,det_thr1);
40002908:	00440513          	addi	a0,s0,4
4000290c:	9501d583          	lhu	a1,-1712(gp) # 40002f30 <det_thr1>
40002910:	a00ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:362
                    axi4litewrite(DET_THR2_ADDR_CAM1,det_thr2);
40002914:	00840513          	addi	a0,s0,8
40002918:	8861d583          	lhu	a1,-1914(gp) # 40002e66 <det_thr2>
4000291c:	9f4ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:365

                    //---- DPC CAM2 for Scale
                    axi4litewrite(DPC_enable_CAM2_SCALE,dpc_sel);
40002920:	60090437          	lui	s0,0x60090
40002924:	00c40513          	addi	a0,s0,12 # 6009000c <__stack_top+0x2008c7dc>
40002928:	8ac1d583          	lhu	a1,-1876(gp) # 40002e8c <dpc_sel>
4000292c:	9e4ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:366
                    axi4litewrite(DPC_bayer_CAM2_SCALE,dpc_bayer);
40002930:	9c21d583          	lhu	a1,-1598(gp) # 40002fa2 <dpc_bayer>
40002934:	60090537          	lui	a0,0x60090
40002938:	9d8ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:367
                    axi4litewrite(DET_THR1_ADDR_CAM2_SCALE,det_thr1);
4000293c:	00440513          	addi	a0,s0,4
40002940:	9501d583          	lhu	a1,-1712(gp) # 40002f30 <det_thr1>
40002944:	9ccff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:368
                    axi4litewrite(DET_THR2_ADDR_CAM2_SCALE,det_thr2);
40002948:	00840513          	addi	a0,s0,8
4000294c:	8861d583          	lhu	a1,-1914(gp) # 40002e66 <det_thr2>
40002950:	9c0ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:371

                    //---- DPC CAM1 for 4K
                    axi4litewrite(DPC_enable_CAM1_4K,dpc_sel);
40002954:	600a0437          	lui	s0,0x600a0
40002958:	00c40513          	addi	a0,s0,12 # 600a000c <__stack_top+0x2009c7dc>
4000295c:	8ac1d583          	lhu	a1,-1876(gp) # 40002e8c <dpc_sel>
40002960:	9b0ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:372
                    axi4litewrite(DPC_bayer_CAM1_4K,dpc_bayer);
40002964:	9c21d583          	lhu	a1,-1598(gp) # 40002fa2 <dpc_bayer>
40002968:	600a0537          	lui	a0,0x600a0
4000296c:	9a4ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:373
                    axi4litewrite(DET_THR1_ADDR_4K,det_thr1);
40002970:	00440513          	addi	a0,s0,4
40002974:	9501d583          	lhu	a1,-1712(gp) # 40002f30 <det_thr1>
40002978:	998ff0ef          	jal	ra,40001b10 <axi4litewrite>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:374
                    axi4litewrite(DET_THR2_ADDR_4K,det_thr2);
4000297c:	00840513          	addi	a0,s0,8
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:376

}
40002980:	02812403          	lw	s0,40(sp)
40002984:	02c12083          	lw	ra,44(sp)
40002988:	02412483          	lw	s1,36(sp)
4000298c:	02012903          	lw	s2,32(sp)
40002990:	01c12983          	lw	s3,28(sp)
40002994:	01812a03          	lw	s4,24(sp)
40002998:	01412a83          	lw	s5,20(sp)
4000299c:	01012b03          	lw	s6,16(sp)
400029a0:	00c12b83          	lw	s7,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:374
                    axi4litewrite(DET_THR2_ADDR_4K,det_thr2);
400029a4:	8861d583          	lhu	a1,-1914(gp) # 40002e66 <det_thr2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:376
}
400029a8:	03010113          	addi	sp,sp,48
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:374
                    axi4litewrite(DET_THR2_ADDR_4K,det_thr2);
400029ac:	964ff06f          	j	40001b10 <axi4litewrite>

400029b0 <main>:
main():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:209
int main(int argc, char **argv) {
400029b0:	fd010113          	addi	sp,sp,-48
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:216
    GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
400029b4:	00200613          	li	a2,2
400029b8:	700055b7          	lui	a1,0x70005
400029bc:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:209
int main(int argc, char **argv) {
400029c0:	02112623          	sw	ra,44(sp)
400029c4:	02812423          	sw	s0,40(sp)
400029c8:	02912223          	sw	s1,36(sp)
400029cc:	03212023          	sw	s2,32(sp)
400029d0:	01312e23          	sw	s3,28(sp)
400029d4:	01412c23          	sw	s4,24(sp)
400029d8:	01512a23          	sw	s5,20(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:213
    counter = 0;
400029dc:	00012623          	sw	zero,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:216
    GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
400029e0:	e7dfe0ef          	jal	ra,4000185c <GPIO_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:218
    GPIO_set_output(&g_gpio_out, LED1, 1);
400029e4:	00100613          	li	a2,1
400029e8:	00000593          	li	a1,0
400029ec:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
400029f0:	f89fe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:222
    MRV_systick_config(SYS_CLK_FREQ / 1000);///100msec delay
400029f4:	0000c537          	lui	a0,0xc
400029f8:	00000593          	li	a1,0
400029fc:	35050513          	addi	a0,a0,848 # c350 <STACK_SIZE+0xbb50>
40002a00:	8e0fe0ef          	jal	ra,40000ae0 <MRV_systick_config>
MRV_enable_local_irq():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
    set_csr(mie, mask);
40002a04:	010007b7          	lui	a5,0x1000
40002a08:	3047a7f3          	csrrs	a5,mie,a5
40002a0c:	020007b7          	lui	a5,0x2000
40002a10:	3047a7f3          	csrrs	a5,mie,a5
40002a14:	040007b7          	lui	a5,0x4000
40002a18:	3047a7f3          	csrrs	a5,mie,a5
main():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:238
    HAL_enable_interrupts();
40002a1c:	b2cfe0ef          	jal	ra,40000d48 <HAL_enable_interrupts>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:240
    GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 0u);
40002a20:	00000613          	li	a2,0
40002a24:	00400593          	li	a1,4
40002a28:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a2c:	f4dfe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:241
    GPIO_set_output(&g_gpio_out, LED2, 1);
40002a30:	00100613          	li	a2,1
40002a34:	00100593          	li	a1,1
40002a38:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a3c:	f3dfe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:242
    HDMI_tx_init();
40002a40:	ab1ff0ef          	jal	ra,400024f0 <HDMI_tx_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:245
    GPIO_set_output(&g_gpio_out, CAM1_RST, 1u);
40002a44:	00100613          	li	a2,1
40002a48:	00800593          	li	a1,8
40002a4c:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a50:	f29fe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:246
    GPIO_set_output(&g_gpio_out, CAM2_RST, 1u);
40002a54:	00100613          	li	a2,1
40002a58:	00700593          	li	a1,7
40002a5c:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a60:	f19fe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:247
    GPIO_set_output(&g_gpio_out, CAM_CLK_EN, 0u);
40002a64:	00000613          	li	a2,0
40002a68:	00900593          	li	a1,9
40002a6c:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a70:	f09fe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:248
    imx334_cam_init();
40002a74:	9e8ff0ef          	jal	ra,40001c5c <imx334_cam_init>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:249
    imx334_cam_reginit(1u);
40002a78:	00100513          	li	a0,1
40002a7c:	a80ff0ef          	jal	ra,40001cfc <imx334_cam_reginit>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:251
    GPIO_set_output(&g_gpio_out, LED3, 1);
40002a80:	00100613          	li	a2,1
40002a84:	00200593          	li	a1,2
40002a88:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002a8c:	eedfe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:252
    msdelay(1000);
40002a90:	3e800513          	li	a0,1000
40002a94:	b49ff0ef          	jal	ra,400025dc <msdelay>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:253
    GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 1u);
40002a98:	00100613          	li	a2,1
40002a9c:	00400593          	li	a1,4
40002aa0:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002aa4:	ed5fe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:254
    GPIO_set_output(&g_gpio_out, LED4, 1);
40002aa8:	00100613          	li	a2,1
40002aac:	00300593          	li	a1,3
40002ab0:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
gain_cal():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:413
    const int16_t hysteresis=4;
    int16_t step;
        if(total_average < (good_average - hysteresis))
            step = 1;
        else
            if(total_average > (good_average + hysteresis))
40002ab4:	19f494b7          	lui	s1,0x19f49
gain_cal1():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:437
    const int16_t good_average=100;
    const int16_t hysteresis=4;
        if(total_average1 < (good_average - hysteresis))
            step1 = 1;
        else
            if(total_average1 > (good_average + hysteresis))
40002ab8:	02e25937          	lui	s2,0x2e25
main():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:254
    GPIO_set_output(&g_gpio_out, LED4, 1);
40002abc:	ebdfe0ef          	jal	ra,40001978 <GPIO_set_output>
gain_cal():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:413
            if(total_average > (good_average + hysteresis))
40002ac0:	80048493          	addi	s1,s1,-2048 # 19f48800 <STACK_SIZE+0x19f48000>
gain_cal1():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:437
            if(total_average1 > (good_average + hysteresis))
40002ac4:	80090913          	addi	s2,s2,-2048 # 2e24800 <STACK_SIZE+0x2e24000>
gain_cal():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:418
        in_gain = in_gain + step;
40002ac8:	00000a17          	auipc	s4,0x0
40002acc:	318a0a13          	addi	s4,s4,792 # 40002de0 <__sdata_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:420
        if(in_gain < 5)
40002ad0:	00400993          	li	s3,4
gain_cal1():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:442
                step1 = -1;
            else
                step1 = 0;

        in_gain1 = in_gain1 + step1;
40002ad4:	00000a97          	auipc	s5,0x0
40002ad8:	30ea8a93          	addi	s5,s5,782 # 40002de2 <in_gain1>
main():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:260
        msdelay(30);
40002adc:	01e00513          	li	a0,30
40002ae0:	afdff0ef          	jal	ra,400025dc <msdelay>
auto_brightness():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:381
    r_gain = (uint16_t)(*(volatile int*) R_GAIN_ADDR);
40002ae4:	70009437          	lui	s0,0x70009
40002ae8:	02042783          	lw	a5,32(s0) # 70009020 <__stack_top+0x300057f0>
40002aec:	88f19623          	sh	a5,-1908(gp) # 40002e6c <r_gain>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:382
    g_gain = (uint16_t)(*(volatile int*) G_GAIN_ADDR);
40002af0:	02442783          	lw	a5,36(s0)
40002af4:	94f19423          	sh	a5,-1720(gp) # 40002f28 <g_gain>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:383
    b_gain = (uint16_t)(*(volatile int*) B_GAIN_ADDR);
40002af8:	02842783          	lw	a5,40(s0)
40002afc:	88f19223          	sh	a5,-1916(gp) # 40002e64 <b_gain>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:384
    contrast = (uint16_t)(*(volatile int*) CONTRAST_ADDR);//8;//Range 3 - 30 (divided by 10 in later steps)
40002b00:	03042783          	lw	a5,48(s0)
40002b04:	92f19c23          	sh	a5,-1736(gp) # 40002f18 <contrast>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:385
    brightness = (uint16_t)(*(volatile int*) BRIGHTNESS_ADDR);
40002b08:	03442783          	lw	a5,52(s0)
40002b0c:	9cf19223          	sh	a5,-1596(gp) # 40002fa4 <brightness>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:386
    alpha = (uint16_t)(*(volatile int*) ALPHA_ADDR_IN);
40002b10:	04042783          	lw	a5,64(s0)
40002b14:	9cf19a23          	sh	a5,-1580(gp) # 40002fb4 <alpha>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:388
    dpc_sel    = (uint16_t)(*(volatile int*) DET_SEL_ADDR  );
40002b18:	10c42783          	lw	a5,268(s0)
40002b1c:	8af19623          	sh	a5,-1876(gp) # 40002e8c <dpc_sel>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:389
    dpc_bayer  = (uint16_t)(*(volatile int*) DET_BAYER_ADDR);
40002b20:	11042783          	lw	a5,272(s0)
40002b24:	9cf19123          	sh	a5,-1598(gp) # 40002fa2 <dpc_bayer>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:390
    det_thr1   = (uint16_t)(*(volatile int*) DET_THR1_ADDR );
40002b28:	11442783          	lw	a5,276(s0)
40002b2c:	94f19823          	sh	a5,-1712(gp) # 40002f30 <det_thr1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:391
    det_thr2   = (uint16_t)(*(volatile int*) DET_THR2_ADDR );
40002b30:	11842783          	lw	a5,280(s0)
40002b34:	88f19323          	sh	a5,-1914(gp) # 40002e66 <det_thr2>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:393
    set_bgr_gain();
40002b38:	b5dff0ef          	jal	ra,40002694 <set_bgr_gain>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:395
    uint32_t total_sum =  (uint32_t)(*(volatile int*) RGB_SUM_ADDR);
40002b3c:	03842783          	lw	a5,56(s0)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:397
    uint32_t total_sum1 =  (uint32_t)(*(volatile int*) RGB_SUM_ADDR1);
40002b40:	03c42403          	lw	s0,60(s0)
gain_cal():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:410
        if(total_average < (good_average - hysteresis))
40002b44:	17bb06b7          	lui	a3,0x17bb0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:411
            step = 1;
40002b48:	00100713          	li	a4,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:410
        if(total_average < (good_average - hysteresis))
40002b4c:	00d7ea63          	bltu	a5,a3,40002b60 <main+0x1b0>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:413
            if(total_average > (good_average + hysteresis))
40002b50:	0097b733          	sltu	a4,a5,s1
40002b54:	fff70713          	addi	a4,a4,-1
40002b58:	01071713          	slli	a4,a4,0x10
40002b5c:	41075713          	srai	a4,a4,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:418
        in_gain = in_gain + step;
40002b60:	000a5783          	lhu	a5,0(s4)
40002b64:	00f70733          	add	a4,a4,a5
40002b68:	01071713          	slli	a4,a4,0x10
40002b6c:	01075713          	srli	a4,a4,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:421
            in_gain = 5;
40002b70:	00500793          	li	a5,5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:420
        if(in_gain < 5)
40002b74:	0ae9fa63          	bgeu	s3,a4,40002c28 <main+0x278>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:423
            if(in_gain >= 100)
40002b78:	06300793          	li	a5,99
40002b7c:	0ae7e463          	bltu	a5,a4,40002c24 <main+0x274>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:418
        in_gain = in_gain + step;
40002b80:	00000797          	auipc	a5,0x0
40002b84:	26e79023          	sh	a4,608(a5) # 40002de0 <__sdata_load>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:426
    gain_setting(1u,in_gain);
40002b88:	00000597          	auipc	a1,0x0
40002b8c:	2585d583          	lhu	a1,600(a1) # 40002de0 <__sdata_load>
40002b90:	00100513          	li	a0,1
40002b94:	919ff0ef          	jal	ra,400024ac <gain_setting>
gain_cal1():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:434
        if(total_average1 < (good_average - hysteresis))
40002b98:	02a30737          	lui	a4,0x2a30
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:435
            step1 = 1;
40002b9c:	00100793          	li	a5,1
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:434
        if(total_average1 < (good_average - hysteresis))
40002ba0:	00e46a63          	bltu	s0,a4,40002bb4 <main+0x204>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:437
            if(total_average1 > (good_average + hysteresis))
40002ba4:	012437b3          	sltu	a5,s0,s2
40002ba8:	fff78793          	addi	a5,a5,-1
40002bac:	01079793          	slli	a5,a5,0x10
40002bb0:	4107d793          	srai	a5,a5,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:442
        in_gain1 = in_gain1 + step1;
40002bb4:	000ad703          	lhu	a4,0(s5)
40002bb8:	00e787b3          	add	a5,a5,a4
40002bbc:	01079793          	slli	a5,a5,0x10
40002bc0:	0107d793          	srli	a5,a5,0x10
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:444

        if(in_gain1 < 5)
40002bc4:	06f9e863          	bltu	s3,a5,40002c34 <main+0x284>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:445
            in_gain1 = 5;
40002bc8:	00500793          	li	a5,5
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:448
        else
            if(in_gain1 >= 100)
                in_gain1 = 100;
40002bcc:	00000717          	auipc	a4,0x0
40002bd0:	20f71b23          	sh	a5,534(a4) # 40002de2 <in_gain1>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:450
    ///////////////////////////////////////////////////////////
     gain_setting(2u,in_gain1);
40002bd4:	00000597          	auipc	a1,0x0
40002bd8:	20e5d583          	lhu	a1,526(a1) # 40002de2 <in_gain1>
40002bdc:	00200513          	li	a0,2
40002be0:	8cdff0ef          	jal	ra,400024ac <gain_setting>
main():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:264
        counter = counter +1;
40002be4:	00c12783          	lw	a5,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:266
            GPIO_set_output(&g_gpio_out, LED1, 0);
40002be8:	00000613          	li	a2,0
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:264
        counter = counter +1;
40002bec:	00178793          	addi	a5,a5,1
40002bf0:	00f12623          	sw	a5,12(sp)
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:265
        if (counter <16){
40002bf4:	00c12703          	lw	a4,12(sp)
40002bf8:	00f00793          	li	a5,15
40002bfc:	00e7f463          	bgeu	a5,a4,40002c04 <main+0x254>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:269
            GPIO_set_output(&g_gpio_out, LED1, 1);
40002c00:	00100613          	li	a2,1
40002c04:	00000593          	li	a1,0
40002c08:	89418513          	addi	a0,gp,-1900 # 40002e74 <g_gpio_out>
40002c0c:	d6dfe0ef          	jal	ra,40001978 <GPIO_set_output>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:271
        if (counter ==32){
40002c10:	00c12703          	lw	a4,12(sp)
40002c14:	02000793          	li	a5,32
40002c18:	ecf712e3          	bne	a4,a5,40002adc <main+0x12c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:272
            counter =0;
40002c1c:	00012623          	sw	zero,12(sp)
40002c20:	ea9ff06f          	j	40002ac8 <main+0x118>
gain_cal():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:424
                in_gain = 100;
40002c24:	06400793          	li	a5,100
40002c28:	00000717          	auipc	a4,0x0
40002c2c:	1af71c23          	sh	a5,440(a4) # 40002de0 <__sdata_load>
40002c30:	f59ff06f          	j	40002b88 <main+0x1d8>
gain_cal1():
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:447
            if(in_gain1 >= 100)
40002c34:	06300713          	li	a4,99
40002c38:	f8f77ae3          	bgeu	a4,a5,40002bcc <main+0x21c>
C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\miv32i-Release/../src/application/main.c:448
                in_gain1 = 100;
40002c3c:	06400793          	li	a5,100
40002c40:	f8dff06f          	j	40002bcc <main+0x21c>

40002c44 <__mulsi3>:
__mulsi3():
40002c44:	00050613          	mv	a2,a0
40002c48:	00000513          	li	a0,0
40002c4c:	0015f693          	andi	a3,a1,1
40002c50:	00068463          	beqz	a3,40002c58 <__mulsi3+0x14>
40002c54:	00c50533          	add	a0,a0,a2
40002c58:	0015d593          	srli	a1,a1,0x1
40002c5c:	00161613          	slli	a2,a2,0x1
40002c60:	fe0596e3          	bnez	a1,40002c4c <__mulsi3+0x8>
40002c64:	00008067          	ret

40002c68 <__divsi3>:
__divsi3():
40002c68:	06054063          	bltz	a0,40002cc8 <__umodsi3+0x10>
40002c6c:	0605c663          	bltz	a1,40002cd8 <__umodsi3+0x20>

40002c70 <__udivsi3>:
40002c70:	00058613          	mv	a2,a1
40002c74:	00050593          	mv	a1,a0
40002c78:	fff00513          	li	a0,-1
40002c7c:	02060c63          	beqz	a2,40002cb4 <__udivsi3+0x44>
40002c80:	00100693          	li	a3,1
40002c84:	00b67a63          	bgeu	a2,a1,40002c98 <__udivsi3+0x28>
40002c88:	00c05863          	blez	a2,40002c98 <__udivsi3+0x28>
40002c8c:	00161613          	slli	a2,a2,0x1
40002c90:	00169693          	slli	a3,a3,0x1
40002c94:	feb66ae3          	bltu	a2,a1,40002c88 <__udivsi3+0x18>
40002c98:	00000513          	li	a0,0
40002c9c:	00c5e663          	bltu	a1,a2,40002ca8 <__udivsi3+0x38>
40002ca0:	40c585b3          	sub	a1,a1,a2
40002ca4:	00d56533          	or	a0,a0,a3
40002ca8:	0016d693          	srli	a3,a3,0x1
40002cac:	00165613          	srli	a2,a2,0x1
40002cb0:	fe0696e3          	bnez	a3,40002c9c <__udivsi3+0x2c>
40002cb4:	00008067          	ret

40002cb8 <__umodsi3>:
40002cb8:	00008293          	mv	t0,ra
40002cbc:	fb5ff0ef          	jal	ra,40002c70 <__udivsi3>
40002cc0:	00058513          	mv	a0,a1
40002cc4:	00028067          	jr	t0
40002cc8:	40a00533          	neg	a0,a0
40002ccc:	0005d863          	bgez	a1,40002cdc <__umodsi3+0x24>
40002cd0:	40b005b3          	neg	a1,a1
40002cd4:	f9dff06f          	j	40002c70 <__udivsi3>
40002cd8:	40b005b3          	neg	a1,a1
40002cdc:	00008293          	mv	t0,ra
40002ce0:	f91ff0ef          	jal	ra,40002c70 <__udivsi3>
40002ce4:	40a00533          	neg	a0,a0
40002ce8:	00028067          	jr	t0

40002cec <__modsi3>:
__modsi3():
40002cec:	00008293          	mv	t0,ra
40002cf0:	0005ca63          	bltz	a1,40002d04 <__modsi3+0x18>
40002cf4:	00054c63          	bltz	a0,40002d0c <__modsi3+0x20>
40002cf8:	f79ff0ef          	jal	ra,40002c70 <__udivsi3>
40002cfc:	00058513          	mv	a0,a1
40002d00:	00028067          	jr	t0
40002d04:	40b005b3          	neg	a1,a1
40002d08:	fe0558e3          	bgez	a0,40002cf8 <__modsi3+0xc>
40002d0c:	40a00533          	neg	a0,a0
40002d10:	f61ff0ef          	jal	ra,40002c70 <__udivsi3>
40002d14:	40b00533          	neg	a0,a1
40002d18:	00028067          	jr	t0

40002d1c <memset>:
memset():
40002d1c:	00050313          	mv	t1,a0
40002d20:	00060a63          	beqz	a2,40002d34 <memset+0x18>
40002d24:	00b30023          	sb	a1,0(t1)
40002d28:	fff60613          	addi	a2,a2,-1
40002d2c:	00130313          	addi	t1,t1,1
40002d30:	fe061ae3          	bnez	a2,40002d24 <memset+0x8>
40002d34:	00008067          	ret
	...

40002d40 <local_irq_handler_table>:
40002d40:	40000d20 40000d1c 40000d24 40000d40      ..@...@$..@@..@
40002d50:	40000d34 40000d34 40000d34 40000d34     4..@4..@4..@4..@
40002d60:	40002634 40002654 40002674 40000d28     4&.@T&.@t&.@(..@
40002d70:	40000d2c 40000d30 40000d38 40000d3c     ,..@0..@8..@<..@

40002d80 <iic_hdmi_out_config>:
40002d80:	104100f9 e09a0398 619d309c a4a3a4a2     ..A......0.a....
40002d90:	00f9d0e0 009410de 60ba40a1 0015c0d6     .........@.`....
40002da0:	02173016 001830d0 00488040 004ca849     .0...0..@.H.I.L.
40002db0:	08560055 000006af 00000000 00000000     U.V.............
	...
