# Creating SmartDesign "ISP_Block_HDMI_4K"
set sd_name {ISP_Block_HDMI_4K}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_ARVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_AWVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_BREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_WVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4KFRAME_END_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_LANE_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_RESET_N_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_ARREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_AWREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_BVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_WREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_ARADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_AWADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_WDATA_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DATA_I_1} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_BRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_RDATA_O_5} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI_RRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O} -port_direction {OUT} -port_range {[95:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O" \
"TDATA:TDATA_O" \
"TSTRB:TSTRB_O" \
"TKEEP:TKEEP_O" \
"TLAST:TLAST_O" \
"TUSER:TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:AXI_AWADDR_I_5" \
"AWVALID:AXI_AWVALID_I_5" \
"AWREADY:AXI_AWREADY_O_5" \
"WDATA:AXI_WDATA_I_5" \
"WVALID:AXI_WVALID_I_5" \
"WREADY:AXI_WREADY_O_5" \
"BRESP:AXI_BRESP_O_5" \
"BVALID:AXI_BVALID_O_5" \
"BREADY:AXI_BREADY_I_5" \
"ARADDR:AXI_ARADDR_I_5" \
"ARVALID:AXI_ARVALID_I_5" \
"ARREADY:AXI_ARREADY_O_5" \
"RDATA:AXI_RDATA_O_5" \
"RRESP:AXI_RRESP_O_5" \
"RVALID:AXI_RVALID_O_5" \
"RREADY:AXI_RREADY_I_5" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:AXI_AWADDR_I_1" \
"AWVALID:AXI_AWVALID_I_1" \
"AWREADY:AXI_AWREADY_O_1" \
"WDATA:AXI_WDATA_I_1" \
"WVALID:AXI_WVALID_I_1" \
"WREADY:AXI_WREADY_O_1" \
"BRESP:AXI_BRESP_O_1" \
"BVALID:AXI_BVALID_O_1" \
"BREADY:AXI_BREADY_I_1" \
"ARADDR:AXI_ARADDR_I_1" \
"ARVALID:AXI_ARVALID_I_1" \
"ARREADY:AXI_ARREADY_O_1" \
"RDATA:AXI_RDATA_O_1" \
"RRESP:AXI_RRESP_O_1" \
"RVALID:AXI_RVALID_O_1" \
"RREADY:AXI_RREADY_I_1" } 

# Add AXI4S_Initiator_IF_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Initiator_IF} -instance_name {AXI4S_Initiator_IF_2}
# Exporting Parameters of instance AXI4S_Initiator_IF_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_2} -params {\
"G_AXIBUS_WIDTH:32" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_2}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_2}



# Add Bayer_Interpolation_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C2} -instance_name {Bayer_Interpolation_C2_0}



# Add Defective_Pixel_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Defective_Pixel_C0} -instance_name {Defective_Pixel_C0_0}



# Add Gamma_Correction_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C0} -instance_name {Gamma_Correction_C0_0}



# Add Image_Enhancement_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C2} -instance_name {Image_Enhancement_C2_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Image_Enhancement_C2_0:Y_AVG_O}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_CLK_I" "Bayer_Interpolation_C2_0:AXI4L_CLK_I" "Defective_Pixel_C0_0:AXI_ACLK_I" "Image_Enhancement_C2_0:AXI4L_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_RESET_I" "Bayer_Interpolation_C2_0:AXI4L_RESETN_I" "Defective_Pixel_C0_0:AXI_ARESETN_I" "Image_Enhancement_C2_0:AXI4L_RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:DATA_VALID_I" "DATA_VALID_I_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:EOF_I" "DDR_READ_4KFRAME_END_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:RESETN_I" "Bayer_Interpolation_C2_0:RESETN_I" "Defective_Pixel_C0_0:RESETN_I" "Gamma_Correction_C0_0:RESETN_I" "HDMI_TX_RESET_N_I" "Image_Enhancement_C2_0:RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:SYS_CLK_I" "Bayer_Interpolation_C2_0:SYS_CLK_I" "Defective_Pixel_C0_0:SYS_CLK_I" "Gamma_Correction_C0_0:SYS_CLK_I" "HDMI_TX_LANE_CLK_I" "Image_Enhancement_C2_0:SYS_CLK_I" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:DATA_I" "DATA_I_1" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_2:AXI4S_Initiator_IF" "Defective_Pixel_C0_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:AXI4L_BAYER" "CAM_4K_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:AXI4Stream_Initiator_Interface" "Gamma_Correction_C0_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:AXI4Stream_Target_Interface" "Defective_Pixel_C0_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_4K_AXI4Lite_Target_IF" "Defective_Pixel_C0_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_4K_IMAGE_AXI4Lite_Target_IF" "Image_Enhancement_C2_0:AXI4L_IMAGE_ENHANCEMENT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H2p0_AXI4Stream_Initiator_IF" "Image_Enhancement_C2_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:AXI4Stream_Initiator_IF" "Image_Enhancement_C2_0:AXI4Stream_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "ISP_Block_HDMI_4K"
generate_component -component_name ${sd_name}
