src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.o: \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy.c \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/phy.h \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/phy_types.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/platform_config/driver_config/phy_sw_cfg.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h \
 ../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h

../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/phy.h:

../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/phy_types.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/platform_config/driver_config/phy_sw_cfg.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h:

../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_reg.h:

../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/uint_32_bit_masks.h:

../src/platform/drivers/fpga_ip/Core10GBaseKR_PHY/core10gbasekr_phy_link_training.h:
