# Creating SmartDesign "HDMI_2p0"
set sd_name {HDMI_2p0}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_VIDEO_TVALID_I_VIDEO} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TX_BIT_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TX_PLL_LOCK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL_TX_PLL_REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {EDID_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_HPD_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_RESET_N_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_SCL_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Target_IF_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_RESET_N_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANEX_CDR_REF_CLK} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_HPD_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_STABLE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_VIDEO_TDATA_I_VIDEO} -port_direction {IN} -port_range {[95:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_VIDEO_TUSER_I_VIDEO} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Target_IF_TKEEP_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Target_IF_TSTRB_I} -port_direction {IN} -port_range {[2:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O} -port_direction {OUT} -port_range {[13:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O" \
"TDATA:TDATA_O" \
"TSTRB:TSTRB_O" \
"TKEEP:TKEEP_O" \
"TLAST:TLAST_O" \
"TUSER:TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:AXI4Stream_Target_IF_VIDEO_TVALID_I_VIDEO" \
"TDATA:AXI4Stream_Target_IF_VIDEO_TDATA_I_VIDEO" \
"TSTRB:HDMI_TX_AXI4Stream_Target_IF_TSTRB_I" \
"TKEEP:HDMI_TX_AXI4Stream_Target_IF_TKEEP_I" \
"TLAST:HDMI_TX_AXI4Stream_Target_IF_TLAST_I" \
"TUSER:AXI4Stream_Target_IF_VIDEO_TUSER_I_VIDEO" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_FROM_TXPLL} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {slave} -port_bif_mapping {\
"LOCK:CLKS_FROM_TXPLL_TX_PLL_LOCK_0" \
"BIT_CLK:CLKS_FROM_TXPLL_TX_BIT_CLK_0" \
"REF_CLK_TO_LANE:CLKS_FROM_TXPLL_TX_PLL_REF_CLK_0" } 

# Add axi_inf_map_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {axi_inf_map} -instance_name {axi_inf_map_0}
# Exporting Parameters of instance axi_inf_map_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {axi_inf_map_0} -params {\
"G_AXIBUS_WIDTH:96" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {axi_inf_map_0}
sd_update_instance -sd_name ${sd_name} -instance_name {axi_inf_map_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:TREADY_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:DATA_TRIGGER_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:DATA_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:HSYNC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:VSYNC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {axi_inf_map_0:FRAME_END_O}



# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_0:D} -value {GND}



# Add HDMI_RX_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_RX_C1} -instance_name {HDMI_RX_C0_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_RX_C0_1:HDMI_DVI_MODE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_RX_C0_1:ACR_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_RX_C0_1:ACR_CTS_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_RX_C0_1:ACR_N_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_RX_C0_1:AXI4Stream_Initiator_IF_Audio}



# Add HDMI_TX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_TX_C1} -instance_name {HDMI_TX_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_TX_C0_0:XCVR_LANE_0_DATA_O}



# Add PF_XCVR_ERM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0} -instance_name {PF_XCVR_ERM_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_CLK_R}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_SLIP} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_VAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_TX_DATA} -value {0000011111000001111100000111110000011111}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_DATA}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "HDMI_RX_C0_1:SDA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:PAD" "HDMI_RX_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "HDMI_RX_C0_1:SDA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"EDID_CLK_I" "HDMI_RX_C0_1:EDID_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:BIT_SLIP_B_O" "PF_XCVR_ERM_C0_0:LANE1_RX_SLIP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:BIT_SLIP_G_O" "PF_XCVR_ERM_C0_0:LANE2_RX_SLIP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:BIT_SLIP_R_O" "PF_XCVR_ERM_C0_0:LANE3_RX_SLIP" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:B_RX_CLK_I" "PF_XCVR_ERM_C0_0:LANE1_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:B_RX_VALID_I" "PF_XCVR_ERM_C0_0:LANE1_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:EDID_RESET_N_I" "HDMI_RX_C0_1:RESET_N_I" "HDMI_RX_RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:G_RX_CLK_I" "PF_XCVR_ERM_C0_0:LANE2_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:G_RX_VALID_I" "PF_XCVR_ERM_C0_0:LANE2_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:HPD_I" "HDMI_RX_HPD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:HPD_O" "HDMI_RX_HPD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:R_RX_CLK_I" "LANE3_RX_CLK_R" "PF_XCVR_ERM_C0_0:LANE3_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:R_RX_VALID_I" "PF_XCVR_ERM_C0_0:LANE3_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:SCL_I" "HDMI_RX_SCL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:B_CLK_I" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:B_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:G_CLK_I" "PF_XCVR_ERM_C0_0:LANE2_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:G_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE2_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:RESET_N_I" "HDMI_TX_RESET_N_I" "PF_XCVR_ERM_C0_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE0_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE2_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE2_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE3_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE3_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:R_CLK_I" "PF_XCVR_ERM_C0_0:LANE3_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:R_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE3_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:SYS_CLK_I" "LANE0_TX_CLK_R" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C0_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C0_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_ERM_C0_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_ERM_C0_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TX_CLK_STABLE" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N" "PF_XCVR_ERM_C0_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P" "PF_XCVR_ERM_C0_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_N" "PF_XCVR_ERM_C0_0:LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_P" "PF_XCVR_ERM_C0_0:LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_N" "PF_XCVR_ERM_C0_0:LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_P" "PF_XCVR_ERM_C0_0:LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_N" "PF_XCVR_ERM_C0_0:LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_P" "PF_XCVR_ERM_C0_0:LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_N" "PF_XCVR_ERM_C0_0:LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_P" "PF_XCVR_ERM_C0_0:LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_N" "PF_XCVR_ERM_C0_0:LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_P" "PF_XCVR_ERM_C0_0:LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANEX_CDR_REF_CLK" "PF_XCVR_ERM_C0_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_ERM_C0_0:LANE1_CDR_REF_CLK_0" "PF_XCVR_ERM_C0_0:LANE2_CDR_REF_CLK_0" "PF_XCVR_ERM_C0_0:LANE3_CDR_REF_CLK_0" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:DATA_B_I" "PF_XCVR_ERM_C0_0:LANE1_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:DATA_G_I" "PF_XCVR_ERM_C0_0:LANE2_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_C0_1:DATA_R_I" "PF_XCVR_ERM_C0_0:LANE3_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_B_O" "PF_XCVR_ERM_C0_0:LANE1_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_G_O" "PF_XCVR_ERM_C0_0:LANE2_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_R_O" "PF_XCVR_ERM_C0_0:LANE3_TX_DATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_FROM_TXPLL" "PF_XCVR_ERM_C0_0:CLKS_FROM_TXPLL_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_AXI4Stream_Initiator_IF" "HDMI_RX_C0_1:AXI4Stream_Initiator_IF_Video" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_AXI4Stream_Target_IF" "axi_inf_map_0:input_inf" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:AXI4Stream_Target_IF_VIDEO" "axi_inf_map_0:output_inf" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "HDMI_2p0"
generate_component -component_name ${sd_name}
