# Creating SmartDesign "Video_Processing_Block_CAM2_SCALE"
set sd_name {Video_Processing_Block_CAM2_SCALE}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WVALID_I_0} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FOR_DELAY_SD_DATA_VALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WREADY_O_0} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TDATA_I_0} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TUSER_I_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WDATA_I_0} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Intensity_Avarage_SCALE} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RDATA_O_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RRESP_O_0} -port_direction {OUT} -port_range {[1:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TVALID_I_0" \
"TREADY:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TREADY_O_0" \
"TDATA:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TDATA_I_0" \
"TLAST:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I" \
"TUSER:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TUSER_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1" \
"AWADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1" \
"AWLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1" \
"AWSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1" \
"AWBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1" \
"AWLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1" \
"AWCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1" \
"AWPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1" \
"AWQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1" \
"AWREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1" \
"AWVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1" \
"AWREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1" \
"WDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1" \
"WSTRB:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1" \
"WLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1" \
"WVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1" \
"WREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1" \
"BID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1" \
"BRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1" \
"BVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1" \
"BREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1" \
"ARID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1" \
"ARADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1" \
"ARLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1" \
"ARSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1" \
"ARBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1" \
"ARLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1" \
"ARCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1" \
"ARPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1" \
"ARQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1" \
"ARREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1" \
"ARVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1" \
"ARREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1" \
"RID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1" \
"RDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1" \
"RRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1" \
"RLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1" \
"RVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1" \
"RREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1" \
"AWUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1" \
"WUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1" \
"BUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1" \
"ARUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1" \
"RUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:AXI4Stream_Initiator_IF_TVALID_O" \
"TDATA:AXI4Stream_Initiator_IF_TDATA_O" \
"TSTRB:AXI4Stream_Initiator_IF_TSTRB_O" \
"TKEEP:AXI4Stream_Initiator_IF_TKEEP_O" \
"TLAST:AXI4Stream_Initiator_IF_TLAST_O" \
"TUSER:AXI4Stream_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWADDR_I_0" \
"AWVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWVALID_I_0" \
"AWREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWREADY_O_0" \
"WDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WDATA_I_0" \
"WVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WVALID_I_0" \
"WREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WREADY_O_0" \
"BRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BRESP_O_0" \
"BVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BVALID_O_0" \
"BREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BREADY_I_0" \
"ARADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARADDR_I_0" \
"ARVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARVALID_I_0" \
"ARREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARREADY_O_0" \
"RDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RDATA_O_0" \
"RRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RRESP_O_0" \
"RVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RVALID_O_0" \
"RREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RREADY_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI4Lite_Target_IF_AXI_RREADY_I" } 

# Add Bayer_Interpolation_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C1} -instance_name {Bayer_Interpolation_C1_0}



# Add Defective_Pixel_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Defective_Pixel_C2} -instance_name {Defective_Pixel_C2_0}



# Add Gamma_Correction_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C1} -instance_name {Gamma_Correction_C1_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Gamma_Correction_C1_0:TDATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Gamma_Correction_C1_0:TDATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Gamma_Correction_C1_0:TDATA_O} -pin_slices {[7:0]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Gamma_Correction_C1_0:AXI4Stream_Initiator_IF} -pin_names {Gamma_Correction_C1_0:TVALID_O}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Gamma_Correction_C1_0:AXI4Stream_Initiator_IF} -pin_names {Gamma_Correction_C1_0:TDATA_O}



# Add Image_Enhancement_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C1} -instance_name {Image_Enhancement_C1_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_CLK_I" "Bayer_Interpolation_C1_0:AXI4L_CLK_I" "Defective_Pixel_C2_0:AXI_ACLK_I" "Image_Enhancement_C1_0:AXI4L_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_RESET_I" "Bayer_Interpolation_C1_0:AXI4L_RESETN_I" "Defective_Pixel_C2_0:AXI_ARESETN_I" "Image_Enhancement_C1_0:AXI4L_RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C1_0:RESETN_I" "Defective_Pixel_C2_0:RESETN_I" "Gamma_Correction_C1_0:RESETN_I" "HDMI_1p4_FAB_RESET_I" "Image_Enhancement_C1_0:RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C1_0:SYS_CLK_I" "Defective_Pixel_C2_0:SYS_CLK_I" "Gamma_Correction_C1_0:SYS_CLK_I" "HDMI_148p5_CLK_I" "Image_Enhancement_C1_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FOR_DELAY_SD_DATA_VALID_O" "Gamma_Correction_C1_0:TVALID_O" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C1_0:Y_AVG_O" "Intensity_Avarage_SCALE" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4Stream_Initiator_IF" "Image_Enhancement_C1_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C1_0:AXI4L_BAYER" "SCALE_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C1_0:AXI4Stream_Initiator_Interface" "Gamma_Correction_C1_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C1_0:AXI4Stream_Target_Interface" "Defective_Pixel_C2_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SCALE_AXI4Lite_Target_IF" "Defective_Pixel_C2_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_AXI4Stream_Target_IF" "Defective_Pixel_C2_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:AXI4Stream_Initiator_IF" "Image_Enhancement_C1_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C1_0:AXI4L_IMAGE_ENHANCEMENT" "SCALE_IMAGE_AXI4Lite_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Processing_Block_CAM2_SCALE"
generate_component -component_name ${sd_name}
