# Creating SmartDesign "Video_Alignment_Selection"
set sd_name {Video_Alignment_Selection}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Frame_end_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {selection_line_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF_TREADY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF_TDATA_I} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_TDATA_I} -port_direction {IN} -port_range {[23:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:AXI4S_Initiator_IF_TVALID_O" \
"TDATA:AXI4S_Initiator_IF_TDATA_O" \
"TSTRB:AXI4S_Initiator_IF_TSTRB_O" \
"TKEEP:AXI4S_Initiator_IF_TKEEP_O" \
"TLAST:AXI4S_Initiator_IF_TLAST_O" \
"TUSER:AXI4S_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_SLAVE_SYNC} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:BIF_1_TVALID_I" \
"TDATA:BIF_1_TDATA_I" \
"TLAST:BIF_1_TLAST_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:AXI4S_Target_IF_TVALID_I" \
"TREADY:AXI4S_Target_IF_TREADY_O" \
"TDATA:AXI4S_Target_IF_TDATA_I" \
"TUSER:AXI4S_Target_IF_TUSER_I" } 

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}
sd_invert_pins -sd_name ${sd_name} -pin_names {AND2_0:B}



# Add AXI4S_Initiator_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Initiator_IF} -instance_name {AXI4S_Initiator_IF_0}
# Exporting Parameters of instance AXI4S_Initiator_IF_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_0} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {AXI4S_Initiator_IF_0:EOF_I} -value {VCC}



# Add AXI4S_SLAVE_SYNC_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_SLAVE_SYNC} -instance_name {AXI4S_SLAVE_SYNC_0}
# Exporting Parameters of instance AXI4S_SLAVE_SYNC_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_SLAVE_SYNC_0} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_SLAVE_SYNC_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_SLAVE_SYNC_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_SLAVE_SYNC_0:DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_SLAVE_SYNC_0:DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_SLAVE_SYNC_0:DATA_O} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_SLAVE_SYNC_0:EOF_O}



# Add AXI4S_Target_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Target_IF} -instance_name {AXI4S_Target_IF_0}
# Exporting Parameters of instance AXI4S_Target_IF_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_Target_IF_0:EOF_O}



# Add MUX_2_to_1_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {MUX_2_to_1} -hdl_file {hdl\MUX_2_to_1.vhd} -instance_name {MUX_2_to_1_0}



# Add video_fifo_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {video_fifo} -instance_name {video_fifo_0}
# Exporting Parameters of instance video_fifo_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {video_fifo_0} -params {\
"g_HALF_EMPTY_THRESHOLD:1280" \
"g_INPUT_VIDEO_DATA_BIT_WIDTH:24" \
"g_VIDEO_FIFO_AWIDTH:12" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {video_fifo_0}
sd_update_instance -sd_name ${sd_name} -instance_name {video_fifo_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {video_fifo_0:wdata_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {video_fifo_0:wdata_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {video_fifo_0:wdata_i} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wfull_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wafull_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:raempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rhempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wdata_count_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rdata_count_o}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "AXI4S_Initiator_IF_0:RESETN_I" "RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "Frame_end_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "video_fifo_0:rresetn_i" "video_fifo_0:wresetn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_0:DATA_VALID_I" "video_fifo_0:rdata_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_0:SYS_CLK_I" "SYS_CLK_I" "video_fifo_0:rclock_i" "video_fifo_0:wclock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_SLAVE_SYNC_0:DATA_VALID_O" "video_fifo_0:wen_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:DATA_VALID_O" "video_fifo_0:ren_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MUX_2_to_1_0:selection_line_i" "selection_line_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_0:DATA_I" "MUX_2_to_1_0:output_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_SLAVE_SYNC_0:DATA_O[15:8]" "video_fifo_0:wdata_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_SLAVE_SYNC_0:DATA_O[23:16]" "video_fifo_0:wdata_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_SLAVE_SYNC_0:DATA_O[7:0]" "video_fifo_0:wdata_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:DATA_O" "MUX_2_to_1_0:input1_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MUX_2_to_1_0:input2_i" "video_fifo_0:rdata_o" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF" "AXI4S_Initiator_IF_0:AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_SLAVE_SYNC" "AXI4S_SLAVE_SYNC_0:BIF_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF" "AXI4S_Target_IF_0:AXI4S_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Alignment_Selection"
generate_component -component_name ${sd_name}
