src/platform/drivers/fpga_ip/miv_plic/miv_plic.o: \
 ../src/platform/drivers/fpga_ip/miv_plic/miv_plic.c \
 ../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h \
 ../src/platform/drivers/fpga_ip/miv_plic/miv_plic_regs.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_regs.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_plic.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_assert.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_subsys.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/fpga_design_config/fpga_design_config.h

../src/platform/drivers/fpga_ip/miv_plic/miv_plic.h:

../src/platform/drivers/fpga_ip/miv_plic/miv_plic_regs.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_regs.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_plic.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_assert.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_subsys.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/fpga_design_config/fpga_design_config.h:
