# Creating SmartDesign "Delay_Compensation"
set sd_name {Delay_Compensation}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_frame_active} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_HPD_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {alpha_valid_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ENABLE_FOR_ALPHA_BLENDING} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_DATA} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_I} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_I} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:TVALID_I" \
"TREADY:TREADY_O" \
"TDATA:TDATA_I" \
"TUSER:TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4S_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O" \
"TDATA:TDATA_O" \
"TSTRB:TSTRB_O" \
"TKEEP:TKEEP_O" \
"TLAST:TLAST_O" \
"TUSER:TUSER_O" } 

# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add AXI4S_Initiator_IF_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Initiator_IF} -instance_name {AXI4S_Initiator_IF_1}
# Exporting Parameters of instance AXI4S_Initiator_IF_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {AXI4S_Initiator_IF_1:EOF_I} -value {VCC}



# Add AXI4S_Target_IF_2 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Target_IF} -instance_name {AXI4S_Target_IF_2}
# Exporting Parameters of instance AXI4S_Target_IF_2
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_2} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_2}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_Target_IF_2:EOF_O}



# Add delay_circuit_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {delay_circuit} -hdl_file {hdl/delay_circuit.vhd} -instance_name {delay_circuit_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {delay_circuit_0:alpha_valid_o}



# Add MUX_2_to_1_1 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {MUX_2_to_1} -hdl_file {hdl/MUX_2_to_1.vhd} -instance_name {MUX_2_to_1_1}



# Add synchronizer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {synchronizer_circuit} -hdl_file {hdl\synchronizer_circuit.vhd} -instance_name {synchronizer_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "DDR_READ_SCALE_frame_active" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "ENABLE_FOR_ALPHA_BLENDING" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:DATA_VALID_I" "delay_circuit_0:img_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:RESETN_I" "HDMI_1p4_FAB_RESET_I" "delay_circuit_0:reset_n" "synchronizer_0:reset_n" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:SYS_CLK_I" "HDMI_148p5_CLK_I" "delay_circuit_0:sys_clk" "synchronizer_0:sys_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_2:DATA_VALID_O" "DATA_VALID_O" "delay_circuit_0:img_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_HPD_I" "synchronizer_0:data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MUX_2_to_1_1:selection_line_i" "synchronizer_0:sync_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"alpha_valid_i" "delay_circuit_0:alpha_valid_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:DATA_I" "MUX_2_to_1_1:output_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_2:DATA_O" "delay_circuit_0:img_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_DATA" "MUX_2_to_1_1:input1_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MUX_2_to_1_1:input2_i" "delay_circuit_0:img_data_o" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF" "AXI4S_Initiator_IF_1:AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF" "AXI4S_Target_IF_2:AXI4S_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Delay_Compensation"
generate_component -component_name ${sd_name}
