# Creating SmartDesign "Alpha_Blending_Histogram"
set sd_name {Alpha_Blending_Histogram}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H1p4_VSYNC_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {EN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {From_Scale_Block_AXI4Stream_Target1_IF_TVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {From_delay_sd_AXI4Stream_Target0_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_CURVE_WE_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ALPHA_DATA_VALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H1p4_EXT_SYNC_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {From_Scale_Block_AXI4Stream_Target1_IF_TREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {From_delay_sd_AXI4Stream_Target0_IF_TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_HIST_RDY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {From_Scale_Block_AXI4Stream_Target1_IF_TDATA_I_0} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {From_Scale_Block_AXI4Stream_Target1_IF_TUSER_I_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {From_delay_sd_AXI4Stream_Target0_IF_TDATA_I} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {From_delay_sd_AXI4Stream_Target0_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WADDR_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WDATA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_ADDR_I} -port_direction {IN} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_BLUE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_GREEN_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_RED_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_DATA_O} -port_direction {OUT} -port_range {[23:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {From_Scale_Block_AXI4Stream_Target1_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:From_Scale_Block_AXI4Stream_Target1_IF_TVALID_I_0" \
"TREADY:From_Scale_Block_AXI4Stream_Target1_IF_TREADY_O_0" \
"TDATA:From_Scale_Block_AXI4Stream_Target1_IF_TDATA_I_0" \
"TUSER:From_Scale_Block_AXI4Stream_Target1_IF_TUSER_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {From_delay_sd_AXI4Stream_Target0_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:From_delay_sd_AXI4Stream_Target0_IF_TVALID_I" \
"TREADY:From_delay_sd_AXI4Stream_Target0_IF_TREADY_O" \
"TDATA:From_delay_sd_AXI4Stream_Target0_IF_TDATA_I" \
"TUSER:From_delay_sd_AXI4Stream_Target0_IF_TUSER_I" } 

# Add Alpha_Blending_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Alpha_Blending_C1} -instance_name {Alpha_Blending_C1_0}



# Add AXI4S_Target_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Target_IF} -instance_name {AXI4S_Target_IF_0}
# Exporting Parameters of instance AXI4S_Target_IF_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0} -params {\
"G_AXIBUS_WIDTH:24" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Target_IF_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_Target_IF_0:DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_Target_IF_0:DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_Target_IF_0:DATA_O} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_Target_IF_0:EOF_O}



# Add Histogram_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Histogram_C0} -instance_name {Histogram_C0_0}



# Add RGBtoYCbCr_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C1} -instance_name {RGBtoYCbCr_C1_0}



# Add YCbCrtoRGB_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C1} -instance_name {YCbCrtoRGB_C1_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ALPHA_DATA_VALID_O" "AXI4S_Target_IF_0:DATA_VALID_O" "RGBtoYCbCr_C1_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_CLK_I" "Alpha_Blending_C1_0:AXI_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_RESETN_I" "Alpha_Blending_C1_0:AXI_RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_C1_0:EN_I" "EN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_C1_0:RESETN_I" "HDMI_1p4_FAB_RESET_I" "Histogram_C0_0:RESET_I" "RGBtoYCbCr_C1_0:RESET_N_I" "YCbCrtoRGB_C1_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_C1_0:SYS_CLK_I" "HDMI_148p5_CLK_I" "Histogram_C0_0:PIXEL_CLK_I" "RGBtoYCbCr_C1_0:CLOCK_I" "YCbCrtoRGB_C1_0:CLOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_EXT_SYNC_O" "YCbCrtoRGB_C1_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_VSYNC_I" "Histogram_C0_0:EOF_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:CURVE_WE_I" "UART_CURVE_WE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:DATA_VALID_I" "RGBtoYCbCr_C1_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:DATA_VALID_O" "YCbCrtoRGB_C1_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:HIST_RDY_O" "UART_HIST_RDY_O" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:DATA_O[15:8]" "RGBtoYCbCr_C1_0:GREEN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:DATA_O[23:16]" "RGBtoYCbCr_C1_0:RED_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:DATA_O[7:0]" "RGBtoYCbCr_C1_0:BLUE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_DATA_BLUE_O" "YCbCrtoRGB_C1_0:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_DATA_GREEN_O" "YCbCrtoRGB_C1_0:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_DATA_RED_O" "YCbCrtoRGB_C1_0:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:CURVE_WADDR_I" "UART_CURVE_WADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:CURVE_WDATA_I" "UART_CURVE_WDATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:Cb_I" "RGBtoYCbCr_C1_0:Cb_OUT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:Cb_O" "YCbCrtoRGB_C1_0:Cb_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:Cr_I" "RGBtoYCbCr_C1_0:Cr_OUT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:Cr_O" "YCbCrtoRGB_C1_0:Cr_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:DATA_Y_I" "RGBtoYCbCr_C1_0:Y_OUT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:HIST_ADDR_I" "UART_HIST_ADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:HIST_DATA_O" "UART_HIST_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Histogram_C0_0:Y_O" "YCbCrtoRGB_C1_0:Y_IN" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_IF_0:AXI4S_Target_IF" "Alpha_Blending_C1_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_AXI4Lite_Target_IF" "Alpha_Blending_C1_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_C1_0:AXI4Stream_Target0_IF" "From_delay_sd_AXI4Stream_Target0_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_C1_0:AXI4Stream_Target1_IF" "From_Scale_Block_AXI4Stream_Target1_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Alpha_Blending_Histogram"
generate_component -component_name ${sd_name}
