# Exporting core AXI4S_ddr_write_bus_target_IF to TCL
# Exporting Create HDL core command for module AXI4S_ddr_write_bus_target_IF
create_hdl_core -file {hdl/AXI4S_ddr_write_bus_target_IF.vhd} -module {AXI4S_ddr_write_bus_target_IF} -library {work} -package {}
# Exporting BIF information of  HDL core command for module AXI4S_ddr_write_bus_target_IF
hdl_core_add_bif -hdl_core_name {AXI4S_ddr_write_bus_target_IF} -bif_definition {AXI4Stream:AMBA:AMBA4:slave} -bif_name {AXI4S_Target_IF} -signal_map {\
"TVALID:TVALID_I" \
"TREADY:TREADY_O" \
"TDATA:TDATA_I" \
"TUSER:TUSER_I" }
