
file copy -force "./src/softconsole/mpf_an5270_v2025p1_df.hex" "./$Prjname/mpf_an5270_v2025p1_df.hex"

# Import source files
import_files -hdl_source {./src/hdl/axi_inf_map.vhd}
import_files -hdl_source {./src/hdl/addr_decoder.vhd}
import_files -hdl_source {./src/hdl/ram_read_uart.vhd}
import_files -hdl_source {./src/hdl/receive_data.vhd}
import_files -hdl_source {./src/hdl/send_data.vhd}
import_files -hdl_source {./src/hdl/timer.vhd}
import_files -hdl_source {./src/hdl/AXI4Stream_Initiator_Broadcaster.vhd}
import_files -hdl_source {./src/hdl/AXI4Stream_Target_Broadcaster.vhd}
import_files -hdl_source {./src/hdl/Broadcaster.vhd}
import_files -hdl_source {./src/hdl/AXI4Stream_Target_ddr_read_4k.vhd}
import_files -hdl_source {./src/hdl/DDR_read_controller_scale.vhd}
import_files -hdl_source {./src/hdl/data_unpacker_scale.vhd}
import_files -hdl_source {./src/hdl/ram2port.vhd}
import_files -hdl_source {./src/hdl/video_fifo.vhd}
import_files -hdl_source {./src/hdl/synchronizer_circuit.vhd}
import_files -hdl_source {./src/hdl/AXI4S_Initiator_IF.vhd}
import_files -hdl_source {./src/hdl/scale_read_channel_BUS_IF.v}
import_files -hdl_source {./src/hdl/AXI4S_ddr_write_bus_target_IF.vhd}
import_files -hdl_source {./src/hdl/AXI4S_Target_IF.vhd}
import_files -hdl_source {./src/hdl/MUX_2_to_1.vhd}
import_files -hdl_source {./src/hdl/delay_circuit.vhd}
import_files -hdl_source {./src/hdl/AXI4S_SLAVE_SYNC.vhd}
import_files -hdl_source {./src/hdl/apb_wrapper.vhd}
import_files -hdl_source {./src/hdl/buffer.vhd}
import_files -hdl_source {./src/hdl/PIP_mode.vhd}
import_files -hdl_source {./src/hdl/selector.vhd}

build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/axi_inf_map.tcl 
source ./src/components/Broadcaster.tcl 
source ./src/components/AXI4S_Target_ddr_read_4k.tcl 
source ./src/components/video_fifo.tcl 
source ./src/components/AXI4S_Initiator_IF.tcl 
source ./src/components/scale_read_channel_BUS_IF.tcl 
source ./src/components/AXI4S_ddr_write_bus_target_IF.tcl 
source ./src/components/AXI4S_Target_IF.tcl 
source ./src/components/AXI4S_SLAVE_SYNC.tcl 
source ./src/components/apb3_if.tcl 

build_design_hierarchy

source ./src/components/CORERESET_PF_C0.tcl 
source ./src/components/CORERESET_PF_C1.tcl 
source ./src/components/CORERESET_PF_C2.tcl 
source ./src/components/CORERESET_PF_C3.tcl 
source ./src/components/CORERESET_PF_C4.tcl 
source ./src/components/CORERESET_PF_C5.tcl 
source ./src/components/CORERESET_PF_C6.tcl 
source ./src/components/PF_CCC_C0.tcl 
source ./src/components/PF_CCC_C1.tcl 
source ./src/components/PF_CCC_C2.tcl 
source ./src/components/PF_INIT_MONITOR_C0.tcl 
source ./src/components/PF_TX_PLL_C0.tcl 
source ./src/components/PF_XCVR_REF_CLK_C0.tcl 
source ./src/components/HDMI_RX_C1.tcl 
source ./src/components/HDMI_TX_C1.tcl 
source ./src/components/PF_XCVR_ERM_C0.tcl 
source ./src/components/MIPI_TRAINING_LITE_C0.tcl 
source ./src/components/MIPI_TRAINING_LITE_C1.tcl 
source ./src/components/MIPI_TRAINING_LITE_C2.tcl 
source ./src/components/MIPI_TRAINING_LITE_C3.tcl 
source ./src/components/PF_IOD_GENERIC_RX_C0.tcl 
source ./src/components/mipicsi2rxdecoderPF_C1.tcl 
source ./src/components/PF_DDR4_C0.tcl 
source ./src/components/COREAXI4INTERCONNECT_C0.tcl 
source ./src/components/COREI2C_C0.tcl 
source ./src/components/COREJTAGDEBUG_C0.tcl 
source ./src/components/CoreAPB3_C0.tcl 
source ./src/components/CoreGPIO_C0.tcl 
source ./src/components/MIV_RV32_C0.tcl 
source ./src/components/PF_SRAM_AHBL_AXI_C0.tcl 

generate_component -component_name PF_SRAM_AHBL_AXI_C0

source ./src/components/COREUART_C0.tcl 
source ./src/components/DDR_AXI4_ARBITER_PF_C0.tcl 
source ./src/components/Display_Controller_C2.tcl 
source ./src/components/Display_Controller_C3.tcl 
source ./src/components/DDR_Read_C3.tcl 
source ./src/components/DDR_Read_C4.tcl 
source ./src/components/DDR_Read_C5.tcl 
source ./src/components/DDR_Write_C3.tcl 
source ./src/components/DDR_Write_C4.tcl 
source ./src/components/DDR_Write_C5.tcl 
source ./src/components/Alpha_Blending_C1.tcl 
source ./src/components/Histogram_C0.tcl 
source ./src/components/RGBtoYCbCr_C1.tcl 
source ./src/components/YCbCrtoRGB_C1.tcl 
source ./src/components/Bayer_Interpolation_C2.tcl 
source ./src/components/Defective_Pixel_C0.tcl 
source ./src/components/Gamma_Correction_C0.tcl 
source ./src/components/Image_Enhancement_C2.tcl 
source ./src/components/Bayer_Interpolation_C1.tcl 
source ./src/components/Defective_Pixel_C2.tcl 
source ./src/components/Gamma_Correction_C1.tcl 
source ./src/components/Image_Enhancement_C1.tcl 
source ./src/components/Edge_Detection_C0.tcl 
source ./src/components/RGBtoYCbCr_C0.tcl 
source ./src/components/YCbCrtoRGB_C0.tcl 
source ./src/components/Bayer_Interpolation_C0.tcl 
source ./src/components/Defective_Pixel_C1.tcl 
source ./src/components/Gamma_Correction_C2.tcl 
source ./src/components/Image_Enhancement_C0.tcl 

# Generate SmartDesign Components
source ./src/components/CAM_IOD_TIP_TOP.tcl 
source ./src/components/IMX334_IF_TOP.tcl 
source ./src/components/UART_interface.tcl 
source ./src/components/Clocks_and_Resets.tcl
source ./src/components/DDR_Read_scale.tcl 
source ./src/components/Alpha_Blending_Histogram.tcl 
source ./src/components/Edge_Detection_Block.tcl 
source ./src/components/Delay_Compensation.tcl 
source ./src/components/Display_Controller_Block.tcl 
source ./src/components/HDMI_2p0.tcl 
source ./src/components/HDMI_RX_FIFO.tcl 
source ./src/components/ISP_BLOCK_CAM1.tcl 
source ./src/components/Video_Processing_Block_CAM2_SCALE.tcl 
source ./src/components/ISP_Block_HDMI_4K.tcl 
source ./src/components/Memory_Read.tcl 
source ./src/components/Memory_Write.tcl 
source ./src/components/Video_Alignment_Selection.tcl 
source ./src/components/Video_Processing_Block_HD_CAM1.tcl 
source ./src/components/Video_Processing_Block_TOP.tcl

build_design_hierarchy 

source ./src/components/Video_Pipelining_Block.tcl 
source ./src/components/PROC_SUBSYSTEM_MiV_AXI.tcl 
build_design_hierarchy 

source ./src/components/top.tcl 

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
