# Creating SmartDesign "Memory_Write"
set sd_name {Memory_Write}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_CAM2_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_CAM2_RESET} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_AWREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_AWREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_CLK_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_AWREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_AWVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_WVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_AWVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_WVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_AWVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_WVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TREADY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_I_0} -port_direction {IN} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_I} -port_direction {IN} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_I_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_I} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_AWADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_AWSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel_WDATA_O} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_display_frame_addr_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_AWADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_AWSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel_WDATA_O} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_display_frame_addr_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_AWADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_AWSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel_WDATA_O} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_display_frame_addr_o} -port_direction {OUT} -port_range {[7:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:TVALID_I" \
"TREADY:TREADY_O" \
"TDATA:TDATA_I" \
"TUSER:TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:TVALID_I_0" \
"TREADY:TREADY_O_0" \
"TDATA:TDATA_I_0" \
"TUSER:TUSER_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_Write_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {master} -port_bif_mapping {\
"AWADDR:CAM1_Write_Channel_AWADDR_O" \
"AWSIZE:CAM1_Write_Channel_AWSIZE_O" \
"AWVALID:CAM1_Write_Channel_AWVALID_O" \
"AWREADY:CAM1_Write_Channel_AWREADY_I" \
"WDATA:CAM1_Write_Channel_WDATA_O" \
"WVALID:CAM1_Write_Channel_WVALID_O" \
"BUSER:CAM1_Write_Channel_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM2_Write_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {master} -port_bif_mapping {\
"AWADDR:CAM2_Write_Channel_AWADDR_O" \
"AWSIZE:CAM2_Write_Channel_AWSIZE_O" \
"AWVALID:CAM2_Write_Channel_AWVALID_O" \
"AWREADY:CAM2_Write_Channel_AWREADY_I" \
"WDATA:CAM2_Write_Channel_WDATA_O" \
"WVALID:CAM2_Write_Channel_WVALID_O" \
"BUSER:CAM2_Write_Channel_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_RX_Write_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {master} -port_bif_mapping {\
"AWADDR:HDMI_RX_Write_Channel_AWADDR_O" \
"AWSIZE:HDMI_RX_Write_Channel_AWSIZE_O" \
"AWVALID:HDMI_RX_Write_Channel_AWVALID_O" \
"AWREADY:HDMI_RX_Write_Channel_AWREADY_I" \
"WDATA:HDMI_RX_Write_Channel_WDATA_O" \
"WVALID:HDMI_RX_Write_Channel_WVALID_O" \
"BUSER:HDMI_RX_Write_Channel_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:TVALID_I_1" \
"TREADY:TREADY_O_1" \
"TDATA:TDATA_I_1" \
"TUSER:TUSER_I_1" } 

# Add AXI4S_ddr_write_target_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_ddr_write_bus_target_IF} -instance_name {AXI4S_ddr_write_target_IF_0}
# Exporting Parameters of instance AXI4S_ddr_write_target_IF_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_0} -params {\
"G_AXIBUS_WIDTH:40" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_0}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[11:10]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_0:DATA_O[11:10]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[19:12]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_0:DATA_O[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[21:20]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_0:DATA_O[21:20]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[29:22]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[31:30]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_0:DATA_O[31:30]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_0:DATA_O} -pin_slices {[9:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_0:VSYNC_O}



# Add AXI4S_ddr_write_target_IF_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_ddr_write_bus_target_IF} -instance_name {AXI4S_ddr_write_target_IF_1}
# Exporting Parameters of instance AXI4S_ddr_write_target_IF_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_1} -params {\
"G_AXIBUS_WIDTH:40" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_1}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_ddr_write_target_IF_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[11:10]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_1:DATA_O[11:10]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[19:12]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_1:DATA_O[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[21:20]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_1:DATA_O[21:20]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[29:22]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[31:30]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_1:DATA_O[31:30]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {AXI4S_ddr_write_target_IF_1:DATA_O} -pin_slices {[9:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {AXI4S_ddr_write_target_IF_1:VSYNC_O}



# Add DDR_Write_CAM1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C3} -instance_name {DDR_Write_CAM1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM1:data_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM1:data_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM1:data_i} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM1:data_i} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_CAM1:line_gap_i} -value {0001000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_CAM1:frame_ddr_addr_i} -value {00000000}



# Add DDR_Write_CAM2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C4} -instance_name {DDR_Write_CAM2}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM2:data_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM2:data_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM2:data_i} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_CAM2:data_i} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_CAM2:line_gap_i} -value {0001000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_CAM2:frame_ddr_addr_i} -value {00000100}



# Add DDR_Write_HDMI_RX instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C5} -instance_name {DDR_Write_HDMI_RX}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX:line_gap_i} -value {0010000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX:frame_ddr_addr_i} -value {00001000}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:DATA_VALID_O" "DDR_Write_CAM1:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:FRAME_VALID_O" "DDR_Write_CAM1:frame_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:DATA_VALID_O" "DDR_Write_CAM2:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:FRAME_VALID_O" "DDR_Write_CAM2:frame_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_CAM2_CLK" "DDR_Write_CAM1:pixel_clk_i" "DDR_Write_CAM2:pixel_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_CAM2_RESET" "DDR_Write_CAM1:rstn_i" "DDR_Write_CAM2:rstn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_CLK_I" "DDR_Write_CAM1:ddr_clk_i" "DDR_Write_CAM2:ddr_clk_i" "DDR_Write_HDMI_RX:ddr_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_CLK_RESET_I" "DDR_Write_CAM1:ddr_clk_rstn_i" "DDR_Write_CAM2:ddr_clk_rstn_i" "DDR_Write_HDMI_RX:ddr_clk_rstn_i" "DDR_Write_HDMI_RX:rstn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_HDMI_RX:pixel_clk_i" "HDMI_RX_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:DATA_O[19:12]" "DDR_Write_CAM1:data_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:DATA_O[29:22]" "DDR_Write_CAM1:data_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:DATA_O[39:32]" "DDR_Write_CAM1:data_i[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:DATA_O[9:2]" "DDR_Write_CAM1:data_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:DATA_O[19:12]" "DDR_Write_CAM2:data_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:DATA_O[29:22]" "DDR_Write_CAM2:data_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:DATA_O[39:32]" "DDR_Write_CAM2:data_i[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:DATA_O[9:2]" "DDR_Write_CAM2:data_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_display_frame_addr_o" "DDR_Write_CAM1:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_display_frame_addr_o" "DDR_Write_CAM2:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_HDMI_RX:display_frame_addr_o" "HDMI_RX_display_frame_addr_o" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_0:AXI4S_Target_IF" "CSI2_RX_DEC0_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_ddr_write_target_IF_1:AXI4S_Target_IF" "CSI2_RX_DEC1_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_Write_Channel" "DDR_Write_CAM1:Write_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_Write_Channel" "DDR_Write_CAM2:Write_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_HDMI_RX:AXI4Stream_Target_IF" "HDMI_RX_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_HDMI_RX:Write_channel" "HDMI_RX_Write_Channel" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Memory_Write"
generate_component -component_name ${sd_name}
