# Creating SmartDesign "PROC_SUBSYSTEM_MiV_AXI"
set sd_name {PROC_SUBSYSTEM_MiV_AXI}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APBmslave9_PREADYS9} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APBmslave9_PSLVERRS9} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APBmslave9_PENABLES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APBmslave9_PSELS9} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APBmslave9_PWRITES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK_EN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APBmslave9_PRDATAS9} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_RUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_BID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RID} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_RUSER} -port_direction {IN} -port_range {[0:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APBmslave9_PADDRS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APBmslave9_PWDATAS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave0_SLAVE0_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave1_SLAVE1_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave2_SLAVE2_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave3_SLAVE3_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave4_SLAVE4_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave5_SLAVE5_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave6_SLAVE6_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave7_SLAVE7_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave8_SLAVE8_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWID} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WSTRB} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4mslave9_SLAVE9_WUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APBmslave9} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"PADDR:APBmslave9_PADDRS" \
"PSELx:APBmslave9_PSELS9" \
"PENABLE:APBmslave9_PENABLES" \
"PWRITE:APBmslave9_PWRITES" \
"PRDATA:APBmslave9_PRDATAS9" \
"PWDATA:APBmslave9_PWDATAS" \
"PREADY:APBmslave9_PREADYS9" \
"PSLVERR:APBmslave9_PSLVERRS9" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave0} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave0_SLAVE0_AWID" \
"AWADDR:AXI4mslave0_SLAVE0_AWADDR" \
"AWLEN:AXI4mslave0_SLAVE0_AWLEN" \
"AWSIZE:AXI4mslave0_SLAVE0_AWSIZE" \
"AWBURST:AXI4mslave0_SLAVE0_AWBURST" \
"AWLOCK:AXI4mslave0_SLAVE0_AWLOCK" \
"AWCACHE:AXI4mslave0_SLAVE0_AWCACHE" \
"AWPROT:AXI4mslave0_SLAVE0_AWPROT" \
"AWQOS:AXI4mslave0_SLAVE0_AWQOS" \
"AWREGION:AXI4mslave0_SLAVE0_AWREGION" \
"AWVALID:AXI4mslave0_SLAVE0_AWVALID" \
"AWREADY:AXI4mslave0_SLAVE0_AWREADY" \
"WDATA:AXI4mslave0_SLAVE0_WDATA" \
"WSTRB:AXI4mslave0_SLAVE0_WSTRB" \
"WLAST:AXI4mslave0_SLAVE0_WLAST" \
"WVALID:AXI4mslave0_SLAVE0_WVALID" \
"WREADY:AXI4mslave0_SLAVE0_WREADY" \
"BID:AXI4mslave0_SLAVE0_BID" \
"BRESP:AXI4mslave0_SLAVE0_BRESP" \
"BVALID:AXI4mslave0_SLAVE0_BVALID" \
"BREADY:AXI4mslave0_SLAVE0_BREADY" \
"ARID:AXI4mslave0_SLAVE0_ARID" \
"ARADDR:AXI4mslave0_SLAVE0_ARADDR" \
"ARLEN:AXI4mslave0_SLAVE0_ARLEN" \
"ARSIZE:AXI4mslave0_SLAVE0_ARSIZE" \
"ARBURST:AXI4mslave0_SLAVE0_ARBURST" \
"ARLOCK:AXI4mslave0_SLAVE0_ARLOCK" \
"ARCACHE:AXI4mslave0_SLAVE0_ARCACHE" \
"ARPROT:AXI4mslave0_SLAVE0_ARPROT" \
"ARQOS:AXI4mslave0_SLAVE0_ARQOS" \
"ARREGION:AXI4mslave0_SLAVE0_ARREGION" \
"ARVALID:AXI4mslave0_SLAVE0_ARVALID" \
"ARREADY:AXI4mslave0_SLAVE0_ARREADY" \
"RID:AXI4mslave0_SLAVE0_RID" \
"RDATA:AXI4mslave0_SLAVE0_RDATA" \
"RRESP:AXI4mslave0_SLAVE0_RRESP" \
"RLAST:AXI4mslave0_SLAVE0_RLAST" \
"RVALID:AXI4mslave0_SLAVE0_RVALID" \
"RREADY:AXI4mslave0_SLAVE0_RREADY" \
"AWUSER:AXI4mslave0_SLAVE0_AWUSER" \
"WUSER:AXI4mslave0_SLAVE0_WUSER" \
"BUSER:AXI4mslave0_SLAVE0_BUSER" \
"ARUSER:AXI4mslave0_SLAVE0_ARUSER" \
"RUSER:AXI4mslave0_SLAVE0_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave1_SLAVE1_AWID" \
"AWADDR:AXI4mslave1_SLAVE1_AWADDR" \
"AWLEN:AXI4mslave1_SLAVE1_AWLEN" \
"AWSIZE:AXI4mslave1_SLAVE1_AWSIZE" \
"AWBURST:AXI4mslave1_SLAVE1_AWBURST" \
"AWLOCK:AXI4mslave1_SLAVE1_AWLOCK" \
"AWCACHE:AXI4mslave1_SLAVE1_AWCACHE" \
"AWPROT:AXI4mslave1_SLAVE1_AWPROT" \
"AWQOS:AXI4mslave1_SLAVE1_AWQOS" \
"AWREGION:AXI4mslave1_SLAVE1_AWREGION" \
"AWVALID:AXI4mslave1_SLAVE1_AWVALID" \
"AWREADY:AXI4mslave1_SLAVE1_AWREADY" \
"WDATA:AXI4mslave1_SLAVE1_WDATA" \
"WSTRB:AXI4mslave1_SLAVE1_WSTRB" \
"WLAST:AXI4mslave1_SLAVE1_WLAST" \
"WVALID:AXI4mslave1_SLAVE1_WVALID" \
"WREADY:AXI4mslave1_SLAVE1_WREADY" \
"BID:AXI4mslave1_SLAVE1_BID" \
"BRESP:AXI4mslave1_SLAVE1_BRESP" \
"BVALID:AXI4mslave1_SLAVE1_BVALID" \
"BREADY:AXI4mslave1_SLAVE1_BREADY" \
"ARID:AXI4mslave1_SLAVE1_ARID" \
"ARADDR:AXI4mslave1_SLAVE1_ARADDR" \
"ARLEN:AXI4mslave1_SLAVE1_ARLEN" \
"ARSIZE:AXI4mslave1_SLAVE1_ARSIZE" \
"ARBURST:AXI4mslave1_SLAVE1_ARBURST" \
"ARLOCK:AXI4mslave1_SLAVE1_ARLOCK" \
"ARCACHE:AXI4mslave1_SLAVE1_ARCACHE" \
"ARPROT:AXI4mslave1_SLAVE1_ARPROT" \
"ARQOS:AXI4mslave1_SLAVE1_ARQOS" \
"ARREGION:AXI4mslave1_SLAVE1_ARREGION" \
"ARVALID:AXI4mslave1_SLAVE1_ARVALID" \
"ARREADY:AXI4mslave1_SLAVE1_ARREADY" \
"RID:AXI4mslave1_SLAVE1_RID" \
"RDATA:AXI4mslave1_SLAVE1_RDATA" \
"RRESP:AXI4mslave1_SLAVE1_RRESP" \
"RLAST:AXI4mslave1_SLAVE1_RLAST" \
"RVALID:AXI4mslave1_SLAVE1_RVALID" \
"RREADY:AXI4mslave1_SLAVE1_RREADY" \
"AWUSER:AXI4mslave1_SLAVE1_AWUSER" \
"WUSER:AXI4mslave1_SLAVE1_WUSER" \
"BUSER:AXI4mslave1_SLAVE1_BUSER" \
"ARUSER:AXI4mslave1_SLAVE1_ARUSER" \
"RUSER:AXI4mslave1_SLAVE1_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave2} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave2_SLAVE2_AWID" \
"AWADDR:AXI4mslave2_SLAVE2_AWADDR" \
"AWLEN:AXI4mslave2_SLAVE2_AWLEN" \
"AWSIZE:AXI4mslave2_SLAVE2_AWSIZE" \
"AWBURST:AXI4mslave2_SLAVE2_AWBURST" \
"AWLOCK:AXI4mslave2_SLAVE2_AWLOCK" \
"AWCACHE:AXI4mslave2_SLAVE2_AWCACHE" \
"AWPROT:AXI4mslave2_SLAVE2_AWPROT" \
"AWQOS:AXI4mslave2_SLAVE2_AWQOS" \
"AWREGION:AXI4mslave2_SLAVE2_AWREGION" \
"AWVALID:AXI4mslave2_SLAVE2_AWVALID" \
"AWREADY:AXI4mslave2_SLAVE2_AWREADY" \
"WDATA:AXI4mslave2_SLAVE2_WDATA" \
"WSTRB:AXI4mslave2_SLAVE2_WSTRB" \
"WLAST:AXI4mslave2_SLAVE2_WLAST" \
"WVALID:AXI4mslave2_SLAVE2_WVALID" \
"WREADY:AXI4mslave2_SLAVE2_WREADY" \
"BID:AXI4mslave2_SLAVE2_BID" \
"BRESP:AXI4mslave2_SLAVE2_BRESP" \
"BVALID:AXI4mslave2_SLAVE2_BVALID" \
"BREADY:AXI4mslave2_SLAVE2_BREADY" \
"ARID:AXI4mslave2_SLAVE2_ARID" \
"ARADDR:AXI4mslave2_SLAVE2_ARADDR" \
"ARLEN:AXI4mslave2_SLAVE2_ARLEN" \
"ARSIZE:AXI4mslave2_SLAVE2_ARSIZE" \
"ARBURST:AXI4mslave2_SLAVE2_ARBURST" \
"ARLOCK:AXI4mslave2_SLAVE2_ARLOCK" \
"ARCACHE:AXI4mslave2_SLAVE2_ARCACHE" \
"ARPROT:AXI4mslave2_SLAVE2_ARPROT" \
"ARQOS:AXI4mslave2_SLAVE2_ARQOS" \
"ARREGION:AXI4mslave2_SLAVE2_ARREGION" \
"ARVALID:AXI4mslave2_SLAVE2_ARVALID" \
"ARREADY:AXI4mslave2_SLAVE2_ARREADY" \
"RID:AXI4mslave2_SLAVE2_RID" \
"RDATA:AXI4mslave2_SLAVE2_RDATA" \
"RRESP:AXI4mslave2_SLAVE2_RRESP" \
"RLAST:AXI4mslave2_SLAVE2_RLAST" \
"RVALID:AXI4mslave2_SLAVE2_RVALID" \
"RREADY:AXI4mslave2_SLAVE2_RREADY" \
"AWUSER:AXI4mslave2_SLAVE2_AWUSER" \
"WUSER:AXI4mslave2_SLAVE2_WUSER" \
"BUSER:AXI4mslave2_SLAVE2_BUSER" \
"ARUSER:AXI4mslave2_SLAVE2_ARUSER" \
"RUSER:AXI4mslave2_SLAVE2_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave3} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave3_SLAVE3_AWID" \
"AWADDR:AXI4mslave3_SLAVE3_AWADDR" \
"AWLEN:AXI4mslave3_SLAVE3_AWLEN" \
"AWSIZE:AXI4mslave3_SLAVE3_AWSIZE" \
"AWBURST:AXI4mslave3_SLAVE3_AWBURST" \
"AWLOCK:AXI4mslave3_SLAVE3_AWLOCK" \
"AWCACHE:AXI4mslave3_SLAVE3_AWCACHE" \
"AWPROT:AXI4mslave3_SLAVE3_AWPROT" \
"AWQOS:AXI4mslave3_SLAVE3_AWQOS" \
"AWREGION:AXI4mslave3_SLAVE3_AWREGION" \
"AWVALID:AXI4mslave3_SLAVE3_AWVALID" \
"AWREADY:AXI4mslave3_SLAVE3_AWREADY" \
"WDATA:AXI4mslave3_SLAVE3_WDATA" \
"WSTRB:AXI4mslave3_SLAVE3_WSTRB" \
"WLAST:AXI4mslave3_SLAVE3_WLAST" \
"WVALID:AXI4mslave3_SLAVE3_WVALID" \
"WREADY:AXI4mslave3_SLAVE3_WREADY" \
"BID:AXI4mslave3_SLAVE3_BID" \
"BRESP:AXI4mslave3_SLAVE3_BRESP" \
"BVALID:AXI4mslave3_SLAVE3_BVALID" \
"BREADY:AXI4mslave3_SLAVE3_BREADY" \
"ARID:AXI4mslave3_SLAVE3_ARID" \
"ARADDR:AXI4mslave3_SLAVE3_ARADDR" \
"ARLEN:AXI4mslave3_SLAVE3_ARLEN" \
"ARSIZE:AXI4mslave3_SLAVE3_ARSIZE" \
"ARBURST:AXI4mslave3_SLAVE3_ARBURST" \
"ARLOCK:AXI4mslave3_SLAVE3_ARLOCK" \
"ARCACHE:AXI4mslave3_SLAVE3_ARCACHE" \
"ARPROT:AXI4mslave3_SLAVE3_ARPROT" \
"ARQOS:AXI4mslave3_SLAVE3_ARQOS" \
"ARREGION:AXI4mslave3_SLAVE3_ARREGION" \
"ARVALID:AXI4mslave3_SLAVE3_ARVALID" \
"ARREADY:AXI4mslave3_SLAVE3_ARREADY" \
"RID:AXI4mslave3_SLAVE3_RID" \
"RDATA:AXI4mslave3_SLAVE3_RDATA" \
"RRESP:AXI4mslave3_SLAVE3_RRESP" \
"RLAST:AXI4mslave3_SLAVE3_RLAST" \
"RVALID:AXI4mslave3_SLAVE3_RVALID" \
"RREADY:AXI4mslave3_SLAVE3_RREADY" \
"AWUSER:AXI4mslave3_SLAVE3_AWUSER" \
"WUSER:AXI4mslave3_SLAVE3_WUSER" \
"BUSER:AXI4mslave3_SLAVE3_BUSER" \
"ARUSER:AXI4mslave3_SLAVE3_ARUSER" \
"RUSER:AXI4mslave3_SLAVE3_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave4} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave4_SLAVE4_AWID" \
"AWADDR:AXI4mslave4_SLAVE4_AWADDR" \
"AWLEN:AXI4mslave4_SLAVE4_AWLEN" \
"AWSIZE:AXI4mslave4_SLAVE4_AWSIZE" \
"AWBURST:AXI4mslave4_SLAVE4_AWBURST" \
"AWLOCK:AXI4mslave4_SLAVE4_AWLOCK" \
"AWCACHE:AXI4mslave4_SLAVE4_AWCACHE" \
"AWPROT:AXI4mslave4_SLAVE4_AWPROT" \
"AWQOS:AXI4mslave4_SLAVE4_AWQOS" \
"AWREGION:AXI4mslave4_SLAVE4_AWREGION" \
"AWVALID:AXI4mslave4_SLAVE4_AWVALID" \
"AWREADY:AXI4mslave4_SLAVE4_AWREADY" \
"WDATA:AXI4mslave4_SLAVE4_WDATA" \
"WSTRB:AXI4mslave4_SLAVE4_WSTRB" \
"WLAST:AXI4mslave4_SLAVE4_WLAST" \
"WVALID:AXI4mslave4_SLAVE4_WVALID" \
"WREADY:AXI4mslave4_SLAVE4_WREADY" \
"BID:AXI4mslave4_SLAVE4_BID" \
"BRESP:AXI4mslave4_SLAVE4_BRESP" \
"BVALID:AXI4mslave4_SLAVE4_BVALID" \
"BREADY:AXI4mslave4_SLAVE4_BREADY" \
"ARID:AXI4mslave4_SLAVE4_ARID" \
"ARADDR:AXI4mslave4_SLAVE4_ARADDR" \
"ARLEN:AXI4mslave4_SLAVE4_ARLEN" \
"ARSIZE:AXI4mslave4_SLAVE4_ARSIZE" \
"ARBURST:AXI4mslave4_SLAVE4_ARBURST" \
"ARLOCK:AXI4mslave4_SLAVE4_ARLOCK" \
"ARCACHE:AXI4mslave4_SLAVE4_ARCACHE" \
"ARPROT:AXI4mslave4_SLAVE4_ARPROT" \
"ARQOS:AXI4mslave4_SLAVE4_ARQOS" \
"ARREGION:AXI4mslave4_SLAVE4_ARREGION" \
"ARVALID:AXI4mslave4_SLAVE4_ARVALID" \
"ARREADY:AXI4mslave4_SLAVE4_ARREADY" \
"RID:AXI4mslave4_SLAVE4_RID" \
"RDATA:AXI4mslave4_SLAVE4_RDATA" \
"RRESP:AXI4mslave4_SLAVE4_RRESP" \
"RLAST:AXI4mslave4_SLAVE4_RLAST" \
"RVALID:AXI4mslave4_SLAVE4_RVALID" \
"RREADY:AXI4mslave4_SLAVE4_RREADY" \
"AWUSER:AXI4mslave4_SLAVE4_AWUSER" \
"WUSER:AXI4mslave4_SLAVE4_WUSER" \
"BUSER:AXI4mslave4_SLAVE4_BUSER" \
"ARUSER:AXI4mslave4_SLAVE4_ARUSER" \
"RUSER:AXI4mslave4_SLAVE4_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave5} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave5_SLAVE5_AWID" \
"AWADDR:AXI4mslave5_SLAVE5_AWADDR" \
"AWLEN:AXI4mslave5_SLAVE5_AWLEN" \
"AWSIZE:AXI4mslave5_SLAVE5_AWSIZE" \
"AWBURST:AXI4mslave5_SLAVE5_AWBURST" \
"AWLOCK:AXI4mslave5_SLAVE5_AWLOCK" \
"AWCACHE:AXI4mslave5_SLAVE5_AWCACHE" \
"AWPROT:AXI4mslave5_SLAVE5_AWPROT" \
"AWQOS:AXI4mslave5_SLAVE5_AWQOS" \
"AWREGION:AXI4mslave5_SLAVE5_AWREGION" \
"AWVALID:AXI4mslave5_SLAVE5_AWVALID" \
"AWREADY:AXI4mslave5_SLAVE5_AWREADY" \
"WDATA:AXI4mslave5_SLAVE5_WDATA" \
"WSTRB:AXI4mslave5_SLAVE5_WSTRB" \
"WLAST:AXI4mslave5_SLAVE5_WLAST" \
"WVALID:AXI4mslave5_SLAVE5_WVALID" \
"WREADY:AXI4mslave5_SLAVE5_WREADY" \
"BID:AXI4mslave5_SLAVE5_BID" \
"BRESP:AXI4mslave5_SLAVE5_BRESP" \
"BVALID:AXI4mslave5_SLAVE5_BVALID" \
"BREADY:AXI4mslave5_SLAVE5_BREADY" \
"ARID:AXI4mslave5_SLAVE5_ARID" \
"ARADDR:AXI4mslave5_SLAVE5_ARADDR" \
"ARLEN:AXI4mslave5_SLAVE5_ARLEN" \
"ARSIZE:AXI4mslave5_SLAVE5_ARSIZE" \
"ARBURST:AXI4mslave5_SLAVE5_ARBURST" \
"ARLOCK:AXI4mslave5_SLAVE5_ARLOCK" \
"ARCACHE:AXI4mslave5_SLAVE5_ARCACHE" \
"ARPROT:AXI4mslave5_SLAVE5_ARPROT" \
"ARQOS:AXI4mslave5_SLAVE5_ARQOS" \
"ARREGION:AXI4mslave5_SLAVE5_ARREGION" \
"ARVALID:AXI4mslave5_SLAVE5_ARVALID" \
"ARREADY:AXI4mslave5_SLAVE5_ARREADY" \
"RID:AXI4mslave5_SLAVE5_RID" \
"RDATA:AXI4mslave5_SLAVE5_RDATA" \
"RRESP:AXI4mslave5_SLAVE5_RRESP" \
"RLAST:AXI4mslave5_SLAVE5_RLAST" \
"RVALID:AXI4mslave5_SLAVE5_RVALID" \
"RREADY:AXI4mslave5_SLAVE5_RREADY" \
"AWUSER:AXI4mslave5_SLAVE5_AWUSER" \
"WUSER:AXI4mslave5_SLAVE5_WUSER" \
"BUSER:AXI4mslave5_SLAVE5_BUSER" \
"ARUSER:AXI4mslave5_SLAVE5_ARUSER" \
"RUSER:AXI4mslave5_SLAVE5_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave6} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave6_SLAVE6_AWID" \
"AWADDR:AXI4mslave6_SLAVE6_AWADDR" \
"AWLEN:AXI4mslave6_SLAVE6_AWLEN" \
"AWSIZE:AXI4mslave6_SLAVE6_AWSIZE" \
"AWBURST:AXI4mslave6_SLAVE6_AWBURST" \
"AWLOCK:AXI4mslave6_SLAVE6_AWLOCK" \
"AWCACHE:AXI4mslave6_SLAVE6_AWCACHE" \
"AWPROT:AXI4mslave6_SLAVE6_AWPROT" \
"AWQOS:AXI4mslave6_SLAVE6_AWQOS" \
"AWREGION:AXI4mslave6_SLAVE6_AWREGION" \
"AWVALID:AXI4mslave6_SLAVE6_AWVALID" \
"AWREADY:AXI4mslave6_SLAVE6_AWREADY" \
"WDATA:AXI4mslave6_SLAVE6_WDATA" \
"WSTRB:AXI4mslave6_SLAVE6_WSTRB" \
"WLAST:AXI4mslave6_SLAVE6_WLAST" \
"WVALID:AXI4mslave6_SLAVE6_WVALID" \
"WREADY:AXI4mslave6_SLAVE6_WREADY" \
"BID:AXI4mslave6_SLAVE6_BID" \
"BRESP:AXI4mslave6_SLAVE6_BRESP" \
"BVALID:AXI4mslave6_SLAVE6_BVALID" \
"BREADY:AXI4mslave6_SLAVE6_BREADY" \
"ARID:AXI4mslave6_SLAVE6_ARID" \
"ARADDR:AXI4mslave6_SLAVE6_ARADDR" \
"ARLEN:AXI4mslave6_SLAVE6_ARLEN" \
"ARSIZE:AXI4mslave6_SLAVE6_ARSIZE" \
"ARBURST:AXI4mslave6_SLAVE6_ARBURST" \
"ARLOCK:AXI4mslave6_SLAVE6_ARLOCK" \
"ARCACHE:AXI4mslave6_SLAVE6_ARCACHE" \
"ARPROT:AXI4mslave6_SLAVE6_ARPROT" \
"ARQOS:AXI4mslave6_SLAVE6_ARQOS" \
"ARREGION:AXI4mslave6_SLAVE6_ARREGION" \
"ARVALID:AXI4mslave6_SLAVE6_ARVALID" \
"ARREADY:AXI4mslave6_SLAVE6_ARREADY" \
"RID:AXI4mslave6_SLAVE6_RID" \
"RDATA:AXI4mslave6_SLAVE6_RDATA" \
"RRESP:AXI4mslave6_SLAVE6_RRESP" \
"RLAST:AXI4mslave6_SLAVE6_RLAST" \
"RVALID:AXI4mslave6_SLAVE6_RVALID" \
"RREADY:AXI4mslave6_SLAVE6_RREADY" \
"AWUSER:AXI4mslave6_SLAVE6_AWUSER" \
"WUSER:AXI4mslave6_SLAVE6_WUSER" \
"BUSER:AXI4mslave6_SLAVE6_BUSER" \
"ARUSER:AXI4mslave6_SLAVE6_ARUSER" \
"RUSER:AXI4mslave6_SLAVE6_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave7} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave7_SLAVE7_AWID" \
"AWADDR:AXI4mslave7_SLAVE7_AWADDR" \
"AWLEN:AXI4mslave7_SLAVE7_AWLEN" \
"AWSIZE:AXI4mslave7_SLAVE7_AWSIZE" \
"AWBURST:AXI4mslave7_SLAVE7_AWBURST" \
"AWLOCK:AXI4mslave7_SLAVE7_AWLOCK" \
"AWCACHE:AXI4mslave7_SLAVE7_AWCACHE" \
"AWPROT:AXI4mslave7_SLAVE7_AWPROT" \
"AWQOS:AXI4mslave7_SLAVE7_AWQOS" \
"AWREGION:AXI4mslave7_SLAVE7_AWREGION" \
"AWVALID:AXI4mslave7_SLAVE7_AWVALID" \
"AWREADY:AXI4mslave7_SLAVE7_AWREADY" \
"WDATA:AXI4mslave7_SLAVE7_WDATA" \
"WSTRB:AXI4mslave7_SLAVE7_WSTRB" \
"WLAST:AXI4mslave7_SLAVE7_WLAST" \
"WVALID:AXI4mslave7_SLAVE7_WVALID" \
"WREADY:AXI4mslave7_SLAVE7_WREADY" \
"BID:AXI4mslave7_SLAVE7_BID" \
"BRESP:AXI4mslave7_SLAVE7_BRESP" \
"BVALID:AXI4mslave7_SLAVE7_BVALID" \
"BREADY:AXI4mslave7_SLAVE7_BREADY" \
"ARID:AXI4mslave7_SLAVE7_ARID" \
"ARADDR:AXI4mslave7_SLAVE7_ARADDR" \
"ARLEN:AXI4mslave7_SLAVE7_ARLEN" \
"ARSIZE:AXI4mslave7_SLAVE7_ARSIZE" \
"ARBURST:AXI4mslave7_SLAVE7_ARBURST" \
"ARLOCK:AXI4mslave7_SLAVE7_ARLOCK" \
"ARCACHE:AXI4mslave7_SLAVE7_ARCACHE" \
"ARPROT:AXI4mslave7_SLAVE7_ARPROT" \
"ARQOS:AXI4mslave7_SLAVE7_ARQOS" \
"ARREGION:AXI4mslave7_SLAVE7_ARREGION" \
"ARVALID:AXI4mslave7_SLAVE7_ARVALID" \
"ARREADY:AXI4mslave7_SLAVE7_ARREADY" \
"RID:AXI4mslave7_SLAVE7_RID" \
"RDATA:AXI4mslave7_SLAVE7_RDATA" \
"RRESP:AXI4mslave7_SLAVE7_RRESP" \
"RLAST:AXI4mslave7_SLAVE7_RLAST" \
"RVALID:AXI4mslave7_SLAVE7_RVALID" \
"RREADY:AXI4mslave7_SLAVE7_RREADY" \
"AWUSER:AXI4mslave7_SLAVE7_AWUSER" \
"WUSER:AXI4mslave7_SLAVE7_WUSER" \
"BUSER:AXI4mslave7_SLAVE7_BUSER" \
"ARUSER:AXI4mslave7_SLAVE7_ARUSER" \
"RUSER:AXI4mslave7_SLAVE7_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave8} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave8_SLAVE8_AWID" \
"AWADDR:AXI4mslave8_SLAVE8_AWADDR" \
"AWLEN:AXI4mslave8_SLAVE8_AWLEN" \
"AWSIZE:AXI4mslave8_SLAVE8_AWSIZE" \
"AWBURST:AXI4mslave8_SLAVE8_AWBURST" \
"AWLOCK:AXI4mslave8_SLAVE8_AWLOCK" \
"AWCACHE:AXI4mslave8_SLAVE8_AWCACHE" \
"AWPROT:AXI4mslave8_SLAVE8_AWPROT" \
"AWQOS:AXI4mslave8_SLAVE8_AWQOS" \
"AWREGION:AXI4mslave8_SLAVE8_AWREGION" \
"AWVALID:AXI4mslave8_SLAVE8_AWVALID" \
"AWREADY:AXI4mslave8_SLAVE8_AWREADY" \
"WDATA:AXI4mslave8_SLAVE8_WDATA" \
"WSTRB:AXI4mslave8_SLAVE8_WSTRB" \
"WLAST:AXI4mslave8_SLAVE8_WLAST" \
"WVALID:AXI4mslave8_SLAVE8_WVALID" \
"WREADY:AXI4mslave8_SLAVE8_WREADY" \
"BID:AXI4mslave8_SLAVE8_BID" \
"BRESP:AXI4mslave8_SLAVE8_BRESP" \
"BVALID:AXI4mslave8_SLAVE8_BVALID" \
"BREADY:AXI4mslave8_SLAVE8_BREADY" \
"ARID:AXI4mslave8_SLAVE8_ARID" \
"ARADDR:AXI4mslave8_SLAVE8_ARADDR" \
"ARLEN:AXI4mslave8_SLAVE8_ARLEN" \
"ARSIZE:AXI4mslave8_SLAVE8_ARSIZE" \
"ARBURST:AXI4mslave8_SLAVE8_ARBURST" \
"ARLOCK:AXI4mslave8_SLAVE8_ARLOCK" \
"ARCACHE:AXI4mslave8_SLAVE8_ARCACHE" \
"ARPROT:AXI4mslave8_SLAVE8_ARPROT" \
"ARQOS:AXI4mslave8_SLAVE8_ARQOS" \
"ARREGION:AXI4mslave8_SLAVE8_ARREGION" \
"ARVALID:AXI4mslave8_SLAVE8_ARVALID" \
"ARREADY:AXI4mslave8_SLAVE8_ARREADY" \
"RID:AXI4mslave8_SLAVE8_RID" \
"RDATA:AXI4mslave8_SLAVE8_RDATA" \
"RRESP:AXI4mslave8_SLAVE8_RRESP" \
"RLAST:AXI4mslave8_SLAVE8_RLAST" \
"RVALID:AXI4mslave8_SLAVE8_RVALID" \
"RREADY:AXI4mslave8_SLAVE8_RREADY" \
"AWUSER:AXI4mslave8_SLAVE8_AWUSER" \
"WUSER:AXI4mslave8_SLAVE8_WUSER" \
"BUSER:AXI4mslave8_SLAVE8_BUSER" \
"ARUSER:AXI4mslave8_SLAVE8_ARUSER" \
"RUSER:AXI4mslave8_SLAVE8_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI4mslave9} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:AXI4mslave9_SLAVE9_AWID" \
"AWADDR:AXI4mslave9_SLAVE9_AWADDR" \
"AWLEN:AXI4mslave9_SLAVE9_AWLEN" \
"AWSIZE:AXI4mslave9_SLAVE9_AWSIZE" \
"AWBURST:AXI4mslave9_SLAVE9_AWBURST" \
"AWLOCK:AXI4mslave9_SLAVE9_AWLOCK" \
"AWCACHE:AXI4mslave9_SLAVE9_AWCACHE" \
"AWPROT:AXI4mslave9_SLAVE9_AWPROT" \
"AWQOS:AXI4mslave9_SLAVE9_AWQOS" \
"AWREGION:AXI4mslave9_SLAVE9_AWREGION" \
"AWVALID:AXI4mslave9_SLAVE9_AWVALID" \
"AWREADY:AXI4mslave9_SLAVE9_AWREADY" \
"WDATA:AXI4mslave9_SLAVE9_WDATA" \
"WSTRB:AXI4mslave9_SLAVE9_WSTRB" \
"WLAST:AXI4mslave9_SLAVE9_WLAST" \
"WVALID:AXI4mslave9_SLAVE9_WVALID" \
"WREADY:AXI4mslave9_SLAVE9_WREADY" \
"BID:AXI4mslave9_SLAVE9_BID" \
"BRESP:AXI4mslave9_SLAVE9_BRESP" \
"BVALID:AXI4mslave9_SLAVE9_BVALID" \
"BREADY:AXI4mslave9_SLAVE9_BREADY" \
"ARID:AXI4mslave9_SLAVE9_ARID" \
"ARADDR:AXI4mslave9_SLAVE9_ARADDR" \
"ARLEN:AXI4mslave9_SLAVE9_ARLEN" \
"ARSIZE:AXI4mslave9_SLAVE9_ARSIZE" \
"ARBURST:AXI4mslave9_SLAVE9_ARBURST" \
"ARLOCK:AXI4mslave9_SLAVE9_ARLOCK" \
"ARCACHE:AXI4mslave9_SLAVE9_ARCACHE" \
"ARPROT:AXI4mslave9_SLAVE9_ARPROT" \
"ARQOS:AXI4mslave9_SLAVE9_ARQOS" \
"ARREGION:AXI4mslave9_SLAVE9_ARREGION" \
"ARVALID:AXI4mslave9_SLAVE9_ARVALID" \
"ARREADY:AXI4mslave9_SLAVE9_ARREADY" \
"RID:AXI4mslave9_SLAVE9_RID" \
"RDATA:AXI4mslave9_SLAVE9_RDATA" \
"RRESP:AXI4mslave9_SLAVE9_RRESP" \
"RLAST:AXI4mslave9_SLAVE9_RLAST" \
"RVALID:AXI4mslave9_SLAVE9_RVALID" \
"RREADY:AXI4mslave9_SLAVE9_RREADY" \
"AWUSER:AXI4mslave9_SLAVE9_AWUSER" \
"WUSER:AXI4mslave9_SLAVE9_WUSER" \
"BUSER:AXI4mslave9_SLAVE9_BUSER" \
"ARUSER:AXI4mslave9_SLAVE9_ARUSER" \
"RUSER:AXI4mslave9_SLAVE9_RUSER" } 

# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_0:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_0:E}



# Add BIBUF_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_1:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_1:E}



# Add BIBUF_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_2:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_2:E}



# Add BIBUF_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_3:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_3:E}



# Add BIBUF_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_4}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_4:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_4:E}



# Add BIBUF_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_5}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_5:D} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {BIBUF_5:E}



# Add CoreAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave6}



# Add COREAXI4INTERCONNECT_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAXI4INTERCONNECT_C0} -instance_name {COREAXI4INTERCONNECT_C0_0}



# Add CoreGPIO_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_C0} -instance_name {CoreGPIO_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[31:10]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_OUT[31:10]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[6:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_OUT[6:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[8:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:INT}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_IN} -value {GND}



# Add COREI2C_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C0} -instance_name {COREI2C_C0_0}



# Add COREI2C_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C0} -instance_name {COREI2C_C0_1}



# Add COREI2C_C0_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C0} -instance_name {COREI2C_C0_2}



# Add COREJTAGDEBUG_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDEBUG_C0} -instance_name {COREJTAGDEBUG_C0_0}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32_C0_0:MSYS_EI} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32_C0_0:MSYS_EI} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32_C0_0:MSYS_EI} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_IRQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:TIME_COUNT_OUT}



# Add PF_SRAM_AHBL_AXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {PF_SRAM_AHBL_AXI_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "COREI2C_C0_0:SCLO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:PAD" "CAM2_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "COREI2C_C0_0:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:E" "COREI2C_C0_0:SDAO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:PAD" "CAM2_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:Y" "COREI2C_C0_0:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:E" "COREI2C_C0_1:SCLO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:PAD" "HDMI_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:Y" "COREI2C_C0_1:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:E" "COREI2C_C0_1:SDAO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:PAD" "HDMI_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:Y" "COREI2C_C0_1:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:E" "COREI2C_C0_2:SCLO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:PAD" "CAM1_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:Y" "COREI2C_C0_2:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:E" "COREI2C_C0_2:SDAO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:PAD" "CAM1_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:Y" "COREI2C_C0_2:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "CoreGPIO_C0_0:GPIO_OUT[8:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RST" "CoreGPIO_C0_0:GPIO_OUT[7:7]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK_EN" "CoreGPIO_C0_0:GPIO_OUT[9:9]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:ACLK" "COREI2C_C0_0:PCLK" "COREI2C_C0_1:PCLK" "COREI2C_C0_2:PCLK" "CoreGPIO_C0_0:PCLK" "MIV_RV32_C0_0:CLK" "PCLK" "PF_SRAM_AHBL_AXI_C0_0:HCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:ARESETN" "COREI2C_C0_0:PRESETN" "COREI2C_C0_1:PRESETN" "COREI2C_C0_2:PRESETN" "CoreGPIO_C0_0:PRESETN" "MIV_RV32_C0_0:RESETN" "PF_SRAM_AHBL_AXI_C0_0:HRESETN" "RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:INT" "MIV_RV32_C0_0:MSYS_EI[0:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_1:INT" "MIV_RV32_C0_0:MSYS_EI[1:1]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_2:INT" "MIV_RV32_C0_0:MSYS_EI[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_OUT[4:4]" "TRNG_RST_N" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_OUT[3:0]" "GPIO_OUT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APBmslave9" "CoreAPB3_C0_0:APBmslave9" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave0" "COREAXI4INTERCONNECT_C0_0:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave1" "COREAXI4INTERCONNECT_C0_0:AXI4mslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave2" "COREAXI4INTERCONNECT_C0_0:AXI4mslave2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave3" "COREAXI4INTERCONNECT_C0_0:AXI4mslave3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave4" "COREAXI4INTERCONNECT_C0_0:AXI4mslave4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave5" "COREAXI4INTERCONNECT_C0_0:AXI4mslave5" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave6" "COREAXI4INTERCONNECT_C0_0:AXI4mslave6" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave7" "COREAXI4INTERCONNECT_C0_0:AXI4mslave7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave8" "COREAXI4INTERCONNECT_C0_0:AXI4mslave8" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4mslave9" "COREAXI4INTERCONNECT_C0_0:AXI4mslave9" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAXI4INTERCONNECT_C0_0:AXI4mmaster0" "MIV_RV32_C0_0:AXI4_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:APBslave" "CoreAPB3_C0_0:APBmslave4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_1:APBslave" "CoreAPB3_C0_0:APBmslave8" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_2:APBslave" "CoreAPB3_C0_0:APBmslave7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APB3mmaster" "MIV_RV32_C0_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APBmslave5" "CoreGPIO_C0_0:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_C0_0:AHBL_M_TARGET" "PF_SRAM_AHBL_AXI_C0_0:AHBSlaveInterface" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "PROC_SUBSYSTEM_MiV_AXI"
generate_component -component_name ${sd_name}
