# Creating SmartDesign "Video_Pipelining_Block"
set sd_name {Video_Pipelining_Block}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_penable_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_psel_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pwrite_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BAYER_EDGE_SEL_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_CAM2_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_CAM2_RESET} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_DDR_PLL_REF_50MHz} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF_TVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H2p0_ENABLE_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_SYS_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_CLK_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4K_disp_clk_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF_TVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_HPD_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_RESET_N_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rlast} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PIP_Source_Select_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PIP_mode_selection_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_CURVE_WE_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_dpc_enable_sel_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_ctrl_ready_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pready_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pslverr_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF_TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF_TREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF_TREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wlast} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_HIST_RDY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {data_enable_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {horz_sync_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {vert_sync_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_paddr_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_pwdata_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF_TDATA_I} -port_direction {IN} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF_TDATA_I_0} -port_direction {IN} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF_TUSER_I_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF_TDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF_TUSER_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rdata} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_Alpha_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WADDR_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WDATA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_ADDR_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_b_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_brightness_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_contrast_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_bayer_sel_i} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_thr1_data_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_thr2_data_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_g_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_h_shift_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_r_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_step_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_v_shift_i} -port_direction {IN} -port_range {[15:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_prdata_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {B_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_5} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {G_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[95:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_araddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awaddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wdata} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wstrb} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_4} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_4} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_4} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_DATA_O} -port_direction {OUT} -port_range {[23:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:MIRRORED_SLAVE_AXI4_awid" \
"AWADDR:MIRRORED_SLAVE_AXI4_awaddr" \
"AWLEN:MIRRORED_SLAVE_AXI4_awlen" \
"AWSIZE:MIRRORED_SLAVE_AXI4_awsize" \
"AWBURST:MIRRORED_SLAVE_AXI4_awburst" \
"AWLOCK:MIRRORED_SLAVE_AXI4_awlock" \
"AWCACHE:MIRRORED_SLAVE_AXI4_awcache" \
"AWPROT:MIRRORED_SLAVE_AXI4_awprot" \
"AWVALID:MIRRORED_SLAVE_AXI4_awvalid" \
"AWREADY:MIRRORED_SLAVE_AXI4_awready" \
"WDATA:MIRRORED_SLAVE_AXI4_wdata" \
"WSTRB:MIRRORED_SLAVE_AXI4_wstrb" \
"WLAST:MIRRORED_SLAVE_AXI4_wlast" \
"WVALID:MIRRORED_SLAVE_AXI4_wvalid" \
"WREADY:MIRRORED_SLAVE_AXI4_wready" \
"BID:MIRRORED_SLAVE_AXI4_bid" \
"BRESP:MIRRORED_SLAVE_AXI4_bresp" \
"BVALID:MIRRORED_SLAVE_AXI4_bvalid" \
"BREADY:MIRRORED_SLAVE_AXI4_bready" \
"ARID:MIRRORED_SLAVE_AXI4_arid" \
"ARADDR:MIRRORED_SLAVE_AXI4_araddr" \
"ARLEN:MIRRORED_SLAVE_AXI4_arlen" \
"ARSIZE:MIRRORED_SLAVE_AXI4_arsize" \
"ARBURST:MIRRORED_SLAVE_AXI4_arburst" \
"ARLOCK:MIRRORED_SLAVE_AXI4_arlock" \
"ARCACHE:MIRRORED_SLAVE_AXI4_arcache" \
"ARPROT:MIRRORED_SLAVE_AXI4_arprot" \
"ARVALID:MIRRORED_SLAVE_AXI4_arvalid" \
"ARREADY:MIRRORED_SLAVE_AXI4_arready" \
"RID:MIRRORED_SLAVE_AXI4_rid" \
"RDATA:MIRRORED_SLAVE_AXI4_rdata" \
"RRESP:MIRRORED_SLAVE_AXI4_rresp" \
"RLAST:MIRRORED_SLAVE_AXI4_rlast" \
"RVALID:MIRRORED_SLAVE_AXI4_rvalid" \
"RREADY:MIRRORED_SLAVE_AXI4_rready" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:CSI2_RX_DEC0_AXI4S_Target_IF_TVALID_I" \
"TREADY:CSI2_RX_DEC0_AXI4S_Target_IF_TREADY_O" \
"TDATA:CSI2_RX_DEC0_AXI4S_Target_IF_TDATA_I" \
"TUSER:CSI2_RX_DEC0_AXI4S_Target_IF_TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:CSI2_RX_DEC1_AXI4S_Target_IF_TVALID_I_0" \
"TREADY:CSI2_RX_DEC1_AXI4S_Target_IF_TREADY_O_0" \
"TDATA:CSI2_RX_DEC1_AXI4S_Target_IF_TDATA_I_0" \
"TUSER:CSI2_RX_DEC1_AXI4S_Target_IF_TUSER_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_RX_AXI4S_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:HDMI_RX_AXI4S_Target_IF_TVALID_I_1" \
"TREADY:HDMI_RX_AXI4S_Target_IF_TREADY_O_1" \
"TDATA:HDMI_RX_AXI4S_Target_IF_TDATA_I_1" \
"TUSER:HDMI_RX_AXI4S_Target_IF_TUSER_I_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_TX_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:HDMI_TX_AXI4Stream_Initiator_IF_TVALID_O" \
"TDATA:HDMI_TX_AXI4Stream_Initiator_IF_TDATA_O" \
"TSTRB:HDMI_TX_AXI4Stream_Initiator_IF_TSTRB_O" \
"TKEEP:HDMI_TX_AXI4Stream_Initiator_IF_TKEEP_O" \
"TLAST:HDMI_TX_AXI4Stream_Initiator_IF_TLAST_O" \
"TUSER:HDMI_TX_AXI4Stream_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {APB_IF} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_IF_paddr_i" \
"PSELx:APB_IF_psel_i" \
"PENABLE:APB_IF_penable_i" \
"PWRITE:APB_IF_pwrite_i" \
"PRDATA:APB_IF_prdata_o" \
"PWDATA:APB_IF_pwdata_i" \
"PREADY:APB_IF_pready_o" \
"PSLVERR:APB_IF_pslverr_o" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_5" \
"AWVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_5" \
"AWREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_5" \
"WDATA:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_5" \
"WVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_5" \
"WREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_5" \
"BRESP:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_5" \
"BVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_5" \
"BREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_5" \
"ARADDR:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_5" \
"ARVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_5" \
"ARREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_5" \
"RDATA:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_5" \
"RRESP:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_5" \
"RVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_5" \
"RREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_5" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_1" \
"AWVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_1" \
"AWREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_1" \
"WDATA:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_1" \
"WVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_1" \
"WREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_1" \
"BRESP:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_1" \
"BVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_1" \
"BREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_1" \
"ARADDR:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_1" \
"ARVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_1" \
"ARREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_1" \
"RDATA:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_1" \
"RRESP:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_1" \
"RVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_1" \
"RREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1" \
"AWADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1" \
"AWLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1" \
"AWSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1" \
"AWBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1" \
"AWLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1" \
"AWCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1" \
"AWPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1" \
"AWQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1" \
"AWREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1" \
"AWVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1" \
"AWREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1" \
"WDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1" \
"WSTRB:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1" \
"WLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1" \
"WVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1" \
"WREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1" \
"BID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1" \
"BRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1" \
"BVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1" \
"BREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1" \
"ARID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1" \
"ARADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1" \
"ARLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1" \
"ARSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1" \
"ARBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1" \
"ARLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1" \
"ARCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1" \
"ARPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1" \
"ARQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1" \
"ARREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1" \
"ARVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1" \
"ARREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1" \
"RID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1" \
"RDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1" \
"RRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1" \
"RLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1" \
"RVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1" \
"RREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1" \
"AWUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1" \
"WUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1" \
"BUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1" \
"ARUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1" \
"RUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_4" \
"AWVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_4" \
"AWREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_4" \
"WDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_4" \
"WVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_4" \
"WREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_4" \
"BRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_4" \
"BVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_4" \
"BREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_4" \
"ARADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_4" \
"ARVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_4" \
"ARREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_4" \
"RDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_4" \
"RRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_4" \
"RVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_4" \
"RREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_4" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_0" \
"AWVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_0" \
"AWREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_0" \
"WDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_0" \
"WVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_0" \
"WREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_0" \
"BRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_0" \
"BVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_0" \
"BREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_0" \
"ARADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_0" \
"ARVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_0" \
"ARREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_0" \
"RDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_0" \
"RRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_0" \
"RVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_0" \
"RREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_0" } 

# Add DDR_AXI4_ARBITER_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0}



# Add Display_Controller_Block instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Display_Controller_Block} -instance_name {Display_Controller_Block}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_Block:DC_H1p4_DATA_O} -pin_slices {[7:0]}



# Add Memory_Read_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Memory_Read} -instance_name {Memory_Read_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Memory_Read_0:DDR_READ_4K_h_offset_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Memory_Read_0:DDR_READ_4K_v_offset_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Memory_Read_0:DDR_READ_HDMI_RX_h_offset_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Memory_Read_0:DDR_READ_HDMI_RX_v_offset_i} -value {GND}



# Add Memory_Write_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Memory_Write} -instance_name {Memory_Write_0}



# Add Video_Processing_Block_TOP instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Processing_Block_TOP} -instance_name {Video_Processing_Block_TOP}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA} -pin_slices {[7:0]}



# Add scalar net connections
sd_create_scalar_net -sd_name ${sd_name} -net_name {Clocks_and_Resets_0_CAMCLK_RESET_N}
sd_create_scalar_net -sd_name ${sd_name} -net_name {Clocks_and_Resets_0_CAM_PARALLEL_CLK}
sd_create_scalar_net -sd_name ${sd_name} -net_name {HDMI_LANE3_RX_CLK_R}
sd_connect_net_to_pins -sd_name ${sd_name} -net_name {Clocks_and_Resets_0_CAMCLK_RESET_N} -pin_names {"CAM1_CAM2_RESET" "Memory_Write_0:CAM1_CAM2_RESET" }
sd_connect_net_to_pins -sd_name ${sd_name} -net_name {Clocks_and_Resets_0_CAM_PARALLEL_CLK} -pin_names {"CAM1_CAM2_CLK" "Memory_Write_0:CAM1_CAM2_CLK" }
sd_connect_net_to_pins -sd_name ${sd_name} -net_name {HDMI_LANE3_RX_CLK_R} -pin_names {"HDMI_RX_CLK" "Memory_Write_0:HDMI_RX_CLK" }

sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_CLK_I" "Video_Processing_Block_TOP:APB_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_RESET_I" "Video_Processing_Block_TOP:APB_RESET_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BAYER_EDGE_SEL_I" "Video_Processing_Block_TOP:BAYER_EDGE_SEL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_DDR_PLL_REF_50MHz" "Video_Processing_Block_TOP:CLK_DDR_PLL_REF_50MHz" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H2p0_ENABLE_I" "Display_Controller_Block:DC_H2p0_ENABLE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR4_SYS_RESET_N" "Video_Processing_Block_TOP:DDR4_SYS_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:reset_i" "DDR_CLK_RESET_I" "Memory_Read_0:DDR_RESET_I" "Memory_Write_0:DDR_CLK_RESET_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "DDR_CLK_I" "Memory_Read_0:DDR_CLK_I" "Memory_Write_0:DDR_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_disp_clk_i" "Display_Controller_Block:DC_H2p0_SYS_CLK_I" "Memory_Read_0:DDR_READ_4K_disp_clk_i" "Video_Processing_Block_TOP:HDMI_TX_LANE_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_TRIGGER_O" "Memory_Read_0:DDR_READ_read_en_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_VALID_O" "data_enable_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_EXT_SYNC_SIGNAL_I" "Video_Processing_Block_TOP:DC_H1p4_EXT_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_FRAME_END_O" "Memory_Read_0:DDR_READ_frame_end_i" "Video_Processing_Block_TOP:DC_H1p4_FRAME_END_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_H_SYNC_O" "horz_sync_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_RESETN_I" "HDMI_1p4_FAB_RESET_I" "Video_Processing_Block_TOP:HDMI_1p4_FAB_RESET_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_SYS_CLK_I" "HDMI_148p5_CLK" "Memory_Read_0:HDMI_148p5_CLK" "Video_Processing_Block_TOP:HDMI_148p5_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_V_SYNC_O" "Video_Processing_Block_TOP:DC_H1p4_VSYNC_I" "vert_sync_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H2p0_RESETN_I" "HDMI_TX_RESET_N_I" "Video_Processing_Block_TOP:HDMI_TX_RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_HPD_I" "Video_Processing_Block_TOP:HDMI_RX_HPD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_4KFRAME_END_O" "Video_Processing_Block_TOP:DDR_READ_4KFRAME_END_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_4K_bayer_dvalid_o" "Video_Processing_Block_TOP:DDR_READ_4K_bayer_dvalid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_HDMI_RX_bayer_dvalid_o" "Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_SCALE_frame_active" "Video_Processing_Block_TOP:DDR_READ_SCALE_frame_active" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PIP_Source_Select_I" "Video_Processing_Block_TOP:PIP_Source_Select_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PIP_mode_selection_i" "Video_Processing_Block_TOP:PIP_mode_selection_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_CURVE_WE_I" "Video_Processing_Block_TOP:UART_CURVE_WE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_HIST_RDY_O" "Video_Processing_Block_TOP:UART_HIST_RDY_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_enable_sel_i" "Video_Processing_Block_TOP:UART_dpc_enable_sel_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_out_o" "Display_Controller_Block:DC_H1p4_DATA_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1_h_offset_i" "Memory_Read_0:DDR_READ_CAM1_h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1_v_offset_i" "Memory_Read_0:DDR_READ_CAM1_v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_h_offset_i" "Memory_Read_0:DDR_READ_SCALE_h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_v_offset_i" "Memory_Read_0:DDR_READ_SCALE_v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_I[15:8]" "Video_Processing_Block_TOP:DC_H1p4_DATA_GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_I[23:16]" "Video_Processing_Block_TOP:DC_H1p4_DATA_RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_I[7:0]" "Video_Processing_Block_TOP:DC_H1p4_DATA_BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_O[15:8]" "G_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_DATA_O[23:16]" "R_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H1p4_H_RES_O" "Memory_Read_0:DDR_READ_horz_resl_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H2p0_H_RES_O" "Memory_Read_0:DDR_READ_4K_horz_resl_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_4K_CAM1_frame_start_addr_i" "Video_Processing_Block_TOP:DDR_READ_4K_CAM1_frame_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_4K_data_o" "Video_Processing_Block_TOP:DDR_READ_4K_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_HDMI_RX_blue_o" "Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_HDMI_RX_frame_start_addr_i" "Memory_Write_0:HDMI_RX_display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_HDMI_RX_green_o" "Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_HDMI_RX_red_o" "Video_Processing_Block_TOP:DDR_READ_HDMI_RX_DATA[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_SCALE_frame_start_addr_i" "Video_Processing_Block_TOP:DDR_READ_SCALE_frame_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_SCALE_h_shift_i" "Video_Processing_Block_TOP:DELAYED_h_shift_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_SCALE_v_shift_i" "Video_Processing_Block_TOP:DELAYED_v_shift_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Write_0:CAM1_display_frame_addr_o" "Video_Processing_Block_TOP:CAM1_display_frame_addr_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Write_0:CAM2_display_frame_addr_o" "Video_Processing_Block_TOP:CAM2_display_frame_addr_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_Alpha_i" "Video_Processing_Block_TOP:UART_Alpha_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_CURVE_WADDR_I" "Video_Processing_Block_TOP:UART_CURVE_WADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_CURVE_WDATA_I" "Video_Processing_Block_TOP:UART_CURVE_WDATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_HIST_ADDR_I" "Video_Processing_Block_TOP:UART_HIST_ADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_HIST_DATA_O" "Video_Processing_Block_TOP:UART_HIST_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_b_gain_i" "Video_Processing_Block_TOP:UART_b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_brightness_i" "Video_Processing_Block_TOP:UART_brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_contrast_i" "Video_Processing_Block_TOP:UART_contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_bayer_sel_i" "Video_Processing_Block_TOP:UART_dpc_bayer_sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_thr1_data_i" "Video_Processing_Block_TOP:UART_dpc_thr1_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_thr2_data_i" "Video_Processing_Block_TOP:UART_dpc_thr2_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_g_gain_i" "Video_Processing_Block_TOP:UART_g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_h_shift_i" "Video_Processing_Block_TOP:UART_h_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_r_gain_i" "Video_Processing_Block_TOP:UART_r_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_step_i" "Video_Processing_Block_TOP:UART_step_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_v_shift_i" "Video_Processing_Block_TOP:UART_v_shift_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_IF" "Video_Processing_Block_TOP:APB_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:Alpha_Blending_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_4K_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM1_4K_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_DPC_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM1_DPC_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SCALE_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM2_SCALE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_4K_BAYER_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM_4K_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_4K_IMAGE_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM_4K_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_BAYER_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IMAGE_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:CAM_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RX_DEC0_AXI4S_Target_IF" "Memory_Write_0:CSI2_RX_DEC0_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RX_DEC1_AXI4S_Target_IF" "Memory_Write_0:CSI2_RX_DEC1_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" "MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_0" "Memory_Read_0:CAM1_Read_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_1" "Memory_Read_0:Scale_read_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_2" "Memory_Read_0:CAM1_4K_Read_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_3" "Memory_Read_0:HDMI_RX_Read_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Write_channel_0" "Memory_Write_0:CAM1_Write_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Write_channel_1" "Memory_Write_0:CAM2_Write_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Write_channel_2" "Memory_Write_0:HDMI_RX_Write_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H2p0_AXI4Stream_Initiator_IF" "Memory_Read_0:DC_H2p0_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:DC_H2p0_AXI4Stream_Target_IF" "Video_Processing_Block_TOP:DC_H2p0_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_Block:HDMI_TX_AXI4Stream_Initiator_IF" "HDMI_TX_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_RX_AXI4S_Target_IF" "Memory_Write_0:HDMI_RX_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_CAM1_AXI4S_Initiator_IF" "Video_Processing_Block_TOP:DDR_READ_CAM1_AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Memory_Read_0:DDR_READ_SCALE_AXI4S_Initiator_IF" "Video_Processing_Block_TOP:DDR_READ_SCALE_AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SCALE_BAYER_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:SCALE_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SCALE_IMAGE_AXI4Lite_Target_IF" "Video_Processing_Block_TOP:SCALE_IMAGE_AXI4Lite_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Pipelining_Block"
generate_component -component_name ${sd_name}
