# Creating SmartDesign "IMX334_IF_TOP"
set sd_name {IMX334_IF_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IMX_CCC_PLL_LOCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_FOR_CSI2_RX_DEC0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_FOR_CSI2_RX_DEC1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G_INS_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G_INS_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRAINING_DONE_C1C2} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O_0} -port_direction {OUT} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O} -port_direction {OUT} -port_range {[39:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O_0} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O_0} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC0_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O" \
"TDATA:TDATA_O" \
"TSTRB:TSTRB_O" \
"TKEEP:TKEEP_O" \
"TLAST:TLAST_O" \
"TUSER:TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CSI2_RX_DEC1_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O_0" \
"TDATA:TDATA_O_0" \
"TSTRB:TSTRB_O_0" \
"TKEEP:TKEEP_O_0" \
"TLAST:TLAST_O_0" \
"TUSER:TUSER_O_0" } 

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add CAM_IOD_TIP_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {CAM_IOD_TIP_TOP_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_0:HS_IO_CLK_PAUSE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_0:HS_SEL} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_0:CLK_TRAIN_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_0:CLK_TRAIN_ERROR}



# Add CAM_IOD_TIP_TOP_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {CAM_IOD_TIP_TOP_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_1:HS_IO_CLK_PAUSE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_1:HS_SEL} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_1:CLK_TRAIN_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CAM_IOD_TIP_TOP_1:CLK_TRAIN_ERROR}



# Add CSI2_RXDecoder_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C1} -instance_name {CSI2_RXDecoder_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ECC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:CRC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:MIPI_INTERRUPT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:VIRTUAL_CHANNEL_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:DATA_TYPE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:WORD_COUNT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:AXI4Lite_Target_IF}



# Add CSI2_RXDecoder_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C1} -instance_name {CSI2_RXDecoder_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:FRAME_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:LINE_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:LINE_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:ECC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:CRC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:MIPI_INTERRUPT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:VIRTUAL_CHANNEL_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:DATA_TYPE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:WORD_COUNT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:AXI4Lite_Target_IF}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CSI2_RXDecoder_0:CAM_PLL_LOCK_I" "CSI2_RXDecoder_1:CAM_PLL_LOCK_I" "IMX_CCC_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CAM_IOD_TIP_TOP_0:TRAINING_RESETN" "CAM_IOD_TIP_TOP_1:TRAINING_RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "CAM_IOD_TIP_TOP_1:training_done_o" "CSI2_RXDecoder_1:TRAINING_DONE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "CAM_IOD_TIP_TOP_0:training_done_o" "CSI2_RXDecoder_0:TRAINING_DONE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "TRAINING_DONE_C1C2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "CAM_IOD_TIP_TOP_0:ARST_N" "CAM_IOD_TIP_TOP_1:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "CAM_IOD_TIP_TOP_0:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "CAM_IOD_TIP_TOP_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_N" "CAM_IOD_TIP_TOP_1:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_P" "CAM_IOD_TIP_TOP_1:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L0_LP_DATA" "CSI2_RXDecoder_0:L0_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L0_LP_DATA_N" "CSI2_RXDecoder_0:L0_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L1_LP_DATA" "CSI2_RXDecoder_0:L1_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L1_LP_DATA_N" "CSI2_RXDecoder_0:L1_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L2_LP_DATA" "CSI2_RXDecoder_0:L2_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L2_LP_DATA_N" "CSI2_RXDecoder_0:L2_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L3_LP_DATA" "CSI2_RXDecoder_0:L3_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L3_LP_DATA_N" "CSI2_RXDecoder_0:L3_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:RX_CLK_G" "CSI2_RXDecoder_0:ACLK_I" "CSI2_RXDecoder_0:CAM_CLOCK_I" "RX_CLK_G_INS_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L0_LP_DATA" "CSI2_RXDecoder_1:L0_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L0_LP_DATA_N" "CSI2_RXDecoder_1:L0_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L1_LP_DATA" "CSI2_RXDecoder_1:L1_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L1_LP_DATA_N" "CSI2_RXDecoder_1:L1_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L2_LP_DATA" "CSI2_RXDecoder_1:L2_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L2_LP_DATA_N" "CSI2_RXDecoder_1:L2_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L3_LP_DATA" "CSI2_RXDecoder_1:L3_LP_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L3_LP_DATA_N" "CSI2_RXDecoder_1:L3_LP_DATA_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:RX_CLK_G" "CSI2_RXDecoder_1:ACLK_I" "CSI2_RXDecoder_1:CAM_CLOCK_I" "RX_CLK_G_INS_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:ARESETN_I" "CSI2_RXDecoder_0:RESET_N_I" "RESET_FOR_CSI2_RX_DEC0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "CSI2_RXDecoder_1:PARALLEL_CLOCK_I" "PARALLEL_CLOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:ARESETN_I" "CSI2_RXDecoder_1:RESET_N_I" "RESET_FOR_CSI2_RX_DEC1" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "CAM_IOD_TIP_TOP_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "CAM_IOD_TIP_TOP_0:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD" "CAM_IOD_TIP_TOP_1:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD_N" "CAM_IOD_TIP_TOP_1:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L0_RXD_DATA" "CSI2_RXDecoder_0:L0_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L1_RXD_DATA" "CSI2_RXDecoder_0:L1_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L2_RXD_DATA" "CSI2_RXDecoder_0:L2_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_0:L3_RXD_DATA" "CSI2_RXDecoder_0:L3_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L0_RXD_DATA" "CSI2_RXDecoder_1:L0_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L1_RXD_DATA" "CSI2_RXDecoder_1:L1_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L2_RXD_DATA" "CSI2_RXDecoder_1:L2_HS_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IOD_TIP_TOP_1:L3_RXD_DATA" "CSI2_RXDecoder_1:L3_HS_DATA_I" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:AXI4Stream_Initiator_IF" "CSI2_RX_DEC0_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:AXI4Stream_Initiator_IF" "CSI2_RX_DEC1_AXI4Stream_Initiator_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "IMX334_IF_TOP"
generate_component -component_name ${sd_name}
