# Creating SmartDesign "Edge_Detection_Block"
set sd_name {Edge_Detection_Block}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TREADY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TDATA_I} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {Edge_Detection_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:AXI4Stream_Initiator_IF_TVALID_O" \
"TDATA:AXI4Stream_Initiator_IF_TDATA_O" \
"TSTRB:AXI4Stream_Initiator_IF_TSTRB_O" \
"TKEEP:AXI4Stream_Initiator_IF_TKEEP_O" \
"TLAST:AXI4Stream_Initiator_IF_TLAST_O" \
"TUSER:AXI4Stream_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {Edge_Detection_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:AXI4Stream_Target_IF_TVALID_I" \
"TREADY:AXI4Stream_Target_IF_TREADY_O" \
"TDATA:AXI4Stream_Target_IF_TDATA_I" \
"TUSER:AXI4Stream_Target_IF_TUSER_I" } 

# Add Edge_Detection_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Edge_Detection_C0} -instance_name {Edge_Detection_C0_0}



# Add RGBtoYCbCr_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGBtoYCbCr_C0_0}



# Add YCbCrtoRGB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCrtoRGB_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_C0_0:RESETN_I" "RESETN_I" "RGBtoYCbCr_C0_0:RESET_N_I" "YCbCrtoRGB_C0_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_C0_0:SYS_CLK_I" "RGBtoYCbCr_C0_0:CLOCK_I" "SYS_CLK_I" "YCbCrtoRGB_C0_0:CLOCK_I" }


# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_AXI4Stream_Initiator_IF" "YCbCrtoRGB_C0_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_AXI4Stream_Target_IF" "RGBtoYCbCr_C0_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_C0_0:AXI4Stream_Initiator_IF" "YCbCrtoRGB_C0_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Edge_Detection_C0_0:AXI4Stream_Target_IF" "RGBtoYCbCr_C0_0:AXI4Stream_Initiator_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Edge_Detection_Block"
generate_component -component_name ${sd_name}
