# Creating SmartDesign "ISP_BLOCK_CAM1"
set sd_name {ISP_BLOCK_CAM1}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_ARVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_AWVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_BREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_RREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_WVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_ARREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_AWREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_BVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_RVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_WREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_ARADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_AWADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_WDATA_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TDATA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Target_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_BRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_RDATA_O_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Lite_Target_IF_AXI_RRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AXI4Stream_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Y_AVG_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:AXI4Stream_Target_IF_TVALID_I" \
"TREADY:AXI4Stream_Target_IF_TREADY_O" \
"TDATA:AXI4Stream_Target_IF_TDATA_I" \
"TLAST:AXI4Stream_Target_IF_TLAST_I" \
"TUSER:AXI4Stream_Target_IF_TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {Image_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:AXI4Stream_Initiator_IF_TVALID_O" \
"TDATA:AXI4Stream_Initiator_IF_TDATA_O" \
"TSTRB:AXI4Stream_Initiator_IF_TSTRB_O" \
"TKEEP:AXI4Stream_Initiator_IF_TKEEP_O" \
"TLAST:AXI4Stream_Initiator_IF_TLAST_O" \
"TUSER:AXI4Stream_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:AXI4Lite_Target_IF_AXI_AWADDR_I_0" \
"AWVALID:AXI4Lite_Target_IF_AXI_AWVALID_I_0" \
"AWREADY:AXI4Lite_Target_IF_AXI_AWREADY_O_0" \
"WDATA:AXI4Lite_Target_IF_AXI_WDATA_I_0" \
"WVALID:AXI4Lite_Target_IF_AXI_WVALID_I_0" \
"WREADY:AXI4Lite_Target_IF_AXI_WREADY_O_0" \
"BRESP:AXI4Lite_Target_IF_AXI_BRESP_O_0" \
"BVALID:AXI4Lite_Target_IF_AXI_BVALID_O_0" \
"BREADY:AXI4Lite_Target_IF_AXI_BREADY_I_0" \
"ARADDR:AXI4Lite_Target_IF_AXI_ARADDR_I_0" \
"ARVALID:AXI4Lite_Target_IF_AXI_ARVALID_I_0" \
"ARREADY:AXI4Lite_Target_IF_AXI_ARREADY_O_0" \
"RDATA:AXI4Lite_Target_IF_AXI_RDATA_O_0" \
"RRESP:AXI4Lite_Target_IF_AXI_RRESP_O_0" \
"RVALID:AXI4Lite_Target_IF_AXI_RVALID_O_0" \
"RREADY:AXI4Lite_Target_IF_AXI_RREADY_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I" } 

# Add Bayer_Interpolation_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C0} -instance_name {Bayer_Interpolation_C0_0}



# Add Defective_Pixel_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Defective_Pixel_C1} -instance_name {Defective_Pixel_C1_0}



# Add Gamma_Correction_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C2} -instance_name {Gamma_Correction_C2_0}



# Add Image_Enhancement_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_CLK_I" "Bayer_Interpolation_C0_0:AXI4L_CLK_I" "Defective_Pixel_C1_0:AXI_ACLK_I" "Image_Enhancement_C0_0:AXI4L_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_RESETN_I" "Bayer_Interpolation_C0_0:AXI4L_RESETN_I" "Defective_Pixel_C1_0:AXI_ARESETN_I" "Image_Enhancement_C0_0:AXI4L_RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:RESETN_I" "Defective_Pixel_C1_0:RESETN_I" "Gamma_Correction_C2_0:RESETN_I" "Image_Enhancement_C0_0:RESETN_I" "RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:SYS_CLK_I" "Defective_Pixel_C1_0:SYS_CLK_I" "Gamma_Correction_C2_0:SYS_CLK_I" "Image_Enhancement_C0_0:SYS_CLK_I" "SYS_CLK_I" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_Y_AVG_O" "Image_Enhancement_C0_0:Y_AVG_O" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:AXI4L_BAYER" "CAM_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:AXI4Stream_Initiator_Interface" "Gamma_Correction_C2_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C0_0:AXI4Stream_Target_Interface" "Defective_Pixel_C1_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_DPC_AXI4Lite_Target_IF" "Defective_Pixel_C1_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IMAGE_AXI4Lite_Target_IF" "Image_Enhancement_C0_0:AXI4L_IMAGE_ENHANCEMENT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1_AXI4Stream_Target_IF" "Defective_Pixel_C1_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:AXI4Stream_Initiator_IF" "Image_Enhancement_C0_0:AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_AXI4Stream_Initiator_IF" "Image_Enhancement_C0_0:AXI4Stream_Initiator_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "ISP_BLOCK_CAM1"
generate_component -component_name ${sd_name}
