# Creating SmartDesign "Memory_Read"
set sd_name {Memory_Read}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_ARREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_RVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_ARREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_RVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4K_disp_clk_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_frame_end_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_read_en_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_ARREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_RVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Scale_read_channel_from_AXI_ARBT_ARREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Scale_read_channel_from_AXI_ARBT_BUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Scale_read_channel_from_AXI_ARBT_RVALID_I} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_ARVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_ARVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4KFRAME_END_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4K_bayer_dvalid_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_bayer_dvalid_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_frame_active} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_ARVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Scale_read_channel_to_AXI_ARBT_ARVALID_I} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TVALID_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_RDATA_I} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_RDATA_I} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_CAM1_frame_start_addr_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_horz_resl_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_frame_start_addr_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_frame_start_addr_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_h_shift_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_v_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_v_shift_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_horz_resl_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_RDATA_I} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Scale_read_channel_from_AXI_ARBT_RDATA_I} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_I} -port_direction {IN} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_ARADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel_ARSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_ARADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel_ARSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_data_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_blue_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_green_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_red_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_ARADDR_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel_ARSIZE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Scale_read_channel_to_AXI_ARBT_ARADDR_I} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Scale_read_channel_to_AXI_ARBT_ARSIZE_I} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O_1} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TDATA_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O_0} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O_0} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {TUSER_O} -port_direction {OUT} -port_range {[3:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4S_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O" \
"TDATA:TDATA_O" \
"TSTRB:TSTRB_O_0" \
"TKEEP:TKEEP_O_0" \
"TLAST:TLAST_O" \
"TUSER:TUSER_O_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TREADY:TREADY_O" \
"TUSER:TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {Scale_read_channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"ARADDR:Scale_read_channel_to_AXI_ARBT_ARADDR_I" \
"ARSIZE:Scale_read_channel_to_AXI_ARBT_ARSIZE_I" \
"ARVALID:Scale_read_channel_to_AXI_ARBT_ARVALID_I" \
"ARREADY:Scale_read_channel_from_AXI_ARBT_ARREADY_I" \
"RDATA:Scale_read_channel_from_AXI_ARBT_RDATA_I" \
"RVALID:Scale_read_channel_from_AXI_ARBT_RVALID_I" \
"BUSER:Scale_read_channel_from_AXI_ARBT_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {HDMI_RX_Read_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"ARADDR:HDMI_RX_Read_Channel_ARADDR_O" \
"ARSIZE:HDMI_RX_Read_Channel_ARSIZE_O" \
"ARVALID:HDMI_RX_Read_Channel_ARVALID_O" \
"ARREADY:HDMI_RX_Read_Channel_ARREADY_I" \
"RDATA:HDMI_RX_Read_Channel_RDATA_I" \
"RVALID:HDMI_RX_Read_Channel_RVALID_I" \
"BUSER:HDMI_RX_Read_Channel_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_Read_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"ARADDR:CAM1_Read_Channel_ARADDR_O" \
"ARSIZE:CAM1_Read_Channel_ARSIZE_O" \
"ARVALID:CAM1_Read_Channel_ARVALID_O" \
"ARREADY:CAM1_Read_Channel_ARREADY_I" \
"RDATA:CAM1_Read_Channel_RDATA_I" \
"RVALID:CAM1_Read_Channel_RVALID_I" \
"BUSER:CAM1_Read_Channel_BUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4S_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:TVALID_O_1" \
"TDATA:TDATA_O_1" \
"TSTRB:TSTRB_O" \
"TKEEP:TKEEP_O" \
"TLAST:TLAST_O_1" \
"TUSER:TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_4K_Read_Channel} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"ARADDR:CAM1_4K_Read_Channel_ARADDR_O" \
"ARSIZE:CAM1_4K_Read_Channel_ARSIZE_O" \
"ARVALID:CAM1_4K_Read_Channel_ARVALID_O" \
"ARREADY:CAM1_4K_Read_Channel_ARREADY_I" \
"RDATA:CAM1_4K_Read_Channel_RDATA_I" \
"RVALID:CAM1_4K_Read_Channel_RVALID_I" \
"BUSER:CAM1_4K_Read_Channel_BUSER_I" } 

# Add AXI4S_Initiator_IF_1 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Initiator_IF} -instance_name {AXI4S_Initiator_IF_1}
# Exporting Parameters of instance AXI4S_Initiator_IF_1
sd_configure_core_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1} -params {\
"G_AXIBUS_WIDTH:8" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1}
sd_update_instance -sd_name ${sd_name} -instance_name {AXI4S_Initiator_IF_1}



# Add AXI4S_Target_ddr_read_4k_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {AXI4S_Target_ddr_read_4k} -instance_name {AXI4S_Target_ddr_read_4k_0}



# Add DDR_READ_CAM1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C3} -instance_name {DDR_READ_CAM1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_READ_CAM1:line_gap_i} -value {0001000000000000}



# Add DDR_Read_HDMI_4K instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C5} -instance_name {DDR_Read_HDMI_4K}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_4K:line_gap_i} -value {0001000000000000}



# Add DDR_Read_HDMI_RX instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C4} -instance_name {DDR_Read_HDMI_RX}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX:data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX:data_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX:data_o} -pin_slices {[31:24]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX:data_o[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX:data_o} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX:line_gap_i} -value {0010000000000000}



# Add DDR_Read_scale instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_scale} -instance_name {DDR_Read_scale}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_scale:beats_to_read_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_scale:beats_to_read_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_scale:beats_to_read_o} -pin_slices {[7:0]}



# Add scale_read_channel_BUS_IF_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {scale_read_channel_BUS_IF} -instance_name {scale_read_channel_BUS_IF_0}
# Exporting Parameters of instance scale_read_channel_BUS_IF_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {scale_read_channel_BUS_IF_0} -params {\
"g_DDR_AXI_DWIDTH_I:512" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {scale_read_channel_BUS_IF_0}
sd_update_instance -sd_name ${sd_name} -instance_name {scale_read_channel_BUS_IF_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:DATA_VALID_I" "DDR_Read_scale:bayer_dvalid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:EOF_I" "DDR_READ_CAM1:frame_start_i" "DDR_READ_frame_end_i" "DDR_Read_HDMI_RX:frame_start_i" "DDR_Read_scale:frame_end_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:RESETN_I" "DDR_READ_CAM1:reset_i" "DDR_RESET_I" "DDR_Read_HDMI_4K:reset_i" "DDR_Read_HDMI_RX:reset_i" "DDR_Read_scale:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:SYS_CLK_I" "DDR_READ_CAM1:pixel_clk_i" "DDR_Read_HDMI_RX:pixel_clk_i" "DDR_Read_scale:disp_clk" "HDMI_148p5_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_ddr_read_4k_0:DATA_TRIGGER_O" "DDR_Read_HDMI_4K:read_en_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_ddr_read_4k_0:FRAME_END_O" "DDR_READ_4KFRAME_END_O" "DDR_Read_HDMI_4K:frame_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_CLK_I" "DDR_READ_CAM1:ddr_clk_i" "DDR_Read_HDMI_4K:ddr_clk_i" "DDR_Read_HDMI_RX:ddr_clk_i" "DDR_Read_scale:sys_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_bayer_dvalid_o" "DDR_Read_HDMI_4K:data_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_disp_clk_i" "DDR_Read_HDMI_4K:pixel_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1:read_en_i" "DDR_READ_read_en_i" "DDR_Read_HDMI_RX:read_en_i" "DDR_Read_scale:read_en_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_bayer_dvalid_o" "DDR_Read_HDMI_RX:data_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_frame_active" "DDR_Read_scale:frame_active_d_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:ddr_data_valid_i" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_ddr_data_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:read_ackn_i" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_read_ackn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:read_done_i" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_read_done" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:read_req_o" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_read_req" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:DATA_I" "DDR_Read_scale:bayer_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_CAM1_frame_start_addr_i" "DDR_READ_CAM1:frame_start_addr_i" "DDR_Read_HDMI_4K:frame_start_addr_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_data_o" "DDR_Read_HDMI_4K:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_h_offset_i" "DDR_Read_HDMI_4K:h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_horz_resl_i" "DDR_Read_HDMI_4K:horz_resl_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_v_offset_i" "DDR_Read_HDMI_4K:v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1:h_offset_i" "DDR_READ_CAM1_h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1:horz_resl_i" "DDR_READ_horz_resl_i" "DDR_Read_HDMI_RX:horz_resl_i" "DDR_Read_scale:horz_resl_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1:v_offset_i" "DDR_READ_CAM1_v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_blue_o" "DDR_Read_HDMI_RX:data_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_frame_start_addr_i" "DDR_Read_HDMI_RX:frame_start_addr_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_green_o" "DDR_Read_HDMI_RX:data_o[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_h_offset_i" "DDR_Read_HDMI_RX:h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_red_o" "DDR_Read_HDMI_RX:data_o[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_v_offset_i" "DDR_Read_HDMI_RX:v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_frame_start_addr_i" "DDR_Read_scale:frame_start_addr_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_h_offset_i" "DDR_Read_scale:h_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_h_shift_i" "DDR_Read_scale:h_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_v_offset_i" "DDR_Read_scale:v_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_v_shift_i" "DDR_Read_scale:v_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:beats_to_read_o[7:0]" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_beats_to_read" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:read_start_addr_o" "scale_read_channel_BUS_IF_0:DDR_READ_SCALE_read_start_addr" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_scale:wdata_i" "scale_read_channel_BUS_IF_0:DDR_SCALE_READ_wdata" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Initiator_IF_1:AXI4S_Initiator_IF" "DDR_READ_SCALE_AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI4S_Target_ddr_read_4k_0:AXI4Stream_Target_IF" "DC_H2p0_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_4K_Read_Channel" "DDR_Read_HDMI_4K:Read_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_Read_Channel" "DDR_READ_CAM1:Read_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1:AXI4Stream_Initiator_IF" "DDR_READ_CAM1_AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX:Read_channel" "HDMI_RX_Read_Channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Scale_read_channel" "scale_read_channel_BUS_IF_0:Scale_read_channel" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Memory_Read"
generate_component -component_name ${sd_name}
