# Creating SmartDesign "Video_Processing_Block_TOP"
set sd_name {Video_Processing_Block_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_penable_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_psel_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pwrite_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BAYER_EDGE_SEL_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_5} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_DDR_PLL_REF_50MHz} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H1p4_FRAME_END_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H1p4_VSYNC_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_SYS_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4KFRAME_END_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_4K_bayer_dvalid_o} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF_TVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_DATA_VALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_TVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_frame_active} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_HPD_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_LANE_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_RESET_N_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PIP_Source_Select_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PIP_mode_selection_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_4} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_CURVE_WE_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_dpc_enable_sel_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pready_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pslverr_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_5} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H1p4_EXT_SYNC_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TLAST_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF_TREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_TREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_4} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_HIST_RDY_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_paddr_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_pwdata_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_display_frame_addr_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_display_frame_addr_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_5} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_data_o} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF_TDATA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF_TUSER_I} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_HDMI_RX_DATA} -port_direction {IN} -port_range {[23:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_TDATA_I_0} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF_TUSER_I_0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_4} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_Alpha_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WADDR_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_CURVE_WDATA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_ADDR_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_b_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_brightness_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_contrast_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_bayer_sel_i} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_thr1_data_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_dpc_thr2_data_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_g_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_h_shift_i} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_r_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_step_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_v_shift_i} -port_direction {IN} -port_range {[15:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_prdata_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_5} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_5} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_BLUE_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_GREEN_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H1p4_DATA_RED_O} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TDATA_O} -port_direction {OUT} -port_range {[95:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TKEEP_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TSTRB_O} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF_TUSER_O} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_4K_CAM1_frame_start_addr_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_frame_start_addr_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DELAYED_h_shift_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DELAYED_v_shift_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_4} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_4} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_4} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {UART_HIST_DATA_O} -port_direction {OUT} -port_range {[23:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {Alpha_Blending_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:Alpha_Blending_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:Alpha_Blending_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:Alpha_Blending_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:Alpha_Blending_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:Alpha_Blending_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:Alpha_Blending_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:Alpha_Blending_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {APB_IF} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_IF_paddr_i" \
"PSELx:APB_IF_psel_i" \
"PENABLE:APB_IF_penable_i" \
"PWRITE:APB_IF_pwrite_i" \
"PRDATA:APB_IF_prdata_o" \
"PWDATA:APB_IF_pwdata_i" \
"PREADY:APB_IF_pready_o" \
"PSLVERR:APB_IF_pslverr_o" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_4K_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_4K_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_4K_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_4K_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_4K_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_4K_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_4K_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_4K_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_4K_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_4K_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_4K_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_4K_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_4K_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_4K_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_4K_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_4K_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DC_H2p0_AXI4Stream_Initiator_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {master} -port_bif_mapping {\
"TVALID:DC_H2p0_AXI4Stream_Initiator_IF_TVALID_O" \
"TDATA:DC_H2p0_AXI4Stream_Initiator_IF_TDATA_O" \
"TSTRB:DC_H2p0_AXI4Stream_Initiator_IF_TSTRB_O" \
"TKEEP:DC_H2p0_AXI4Stream_Initiator_IF_TKEEP_O" \
"TLAST:DC_H2p0_AXI4Stream_Initiator_IF_TLAST_O" \
"TUSER:DC_H2p0_AXI4Stream_Initiator_IF_TUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_5" \
"AWVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_5" \
"AWREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_5" \
"WDATA:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_5" \
"WVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_5" \
"WREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_5" \
"BRESP:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_5" \
"BVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_5" \
"BREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_5" \
"ARADDR:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_5" \
"ARVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_5" \
"ARREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_5" \
"RDATA:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_5" \
"RRESP:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_5" \
"RVALID:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_5" \
"RREADY:CAM_4K_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_5" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_4K_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_1" \
"AWVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_1" \
"AWREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_1" \
"WDATA:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_1" \
"WVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_1" \
"WREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_1" \
"BRESP:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_1" \
"BVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_1" \
"BREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_1" \
"ARADDR:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_1" \
"ARVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_1" \
"ARREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_1" \
"RDATA:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_1" \
"RRESP:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_1" \
"RVALID:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_1" \
"RREADY:CAM_4K_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_CAM1_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:DDR_READ_CAM1_AXI4Stream_Target_IF_TVALID_I" \
"TREADY:DDR_READ_CAM1_AXI4Stream_Target_IF_TREADY_O" \
"TDATA:DDR_READ_CAM1_AXI4Stream_Target_IF_TDATA_I" \
"TLAST:DDR_READ_CAM1_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I" \
"TUSER:DDR_READ_CAM1_AXI4Stream_Target_IF_TUSER_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM1_DPC_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWID_I" \
"AWADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLEN_I" \
"AWSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWSIZE_I" \
"AWBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWBURST_I" \
"AWLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWLOCK_I" \
"AWCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWCACHE_I" \
"AWPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWPROT_I" \
"AWQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWQOS_I" \
"AWREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREGION_I" \
"AWVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WSTRB:CAM1_DPC_AXI4Lite_Target_IF_AXI_WSTRB_I" \
"WLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_WLAST_I" \
"WVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BID_O" \
"BRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARID_I" \
"ARADDR:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARLEN:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLEN_I" \
"ARSIZE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARSIZE_I" \
"ARBURST:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARBURST_I" \
"ARLOCK:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARLOCK_I" \
"ARCACHE:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARCACHE_I" \
"ARPROT:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARPROT_I" \
"ARQOS:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARQOS_I" \
"ARREGION:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREGION_I" \
"ARVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RID_O" \
"RDATA:CAM1_DPC_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM1_DPC_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RLAST:CAM1_DPC_AXI4Lite_Target_IF_AXI_RLAST_O" \
"RVALID:CAM1_DPC_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM1_DPC_AXI4Lite_Target_IF_AXI_RREADY_I" \
"AWUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_AWUSER_I" \
"WUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_WUSER_I" \
"BUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_BUSER_O" \
"ARUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_ARUSER_I" \
"RUSER:CAM1_DPC_AXI4Lite_Target_IF_AXI_RUSER_O" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I" \
"AWVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I" \
"AWREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O" \
"WDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I" \
"WVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I" \
"WREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O" \
"BRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O" \
"BVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O" \
"BREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I" \
"ARADDR:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I" \
"ARVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I" \
"ARREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O" \
"RDATA:CAM_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O" \
"RRESP:CAM_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O" \
"RVALID:CAM_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O" \
"RREADY:CAM_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {DDR_READ_SCALE_AXI4Stream_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4Stream:r0p0_1} -port_bif_role {slave} -port_bif_mapping {\
"TVALID:DDR_READ_SCALE_AXI4Stream_Target_IF_TVALID_I_0" \
"TREADY:DDR_READ_SCALE_AXI4Stream_Target_IF_TREADY_O_0" \
"TDATA:DDR_READ_SCALE_AXI4Stream_Target_IF_TDATA_I_0" \
"TLAST:DDR_READ_SCALE_AXI4Stream_Target_IF_AXI4Stream_Target_IF_TLAST_I" \
"TUSER:DDR_READ_SCALE_AXI4Stream_Target_IF_TUSER_I_0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {CAM2_SCALE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWID_I_1" \
"AWADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWADDR_I_1" \
"AWLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLEN_I_1" \
"AWSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWSIZE_I_1" \
"AWBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWBURST_I_1" \
"AWLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWLOCK_I_1" \
"AWCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWCACHE_I_1" \
"AWPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWPROT_I_1" \
"AWQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWQOS_I_1" \
"AWREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREGION_I_1" \
"AWVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWVALID_I_1" \
"AWREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWREADY_O_1" \
"WDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WDATA_I_1" \
"WSTRB:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WSTRB_I_1" \
"WLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WLAST_I_1" \
"WVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WVALID_I_1" \
"WREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WREADY_O_1" \
"BID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BID_O_1" \
"BRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BRESP_O_1" \
"BVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BVALID_O_1" \
"BREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BREADY_I_1" \
"ARID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARID_I_1" \
"ARADDR:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARADDR_I_1" \
"ARLEN:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLEN_I_1" \
"ARSIZE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARSIZE_I_1" \
"ARBURST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARBURST_I_1" \
"ARLOCK:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARLOCK_I_1" \
"ARCACHE:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARCACHE_I_1" \
"ARPROT:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARPROT_I_1" \
"ARQOS:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARQOS_I_1" \
"ARREGION:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREGION_I_1" \
"ARVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARVALID_I_1" \
"ARREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARREADY_O_1" \
"RID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RID_O_1" \
"RDATA:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RDATA_O_1" \
"RRESP:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RRESP_O_1" \
"RLAST:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RLAST_O_1" \
"RVALID:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RVALID_O_1" \
"RREADY:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RREADY_I_1" \
"AWUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_AWUSER_I_1" \
"WUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_WUSER_I_1" \
"BUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_BUSER_O_1" \
"ARUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_ARUSER_I_1" \
"RUSER:CAM2_SCALE_AXI4Lite_Target_IF_AXI_RUSER_O_1" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_IMAGE_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWADDR_I_4" \
"AWVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWVALID_I_4" \
"AWREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_AWREADY_O_4" \
"WDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WDATA_I_4" \
"WVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WVALID_I_4" \
"WREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_WREADY_O_4" \
"BRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BRESP_O_4" \
"BVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BVALID_O_4" \
"BREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_BREADY_I_4" \
"ARADDR:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARADDR_I_4" \
"ARVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARVALID_I_4" \
"ARREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_ARREADY_O_4" \
"RDATA:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RDATA_O_4" \
"RRESP:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RRESP_O_4" \
"RVALID:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RVALID_O_4" \
"RREADY:SCALE_IMAGE_AXI4Lite_Target_IF_AXI_RREADY_I_4" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {SCALE_BAYER_AXI4Lite_Target_IF} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWADDR_I_0" \
"AWVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWVALID_I_0" \
"AWREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_AWREADY_O_0" \
"WDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WDATA_I_0" \
"WVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WVALID_I_0" \
"WREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_WREADY_O_0" \
"BRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BRESP_O_0" \
"BVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BVALID_O_0" \
"BREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_BREADY_I_0" \
"ARADDR:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARADDR_I_0" \
"ARVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARVALID_I_0" \
"ARREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_ARREADY_O_0" \
"RDATA:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RDATA_O_0" \
"RRESP:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RRESP_O_0" \
"RVALID:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RVALID_O_0" \
"RREADY:SCALE_BAYER_AXI4Lite_Target_IF_AXI_RREADY_I_0" } 

# Add Alpha_Blending_Histogram_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Alpha_Blending_Histogram} -instance_name {Alpha_Blending_Histogram_0}



# Add apb3_if_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {apb3_if} -instance_name {apb3_if_0}
# Exporting Parameters of instance apb3_if_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -params {\
"g_APB3_IF_DATA_WIDTH:32" \
"g_CONST_WIDTH:12" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_update_instance -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:mode_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALAR_RESET_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:alpha_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:step_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:rconst_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:gconst_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:bconst_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:second_const_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:frame_tcount_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_IN_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:VERT_RES_IN_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:VERT_RES_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALE_FACTOR_HORZ_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALE_FACTOR_VERT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:RED_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:GREEN_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:BLUE_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_DDR_RD_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:DDR_READ_FRAME_START_ADDR_O}



# Add delay_buffer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {delay_buffer} -hdl_file {hdl\buffer.vhd} -instance_name {delay_buffer_0}



# Add Delay_Compensation_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Delay_Compensation} -instance_name {Delay_Compensation_0}



# Add HDMI_RX_FIFO_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_RX_FIFO} -instance_name {HDMI_RX_FIFO_0}



# Add ISP_Block_HDMI_4K_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {ISP_Block_HDMI_4K} -instance_name {ISP_Block_HDMI_4K_0}



# Add pip_mode_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pip_mode} -hdl_file {hdl\PIP_mode.vhd} -instance_name {pip_mode_0}



# Add selector_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {selector} -hdl_file {hdl\selector.vhd} -instance_name {selector_0}



# Add Video_Processing_Block_CAM2_SCALE_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Processing_Block_CAM2_SCALE} -instance_name {Video_Processing_Block_CAM2_SCALE_0}



# Add Video_Processing_Block_HD_CAM1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Processing_Block_HD_CAM1} -instance_name {Video_Processing_Block_HD_CAM1_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_CLK_I" "Alpha_Blending_Histogram_0:AXI_CLK_I" "ISP_Block_HDMI_4K_0:APB_CLK_I" "Video_Processing_Block_CAM2_SCALE_0:APB_CLK_I" "Video_Processing_Block_HD_CAM1_0:APB_CLK_I" "apb3_if_0:pclk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_RESET_I" "Alpha_Blending_Histogram_0:AXI_RESETN_I" "ISP_Block_HDMI_4K_0:APB_RESET_I" "Video_Processing_Block_CAM2_SCALE_0:APB_RESET_I" "Video_Processing_Block_HD_CAM1_0:APB_RESET_I" "apb3_if_0:preset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:ALPHA_DATA_VALID_O" "Delay_Compensation_0:alpha_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:DC_H1p4_EXT_SYNC_O" "DC_H1p4_EXT_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:DC_H1p4_VSYNC_I" "DC_H1p4_VSYNC_I" "HDMI_RX_FIFO_0:FRAME_END_I" "Video_Processing_Block_HD_CAM1_0:DC_H1p4_VSYNC_I" "apb3_if_0:frame_end_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:EN_I" "Delay_Compensation_0:ENABLE_FOR_ALPHA_BLENDING" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:HDMI_148p5_CLK_I" "Delay_Compensation_0:HDMI_148p5_CLK_I" "HDMI_148p5_CLK_I" "HDMI_RX_FIFO_0:HDMI_148p5_CLK_I" "Video_Processing_Block_CAM2_SCALE_0:HDMI_148p5_CLK_I" "Video_Processing_Block_HD_CAM1_0:HDMI_148p5_CLK_I" "delay_buffer_0:sys_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:HDMI_1p4_FAB_RESET_I" "Delay_Compensation_0:HDMI_1p4_FAB_RESET_I" "HDMI_1p4_FAB_RESET_I" "HDMI_RX_FIFO_0:HDMI_1p4_FAB_RESET_I" "Video_Processing_Block_CAM2_SCALE_0:HDMI_1p4_FAB_RESET_I" "Video_Processing_Block_HD_CAM1_0:HDMI_1p4_FAB_RESET_I" "delay_buffer_0:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_CURVE_WE_I" "UART_CURVE_WE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_HIST_RDY_O" "UART_HIST_RDY_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BAYER_EDGE_SEL_I" "Video_Processing_Block_HD_CAM1_0:selection_line_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_DDR_PLL_REF_50MHz" "pip_mode_0:sys_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H1p4_FRAME_END_I" "delay_buffer_0:eof_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR4_SYS_RESET_N" "pip_mode_0:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4KFRAME_END_I" "ISP_Block_HDMI_4K_0:DDR_READ_4KFRAME_END_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_bayer_dvalid_o" "ISP_Block_HDMI_4K_0:DATA_VALID_I_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_DATA_VALID" "HDMI_RX_FIFO_0:DDR_READ_HDMI_RX_DATA_VALID" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_frame_active" "Delay_Compensation_0:DDR_READ_SCALE_frame_active" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Delay_Compensation_0:DATA_VALID_I" "Video_Processing_Block_CAM2_SCALE_0:FOR_DELAY_SD_DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Delay_Compensation_0:DATA_VALID_O" "HDMI_RX_FIFO_0:DATA_VALID_DELAY_SD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Delay_Compensation_0:HDMI_RX_HPD_I" "HDMI_RX_HPD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_LANE_CLK_I" "ISP_Block_HDMI_4K_0:HDMI_TX_LANE_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_RESET_N_I" "ISP_Block_HDMI_4K_0:HDMI_TX_RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PIP_Source_Select_I" "selector_0:source_select_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PIP_mode_selection_i" "pip_mode_0:mode_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_enable_sel_i" "apb3_if_0:dpc_enable_sel_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:DC_H1p4_DATA_BLUE_O" "DC_H1p4_DATA_BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:DC_H1p4_DATA_GREEN_O" "DC_H1p4_DATA_GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:DC_H1p4_DATA_RED_O" "DC_H1p4_DATA_RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_CURVE_WADDR_I" "UART_CURVE_WADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_CURVE_WDATA_I" "UART_CURVE_WDATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_HIST_ADDR_I" "UART_HIST_ADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:UART_HIST_DATA_O" "UART_HIST_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_display_frame_addr_I" "selector_0:frame_start_address1_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_display_frame_addr_I" "selector_0:frame_start_address2_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_CAM1_frame_start_addr_o" "selector_0:frame_start_address1_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_4K_data_o" "ISP_Block_HDMI_4K_0:DATA_I_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_HDMI_RX_DATA" "HDMI_RX_FIFO_0:DDR_READ_HDMI_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_frame_start_addr_o" "selector_0:frame_start_address2_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DELAYED_h_shift_o" "delay_buffer_0:h_shift_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DELAYED_v_shift_o" "delay_buffer_0:v_shift_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Delay_Compensation_0:HDMI_RX_DATA" "HDMI_RX_FIFO_0:HDMI_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_Alpha_i" "apb3_if_0:Alpha_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_b_gain_i" "apb3_if_0:b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_brightness_i" "apb3_if_0:brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_contrast_i" "apb3_if_0:contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_bayer_sel_i" "apb3_if_0:dpc_bayer_sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_thr1_data_i" "apb3_if_0:dpc_thr1_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_dpc_thr2_data_i" "apb3_if_0:dpc_thr2_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_g_gain_i" "apb3_if_0:g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_h_shift_i" "pip_mode_0:h_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_r_gain_i" "apb3_if_0:r_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_step_i" "pip_mode_0:step_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_v_shift_i" "pip_mode_0:v_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_CAM2_SCALE_0:Intensity_Avarage_SCALE" "apb3_if_0:RGB_SUM_B2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_HD_CAM1_0:Intensity_Avarage_CAM1" "apb3_if_0:RGB_SUM_B1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"delay_buffer_0:h_shift_i" "pip_mode_0:h_shift_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"delay_buffer_0:v_shift_i" "pip_mode_0:v_shift_o" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_IF" "apb3_if_0:APB_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_AXI4Lite_Target_IF" "Alpha_Blending_Histogram_0:Alpha_Blending_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:From_Scale_Block_AXI4Stream_Target1_IF" "Video_Processing_Block_CAM2_SCALE_0:AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Alpha_Blending_Histogram_0:From_delay_sd_AXI4Stream_Target0_IF" "Delay_Compensation_0:AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_4K_AXI4Lite_Target_IF" "ISP_Block_HDMI_4K_0:CAM1_4K_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_DPC_AXI4Lite_Target_IF" "Video_Processing_Block_HD_CAM1_0:CAM1_DPC_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SCALE_AXI4Lite_Target_IF" "Video_Processing_Block_CAM2_SCALE_0:CAM2_SCALE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_4K_BAYER_AXI4Lite_Target_IF" "ISP_Block_HDMI_4K_0:CAM_4K_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_4K_IMAGE_AXI4Lite_Target_IF" "ISP_Block_HDMI_4K_0:CAM_4K_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_BAYER_AXI4Lite_Target_IF" "Video_Processing_Block_HD_CAM1_0:CAM_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_IMAGE_AXI4Lite_Target_IF" "Video_Processing_Block_HD_CAM1_0:CAM_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DC_H2p0_AXI4Stream_Initiator_IF" "ISP_Block_HDMI_4K_0:DC_H2p0_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_CAM1_AXI4Stream_Target_IF" "Video_Processing_Block_HD_CAM1_0:DDR_READ_CAM1_AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_READ_SCALE_AXI4Stream_Target_IF" "Video_Processing_Block_CAM2_SCALE_0:DDR_READ_SCALE_AXI4Stream_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Delay_Compensation_0:AXI4S_Target_IF" "Video_Processing_Block_HD_CAM1_0:AXI4S_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SCALE_BAYER_AXI4Lite_Target_IF" "Video_Processing_Block_CAM2_SCALE_0:SCALE_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SCALE_IMAGE_AXI4Lite_Target_IF" "Video_Processing_Block_CAM2_SCALE_0:SCALE_IMAGE_AXI4Lite_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Processing_Block_TOP"
generate_component -component_name ${sd_name}
