# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_IN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_SCL_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPD_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ACT_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BG} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_XMASTER} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_XMASTER} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK_EN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_INCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMIO_PD} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HPD_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD2} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD3} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD4} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD5} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD6} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD7} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {data_enable_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {hdmi_clk} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {horz_sync_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {vert_sync_o} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RX_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[13:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {B_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM_N} -port_direction {OUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {G_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_out_o} -port_direction {OUT} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[63:0]} -port_is_pad {1}

sd_invert_pins -sd_name ${sd_name} -pin_names {HPD_I}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM1_XMASTER} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM2_XMASTER} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CAM_INCK} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMIO_PD} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {HPD_O}
# Add Clocks_and_Resets_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Clocks_and_Resets} -instance_name {Clocks_and_Resets_0}



# Add HDMI instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_2p0} -instance_name {HDMI}
sd_create_pin_group -sd_name ${sd_name} -group_name {PADs_IN} -instance_name {HDMI} -pin_names {"LANE0_RXD_P" "LANE0_RXD_N" "LANE1_RXD_P" "LANE1_RXD_N" "LANE2_RXD_P" "LANE2_RXD_N" "LANE3_RXD_P" "LANE3_RXD_N" }
sd_create_pin_group -sd_name ${sd_name} -group_name {PADs_OUT} -instance_name {HDMI} -pin_names {"LANE0_TXD_P" "LANE0_TXD_N" "LANE1_TXD_P" "LANE1_TXD_N" "LANE2_TXD_P" "LANE2_TXD_N" "LANE3_TXD_P" "LANE3_TXD_N" }



# Add IMX334_IF_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX334_IF_TOP} -instance_name {IMX334_IF_TOP_0}



# Add PF_DDR4_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DDR4_C0} -instance_name {PF_DDR4_C0_0}



# Add PROC_SUBSYSTEM_MiV_AXI_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PROC_SUBSYSTEM_MiV_AXI} -instance_name {PROC_SUBSYSTEM_MiV_AXI_0}



# Add UART_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_interface} -instance_name {UART_interface_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {UART_interface_0:ram_data_i} -pin_slices {[23:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {UART_interface_0:ram_data_i} -pin_slices {[31:24]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {UART_interface_0:ram_data_i[31:24]} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_format0_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_format1_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_format2_o}



# Add Video_Pipelining_Block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Pipelining_Block} -instance_name {Video_Pipelining_Block_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACT_N" "PF_DDR4_C0_0:ACT_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BG" "PF_DDR4_C0_0:BG" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "PROC_SUBSYSTEM_MiV_AXI_0:CAM1_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "IMX334_IF_TOP_0:CAM1_RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "IMX334_IF_TOP_0:CAM1_RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_SCL" "PROC_SUBSYSTEM_MiV_AXI_0:CAM1_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_SDA" "PROC_SUBSYSTEM_MiV_AXI_0:CAM1_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RST" "PROC_SUBSYSTEM_MiV_AXI_0:CAM2_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_N" "IMX334_IF_TOP_0:CAM2_RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_P" "IMX334_IF_TOP_0:CAM2_RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SCL" "PROC_SUBSYSTEM_MiV_AXI_0:CAM2_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SDA" "PROC_SUBSYSTEM_MiV_AXI_0:CAM2_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "Clocks_and_Resets_0:CAM_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK_EN" "PROC_SUBSYSTEM_MiV_AXI_0:CAM_CLK_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "PF_DDR4_C0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "PF_DDR4_C0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "PF_DDR4_C0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "PF_DDR4_C0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_IN" "Clocks_and_Resets_0:CLK_IN_27MHz" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "PF_DDR4_C0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:AUTOCALIB_DONE" "IMX334_IF_TOP_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:CAMCLK_RESET_N" "Video_Pipelining_Block_0:CAM1_CAM2_RESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:CAM_PARALLEL_CLK" "IMX334_IF_TOP_0:PARALLEL_CLOCK_I" "Video_Pipelining_Block_0:CAM1_CAM2_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:CLK_DDR_PLL_REF_50MHz" "PF_DDR4_C0_0:PLL_REF_CLK" "PROC_SUBSYSTEM_MiV_AXI_0:PCLK" "UART_interface_0:sys_clk_i" "Video_Pipelining_Block_0:APB_CLK_I" "Video_Pipelining_Block_0:CLK_DDR_PLL_REF_50MHz" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DDR4_CTRLR_READY" "PF_DDR4_C0_0:CTRLR_READY" "Video_Pipelining_Block_0:ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DDR4_PLL_LOCK" "PF_DDR4_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DDR4_RESET_FOR_W_R_AR" "Video_Pipelining_Block_0:DDR_CLK_RESET_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DDR4_SYS_RESET_N" "PF_DDR4_C0_0:SYS_RESET_N" "PROC_SUBSYSTEM_MiV_AXI_0:RESETN" "UART_interface_0:reset_i" "Video_Pipelining_Block_0:APB_RESET_I" "Video_Pipelining_Block_0:DDR4_SYS_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DDR_SYS_CLK" "PF_DDR4_C0_0:SYS_CLK" "Video_Pipelining_Block_0:DDR_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:DEVICE_INIT_DONE" "HDMI:HDMI_RX_RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:HDMI_148p5_CLK" "Video_Pipelining_Block_0:HDMI_148p5_CLK" "hdmi_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:HDMI_1p4_FAB_RESET" "Video_Pipelining_Block_0:HDMI_1p4_FAB_RESET_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:HDMI_EDID_CLK" "HDMI:EDID_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:HDMI_TX_RESET_O" "HDMI:HDMI_TX_RESET_N_I" "Video_Pipelining_Block_0:HDMI_TX_RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:IMX_CCC_PLL_LOCK" "IMX334_IF_TOP_0:IMX_CCC_PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:LANE0_TX_CLK_R" "HDMI:LANE0_TX_CLK_R" "Video_Pipelining_Block_0:DDR_READ_4K_disp_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:LANEx_CDR_REF_CLK" "HDMI:LANEX_CDR_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:RESET_FOR_CSI2_RX_DEC0" "IMX334_IF_TOP_0:RESET_FOR_CSI2_RX_DEC0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:RESET_FOR_CSI2_RX_DEC1" "IMX334_IF_TOP_0:RESET_FOR_CSI2_RX_DEC1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:RX_CLK_G_INS_0" "IMX334_IF_TOP_0:RX_CLK_G_INS_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:RX_CLK_G_INS_1" "IMX334_IF_TOP_0:RX_CLK_G_INS_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:TRANING_DONE" "IMX334_IF_TOP_0:TRAINING_DONE_C1C2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_RX_HPD_I" "HPD_I" "Video_Pipelining_Block_0:HDMI_RX_HPD_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_RX_HPD_O" "HPD_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_RX_SCL_I" "HDMI_RX_SCL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_RX_SDA" "HDMI_RX_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE0_RXD_N" "LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE0_RXD_P" "LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE0_TXD_N" "LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE0_TXD_P" "LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE0_TX_CLK_STABLE" "Video_Pipelining_Block_0:DC_H2p0_ENABLE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE1_RXD_N" "LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE1_RXD_P" "LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE1_TXD_N" "LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE1_TXD_P" "LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE2_RXD_N" "LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE2_RXD_P" "LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE2_TXD_N" "LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE2_TXD_P" "LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE3_RXD_N" "LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE3_RXD_P" "LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE3_RX_CLK_R" "Video_Pipelining_Block_0:HDMI_RX_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE3_TXD_N" "LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:LANE3_TXD_P" "LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_SCL" "PROC_SUBSYSTEM_MiV_AXI_0:HDMI_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_SDA" "PROC_SUBSYSTEM_MiV_AXI_0:HDMI_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:TRNG_RST_N" "PROC_SUBSYSTEM_MiV_AXI_0:TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "PF_DDR4_C0_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD2" "SHIELD2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD3" "SHIELD3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD4" "SHIELD4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD5" "SHIELD5" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD6" "SHIELD6" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD7" "SHIELD7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_interface_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_interface_0:TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bayer_edge_sel_o" "Video_Pipelining_Block_0:BAYER_EDGE_SEL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:curve_valid_o" "Video_Pipelining_Block_0:UART_CURVE_WE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:dpc_enable_sel" "Video_Pipelining_Block_0:UART_dpc_enable_sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:mem_rdy_i" "Video_Pipelining_Block_0:UART_HIST_RDY_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:pip_mode_sel_o" "Video_Pipelining_Block_0:PIP_mode_selection_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:pip_select_o" "Video_Pipelining_Block_0:PIP_Source_Select_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Pipelining_Block_0:data_enable_o" "data_enable_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Pipelining_Block_0:horz_sync_o" "horz_sync_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Pipelining_Block_0:vert_sync_o" "vert_sync_o" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "PF_DDR4_C0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "PF_DDR4_C0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_out_o" "Video_Pipelining_Block_0:B_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "IMX334_IF_TOP_0:CAM1_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "IMX334_IF_TOP_0:CAM1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD" "IMX334_IF_TOP_0:CAM2_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD_N" "IMX334_IF_TOP_0:CAM2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM_N" "PF_DDR4_C0_0:DM_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "PF_DDR4_C0_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "PF_DDR4_C0_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "PF_DDR4_C0_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT_0" "PROC_SUBSYSTEM_MiV_AXI_0:GPIO_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"G_out_o" "Video_Pipelining_Block_0:G_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"R_out_o" "Video_Pipelining_Block_0:R_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:alpha_o" "Video_Pipelining_Block_0:UART_Alpha_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bgain_o" "Video_Pipelining_Block_0:UART_b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:brightness_o" "Video_Pipelining_Block_0:UART_brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:contrast_o" "Video_Pipelining_Block_0:UART_contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:curve_addr_o" "Video_Pipelining_Block_0:UART_CURVE_WADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:curve_data_o" "Video_Pipelining_Block_0:UART_CURVE_WDATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:dpc_bayer_sel" "Video_Pipelining_Block_0:UART_dpc_bayer_sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:dpc_thr1_data" "Video_Pipelining_Block_0:UART_dpc_thr1_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:dpc_thr2_data" "Video_Pipelining_Block_0:UART_dpc_thr2_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:ggain_o" "Video_Pipelining_Block_0:UART_g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_pan_c1_o" "Video_Pipelining_Block_0:DDR_READ_CAM1_h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_pan_c2_o" "Video_Pipelining_Block_0:DDR_READ_SCALE_h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_shift_o" "Video_Pipelining_Block_0:UART_h_shift_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:ram_addr_o" "Video_Pipelining_Block_0:UART_HIST_ADDR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:ram_data_i[23:0]" "Video_Pipelining_Block_0:UART_HIST_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:rgain_o" "Video_Pipelining_Block_0:UART_r_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:step_o" "Video_Pipelining_Block_0:UART_step_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_pan_c1_o" "Video_Pipelining_Block_0:DDR_READ_CAM1_v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_pan_c2_o" "Video_Pipelining_Block_0:DDR_READ_SCALE_v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_shift_o" "Video_Pipelining_Block_0:UART_v_shift_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:CLKS_TO_XCVR" "HDMI:CLKS_FROM_TXPLL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_RX_AXI4Stream_Initiator_IF" "Video_Pipelining_Block_0:HDMI_RX_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI:HDMI_TX_AXI4Stream_Target_IF" "Video_Pipelining_Block_0:HDMI_TX_AXI4Stream_Initiator_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:CSI2_RX_DEC0_AXI4Stream_Initiator_IF" "Video_Pipelining_Block_0:CSI2_RX_DEC0_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:CSI2_RX_DEC1_AXI4Stream_Initiator_IF" "Video_Pipelining_Block_0:CSI2_RX_DEC1_AXI4S_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:AXI4slave0" "Video_Pipelining_Block_0:MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:APBmslave9" "Video_Pipelining_Block_0:APB_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave0" "Video_Pipelining_Block_0:CAM_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave1" "Video_Pipelining_Block_0:SCALE_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave2" "Video_Pipelining_Block_0:CAM_4K_BAYER_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave3" "Video_Pipelining_Block_0:Alpha_Blending_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave4" "Video_Pipelining_Block_0:CAM_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave5" "Video_Pipelining_Block_0:SCALE_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave6" "Video_Pipelining_Block_0:CAM_4K_IMAGE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave7" "Video_Pipelining_Block_0:CAM1_DPC_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave8" "Video_Pipelining_Block_0:CAM2_SCALE_AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_MiV_AXI_0:AXI4mslave9" "Video_Pipelining_Block_0:CAM1_4K_AXI4Lite_Target_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
