src/application/main.o: ../src/application/main.c \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_regs.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_plic.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_assert.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_subsys.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/fpga_design_config/fpga_design_config.h \
 ../src/application/../platform/drivers/fpga_ip/CoreGPIO/core_gpio.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h \
 ../src/application/../platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.h \
 ../src/application/../platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.h \
 ../src/application/../platform/drivers/fpga_ip/CoreI2c/core_i2c.h \
 ../src/application/../platform/hal/hal.h \
 ../src/application/../application/imx334_corei2c/imx334_corei2c.h \
 c:\work_folder_akhil\q3_2024_2025\arena_finalizing\polarfire\an5270_pip\new_softconsole\mpf_an5270_v2025p1_df\src\platform\drivers\fpga_ip\corei2c\core_i2c.h \
 C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/drivers/fpga_ip/CoreGPIO/core_gpio.h \
 c:\work_folder_akhil\q3_2024_2025\arena_finalizing\polarfire\an5270_pip\new_softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design\fpga_design_config\fpga_design_config.h \
 ../src/application/../application/hdmi_config/hdmi_tx.h

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_hal.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_regs.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_plic.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_assert.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/miv_rv32_hal/miv_rv32_subsys.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design/fpga_design_config/fpga_design_config.h:

../src/application/../platform/drivers/fpga_ip/CoreGPIO/core_gpio.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/cpu_types.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hw_reg_access.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/hal/hal_assert.h:

../src/application/../platform/drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.h:

../src/application/../platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.h:

../src/application/../platform/drivers/fpga_ip/CoreI2c/core_i2c.h:

../src/application/../platform/hal/hal.h:

../src/application/../application/imx334_corei2c/imx334_corei2c.h:

c:\work_folder_akhil\q3_2024_2025\arena_finalizing\polarfire\an5270_pip\new_softconsole\mpf_an5270_v2025p1_df\src\platform\drivers\fpga_ip\corei2c\core_i2c.h:

C:\Work_Folder_Akhil\Q3_2024_2025\Arena_finalizing\PolarFire\AN5270_PIP\New_Softconsole\mpf_an5270_v2025p1_df\src\platform/drivers/fpga_ip/CoreGPIO/core_gpio.h:

c:\work_folder_akhil\q3_2024_2025\arena_finalizing\polarfire\an5270_pip\new_softconsole\mpf_an5270_v2025p1_df\src\boards\polarfire-eval-kit\miv-rv32-design\fpga_design_config\fpga_design_config.h:

../src/application/../application/hdmi_config/hdmi_tx.h:
