# Creating SmartDesign "Clocks_and_Resets"
set sd_name {Clocks_and_Resets}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_IN_27MHz} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_CTRLR_READY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_PLL_LOCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR_SYS_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_R} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G_INS_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_G_INS_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRANING_DONE} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AUTOCALIB_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_PARALLEL_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_TO_XCVR_BIT_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_TO_XCVR_LOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLKS_TO_XCVR_REF_CLK_TO_LANE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_DDR_PLL_REF_50MHz} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_RESET_FOR_W_R_AR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DDR4_SYS_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_148p5_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_1p4_FAB_RESET} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_EDID_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_TX_RESET_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IMX_CCC_PLL_LOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANEx_CDR_REF_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_FOR_CSI2_RX_DEC0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_FOR_CSI2_RX_DEC1} -port_direction {OUT}



# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {CLKS_TO_XCVR} -port_bif_vlnv {Actel:busdef.clock:PF_TXPLL_XCVR_CLK:1.0} -port_bif_role {master} -port_bif_mapping {\
"LOCK:CLKS_TO_XCVR_LOCK" \
"BIT_CLK:CLKS_TO_XCVR_BIT_CLK" \
"REF_CLK_TO_LANE:CLKS_TO_XCVR_REF_CLK_TO_LANE" } 

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND3_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_0}



# Add CLK_50MHz_RESET instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C6} -instance_name {CLK_50MHz_RESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CLK_50MHz_RESET:PLL_POWERDOWN_B}



# Add DDR4_SYS_CLK_RESET instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C4} -instance_name {DDR4_SYS_CLK_RESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR4_SYS_CLK_RESET:PLL_POWERDOWN_B}



# Add HDMI_1P4_RESET instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C5} -instance_name {HDMI_1P4_RESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_1P4_RESET:PLL_POWERDOWN_B}



# Add HDMI_TOP_RESET instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C3} -instance_name {HDMI_TOP_RESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {HDMI_TOP_RESET:PLL_POWERDOWN_B}



# Add IMX334_IF_TOP_RESET_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {IMX334_IF_TOP_RESET_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_1:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_1:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_1:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_1:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_1:PLL_POWERDOWN_B}



# Add IMX334_IF_TOP_RESET_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {IMX334_IF_TOP_RESET_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_2:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_2:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_2:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_2:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_2:PLL_POWERDOWN_B}



# Add IMX334_IF_TOP_RESET_3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C2} -instance_name {IMX334_IF_TOP_RESET_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_3:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_3:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_3:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_3:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_RESET_3:PLL_POWERDOWN_B}



# Add IN_27MHz_148p5MHz instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {IN_27MHz_148p5MHz}



# Add IN_27MHz_OUT_150MHz_50MHz instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {IN_27MHz_OUT_150MHz_50MHz}



# Add IN_CAM_CLK_150MHz_OUT_PAL_CLK instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {IN_CAM_CLK_150MHz_OUT_PAL_CLK}



# Add PF_INIT_MONITOR_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_INIT_MONITOR_C0} -instance_name {PF_INIT_MONITOR_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SPI_DONE}



# Add PF_TX_PLL_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C0} -instance_name {PF_TX_PLL_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_C0_0:PLL_LOCK}



# Add PF_XCVR_REF_CLK_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "AND3_0:A" "IN_27MHz_OUT_150MHz_50MHz:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CLK_50MHz_RESET:INIT_DONE" "DDR4_SYS_CLK_RESET:INIT_DONE" "DEVICE_INIT_DONE" "HDMI_1P4_RESET:INIT_DONE" "HDMI_TOP_RESET:INIT_DONE" "IMX334_IF_TOP_RESET_1:INIT_DONE" "IMX334_IF_TOP_RESET_2:INIT_DONE" "IMX334_IF_TOP_RESET_3:INIT_DONE" "PF_INIT_MONITOR_C0_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CLK_50MHz_RESET:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:B" "DDR4_PLL_LOCK" "DDR4_SYS_CLK_RESET:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:C" "DDR4_CTRLR_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:Y" "HDMI_TOP_RESET:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AUTOCALIB_DONE" "PF_INIT_MONITOR_C0_0:AUTOCALIB_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "IMX334_IF_TOP_RESET_1:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK" "IMX334_IF_TOP_RESET_2:CLK" "IN_CAM_CLK_150MHz_OUT_PAL_CLK:REF_CLK_0" "RX_CLK_G_INS_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_PARALLEL_CLK" "IMX334_IF_TOP_RESET_1:CLK" "IN_CAM_CLK_150MHz_OUT_PAL_CLK:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz_RESET:CLK" "CLK_DDR_PLL_REF_50MHz" "IN_27MHz_OUT_150MHz_50MHz:OUT1_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz_RESET:FABRIC_RESET_N" "DDR4_SYS_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_50MHz_RESET:FPGA_POR_N" "DDR4_SYS_CLK_RESET:FPGA_POR_N" "HDMI_1P4_RESET:FPGA_POR_N" "HDMI_TOP_RESET:FPGA_POR_N" "IMX334_IF_TOP_RESET_1:FPGA_POR_N" "IMX334_IF_TOP_RESET_2:FPGA_POR_N" "IMX334_IF_TOP_RESET_3:FPGA_POR_N" "PF_INIT_MONITOR_C0_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_IN_27MHz" "IN_27MHz_148p5MHz:REF_CLK_0" "IN_27MHz_OUT_150MHz_50MHz:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR4_RESET_FOR_W_R_AR" "DDR4_SYS_CLK_RESET:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR4_SYS_CLK_RESET:CLK" "DDR_SYS_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_148p5_CLK" "HDMI_1P4_RESET:CLK" "IN_27MHz_148p5MHz:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_1P4_RESET:FABRIC_RESET_N" "HDMI_1p4_FAB_RESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_1P4_RESET:PLL_LOCK" "IN_27MHz_148p5MHz:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_EDID_CLK" "IN_27MHz_OUT_150MHz_50MHz:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TOP_RESET:CLK" "LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TOP_RESET:FABRIC_RESET_N" "HDMI_TX_RESET_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_RESET_1:EXT_RST_N" "IMX334_IF_TOP_RESET_2:EXT_RST_N" "IMX334_IF_TOP_RESET_3:EXT_RST_N" "TRANING_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_RESET_1:PLL_LOCK" "IMX334_IF_TOP_RESET_2:PLL_LOCK" "IMX334_IF_TOP_RESET_3:PLL_LOCK" "IMX_CCC_PLL_LOCK" "IN_CAM_CLK_150MHz_OUT_PAL_CLK:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_RESET_2:FABRIC_RESET_N" "RESET_FOR_CSI2_RX_DEC0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_RESET_3:CLK" "RX_CLK_G_INS_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_RESET_3:FABRIC_RESET_N" "RESET_FOR_CSI2_RX_DEC1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANEx_CDR_REF_CLK" "PF_TX_PLL_C0_0:REF_CLK" "PF_XCVR_REF_CLK_C0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }


# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKS_TO_XCVR" "PF_TX_PLL_C0_0:CLKS_TO_XCVR" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Clocks_and_Resets"
generate_component -component_name ${sd_name}
