///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: BaseR_TOP_TB.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::PolarFire> <Die::MPF300TS> <Package::FCG1152>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/100ps

module BaseR_TOP_TB;

parameter SYSCLK_PERIOD = 6.4;// 156.25MHZ

//Reg and Wire Declarations for connections
reg SYSCLK;
reg NSYSRESET;
//TX Signals
wire LANE0_TXD_P;
wire LANE0_TXD_N;


   
initial
begin
  SYSCLK = 1'b0;
  NSYSRESET = 1'b0;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
  #(SYSCLK_PERIOD * 10 )
  NSYSRESET = 1'b1;
end


//////////////////////////////////////////////////////////////////////
// Clock Driver
// //Ref clock of 156.25 MHz
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
  #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;



//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  BaseR_TOP
//////////////////////////////////////////////////////////////////////
BaseR_TOP BaseR_TOP_0 (
    // Inputs
    .LANE0_RXD_N(LANE0_TXD_N),
    .LANE0_RXD_P(LANE0_TXD_P),
    .REF_CLK_PAD_N(~SYSCLK),
    .REF_CLK_PAD_P(SYSCLK),
    // Outputs
    .LANE0_TXD_N(LANE0_TXD_N),
    .LANE0_TXD_P(LANE0_TXD_P )
);
///Block to start the packet transmission and stop the transmission   
initial
begin  
   wait(BaseR_TOP_0.PF_XCVR_ERM_C0_0.LANE0_RX_VAL == 1) // Wait on XCVR RX valid
   force BaseR_TOP_0.mac_tx_mux_inst_0.sim_validation = 1'b1;  
   repeat (500) @(posedge SYSCLK);  // Then wait for 100 additional clock cycles:
   force BaseR_TOP_0.pckt_generator_checker_0.pckt_length_reg = 11'd64; //Packet length 256Bytes
   force BaseR_TOP_0.pckt_generator_checker_0.no_of_Packets_reg = 11'd100; //100 packets transmission
   repeat (10) @(posedge SYSCLK);
   force BaseR_TOP_0.pckt_generator_checker_0.start = 1'b1;  //Start transmission
   repeat (2000) @(posedge SYSCLK);
   force BaseR_TOP_TB.BaseR_TOP_0.pckt_generator_checker_0.stop = 1'b1;  //Stop transmission

end

endmodule

