/*------------------------------------------------------------------------------
© [2025] Microchip Technology Inc. and its subsidiaries
Subject to your compliance with the terms and conditions of the license 
agreement accompanying this software, you may use this Microchip software and 
any derivatives exclusively with Microchip products. You are responsible for 
complying with third party license terms applicable to your use of third party 
software (including open source software) that may accompany this Microchip 
software. SOFTWARE IS AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR 
STATUTORY, APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF 
NON-INFRINGEMENT, MERCHANTABILITY, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO 
EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL 
OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED 
TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE 
POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY 
LAW, MICROCHIP’S TOTAL LIABILITY ON ALL CLAIMS RELATED TO THE SOFTWARE WILL 
NOT EXCEED AMOUNT OF FEES, IF ANY, YOU PAID DIRECTLY TO MICROCHIP FOR THIS 
SOFTWARE
------------------------------------------------------------------------------*/

/*******************************************************************************
**    File Name       : mac_tx_mux.v
**    Description     : This MUX module interfaces between loopback FIFO and
						packet generator. During simulation Packet generator   
**						data is transmitted and during validation loopback fifo
**						data is transmitted based on selector signal.
**    Targeted device : Microchip FPGAs
/******************************************************************************/
module mac_tx_mux (
    // Inputs from FiFo_wrapper_Top
    input  wire fifo_tx_en,
    input  wire fifo_tx_sop,
    input  wire fifo_tx_eop,
    input  wire [7:0] fifo_tx_bc,
    input  wire [63:0] fifo_tx_data,
    // Inputs from pckt_generator_checker
    input  wire pkt_tx_val,
    input  wire pkt_tx_sop,
    input  wire pkt_tx_eop,
    input  wire [63:0] pkt_tx_data,
    // Outputs
    output wire mux_tx_en,
    output wire mux_tx_sop,
    output wire mux_tx_eop,
    output wire [7:0] mux_tx_bc,
    output wire [63:0] mux_tx_data
);

wire sim_validation = 1'b0;

    // Mux logic
    assign mux_tx_en   = sim_validation ? pkt_tx_val : fifo_tx_en;
    assign mux_tx_sop  = sim_validation ? pkt_tx_sop : fifo_tx_sop;
    assign mux_tx_eop  = sim_validation ? pkt_tx_eop : fifo_tx_eop;
    assign mux_tx_bc   = sim_validation ? 8'hFF      : fifo_tx_bc; 
    assign mux_tx_data = sim_validation ? pkt_tx_data: fifo_tx_data;

endmodule