# Creating SmartDesign "BASEKR_IP_0"
set sd_name {BASEKR_IP_0}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HRESP} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBtarget_HREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBtarget_HSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBtarget_HWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FABRIC_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_CLK_50M} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_156p25M} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_CTRL_ARSTN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_CTRL_CLK} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HMASTLOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HWRITE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBtarget_HREADYOUT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_156p25M} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SIGNAL_DETECT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_TX} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HRDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBtarget_HADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBtarget_HTRANS} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBtarget_HWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HBURST} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HPROT} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HTRANS} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR_AHB_HWDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBtarget_HRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBtarget_HRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE_LANE0_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE0_DRI_SLAVE_LANE0_DRI_CLK" \
"DRI_ARST_N:LANE0_DRI_SLAVE_LANE0_DRI_ARST_N" \
"DRI_CTRL:LANE0_DRI_SLAVE_LANE0_DRI_CTRL" \
"DRI_RDATA:LANE0_DRI_SLAVE_LANE0_DRI_RDATA" \
"DRI_WDATA:LANE0_DRI_SLAVE_LANE0_DRI_WDATA" \
"DRI_INTERRUPT:LANE0_DRI_SLAVE_LANE0_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AHBL_INITIATOR} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {master} -port_bif_mapping {\
"HADDR:AHBL_INITIATOR_AHB_HADDR" \
"HTRANS:AHBL_INITIATOR_AHB_HTRANS" \
"HWRITE:AHBL_INITIATOR_AHB_HWRITE" \
"HSIZE:AHBL_INITIATOR_AHB_HSIZE" \
"HBURST:AHBL_INITIATOR_AHB_HBURST" \
"HPROT:AHBL_INITIATOR_AHB_HPROT" \
"HWDATA:AHBL_INITIATOR_AHB_HWDATA" \
"HLOCK:AHBL_INITIATOR_AHB_HMASTLOCK" \
"HRDATA:AHBL_INITIATOR_AHB_HRDATA" \
"HREADY:AHBL_INITIATOR_AHB_HREADY" \
"HRESP:AHBL_INITIATOR_AHB_HRESP" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AHBtarget} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"HADDR:AHBtarget_HADDR" \
"HTRANS:AHBtarget_HTRANS" \
"HWRITE:AHBtarget_HWRITE" \
"HWDATA:AHBtarget_HWDATA" \
"HSELx:AHBtarget_HSEL" \
"HRDATA:AHBtarget_HRDATA" \
"HREADY:AHBtarget_HREADY" \
"HREADYOUT:AHBtarget_HREADYOUT" \
"HRESP:AHBtarget_HRESP" } 

# Add AHB2APB3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {AHB2APB3} -instance_name {AHB2APB3}



# Add APB3_SLAVES instance
sd_instantiate_component -sd_name ${sd_name} -component_name {APB3_0} -instance_name {APB3_SLAVES}



# Add BKR_RX_READY_SEL_MUX instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {mux} -hdl_file {hdl\MUX.v} -instance_name {BKR_RX_READY_SEL_MUX}
sd_invert_pins -sd_name ${sd_name} -pin_names {BKR_RX_READY_SEL_MUX:sel}



# Add BKR_RX_VAL_SEL instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {mux} -hdl_file {hdl\MUX.v} -instance_name {BKR_RX_VAL_SEL}
sd_invert_pins -sd_name ${sd_name} -pin_names {BKR_RX_VAL_SEL:sel}



# Add CORE10GBKR_PHY instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE10GBKR_PHY_C0} -instance_name {CORE10GBKR_PHY}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_PCS49_TX_SRESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_BYPASS_SCRAMBLER} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PATTERN_SEED_A} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_TX_TEST_PATTERN_SEED_B} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_PCS49_RX_SRESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_RX_BYPASS_SCRAMBLER} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_RX_TEST_PRBS31_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_RX_TEST_PATTERN_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_RX_TEST_PATTERN_TYPE_SEL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:I_CFG_PCS49_RX_TEST_PATTERN_DATA_SEL} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_BLOCK_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_HI_BER}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_STATUS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_BER_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_BER_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_TEST_MODE_ERR_STRB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_PCS49_RX_TEST_MODE_ERR_CNT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_FCFEC_RX_BLOCK_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_FCFEC_RX_BLOCK_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_FCFEC_RX_CORRECTED_BLOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:O_FCFEC_RX_UNCORRECTED_BLOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:AN_LINK_GOOD_CHECK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:AUTONEG_COMPLETE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:LT_FRM_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:REQ_TX_EQUALIZATION}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:REQ_RX_CAL}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:RX_CAL_DONE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:REMOTE_RCVR_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:TRAINING_FAIL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:ELASTIC_BUFFER_OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GBKR_PHY:ELASTIC_BUFFER_UNDERFLOW}



# Add CORE10GMAC instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE10GMAC_C0_0} -instance_name {CORE10GMAC}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE10GMAC:O_SYS_MAC_RX_ERR_W} -pin_slices {[7:7]}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC:I_SYS_TX_SRESET}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC:I_SYS_RX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_CORE_TX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_CORE_RX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_TX_FAULT}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC:I_SYS_MAC_TX_BC} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_TX_ERR_BUS_PROTOCOL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_TX_ERR_FIFO_OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_TX_ERR_FIFO_UNDERRUN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_TX_STATS_VECTOR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_RX_RDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_RX_BC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_RX_ERR_FIFO_OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_RX_STATS_VECTOR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC:I_CFG_RS_TX_FAULT_EN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC:I_CFG_RS_TX_FAULT_LOCAL} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC:I_CFG_RS_TX_FAULT_REMOTE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE10GMAC:I_CFG_RS_TX_IDLE} -value {GND}
sd_invert_pins -sd_name ${sd_name} -pin_names {CORE10GMAC:I_RS_RX_SRESET}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_RS_RX_FAULT_LOCAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_RS_RX_FAULT_REMOTE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORE10GMAC:O_SYS_MAC_RX_PREAMBLE}



# Add MIV_RV32_BKR_IP instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0_0} -instance_name {MIV_RV32_BKR_IP}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_BKR_IP:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_BKR_IP:TIME_COUNT_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_BKR_IP:JTAG_TDO_DR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_BKR_IP:EXT_IRQ} -value {GND}



# Add PCKT_GEN_FIFO_RDY instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {PCKT_GEN_FIFO_RDY}
sd_invert_pins -sd_name ${sd_name} -pin_names {PCKT_GEN_FIFO_RDY:B}



# Add pckt_generator_checker instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {pckt_generator_checker} -instance_name {pckt_generator_checker}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pckt_generator_checker:INTERRUPT_IN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pckt_generator_checker:PKT_RX_MOD_IN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pckt_generator_checker:ERR_TYPE_IN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pckt_generator_checker:RX_STAT_IN} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pckt_generator_checker:PKT_TX_MOD_OUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pckt_generator_checker:PKT_RX_READY_OUT}



# Add TX_PLL instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C0_0} -instance_name {TX_PLL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {TX_PLL:PLL_LOCK}



# Add UART instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_C0_0} -instance_name {UART}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART:TXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART:RXRDY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART:PARITY_ERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART:OVERFLOW}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART:FRAMING_ERR}



# Add XCVR_ERM instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0_0} -instance_name {XCVR_ERM}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_ERM:LANE0_RX_CLK_G}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_ERM:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_ERM:LANE0_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {XCVR_ERM:LANE0_CALIB_REQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_ERM:LANE0_CALIBRATING}



# Add XCVR_RF_CLK instance
sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_RF_CLK_0} -instance_name {XCVR_RF_CLK}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHB2APB3:HCLK" "CORE10GBKR_PHY:PCLK" "CORE10GMAC:PCLK" "FAB_CLK_50M" "MIV_RV32_BKR_IP:CLK" "UART:PCLK" "pckt_generator_checker:PCLK_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHB2APB3:HRESETN" "CORE10GBKR_PHY:PRESETN" "CORE10GMAC:PRESETN" "FABRIC_RESET_N" "MIV_RV32_BKR_IP:RESETN" "UART:PRESETN" "pckt_generator_checker:PRESET_N_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_READY_SEL_MUX:din_0" "XCVR_ERM:LANE0_RX_READY_CDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_READY_SEL_MUX:din_1" "XCVR_ERM:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_READY_SEL_MUX:mux_out" "CORE10GBKR_PHY:I_PMA_RX_RAW_RDY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_READY_SEL_MUX:sel" "BKR_RX_VAL_SEL:sel" "CORE10GBKR_PHY:XCVR_LOS" "XCVR_ERM:LANE0_LOS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_VAL_SEL:din_0" "XCVR_ERM:LANE0_RX_VAL_CDR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_VAL_SEL:din_1" "CORE10GBKR_PHY:I_PCS49_RX_SRESET" "CORE10GBKR_PHY:I_RXCLK_RESETN" "CORE10GBKR_PHY:I_XGMII_RXRSTN" "CORE10GMAC:I_RS_RX_SRESET" "CORE10GMAC:I_SYS_RX_SRESET" "XCVR_ERM:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BKR_RX_VAL_SEL:mux_out" "CORE10GBKR_PHY:I_PCS73_VAL" "CORE10GBKR_PHY:I_PMA_RX_RAW_EN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_PCS49_TX_SRESET" "CORE10GBKR_PHY:I_TXCLK_RESETN" "CORE10GBKR_PHY:I_XGMII_TXRSTN" "CORE10GMAC:I_SYS_TX_SRESET" "XCVR_ERM:LANE0_TX_CLK_STABLE" "pckt_generator_checker:SYSRST_N_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_PCS73_RX_CLK" "CORE10GBKR_PHY:I_RX_CLK" "XCVR_ERM:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_PCS73_TX_CLK" "CORE10GBKR_PHY:I_TX_CLK" "XCVR_ERM:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_XGMII_RXCLK" "CORE10GBKR_PHY:I_XGMII_TXCLK" "CORE10GMAC:I_CORE_RX_CLK" "CORE10GMAC:I_CORE_TX_CLK" "CORE10GMAC:I_SYS_CLK" "SYS_CLK_156p25M" "pckt_generator_checker:SYSCLK_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:SIGNAL_DETECT" "SIGNAL_DETECT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:I_SYS_MAC_TX_EN" "pckt_generator_checker:PKT_TX_VAL_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:I_SYS_MAC_TX_EOP" "pckt_generator_checker:PKT_TX_EOP_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:I_SYS_MAC_TX_SOP" "pckt_generator_checker:PKT_TX_SOP_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_EN" "pckt_generator_checker:PKT_RX_VAL_IN" "pckt_generator_checker:RX_STAT_VLD_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_EOP" "pckt_generator_checker:PKT_RX_EOP_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_ERR" "pckt_generator_checker:PKT_RX_ERR_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_SOP" "pckt_generator_checker:PKT_RX_SOP_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_TX_FIFO_AF" "PCKT_GEN_FIFO_RDY:B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_TX_RDY" "PCKT_GEN_FIFO_RDY:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "XCVR_ERM:LANE0_PCS_ARST_N" "XCVR_ERM:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "XCVR_ERM:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "XCVR_ERM:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "XCVR_ERM:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "XCVR_ERM:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_BKR_IP:JTAG_TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_BKR_IP:JTAG_TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_BKR_IP:JTAG_TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_BKR_IP:JTAG_TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_BKR_IP:JTAG_TRSTN" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCKT_GEN_FIFO_RDY:Y" "pckt_generator_checker:PKT_TX_FIFO_READY_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_156p25M" "XCVR_RF_CLK:FAB_REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "XCVR_RF_CLK:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "XCVR_RF_CLK:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX_PLL:REF_CLK" "XCVR_ERM:LANE0_CDR_REF_CLK_0" "XCVR_RF_CLK:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART:RX" "UART_RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART:TX" "UART_TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_CTRL_ARSTN" "XCVR_ERM:CTRL_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_CTRL_CLK" "XCVR_ERM:CTRL_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_PCS73_DATA" "CORE10GBKR_PHY:I_PMA_RX_RAW_DATA" "XCVR_ERM:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_XGMII_RXC" "CORE10GMAC:O_XGMII_TXC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:I_XGMII_RXD" "CORE10GMAC:O_XGMII_TXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:O_PMA_TX_RAW_DATA" "XCVR_ERM:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:O_XGMII_TXC" "CORE10GMAC:I_XGMII_RXC" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GBKR_PHY:O_XGMII_TXD" "CORE10GMAC:I_XGMII_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:I_SYS_MAC_TX_DATA" "pckt_generator_checker:PKT_TX_DATA_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_DATA" "pckt_generator_checker:PKT_RX_DATA_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE10GMAC:O_SYS_MAC_RX_ERR_W" "pckt_generator_checker:PKT_RX_ERR_TYPE" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHB2APB3:AHBtarget" "AHBtarget" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHB2APB3:APBinitiator" "APB3_SLAVES:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHBL_INITIATOR" "MIV_RV32_BKR_IP:AHBL_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_SLAVES:APBmslave1" "CORE10GBKR_PHY:APB_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_SLAVES:APBmslave2" "UART:APB_bif" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_SLAVES:APBmslave4" "CORE10GMAC:APB_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB3_SLAVES:APBmslave6" "pckt_generator_checker:BIF_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_DRI_SLAVE" "XCVR_ERM:LANE0_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX_PLL:CLKS_TO_XCVR" "XCVR_ERM:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "BASEKR_IP_0"
generate_component -component_name ${sd_name}
