# Import source files

file copy -force "./src/softconsole/miv-rv32-core10gbasekr-example.hex" "../Libero_design/$Prjname/miv-rv32-core10gbasekr-example.hex"

# Import source files
import_files -hdl_source {./src/hdl/MUX.v}
import_files -hdl_source {./src/hdl/pckt_generator_checker.v}

build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/PF_OSC_C1_0.tcl
source ./src/components/PF_INIT_MONITOR_C2.tcl
source ./src/components/CTRL_CLK_DIVIDER.tcl
source ./src/components/COREJTAGDEBUG_C1.tcl
source ./src/components/XCVR_RF_CLK_0.tcl
source ./src/components/PF_XCVR_ERM_C0_0.tcl
source ./src/components/PF_TX_PLL_C0_0.tcl
source ./src/components/MIV_RV32_C0_0.tcl
source ./src/components/CoreUARTapb_C0_0.tcl
source ./src/components/CORE10GMAC_C0_0.tcl
source ./src/components/CORE10GBKR_PHY_C0.tcl
source ./src/components/APB3_0.tcl
source ./src/components/AHB2APB3.tcl
source ./src/components/Reset_PF_0.tcl
source ./src/components/PF_DRI_C0_0.tcl
source ./src/components/PF_CCC_C0.tcl
source ./src/components/KR_AHB_Lite_0.tcl
source ./src/components/KR_AHB2APB3_0.tcl
source ./src/components/pckt_generator_checker.tcl

file copy -force "./src/hdl/miv_rv32_subsys_pkg.v" "../Libero_design/$Prjname/component/Microsemi/MiV/MIV_RV32/$MIV_RV32ver/pkg/miv_rv32_subsys_pkg.v"


# Generate SmartDesign Components
build_design_hierarchy 
source ./src/components/BASEKR_IP_0.tcl
source ./src/components/BASEKR_CMN_0.tcl
source ./src/components/BASEKR_TOP.tcl

# Set top level module
set_root -module {BASEKR_TOP::work} 
build_design_hierarchy 

save_project
puts "Design generated successfully\n"
