# Creating SmartDesign "BASEKR_CMN_0"
set sd_name {BASEKR_CMN_0}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmmaster0_HMASTLOCK_M0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmmaster0_HWRITE_M0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmslave1_HREADYOUT_S1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_POR_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_INTERRUPT} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_IN_156p25M} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmmaster0_HREADY_M0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmslave1_HMASTLOCK_S1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmslave1_HREADY_S1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmslave1_HSEL_S1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AHBmslave1_HWRITE_S1} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FABRIC_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FAB_CLK_50M} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_DRI_ARST_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_DRI_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_156p25M} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HADDR_M0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HBURST_M0} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HPROT_M0} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HSIZE_M0} -port_direction {IN} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HTRANS_M0} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HWDATA_M0} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HRDATA_S1} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HRESP_S1} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_RDATA} -port_direction {IN} -port_range {[32:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HRDATA_M0} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmmaster0_HRESP_M0} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HADDR_S1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HBURST_S1} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HPROT_S1} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HSIZE_S1} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HTRANS_S1} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {AHBmslave1_HWDATA_S1} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_CTRL} -port_direction {OUT} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI_DRI_WDATA} -port_direction {OUT} -port_range {[32:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {Q2_LANE0_DRI} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"DRI_CLK:Q2_LANE0_DRI_DRI_CLK" \
"DRI_ARST_N:Q2_LANE0_DRI_DRI_ARST_N" \
"DRI_CTRL:Q2_LANE0_DRI_CTRL" \
"DRI_RDATA:Q2_LANE0_DRI_RDATA" \
"DRI_WDATA:Q2_LANE0_DRI_DRI_WDATA" \
"DRI_INTERRUPT:Q2_LANE0_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AHBmmaster0} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {mirroredMaster} -port_bif_mapping {\
"HADDR:AHBmmaster0_HADDR_M0" \
"HTRANS:AHBmmaster0_HTRANS_M0" \
"HWRITE:AHBmmaster0_HWRITE_M0" \
"HSIZE:AHBmmaster0_HSIZE_M0" \
"HBURST:AHBmmaster0_HBURST_M0" \
"HPROT:AHBmmaster0_HPROT_M0" \
"HWDATA:AHBmmaster0_HWDATA_M0" \
"HLOCK:AHBmmaster0_HMASTLOCK_M0" \
"HRDATA:AHBmmaster0_HRDATA_M0" \
"HREADY:AHBmmaster0_HREADY_M0" \
"HRESP:AHBmmaster0_HRESP_M0" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AHBmslave1} -port_bif_vlnv {AMBA:AMBA2:AHB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"HADDR:AHBmslave1_HADDR_S1" \
"HTRANS:AHBmslave1_HTRANS_S1" \
"HWRITE:AHBmslave1_HWRITE_S1" \
"HSIZE:AHBmslave1_HSIZE_S1" \
"HBURST:AHBmslave1_HBURST_S1" \
"HPROT:AHBmslave1_HPROT_S1" \
"HWDATA:AHBmslave1_HWDATA_S1" \
"HSELx:AHBmslave1_HSEL_S1" \
"HMASTLOCK:AHBmslave1_HMASTLOCK_S1" \
"HRDATA:AHBmslave1_HRDATA_S1" \
"HREADY:AHBmslave1_HREADY_S1" \
"HREADYOUT:AHBmslave1_HREADYOUT_S1" \
"HRESP:AHBmslave1_HRESP_S1" } 

# Add DRI_IF_AHB2APB3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {KR_AHB2APB3_0} -instance_name {DRI_IF_AHB2APB3}



# Add KR_AHB_Lite_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {KR_AHB_Lite_0} -instance_name {KR_AHB_Lite_0_0}



# Add PF_DRI_C0_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DRI_C0_0} -instance_name {PF_DRI_C0_0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_DRI_C0_0_0:PSTRB} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0_0:BUSERROR}



# Add SYS_FAB_CCC instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {SYS_FAB_CCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYS_FAB_CCC:PLL_POWERDOWN_N_0} -value {VCC}



# Add SYSTEM_RESET instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_PF_0} -instance_name {SYSTEM_RESET}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYSTEM_RESET:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYSTEM_RESET:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYSTEM_RESET:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYSTEM_RESET:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SYSTEM_RESET:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SYSTEM_RESET:PLL_POWERDOWN_B}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"DRI_IF_AHB2APB3:HCLK" "FAB_CLK_50M" "KR_AHB_Lite_0_0:HCLK" "PF_DRI_C0_0_0:PCLK" "SYSTEM_RESET:CLK" "SYS_FAB_CCC:OUT1_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DRI_IF_AHB2APB3:HRESETN" "FABRIC_RESET_N" "KR_AHB_Lite_0_0:HRESETN" "PF_DRI_C0_0_0:PRESETN" "SYSTEM_RESET:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FPGA_POR_N" "SYSTEM_RESET:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "SYSTEM_RESET:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_IN_156p25M" "SYS_FAB_CCC:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSTEM_RESET:PLL_LOCK" "SYS_FAB_CCC:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SYS_CLK_156p25M" "SYS_FAB_CCC:OUT0_FABCLK_0" }


# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHBmmaster0" "KR_AHB_Lite_0_0:AHBmmaster0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AHBmslave1" "KR_AHB_Lite_0_0:AHBmslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DRI_IF_AHB2APB3:AHBtarget" "KR_AHB_Lite_0_0:AHBmslave2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DRI_IF_AHB2APB3:APBinitiator" "PF_DRI_C0_0_0:APBS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0_0:Q2_LANE0_DRI" "Q2_LANE0_DRI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "BASEKR_CMN_0"
generate_component -component_name ${sd_name}
