# Creating SmartDesign "IMX334_IF_TOP_C1_C2"
set sd_name {IMX334_IF_TOP_C1_C2}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {C1_FRAME_START_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {C2_FRAME_START_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMCLK_RESET_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PARALLEL_CLOCK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {c1_line_valid_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {c2_line_valid_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM2_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {c1_data_out_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {c2_data_out_o} -port_direction {OUT} -port_range {[31:0]}


sd_create_pin_slices -sd_name ${sd_name} -pin_name {c1_data_out_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c1_data_out_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c1_data_out_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c1_data_out_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c2_data_out_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c2_data_out_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c2_data_out_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {c2_data_out_o} -pin_slices {[7:0]}
# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}



# Add CSI2_RXDecoder_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C1} -instance_name {CSI2_RXDecoder_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[19:12]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[29:22]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_0:DATA_O} -pin_slices {[9:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:FRAME_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:LINE_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:ECC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:CRC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:MIPI_INTERRUPT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:VIRTUAL_CHANNEL_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:DATA_TYPE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:WORD_COUNT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_0:AXI4Lite_Target_IF}



# Add CSI2_RXDecoder_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {mipicsi2rxdecoderPF_C1} -instance_name {CSI2_RXDecoder_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_1:DATA_O} -pin_slices {[19:12]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_1:DATA_O} -pin_slices {[29:22]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_1:DATA_O} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CSI2_RXDecoder_1:DATA_O} -pin_slices {[9:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:FRAME_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:FRAME_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:LINE_START_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:LINE_END_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:ECC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:CRC_ERROR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:MIPI_INTERRUPT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:VIRTUAL_CHANNEL_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:DATA_TYPE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:WORD_COUNT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CSI2_RXDecoder_1:AXI4Lite_Target_IF}



# Add PF_CCC_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0}



# Add PF_IOD_GENERIC_RX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_IO_CLK_PAUSE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:HS_SEL} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_0:CLK_TRAIN_ERROR}



# Add PF_IOD_GENERIC_RX_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CAM_IOD_TIP_TOP} -instance_name {PF_IOD_GENERIC_RX_C0_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_1:HS_IO_CLK_PAUSE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_1:HS_SEL} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_1:CLK_TRAIN_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_IOD_GENERIC_RX_C0_1:CLK_TRAIN_ERROR}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "CORERESET_PF_C1_0:PLL_LOCK" "CSI2_RXDecoder_0:CAM_PLL_LOCK_I" "CSI2_RXDecoder_1:CAM_PLL_LOCK_I" "PF_CCC_C2_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "PF_IOD_GENERIC_RX_C0_0:TRAINING_RESETN" "PF_IOD_GENERIC_RX_C0_1:TRAINING_RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "CSI2_RXDecoder_0:TRAINING_DONE_I" "PF_IOD_GENERIC_RX_C0_0:training_done_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "CSI2_RXDecoder_1:TRAINING_DONE_I" "PF_IOD_GENERIC_RX_C0_1:training_done_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "CORERESET_PF_C1_0:EXT_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "PF_IOD_GENERIC_RX_C0_0:ARST_N" "PF_IOD_GENERIC_RX_C0_1:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"C1_FRAME_START_O" "CSI2_RXDecoder_0:FRAME_START_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"C2_FRAME_START_O" "CSI2_RXDecoder_1:FRAME_START_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_N" "PF_IOD_GENERIC_RX_C0_1:RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RX_CLK_P" "PF_IOD_GENERIC_RX_C0_1:RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMCLK_RESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" "CSI2_RXDecoder_0:ARESETN_I" "CSI2_RXDecoder_0:RESET_N_I" "CSI2_RXDecoder_1:ARESETN_I" "CSI2_RXDecoder_1:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "CSI2_RXDecoder_0:ACLK_I" "CSI2_RXDecoder_0:CAM_CLOCK_I" "PF_CCC_C2_0:REF_CLK_0" "PF_IOD_GENERIC_RX_C0_0:RX_CLK_G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CSI2_RXDecoder_0:PARALLEL_CLOCK_I" "CSI2_RXDecoder_1:PARALLEL_CLOCK_I" "PARALLEL_CLOCK" "PF_CCC_C2_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L0_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L1_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L2_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_0:L3_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:LINE_VALID_O" "c1_line_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:ACLK_I" "CSI2_RXDecoder_1:CAM_CLOCK_I" "PF_IOD_GENERIC_RX_C0_1:RX_CLK_G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L0_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L0_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L0_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_1:L0_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L1_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L1_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L1_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_1:L1_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L2_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L2_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L2_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_1:L2_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L3_LP_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L3_LP_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L3_LP_DATA_N_I" "PF_IOD_GENERIC_RX_C0_1:L3_LP_DATA_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:LINE_VALID_O" "c2_line_valid_o" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "PF_IOD_GENERIC_RX_C0_0:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "PF_IOD_GENERIC_RX_C0_0:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD" "PF_IOD_GENERIC_RX_C0_1:RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_RXD_N" "PF_IOD_GENERIC_RX_C0_1:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[19:12]" "c1_data_out_o[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[29:22]" "c1_data_out_o[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[39:32]" "c1_data_out_o[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:DATA_O[9:2]" "c1_data_out_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L0_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L1_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L2_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_0:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_0:L3_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:DATA_O[19:12]" "c2_data_out_o[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:DATA_O[29:22]" "c2_data_out_o[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:DATA_O[39:32]" "c2_data_out_o[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:DATA_O[9:2]" "c2_data_out_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L0_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L0_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L1_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L1_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L2_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L2_RXD_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CSI2_RXDecoder_1:L3_HS_DATA_I" "PF_IOD_GENERIC_RX_C0_1:L3_RXD_DATA" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "IMX334_IF_TOP_C1_C2"
generate_component -component_name ${sd_name}
