# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {EXT_RST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {sel_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ACT_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BG} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD2} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD3} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD4} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD5} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD6} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD7} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {lsuc_serial_data_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[13:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM_N} -port_direction {OUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT_0} -port_direction {OUT} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[63:0]} -port_is_pad {1}

# Add CLKINT_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {CLKINT} -instance_name {CLKINT_0}



# Add CLOCKS_AND_RESETS_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CLOCKS_AND_RESETS} -instance_name {CLOCKS_AND_RESETS_0}



# Add CXP_HOST_SD_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CXP_HOST_SD} -instance_name {CXP_HOST_SD_0}



# Add PF_DDR4_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DDR4_C0} -instance_name {PF_DDR4_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DDR4_C0_0:PLL_LOCK}



# Add PF_DRI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DRI_C0} -instance_name {PF_DRI_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DRI_C0_0:BUSERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_DRI_C0_0:PSTRB} -value {VCC}



# Add PROC_SS_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PROC_SS} -instance_name {PROC_SS_0}



# Add UART_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_interface} -instance_name {UART_interface_0}



# Add Video_Pipeline_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Pipeline} -instance_name {Video_Pipeline_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACT_N" "PF_DDR4_C0_0:ACT_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BG" "PF_DDR4_C0_0:BG" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "PF_DDR4_C0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "PF_DDR4_C0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "PF_DDR4_C0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "PF_DDR4_C0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:A" "REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:Y" "CLOCKS_AND_RESETS_0:REF_CLK_0" "CXP_HOST_SD_0:clk50m_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:CLK50" "PF_DDR4_C0_0:PLL_REF_CLK" "PF_DRI_C0_0:PCLK" "PROC_SS_0:PCLK" "UART_interface_0:sys_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:DDR_CLK" "PF_DDR4_C0_0:SYS_CLK" "Video_Pipeline_0:ddr_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:DDR_PLL_LOCK" "CLOCKS_AND_RESETS_0:HDMI_PLL_LOCK" "PF_DDR4_C0_0:CTRLR_READY" "Video_Pipeline_0:ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:DDR_RESET_N" "Video_Pipeline_0:ddr_clk_rstn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:EXT_RST_N" "EXT_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:FABRIC_RESET_N" "CXP_HOST_SD_0:grst_n_i" "PF_DDR4_C0_0:SYS_RESET_N" "PF_DRI_C0_0:PRESETN" "PROC_SS_0:RESETN" "UART_interface_0:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:HDMI_CLK" "Video_Pipeline_0:HDMI_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:HDMI_RESET_N" "Video_Pipeline_0:RESET_HDMI_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLOCKS_AND_RESETS_0:XCVR_INIT_DONE" "CXP_HOST_SD_0:XCVR_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "PF_DDR4_C0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:CXP_RX_CLK" "Video_Pipeline_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:FRAME_START_O" "Video_Pipeline_0:frm_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:INT_O" "PROC_SS_0:CXP_HOST_INT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LANE0_RXD_N" "LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LANE0_RXD_P" "LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LANE0_TXD_N" "LANE0_TXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LANE0_TXD_P" "LANE0_TXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LINE_DVAL_O" "Video_Pipeline_0:line_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LSUC_SERIAL_DATA_O" "lsuc_serial_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:OUT1_FABCLK_0" "PROC_SS_0:cxp_axi_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:REF_CLK_PAD_N" "REF_CLK_PAD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:REF_CLK_PAD_P" "REF_CLK_PAD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "Video_Pipeline_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "Video_Pipeline_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_N" "Video_Pipeline_0:LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_P" "Video_Pipeline_0:LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_N" "Video_Pipeline_0:LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_P" "Video_Pipeline_0:LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_N" "Video_Pipeline_0:LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_P" "Video_Pipeline_0:LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "PF_DDR4_C0_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD2" "SHIELD2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD3" "SHIELD3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD4" "SHIELD4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD5" "SHIELD5" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD6" "SHIELD6" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD7" "SHIELD7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:GPIO_IN" "UART_interface_0:sel_4k_i" "Video_Pipeline_0:sel_i" "sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:UART_INT" "UART_interface_0:cxp_send_host_cmd_intr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:display_controller_en" "Video_Pipeline_0:ENABLE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "Video_Pipeline_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "Video_Pipeline_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_interface_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_interface_0:TX" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "PF_DDR4_C0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "PF_DDR4_C0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LINE_DATA_O" "Video_Pipeline_0:line_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:SID_O" "Video_Pipeline_0:sid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM_N" "PF_DDR4_C0_0:DM_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "PF_DDR4_C0_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "PF_DDR4_C0_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "PF_DDR4_C0_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT_0" "PROC_SS_0:LED" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:alpha_o" "Video_Pipeline_0:ALPHA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bconst_o" "Video_Pipeline_0:B_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:cxp_sid0_o" "Video_Pipeline_0:sid0_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:cxp_sid1_o" "Video_Pipeline_0:sid1_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:gconst_o" "Video_Pipeline_0:G_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_pan_c1_o" "Video_Pipeline_0:h_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_pan_c2_o" "Video_Pipeline_0:h_pan_i_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:rconst_o" "Video_Pipeline_0:R_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:second_const_o" "Video_Pipeline_0:COMMON_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_pan_c1_o" "Video_Pipeline_0:v_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_pan_c2_o" "Video_Pipeline_0:v_pan_i_0" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:BIF_1" "PROC_SS_0:AXI4mslave0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:LANE0_DRI_SLAVE" "PF_DRI_C0_0:Q1_LANE0_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_HOST_SD_0:TxPLL_DRI" "PF_DRI_C0_0:Q1_TXPLL_SSC_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:AXI4slave0" "Video_Pipeline_0:MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:APBS" "PROC_SS_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:Q2_LANE0_DRI" "Video_Pipeline_0:LANE0_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:Q2_LANE1_DRI" "Video_Pipeline_0:LANE1_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:Q2_LANE2_DRI" "Video_Pipeline_0:LANE2_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:Q2_LANE3_DRI" "Video_Pipeline_0:LANE3_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DRI_C0_0:Q2_TXPLL_SSC_DRI" "Video_Pipeline_0:TxPLL_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:APBmslave1" "UART_interface_0:BIF_1" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
