# Creating SmartDesign "Video_Pipeline"
set sd_name {Video_Pipeline}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ENABLE_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_HDMI_N_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {arready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {awready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {bvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clk_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clk_rstn_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_ctrl_ready_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {frm_start_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {line_valid_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rlast} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {sel_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {wready} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {arvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {awvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {bready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {wlast} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {wvalid} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {ALPHA_I} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {B_CONST_I} -port_direction {IN} -port_range {[9:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {COMMON_CONST_I} -port_direction {IN} -port_range {[19:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {G_CONST_I} -port_direction {IN} -port_range {[9:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE1_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE1_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE2_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE2_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE3_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE3_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_CONST_I} -port_direction {IN} -port_range {[9:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {bid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {bresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {h_pan_i_0} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {h_pan_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {line_data_i} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {rdata} -port_direction {IN} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {rid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {rresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {sid0_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {sid1_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {sid_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {v_pan_i_0} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {v_pan_i} -port_direction {IN} -port_range {[11:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE1_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE2_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE3_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {araddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {arsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awaddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {awsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {wdata} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {wstrb} -port_direction {OUT} -port_range {[63:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:awid" \
"AWADDR:awaddr" \
"AWLEN:awlen" \
"AWSIZE:awsize" \
"AWBURST:awburst" \
"AWLOCK:awlock" \
"AWCACHE:awcache" \
"AWPROT:awprot" \
"AWVALID:awvalid" \
"AWREADY:awready" \
"WDATA:wdata" \
"WSTRB:wstrb" \
"WLAST:wlast" \
"WVALID:wvalid" \
"WREADY:wready" \
"BID:bid" \
"BRESP:bresp" \
"BVALID:bvalid" \
"BREADY:bready" \
"ARID:arid" \
"ARADDR:araddr" \
"ARLEN:arlen" \
"ARSIZE:arsize" \
"ARBURST:arburst" \
"ARLOCK:arlock" \
"ARCACHE:arcache" \
"ARPROT:arprot" \
"ARVALID:arvalid" \
"ARREADY:arready" \
"RID:rid" \
"RDATA:rdata" \
"RRESP:rresp" \
"RLAST:rlast" \
"RVALID:rvalid" \
"RREADY:rready" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE0_DRI_CLK" \
"DRI_ARST_N:LANE0_DRI_ARST_N" \
"DRI_CTRL:LANE0_DRI_CTRL" \
"DRI_RDATA:LANE0_DRI_RDATA" \
"DRI_WDATA:LANE0_DRI_WDATA" \
"DRI_INTERRUPT:LANE0_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {LANE1_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE1_DRI_CLK" \
"DRI_ARST_N:LANE1_DRI_ARST_N" \
"DRI_CTRL:LANE1_DRI_CTRL" \
"DRI_RDATA:LANE1_DRI_RDATA" \
"DRI_WDATA:LANE1_DRI_WDATA" \
"DRI_INTERRUPT:LANE1_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {LANE2_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE2_DRI_CLK" \
"DRI_ARST_N:LANE2_DRI_ARST_N" \
"DRI_CTRL:LANE2_DRI_CTRL" \
"DRI_RDATA:LANE2_DRI_RDATA" \
"DRI_WDATA:LANE2_DRI_WDATA" \
"DRI_INTERRUPT:LANE2_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {LANE3_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE3_DRI_CLK" \
"DRI_ARST_N:LANE3_DRI_ARST_N" \
"DRI_CTRL:LANE3_DRI_CTRL" \
"DRI_RDATA:LANE3_DRI_RDATA" \
"DRI_WDATA:LANE3_DRI_WDATA" \
"DRI_INTERRUPT:LANE3_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {TxPLL_DRI} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:DRI_CLK" \
"DRI_ARST_N:DRI_ARST_N" \
"DRI_CTRL:DRI_CTRL" \
"DRI_RDATA:DRI_RDATA" \
"DRI_WDATA:DRI_WDATA" \
"DRI_INTERRUPT:DRI_INTERRUPT" } 

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add CXP_FRM_DEMUX_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {CXP_FRM_DEMUX} -hdl_file {hdl\CXP_FRM_DEMUX.v} -instance_name {CXP_FRM_DEMUX_0}



# Add DDR_AXI4_ARBITER_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0}



# Add DDR_Read_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C0} -instance_name {DDR_Read_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_C0_0:line_gap_i} -value {0001000000000000}



# Add DDR_Read_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C0} -instance_name {DDR_Read_C0_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_C0_1:line_gap_i} -value {0001000000000000}



# Add DDR_Write_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C0} -instance_name {DDR_Write_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_0:line_gap_i} -value {0001000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_0:frame_ddr_addr_i} -value {GND}



# Add DDR_Write_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C0} -instance_name {DDR_Write_C0_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_1:line_gap_i} -value {0001000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_1:frame_ddr_addr_i} -value {00000100}



# Add Display_Controller_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Display_Controller_C0} -instance_name {Display_Controller_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[95:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[63:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[95:64]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:V_ACTIVE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:V_RES_O}



# Add FHD_4K_SEL_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {FHD_4K_SEL} -hdl_file {hdl\FHD_4K_SEL.v} -instance_name {FHD_4K_SEL_0}



# Add HDMI_2P0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_2P0} -instance_name {HDMI_2P0_0}



# Add Video_Processing_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Processing} -instance_name {Video_Processing_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CXP_FRM_DEMUX_0:resetn_i" "DDR_Write_C0_0:rstn_i" "DDR_Write_C0_1:rstn_i" "RESET_HDMI_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "ENABLE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "DDR_Read_C0_0:reset_i" "DDR_Read_C0_1:reset_i" "Display_Controller_C0_0:RESETN_I" "HDMI_2P0_0:RESET_N_I" "Video_Processing_0:RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:clk_i" "DDR_Write_C0_0:pixel_clk_i" "DDR_Write_C0_1:pixel_clk_i" "SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:frm_start0_o" "DDR_Write_C0_0:frame_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:frm_start1_o" "DDR_Write_C0_1:frame_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:frm_start_i" "frm_start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_valid0_o" "DDR_Write_C0_0:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_valid1_o" "DDR_Write_C0_1:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_valid_i" "line_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:reset_i" "DDR_Write_C0_0:ddr_clk_rstn_i" "DDR_Write_C0_1:ddr_clk_rstn_i" "ddr_clk_rstn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "DDR_Read_C0_0:ddr_clk_i" "DDR_Read_C0_1:ddr_clk_i" "DDR_Write_C0_0:ddr_clk_i" "DDR_Write_C0_1:ddr_clk_i" "ddr_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:data_valid_o" "Video_Processing_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:frame_end_i" "DDR_Read_C0_1:frame_end_i" "Display_Controller_C0_0:V_SYNC_O" "HDMI_2P0_0:V_SYNC_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:pixel_clk_i" "DDR_Read_C0_1:pixel_clk_i" "Display_Controller_C0_0:SYS_CLK_I" "HDMI_2P0_0:HDMI_CLK" "HDMI_CLK" "Video_Processing_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:read_en_i" "DDR_Read_C0_1:read_en_i" "Display_Controller_C0_0:DATA_TRIGGER_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_1:data_valid_o" "Video_Processing_0:DATA_VALID_I_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_VALID_O" "HDMI_2P0_0:VIDEO_DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:EXT_SYNC_SIGNAL_I" "Video_Processing_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:FRAME_END_O" "Video_Processing_0:EOF_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_SYNC_O" "HDMI_2P0_0:H_SYNC_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FHD_4K_SEL_0:sel_i" "sel_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE0_TXD_N" "LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE0_TXD_P" "LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE1_TXD_N" "LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE1_TXD_P" "LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE2_TXD_N" "LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE2_TXD_P" "LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE3_TXD_N" "LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE3_TXD_P" "LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ALPHA_I" "Video_Processing_0:ALPHA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_CONST_I" "Video_Processing_0:B_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COMMON_CONST_I" "Video_Processing_0:COMMON_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_data0_o" "DDR_Write_C0_0:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_data1_o" "DDR_Write_C0_1:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:line_data_i" "line_data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:sid0_i" "sid0_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:sid1_i" "sid1_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_FRM_DEMUX_0:sid_i" "sid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:data_o" "Video_Processing_0:DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:frame_start_addr_i" "DDR_Write_C0_0:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:h_pan_i" "h_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:horz_resl_i" "DDR_Read_C0_1:horz_resl_i" "Display_Controller_C0_0:H_RES_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:v_pan_i" "v_pan_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_1:data_o" "Video_Processing_0:DATA_I_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_1:frame_start_addr_i" "DDR_Write_C0_1:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_1:h_pan_i" "h_pan_i_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_1:v_pan_i" "v_pan_i_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[31:0]" "Video_Processing_0:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[63:32]" "Video_Processing_0:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[95:64]" "Video_Processing_0:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_O[31:0]" "HDMI_2P0_0:DATA_B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_O[63:32]" "HDMI_2P0_0:DATA_G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_O[95:64]" "HDMI_2P0_0:DATA_R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_B_PORCH_I" "FHD_4K_SEL_0:h_b_porch_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_F_PORCH_I" "FHD_4K_SEL_0:h_f_porch_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_RESOLUTION_I" "FHD_4K_SEL_0:h_resolution_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_SYNC_WIDTH_I" "FHD_4K_SEL_0:h_sync_width_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:V_B_PORCH_I" "FHD_4K_SEL_0:v_b_porch_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:V_F_PORCH_I" "FHD_4K_SEL_0:v_f_porch_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:V_RESOLUTION_I" "FHD_4K_SEL_0:v_resolution_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:V_SYNC_WIDTH_I" "FHD_4K_SEL_0:v_sync_width_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"G_CONST_I" "Video_Processing_0:G_CONST_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"R_CONST_I" "Video_Processing_0:R_CONST_I" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" "MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_0" "DDR_Read_C0_0:Read_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Read_channel_1" "DDR_Read_C0_1:Read_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Write_channel_0" "DDR_Write_C0_0:Write_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:Write_channel_1" "DDR_Write_C0_1:Write_channel" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE0_DRI_SLAVE" "LANE0_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE1_DRI_SLAVE" "LANE1_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE2_DRI_SLAVE" "LANE2_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:LANE3_DRI_SLAVE" "LANE3_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_0:TxPLL_DRI" "TxPLL_DRI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Pipeline"
generate_component -component_name ${sd_name}
