# Creating SmartDesign "CXP_DEVICE_TOP"
set sd_name {CXP_DEVICE_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {clk50m_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {grst_n_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {lsuc_din} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {mipi0_clk} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {mipi0_rstn} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT0_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {gen_intr} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_ARADDR_I} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_AWADDR_I} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {FRAME_START_I} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LINE_DATA_I} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LINE_DVAL_I} -port_direction {IN} -port_range {[1:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE0_DRI_CLK" \
"DRI_ARST_N:LANE0_DRI_ARST_N" \
"DRI_CTRL:LANE0_DRI_CTRL" \
"DRI_RDATA:LANE0_DRI_RDATA" \
"DRI_WDATA:LANE0_DRI_WDATA" \
"DRI_INTERRUPT:LANE0_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {TxPLL_DRI} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:DRI_CLK" \
"DRI_ARST_N:DRI_ARST_N" \
"DRI_CTRL:DRI_CTRL" \
"DRI_RDATA:DRI_RDATA" \
"DRI_WDATA:DRI_WDATA" \
"DRI_INTERRUPT:DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:BIF_1_AWADDR_I" \
"AWVALID:BIF_1_AWVALID_I" \
"AWREADY:BIF_1_AWREADY_O" \
"WDATA:BIF_1_WDATA_I" \
"WVALID:BIF_1_WVALID_I" \
"WREADY:BIF_1_WREADY_O" \
"BRESP:BIF_1_BRESP_O" \
"BVALID:BIF_1_BVALID_O" \
"BREADY:BIF_1_BREADY_I" \
"ARADDR:BIF_1_ARADDR_I" \
"ARVALID:BIF_1_ARVALID_I" \
"ARREADY:BIF_1_ARREADY_O" \
"RDATA:BIF_1_RDATA_O" \
"RRESP:BIF_1_RRESP_O" \
"RVALID:BIF_1_RVALID_O" \
"RREADY:BIF_1_RREADY_I" } 

# Add CoaXpress_TOP_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoaXpress_TOP_C0} -instance_name {CoaXpress_TOP_C0_0}
sd_create_pin_group -sd_name ${sd_name} -group_name {Group} -instance_name {CoaXpress_TOP_C0_0} -pin_names {"HSDC0_REQ_TX_R_TRIGGER_I" "LSUC0_RX_R_TRIGGER_IND_O" "LSUC0_RX_F_TRIGGER_IND_O" "LSUC0_RX_R_TRIGGER_DELAY_O" "LSUC0_RX_F_TRIGGER_DELAY_O" "HSDC0_TRIGGER_SRC_I" "HSDC0_REQ_TX_F_TRIGGER_I" }
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_REQ_TX_R_TRIGGER_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_REQ_TX_F_TRIGGER_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC0_RX_F_TRIGGER_IND_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC0_RX_R_TRIGGER_IND_O}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_TRIGGER_SRC_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC0_RX_F_TRIGGER_DELAY_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC0_RX_R_TRIGGER_DELAY_O}



# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}



# Add hs8b10b_encoder_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {hs8b10b_encoder} -instance_name {hs8b10b_encoder_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:EPCS_READY} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:EPCS_PWRDN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:EPCS_TXOOB}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:EPCS_TxVAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:INVALID_K}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:FORCE_DISP} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_encoder_0:DISP_SEL} -value {GND}



# Add hsi_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0} -instance_name {hsi_0}



# Add hsi_refclk_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {hsi_refclk} -instance_name {hsi_refclk_0}



# Add hsi_txpll_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {hsi_txpll} -instance_name {hsi_txpll_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hsi_txpll_0:PLL_LOCK}



# Add pll250m_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {pll250m} -instance_name {pll250m_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pll250m_0:PLL_LOCK_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:CLK" "CoaXpress_TOP_C0_0:TX0_CLK_I" "hs8b10b_encoder_0:EPCS_TxCLK" "hsi_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:FABRIC_RESET_N" "CoaXpress_TOP_C0_0:TX0_RSTN_I" "hs8b10b_encoder_0:EPCS_TxRSTn" "hs8b10b_encoder_0:RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:INIT_DONE" "INIT_DONE" "hsi_0:LANE0_PCS_ARST_N" "hsi_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_0:PLL_LOCK" "hsi_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:INT_O" "gen_intr" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LSUC_CLK125_I" "OUT0_FABCLK_0" "pll250m_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LSUC_SERIAL0_DATA_I" "lsuc_din" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:OS_CLK250_I" "pll250m_0:OUT1_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:PIX_CLK_I" "mipi0_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:PIX_RSTN_I" "mipi0_rstn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:RSTN_I" "grst_n_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "hsi_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "hsi_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "hsi_refclk_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "hsi_refclk_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"clk50m_i" "pll250m_0:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"hsi_refclk_0:REF_CLK" "hsi_txpll_0:REF_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:FRAME_START_I" "FRAME_START_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:HSDC0_TX_DATA_O" "hs8b10b_encoder_0:TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:HSDC0_TX_K_O" "hs8b10b_encoder_0:TX_K_CHAR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LINE_DATA_I" "LINE_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LINE_DVAL_I" "LINE_DVAL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"hs8b10b_encoder_0:EPCS_TxDATA" "hsi_0:LANE0_TX_DATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "CoaXpress_TOP_C0_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_DRI_SLAVE" "hsi_0:LANE0_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TxPLL_DRI" "hsi_txpll_0:TxPLL_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"hsi_0:CLKS_FROM_TXPLL_0" "hsi_txpll_0:CLKS_TO_XCVR" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "CXP_DEVICE_TOP"
generate_component -component_name ${sd_name}
