
file copy -force "./src/softconsole/miv-rv32i-cxp-host.hex" "./$Prjname/miv-rv32i-cxp-host.hex"

# Import source files
import_files -hdl_source {./src/hdl/dual_reg_sync.v}
import_files -hdl_source {./src/hdl/cxp_host_reset.v}
import_files -hdl_source {./src/hdl/CXP_FRM_DEMUX.v}
import_files -hdl_source {./src/hdl/addr_decoder.vhd}
import_files -hdl_source {./src/hdl/apb_wrapper.vhd}
import_files -hdl_source {./src/hdl/ram2port.vhd}
import_files -hdl_source {./src/hdl/video_fifo.vhd}
import_files -hdl_source {./src/hdl/receive_data.vhd}
import_files -hdl_source {./src/hdl/send_data.vhd}
import_files -hdl_source {./src/hdl/FHD_4K_SEL.v}

build_design_hierarchy

#Sourcing the Tcl files in which HDL+ core definitions are created for HDL modules
source ./src/components/apb3_if.tcl 
source ./src/components/video_fifo.tcl 
build_design_hierarchy

#Sourcing the Tcl files for creating individual ${src_path}/components under the top level
source ./src/components/CORERESET_PF_C0.tcl 
source ./src/components/PF_CCC_C0.tcl 
source ./src/components/PF_INIT_MONITOR_C0.tcl 
source ./src/components/CLOCKS_AND_RESETS.tcl 

source ./src/components/CoaXpress_TOP_C0.tcl 
source ./src/components/PF_CCC_C1.tcl 
source ./src/components/PF_CLK_DIV_C0.tcl 
source ./src/components/PF_OSC_C0.tcl 
source ./src/components/PF_TX_PLL_C1.tcl 
source ./src/components/PF_XCVR_ERM_C1.tcl 
source ./src/components/PF_XCVR_REF_CLK_C1.tcl 
source ./src/components/hs8b10b_decoder.tcl 
source ./src/components/CXP_HOST_SD.tcl 

source ./src/components/COREAHBTOAPB3_C0.tcl 
source ./src/components/CoreAPB3_C0.tcl 
source ./src/components/COREAXI4INTERCONNECT_C0.tcl 
source ./src/components/CoreGPIO_C0.tcl 
source ./src/components/COREAXITOAHBL_C0.tcl 
source ./src/components/MIV_RV32_C0.tcl 
source ./src/components/PF_SRAM_AHBL_AXI_C0.tcl 

generate_component -component_name {PF_SRAM_AHBL_AXI_C0}

build_design_hierarchy

source ./src/components/COREJTAGDEBUG_C0.tcl 
source ./src/components/PROC_SS.tcl 

build_design_hierarchy

source ./src/components/COREUART_C0.tcl 
source ./src/components/UART_interface.tcl 

source ./src/components/Bayer_Interpolation_C0.tcl 
source ./src/components/Gamma_Correction_C0.tcl 
source ./src/components/Image_Enhancement_C0.tcl 
source ./src/components/Alpha_Blending_C0.tcl 
source ./src/components/Alpha_Blending_4pixel.tcl 
source ./src/components/Video_Processing.tcl 

source ./src/components/DDR_AXI4_ARBITER_PF_C0.tcl 
source ./src/components/DDR_Read_C0.tcl 
source ./src/components/DDR_Write_C0.tcl 
source ./src/components/Display_Controller_C0.tcl 

source ./src/components/HDMI_TX_C0.tcl 
source ./src/components/PF_TX_PLL_C0.tcl 
source ./src/components/PF_XCVR_ERM_C0.tcl 
source ./src/components/PF_XCVR_REF_CLK_C0.tcl 
source ./src/components/HDMI_2P0.tcl 

source ./src/components/Video_Pipeline.tcl 
source ./src/components/PF_DDR4_C0.tcl 
source ./src/components/PF_DRI_C0.tcl 

build_design_hierarchy 

# Create, configure and generate core components
#
# Generate SmartDesign Components

source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
