src/platform/miv_rv32_hal/miv_rv32_hal.o: \
 ../src/platform/miv_rv32_hal/miv_rv32_hal.c \
 ../src/platform/miv_rv32_hal/miv_rv32_hal.h \
 ../src/platform/miv_rv32_hal/miv_rv32_regs.h \
 ../src/platform/miv_rv32_hal/miv_rv32_plic.h \
 ../src/platform/miv_rv32_hal/miv_rv32_assert.h \
 ../src/platform/miv_rv32_hal/miv_rv32_subsys.h \
 ../src/platform/miv_rv32_hal/../../boards/polarfire-video-kit/miv-rv32-design/fpga_design_config/fpga_design_config.h

../src/platform/miv_rv32_hal/miv_rv32_hal.h:

../src/platform/miv_rv32_hal/miv_rv32_regs.h:

../src/platform/miv_rv32_hal/miv_rv32_plic.h:

../src/platform/miv_rv32_hal/miv_rv32_assert.h:

../src/platform/miv_rv32_hal/miv_rv32_subsys.h:

../src/platform/miv_rv32_hal/../../boards/polarfire-video-kit/miv-rv32-design/fpga_design_config/fpga_design_config.h:
