# Creating SmartDesign "CXP_HOST_SD"
set sd_name {CXP_HOST_SD}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_ARVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_AWVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_BREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_RREADY_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_WVALID_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {XCVR_RESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {clk50m_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {grst_n_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_ARREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_AWREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_BVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_RVALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BIF_1_WREADY_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CXP_RX_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FRAME_START_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INT_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_DRI_INTERRUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LINE_DVAL_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LSUC_SERIAL_DATA_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT1_FABCLK_0} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_ARADDR_I} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_AWADDR_I} -port_direction {IN} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_WDATA_I} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_WDATA} -port_direction {IN} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_CTRL} -port_direction {IN} -port_range {[10:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_WDATA} -port_direction {IN} -port_range {[32:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_BRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_RDATA_O} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BIF_1_RRESP_O} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LANE0_DRI_RDATA} -port_direction {OUT} -port_range {[32:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {LINE_DATA_O} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SID_O} -port_direction {OUT} -port_range {[7:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {TxPLL_DRI} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:DRI_CLK" \
"DRI_ARST_N:DRI_ARST_N" \
"DRI_CTRL:DRI_CTRL" \
"DRI_RDATA:DRI_RDATA" \
"DRI_WDATA:DRI_WDATA" \
"DRI_INTERRUPT:DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {LANE0_DRI_SLAVE} -port_bif_vlnv {Actel:busdef.dri:PF_DRI:1.0} -port_bif_role {slave} -port_bif_mapping {\
"DRI_CLK:LANE0_DRI_CLK" \
"DRI_ARST_N:LANE0_DRI_ARST_N" \
"DRI_CTRL:LANE0_DRI_CTRL" \
"DRI_RDATA:LANE0_DRI_RDATA" \
"DRI_WDATA:LANE0_DRI_WDATA" \
"DRI_INTERRUPT:LANE0_DRI_INTERRUPT" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {BIF_1} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWADDR:BIF_1_AWADDR_I" \
"AWVALID:BIF_1_AWVALID_I" \
"AWREADY:BIF_1_AWREADY_O" \
"WDATA:BIF_1_WDATA_I" \
"WVALID:BIF_1_WVALID_I" \
"WREADY:BIF_1_WREADY_O" \
"BRESP:BIF_1_BRESP_O" \
"BVALID:BIF_1_BVALID_O" \
"BREADY:BIF_1_BREADY_I" \
"ARADDR:BIF_1_ARADDR_I" \
"ARVALID:BIF_1_ARVALID_I" \
"ARREADY:BIF_1_ARREADY_O" \
"RDATA:BIF_1_RDATA_O" \
"RRESP:BIF_1_RRESP_O" \
"RVALID:BIF_1_RVALID_O" \
"RREADY:BIF_1_RREADY_I" } 

# Add CoaXpress_TOP_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoaXpress_TOP_C0} -instance_name {CoaXpress_TOP_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC_REQ_TX_R_TRIGGER_I} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:LSUC_REQ_TX_F_TRIGGER_I} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_F_TRIGGER_IND_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_R_TRIGGER_IND_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_HEARTBEAT_IND_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:SDP_CRC_ERR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_TRIGGER_SRC_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_TRIGGER_DELAY_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_HEARTBEAT_ID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:HSDC0_RX_HEARTBEAT_TIMESTAMP_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:SDP_TAG_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:SDP_PKT_CRC_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoaXpress_TOP_C0_0:SDP_EXP_CRC_O}



# Add cxp_host_reset_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {cxp_host_reset} -hdl_file {hdl\cxp_host_reset.v} -instance_name {cxp_host_reset_0}



# Add hs8b10b_decoder_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {hs8b10b_decoder} -instance_name {hs8b10b_decoder_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:EPCS_READY} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:EPCS_PWRDN}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:EPCS_RxVAL} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:EPCS_RxIDLE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:EPCS_RxERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:ALIGNED}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:CODE_ERR_N}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:B_CERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {hs8b10b_decoder_0:RD_ERR}



# Add PF_CCC_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_CCC_C1_0:PLL_LOCK_0}



# Add PF_CLK_DIV_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}



# Add PF_OSC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_C0} -instance_name {PF_OSC_C0_0}



# Add PF_TX_PLL_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C1} -instance_name {PF_TX_PLL_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_C1_0:PLL_LOCK}



# Add PF_XCVR_ERM_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C1} -instance_name {PF_XCVR_ERM_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_TX_CLK_R}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_SLIP} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_TX_CLK_STABLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_TX_DATA} -value {00000000000000000000000000000000000000000000000001010101010101010101010101010101}



# Add PF_XCVR_REF_CLK_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C1} -instance_name {PF_XCVR_REF_CLK_C1_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CXP_RX_CLK" "CoaXpress_TOP_C0_0:RX0_CLK_I" "PF_XCVR_ERM_C1_0:LANE0_RX_CLK_R" "cxp_host_reset_0:host_rx_clk_i" "hs8b10b_decoder_0:EPCS_RxCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:FRAME_START_O" "FRAME_START_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:INT_O" "INT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LINE_DVAL_O" "LINE_DVAL_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LSUC_CLK125_I" "OUT1_FABCLK_0" "PF_CCC_C1_0:OUT1_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LSUC_SERIAL0_DATA_O" "LSUC_SERIAL_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:OS_CLK250_I" "PF_CCC_C1_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:RSTN_I" "cxp_host_reset_0:grst_n_i" "grst_n_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:RX0_RSTN_I" "cxp_host_reset_0:host_rx_rst_n_o" "hs8b10b_decoder_0:EPCS_RxRSTn" "hs8b10b_decoder_0:RESET_N" "hs8b10b_decoder_0:WA_RSTn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C1_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C1_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_ERM_C1_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_ERM_C1_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C1_0:REF_CLK_0" "clk50m_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "PF_OSC_C0_0:RCOSC_160MHZ_CLK_DIV" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "PF_XCVR_ERM_C1_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:REF_CLK" "PF_XCVR_ERM_C1_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_C1_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:CTRL_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PMA_ARST_N" "XCVR_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_READY" "cxp_host_reset_0:host_hsi_rx_rdy_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_VAL" "cxp_host_reset_0:host_hsi_rx_vld_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C1_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C1_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:HSDC0_RX_DATA_I" "hs8b10b_decoder_0:RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:HSDC0_RX_K_I" "hs8b10b_decoder_0:RX_K_CHAR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:LINE_DATA_O" "LINE_DATA_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoaXpress_TOP_C0_0:SID_O" "SID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_DATA" "hs8b10b_decoder_0:EPCS_RxDATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIF_1" "CoaXpress_TOP_C0_0:AXI4Lite_Target_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_DRI_SLAVE" "PF_XCVR_ERM_C1_0:LANE0_DRI_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C1_0:CLKS_FROM_TXPLL_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:TxPLL_DRI" "TxPLL_DRI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "CXP_HOST_SD"
generate_component -component_name ${sd_name}
