///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: testbench_TVS.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::PolarFire> <Die::MPF300T_ES> <Package::FCG1152>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/100ps

module testbench_TVS;

parameter SYSCLK_PERIOD = 20;// 50MHZ

reg SYSCLK;
reg clk_100;
reg NSYSRESET;

reg cpucontrol_WEn; 
reg cpucontrol_OEn;
reg [7:0] cpucontrol_data;

wire cpu_tx,cpu_rx;
wire Core_UART_0_TXRDY,Core_UART_0_RXRDY;
wire [7:0] Core_UART_0_DATA_OUT;

initial
begin
    SYSCLK = 1'b0;
    clk_100 = 1'b0;
    NSYSRESET = 1'b0;
 cpucontrol_WEn = 1'b1; 
 cpucontrol_OEn = 1'b1;
 //set baud value to 0x1 for faster simulation time
 force testbench_TVS.top_0.Core_UART_0.BAUD_VAL = 13'b0000000000001;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end


//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;

always @(clk_100)
    #(10 / 2.0) clk_100 <= !clk_100;

initial
begin
    wait(NSYSRESET);
    #400
    cpu_write(8'h62);
    cpu_read;
//Each channel valid pushes 4 bytes of data to FIFO
//use cpu_read to read each byte
//ch0
    cpu_read;
    cpu_read;
    cpu_read;
    cpu_read;
//ch1
    cpu_read;
    cpu_read;
    cpu_read;
    cpu_read;
//ch2
    cpu_read;
    cpu_read;
    cpu_read;
    cpu_read;
//ch3
    cpu_read;
    cpu_read;
    cpu_read;
    cpu_read;
	
	$stop;
end
//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  test
//////////////////////////////////////////////////////////////////////
top top_0 (
    // Inputs
    .RX(cpu_tx),
    .REF_CLK_0(SYSCLK),
    .EXT_RST_N(NSYSRESET),

    // Outputs
    .TX(cpu_rx )

    // Inouts

);

//--------Core_UART
Core_UART cpu_UART(
        // Inputs
        .BIT8        ( 1'b1 ),
        .CLK         ( clk_100 ),
        .CSN         ( 1'b0 ),
        .ODD_N_EVEN  ( 1'b0 ),
        .OEN         ( cpucontrol_OEn ),
        .PARITY_EN   ( 1'b0 ),
        .RESET_N     ( NSYSRESET ),
        .RX          ( cpu_rx ),
        .WEN         ( cpucontrol_WEn ),
        .BAUD_VAL    ( 13'b0000000000001 ),
        .DATA_IN     ( cpucontrol_data ),
        // Outputs
        .OVERFLOW    (  ),
        .PARITY_ERR  (  ),
        .RXRDY       ( Core_UART_0_RXRDY ),
        .TX          ( cpu_tx ),
        .TXRDY       ( Core_UART_0_TXRDY ),
        .FRAMING_ERR (  ),
        .DATA_OUT    ( Core_UART_0_DATA_OUT ) 
        );

   task cpu_write;
     input [7:0] data; 

     begin
       wait(Core_UART_0_TXRDY);
       cpucontrol_data = data ; 
       cpucontrol_WEn = 1'b0 ; 
       @(posedge clk_100); 
       cpucontrol_WEn = 1'b1 ; 
       @(posedge clk_100); 
     end
   endtask

   task cpu_read;
     begin
       wait(Core_UART_0_RXRDY);
       cpucontrol_OEn = 1'b0 ; 
       @(posedge clk_100); 
       cpucontrol_OEn = 1'b1 ; 
       repeat (4) @(posedge clk_100); 
     end
   endtask



endmodule

