# Import source files
import_files -hdl_source {./src/hdl/TVS_to_UART.v}


build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/clock_gen.tcl
source ./src/components/Core_UART.tcl
source ./src/components/FIFO.tcl
source ./src/components/INIT_MONITOR.tcl
source ./src/components/PF_RESET.tcl
source ./src/components/TVS_IP.tcl



# Generate SmartDesign Components

source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
