# Exporting core FIFO to TCL
# Exporting Create design command for core FIFO
create_and_configure_core -core_vlnv Actel:DirectCore:COREFIFO:$COREFIFOver -component_name {FIFO} -params {\
"AE_STATIC_EN:false"  \
"AEVAL:4"  \
"AF_STATIC_EN:true"  \
"AFVAL:1020"  \
"CTRL_TYPE:2"  \
"ECC:0"  \
"ESTOP:true"  \
"FAMILY:26"  \
"FSTOP:true"  \
"FWFT:false"  \
"NUM_STAGES:2"  \
"OVERFLOW_EN:false"  \
"PIPE:1"  \
"PREFETCH:false"  \
"RDCNT_EN:false"  \
"RDEPTH:1024"  \
"RE_POLARITY:0"  \
"READ_DVALID:true"  \
"RWIDTH:8"  \
"SYNC:1"  \
"testbench:User"  \
"UNDERFLOW_EN:false"  \
"WDEPTH:1024"  \
"WE_POLARITY:0"  \
"WRCNT_EN:false"  \
"WRITE_ACK:false"  \
"WWIDTH:8"   } -inhibit_configurator 1
# Exporting core FIFO to TCL done
