# Creating SmartDesign "MiV_SS"
set sd_name {MiV_SS}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARESETN_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IRQ} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MiV_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIe_AXI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PREADYS3} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSLVERRS3} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {PENABLES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSELS3} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PWRITES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE0_WVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {PRDATAS3} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BID} -port_direction {IN} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RID} -port_direction {IN} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_RUSER} -port_direction {IN} -port_range {[0:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {PADDRS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PWDATAS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARID} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWID} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WSTRB} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE0_WUSER} -port_direction {OUT} -port_range {[0:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {PCIe_AXI} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:SLAVE0_AWID" \
"AWADDR:SLAVE0_AWADDR" \
"AWLEN:SLAVE0_AWLEN" \
"AWSIZE:SLAVE0_AWSIZE" \
"AWBURST:SLAVE0_AWBURST" \
"AWLOCK:SLAVE0_AWLOCK" \
"AWCACHE:SLAVE0_AWCACHE" \
"AWPROT:SLAVE0_AWPROT" \
"AWQOS:SLAVE0_AWQOS" \
"AWREGION:SLAVE0_AWREGION" \
"AWVALID:SLAVE0_AWVALID" \
"AWREADY:SLAVE0_AWREADY" \
"WDATA:SLAVE0_WDATA" \
"WSTRB:SLAVE0_WSTRB" \
"WLAST:SLAVE0_WLAST" \
"WVALID:SLAVE0_WVALID" \
"WREADY:SLAVE0_WREADY" \
"BID:SLAVE0_BID" \
"BRESP:SLAVE0_BRESP" \
"BVALID:SLAVE0_BVALID" \
"BREADY:SLAVE0_BREADY" \
"ARID:SLAVE0_ARID" \
"ARADDR:SLAVE0_ARADDR" \
"ARLEN:SLAVE0_ARLEN" \
"ARSIZE:SLAVE0_ARSIZE" \
"ARBURST:SLAVE0_ARBURST" \
"ARLOCK:SLAVE0_ARLOCK" \
"ARCACHE:SLAVE0_ARCACHE" \
"ARPROT:SLAVE0_ARPROT" \
"ARQOS:SLAVE0_ARQOS" \
"ARREGION:SLAVE0_ARREGION" \
"ARVALID:SLAVE0_ARVALID" \
"ARREADY:SLAVE0_ARREADY" \
"RID:SLAVE0_RID" \
"RDATA:SLAVE0_RDATA" \
"RRESP:SLAVE0_RRESP" \
"RLAST:SLAVE0_RLAST" \
"RVALID:SLAVE0_RVALID" \
"RREADY:SLAVE0_RREADY" \
"AWUSER:SLAVE0_AWUSER" \
"WUSER:SLAVE0_WUSER" \
"BUSER:SLAVE0_BUSER" \
"ARUSER:SLAVE0_ARUSER" \
"RUSER:SLAVE0_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {PCIe_APB} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"PADDR:PADDRS" \
"PSELx:PSELS3" \
"PENABLE:PENABLES" \
"PWRITE:PWRITES" \
"PRDATA:PRDATAS3" \
"PWDATA:PWDATAS" \
"PREADY:PREADYS3" \
"PSLVERR:PSLVERRS3" } 

# Add AXI_Interconnect_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {AXI_Interconnect} -instance_name {AXI_Interconnect_0}



# Add Core_JTAG_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Core_JTAG} -instance_name {Core_JTAG_0}



# Add MIV_ESS_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_C0} -instance_name {MIV_ESS_C0_0}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_RESETN}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:TMR_IRQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:TIME_COUNT_IN} -value {GND}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN" "MIV_ESS_C0_0:PRESETN" "MIV_RV32_C0_0:RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN_0" "AXI_Interconnect_0:ARESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_Interconnect_0:ACLK" "PCIe_AXI_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_Interconnect_0:M_CLK0" "MIV_ESS_C0_0:PCLK" "MIV_RV32_C0_0:CLK" "MiV_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Core_JTAG_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IRQ" "MIV_RV32_C0_0:EXT_IRQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_RX" "RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_TX" "TX" }


# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_Interconnect_0:AXI4mmaster0" "MIV_RV32_C0_0:AXI4_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_Interconnect_0:AXI4mslave0" "PCIe_AXI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_0_mINITIATOR" "MIV_RV32_C0_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_3_mTARGET" "PCIe_APB" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "MiV_SS"
generate_component -component_name ${sd_name}
