# Creating SmartDesign "PCIe_RP"
set sd_name {PCIe_RP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PENABLE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PRESET_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PSEL} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PWRITE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARESETN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_CLK_STABLE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {AXI_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MiV_CLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_BREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_WLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_WVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD0_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD1_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD1_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD2_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD2_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD3_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_RXD3_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_ARREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_AWREADY} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_BVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_RLAST} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_RVALID} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_WREADY} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_S_PSLVERR} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK0_7_CALIB_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_6_VDDI_STATUS} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVICE_INIT_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FABRIC_POR_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_BVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_WREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD0_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD1_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD1_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD2_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD2_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD3_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIESS_LANE_TXD3_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_0_INTERRUPT_OUT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCIE_1_PERST_OUT_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_ARVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_AWVALID} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_BREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_RREADY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_WLAST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLAVE1_WVALID} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PADDR} -port_direction {IN} -port_range {[25:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PWDATA} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARLEN} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_ARSIZE} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWADDR} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWBURST} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWID} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWLEN} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_AWSIZE} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_WDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_WSTRB} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_BID} -port_direction {IN} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_BRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_BUSER} -port_direction {IN} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_RDATA} -port_direction {IN} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_RID} -port_direction {IN} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_RRESP} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_RUSER} -port_direction {IN} -port_range {[0:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APB_S_PRDATA} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_BID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_BRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RID} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIESS_AXI_1_S_RRESP} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PCIE_0_LTSSM} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARID} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_ARUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWADDR} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWBURST} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWCACHE} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWID} -port_direction {OUT} -port_range {[4:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWLEN} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWLOCK} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWPROT} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWQOS} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWREGION} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWSIZE} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_AWUSER} -port_direction {OUT} -port_range {[0:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_WDATA} -port_direction {OUT} -port_range {[63:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_WSTRB} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {SLAVE1_WUSER} -port_direction {OUT} -port_range {[0:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {DDR4_AXI} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:SLAVE1_AWID" \
"AWADDR:SLAVE1_AWADDR" \
"AWLEN:SLAVE1_AWLEN" \
"AWSIZE:SLAVE1_AWSIZE" \
"AWBURST:SLAVE1_AWBURST" \
"AWLOCK:SLAVE1_AWLOCK" \
"AWCACHE:SLAVE1_AWCACHE" \
"AWPROT:SLAVE1_AWPROT" \
"AWQOS:SLAVE1_AWQOS" \
"AWREGION:SLAVE1_AWREGION" \
"AWVALID:SLAVE1_AWVALID" \
"AWREADY:SLAVE1_AWREADY" \
"WDATA:SLAVE1_WDATA" \
"WSTRB:SLAVE1_WSTRB" \
"WLAST:SLAVE1_WLAST" \
"WVALID:SLAVE1_WVALID" \
"WREADY:SLAVE1_WREADY" \
"BID:SLAVE1_BID" \
"BRESP:SLAVE1_BRESP" \
"BVALID:SLAVE1_BVALID" \
"BREADY:SLAVE1_BREADY" \
"ARID:SLAVE1_ARID" \
"ARADDR:SLAVE1_ARADDR" \
"ARLEN:SLAVE1_ARLEN" \
"ARSIZE:SLAVE1_ARSIZE" \
"ARBURST:SLAVE1_ARBURST" \
"ARLOCK:SLAVE1_ARLOCK" \
"ARCACHE:SLAVE1_ARCACHE" \
"ARPROT:SLAVE1_ARPROT" \
"ARQOS:SLAVE1_ARQOS" \
"ARREGION:SLAVE1_ARREGION" \
"ARVALID:SLAVE1_ARVALID" \
"ARREADY:SLAVE1_ARREADY" \
"RID:SLAVE1_RID" \
"RDATA:SLAVE1_RDATA" \
"RRESP:SLAVE1_RRESP" \
"RLAST:SLAVE1_RLAST" \
"RVALID:SLAVE1_RVALID" \
"RREADY:SLAVE1_RREADY" \
"AWUSER:SLAVE1_AWUSER" \
"WUSER:SLAVE1_WUSER" \
"BUSER:SLAVE1_BUSER" \
"ARUSER:SLAVE1_ARUSER" \
"RUSER:SLAVE1_RUSER" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {AXI_1_SLAVE} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {slave} -port_bif_mapping {\
"AWID:PCIESS_AXI_1_S_AWID" \
"AWADDR:PCIESS_AXI_1_S_AWADDR" \
"AWLEN:PCIESS_AXI_1_S_AWLEN" \
"AWSIZE:PCIESS_AXI_1_S_AWSIZE" \
"AWBURST:PCIESS_AXI_1_S_AWBURST" \
"AWVALID:PCIESS_AXI_1_S_AWVALID" \
"AWREADY:PCIESS_AXI_1_S_AWREADY" \
"WDATA:PCIESS_AXI_1_S_WDATA" \
"WSTRB:PCIESS_AXI_1_S_WSTRB" \
"WLAST:PCIESS_AXI_1_S_WLAST" \
"WVALID:PCIESS_AXI_1_S_WVALID" \
"WREADY:PCIESS_AXI_1_S_WREADY" \
"BID:PCIESS_AXI_1_S_BID" \
"BRESP:PCIESS_AXI_1_S_BRESP" \
"BVALID:PCIESS_AXI_1_S_BVALID" \
"BREADY:PCIESS_AXI_1_S_BREADY" \
"ARID:PCIESS_AXI_1_S_ARID" \
"ARADDR:PCIESS_AXI_1_S_ARADDR" \
"ARLEN:PCIESS_AXI_1_S_ARLEN" \
"ARSIZE:PCIESS_AXI_1_S_ARSIZE" \
"ARBURST:PCIESS_AXI_1_S_ARBURST" \
"ARVALID:PCIESS_AXI_1_S_ARVALID" \
"ARREADY:PCIESS_AXI_1_S_ARREADY" \
"RID:PCIESS_AXI_1_S_RID" \
"RDATA:PCIESS_AXI_1_S_RDATA" \
"RRESP:PCIESS_AXI_1_S_RRESP" \
"RLAST:PCIESS_AXI_1_S_RLAST" \
"RVALID:PCIESS_AXI_1_S_RVALID" \
"RREADY:PCIESS_AXI_1_S_RREADY" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {PCIE_APB_SLAVE} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_S_PADDR" \
"PSELx:APB_S_PSEL" \
"PENABLE:APB_S_PENABLE" \
"PWRITE:APB_S_PWRITE" \
"PRDATA:APB_S_PRDATA" \
"PWDATA:APB_S_PWDATA" \
"PREADY:APB_S_PREADY" \
"PSLVERR:APB_S_PSLVERR" } 

# Add PCIe_AXI_SRAM_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PCIe_AXI_SRAM} -instance_name {PCIe_AXI_SRAM_0}



# Add PCIe_TL_CLK_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PCIe_TL_CLK} -instance_name {PCIe_TL_CLK_0}



# Add PCIe_Tx_PLL_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PCIe_Tx_PLL} -instance_name {PCIe_Tx_PLL_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PCIe_Tx_PLL_0:PLL_LOCK}



# Add PCIeM_AXI4Connect_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PCIeM_AXI4Connect} -instance_name {PCIeM_AXI4Connect_0}



# Add PF_PCIE_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_PCIE_C0} -instance_name {PF_PCIE_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_INTERRUPT} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_M_RDERR} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_S_WDERR} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_M_WDERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_S_RDERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_HOT_RST_EXIT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_PCIE_C0_0:PCIE_1_DLUP_EXIT}



# Add PF_XCVR_REF_CLK_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_S_PRESET_N" "PF_PCIE_C0_0:APB_S_PRESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARESETN" "PCIeM_AXI4Connect_0:ARESETN" "PCIe_AXI_SRAM_0:ARESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_CLK" "PCIeM_AXI4Connect_0:ACLK" "PCIe_AXI_SRAM_0:ACLK" "PF_PCIE_C0_0:AXI_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_CLK_STABLE" "PF_PCIE_C0_0:AXI_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK0_7_CALIB_DONE" "PCIe_TL_CLK_0:BANK0_7_CALIB_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BANK_6_VDDI_STATUS" "PCIe_TL_CLK_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DEVICE_INIT_DONE" "PCIe_TL_CLK_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FABRIC_POR_N" "PCIe_TL_CLK_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MiV_CLK" "PF_PCIE_C0_0:APB_S_PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD0_N" "PF_PCIE_C0_0:PCIESS_LANE_RXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD0_P" "PF_PCIE_C0_0:PCIESS_LANE_RXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD1_N" "PF_PCIE_C0_0:PCIESS_LANE_RXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD1_P" "PF_PCIE_C0_0:PCIESS_LANE_RXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD2_N" "PF_PCIE_C0_0:PCIESS_LANE_RXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD2_P" "PF_PCIE_C0_0:PCIESS_LANE_RXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD3_N" "PF_PCIE_C0_0:PCIESS_LANE_RXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_RXD3_P" "PF_PCIE_C0_0:PCIESS_LANE_RXD3_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD0_N" "PF_PCIE_C0_0:PCIESS_LANE_TXD0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD0_P" "PF_PCIE_C0_0:PCIESS_LANE_TXD0_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD1_N" "PF_PCIE_C0_0:PCIESS_LANE_TXD1_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD1_P" "PF_PCIE_C0_0:PCIESS_LANE_TXD1_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD2_N" "PF_PCIE_C0_0:PCIESS_LANE_TXD2_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD2_P" "PF_PCIE_C0_0:PCIESS_LANE_TXD2_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD3_N" "PF_PCIE_C0_0:PCIESS_LANE_TXD3_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIESS_LANE_TXD3_P" "PF_PCIE_C0_0:PCIESS_LANE_TXD3_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_0_INTERRUPT_OUT" "PF_PCIE_C0_0:PCIE_1_INTERRUPT_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_1_PERST_OUT_N" "PF_PCIE_C0_0:PCIE_1_PERST_OUT_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIe_TL_CLK_0:CLK_125MHz" "PCIe_Tx_PLL_0:CLK_125" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIe_TL_CLK_0:PCIE_INIT_DONE" "PF_PCIE_C0_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIe_TL_CLK_0:TL_CLK" "PF_PCIE_C0_0:PCIE_1_TL_CLK_125MHz" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIe_Tx_PLL_0:REF_CLK" "PF_PCIE_C0_0:PCIESS_LANE0_CDR_REF_CLK_0" "PF_PCIE_C0_0:PCIESS_LANE1_CDR_REF_CLK_0" "PF_PCIE_C0_0:PCIESS_LANE2_CDR_REF_CLK_0" "PF_PCIE_C0_0:PCIESS_LANE3_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_0_LTSSM" "PF_PCIE_C0_0:PCIE_1_LTSSM" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AXI_1_SLAVE" "PF_PCIE_C0_0:AXI_1_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR4_AXI" "PCIeM_AXI4Connect_0:AXI4mslave1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIE_APB_SLAVE" "PF_PCIE_C0_0:PCIE_APB_SLAVE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIeM_AXI4Connect_0:AXI4mmaster0" "PF_PCIE_C0_0:AXI_1_MASTER" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIeM_AXI4Connect_0:AXI4mslave0" "PCIe_AXI_SRAM_0:AXI4_Slave" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCIe_Tx_PLL_0:CLKS_TO_XCVR" "PF_PCIE_C0_0:CLKS_FROM_TXPLL_TO_PCIE_1" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "PCIe_RP"
generate_component -component_name ${sd_name}
