# Import source files

file copy -force "./src/softconsole/PCIe_RP_Demo.hex" "./$Prjname/PCIe_RP_Demo.hex"

# Create, configure and generate core components
source ./src/components/AXI_Interconnect.tcl 
source ./src/components/PF_CCC_C0.tcl 
source ./src/components/CLK_DIV2.tcl 
source ./src/components/CORERESET_PF_C0.tcl 
source ./src/components/Core_JTAG.tcl 
source ./src/components/MIV_RV32_C0.tcl  
source ./src/components/MIV_ESS_C0.tcl
source ./src/components/NGMUX.tcl 
source ./src/components/OSC_160MHz.tcl 
source ./src/components/PCIeM_AXI4Connect.tcl 
source ./src/components/PCIe_AXI_SRAM.tcl 
source ./src/components/PCIe_INIT_MONITOR.tcl  
source ./src/components/PCIe_Tx_PLL.tcl 
source ./src/components/PF_DDR4_SS.tcl 
source ./src/components/Reset_AXI_IF.tcl 
source ./src/components/Reset_MIV.tcl 
source ./src/components/PF_XCVR_REF_CLK_C0.tcl
source ./src/components/PF_PCIE_C0.tcl


file copy -force "./src/hdl/miv_rv32_subsys_pkg.v" "./$Prjname/component/Microsemi/MiV/MIV_RV32/$MIV_RV32ver/pkg/miv_rv32_subsys_pkg.v"

# Generate SmartDesign Components
build_design_hierarchy 
source ./src/components/MiV_SS.tcl
build_design_hierarchy 
source ./src/components/PCIe_TL_CLK.tcl
build_design_hierarchy 
source ./src/components/PCIe_RP.tcl
build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"