module prbs_asic_chk(input scan_mode,
                     input arxclk,
                     input arxrstn,
                     input atxclk,
                     input cdrpll_fine,
                     input meso_lpbk,
                     output meso_sync,
                     input custom_sel,
                     input custom_auto,
                     input custom_skip,
                     input[79 : 0] custom_pattern,
                     output custom_sync,
                     input custom_chk,
                     output[3 : 0] custom_err,
                     output[2 : 0] custom_state,
                     output rxskip,
                     input prbs_en,
                     input[1 : 0] prbs_typ,
                     input[4 : 0] prbs_rxn,
                     input[39 : 0] prbs_in,
                     input reg_clk,
                     input reg_rstn,
                     output prbs_cur,
                     `ifdef O
                       output reg[49 : 0] prbs_err_cyc_first,
                       output reg[49 : 0] prbs_err_cyc_last,
                     `endif
                     output reg[7 : 0] prbs_err,
                     output wire det_err);
  reg I;
  reg l;
  reg o;
  reg[1 : 0] i;
  reg OI;
  reg II;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          I <= 1'b0;
          l <= 1'b0;
          o <= 1'b0;
          i <= 2'b00;
          OI <= 1'b0;
          II <= 1'b0;
        end
      else
        begin
          I <= prbs_en;
          l <= I;
          o <= l;
          if (l && !o)
            i <= prbs_typ;
          OI <= cdrpll_fine;
          II <= OI;
        end
    end
  assign prbs_cur = l;
  reg[39 : 0] lI;
  reg[39 : 0] oI;
  reg[39 : 0] iI;
  reg[39 : 0] Ol;
  reg[39 : 0] Il;
  reg[39 : 0] ll;
  reg[39 : 0] ol;
  always
    @*
    begin: il
      integer O0,
              I0,
              l0,
              o0,
              i0,
              O1;
      oI = lI;
      iI = lI;
      Ol = lI;
      Il = lI;
      ll = lI;
      ol = lI;
      for (O0 = 0; O0 < 5; O0 = O0 + 1)
        begin: I1
          oI = { oI[39 : 0], oI[6] ^ oI[5] };
        end
      for (I0 = 0; I0 < 10; I0 = I0 + 1)
        begin: l1
          iI = { iI[39 : 0], iI[6] ^ iI[5] };
        end
      for (l0 = 0; l0 < 20; l0 = l0 + 1)
        begin: o1
          Ol = { Ol[39 : 0], Ol[6] ^ Ol[5] };
        end
      for (o0 = 0; o0 < 8; o0 = o0 + 1)
        begin: i1
          Il = { Il[39 : 0], Il[6] ^ Il[5] };
        end
      for (i0 = 0; i0 < 16; i0 = i0 + 1)
        begin: Oo
          ll = { ll[39 : 0], ll[6] ^ ll[5] };
        end
      for (O1 = 0; O1 < 40; O1 = O1 + 1)
        begin: Io
          ol = { ol[39 : 0], ol[6] ^ ol[5] };
        end
    end
  reg[39 : 0] lo;
  reg[39 : 0] oo;
  reg[39 : 0] io;
  reg[39 : 0] Oi;
  reg[39 : 0] Ii;
  always
    @*
    begin: li
      integer O0,
              I0,
              l0,
              o0,
              i0;
      lo = lI;
      oo = lI;
      io = lI;
      Oi = lI;
      Ii = lI;
      for (O0 = 0; O0 < 5; O0 = O0 + 1)
        begin: oi
          lo = { lo[29 : 0], lo[10] ^ lo[8] };
        end
      for (I0 = 0; I0 < 10; I0 = I0 + 1)
        begin: ii
          oo = { oo[29 : 0], oo[10] ^ oo[8] };
        end
      for (l0 = 0; l0 < 20; l0 = l0 + 1)
        begin: OOI
          io = { io[29 : 0], io[10] ^ io[8] };
        end
      for (o0 = 0; o0 < 8; o0 = o0 + 1)
        begin: IOI
          Oi = { Oi[29 : 0], Oi[10] ^ Oi[8] };
        end
      for (i0 = 0; i0 < 16; i0 = i0 + 1)
        begin: lOI
          Ii = { Ii[29 : 0], Ii[10] ^ Ii[8] };
        end
    end
  reg[39 : 0] oOI;
  reg[39 : 0] iOI;
  reg[39 : 0] OII;
  reg[39 : 0] III;
  reg[39 : 0] lII;
  always
    @*
    begin: oII
      integer O0,
              I0,
              l0,
              o0,
              i0,
              O1;
      oOI = lI;
      iOI = lI;
      OII = lI;
      III = lI;
      lII = lI;
      for (O0 = 0; O0 < 5; O0 = O0 + 1)
        begin: iII
          oOI = { oOI[29 : 0], oOI[22] ^ oOI[17] };
        end
      for (I0 = 0; I0 < 10; I0 = I0 + 1)
        begin: OlI
          iOI = { iOI[29 : 0], iOI[22] ^ iOI[17] };
        end
      for (l0 = 0; l0 < 20; l0 = l0 + 1)
        begin: IlI
          OII = { OII[29 : 0], OII[22] ^ OII[17] };
        end
      for (o0 = 0; o0 < 8; o0 = o0 + 1)
        begin: llI
          III = { III[29 : 0], III[22] ^ III[17] };
        end
      for (i0 = 0; i0 < 16; i0 = i0 + 1)
        begin: olI
          lII = { lII[29 : 0], lII[22] ^ lII[17] };
        end
    end
  reg[39 : 0] ilI;
  reg[39 : 0] O0I;
  reg[39 : 0] I0I;
  reg[39 : 0] l0I;
  reg[39 : 0] o0I;
  always
    @*
    begin: i0I
      integer O0,
              I0,
              l0,
              o0,
              i0;
      ilI = lI;
      O0I = lI;
      I0I = lI;
      l0I = lI;
      o0I = lI;
      for (O0 = 0; O0 < 5; O0 = O0 + 1)
        begin: O1I
          ilI = { ilI[29 : 0], ilI[30] ^ ilI[27] };
        end
      for (I0 = 0; I0 < 10; I0 = I0 + 1)
        begin: I1I
          O0I = { O0I[29 : 0], O0I[30] ^ O0I[27] };
        end
      for (l0 = 0; l0 < 20; l0 = l0 + 1)
        begin: l1I
          I0I = { I0I[29 : 0], I0I[30] ^ I0I[27] };
        end
      for (o0 = 0; o0 < 8; o0 = o0 + 1)
        begin: o1I
          l0I = { l0I[29 : 0], l0I[30] ^ l0I[27] };
        end
      for (i0 = 0; i0 < 16; i0 = i0 + 1)
        begin: i1I
          o0I = { o0I[29 : 0], o0I[30] ^ o0I[27] };
        end
    end
  reg[7 : 0] OoI;
  reg IoI;
  reg[39 : 0] loI;
  always
    @*
    begin: ooI
      integer O0;
      for (O0 = 0; O0 < 40; O0 = O0 + 1)
        begin
          loI[O0] = ~prbs_in[39 - O0];
        end
    end
  reg[39 : 0] ioI;
  wire OiI;
  wire IiI;
  wire liI;
  wire oiI;
  wire iiI;
  wire OOl;
  reg[7 : 0] IOl;
  reg[7 : 0] lOl;
  reg oOl,
      iOl,
      OIl;
  reg IIl;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          OoI <= 8'h00;
          IoI <= 1'b0;
          lI <= { 40 { 1'b1 } };
          IOl <= 8'h00;
          ioI <= 40'h00000;
          IIl <= 1'b0;
        end
      else
        if (!o)
          begin
            IOl <= 8'hFF;
            OoI <= 8'h00;
            IoI <= 1'b0;
            lI <= { 40 { 1'b1 } };
            IIl <= 1'b0;
          end
        else
          begin
            if (!II)
              OoI <= 8'h00;
            else
              if (OoI != 8'hFF)
                OoI <= OoI + 1'b1;
            IoI <= (OoI == 8'hFF);
            IIl <= (lI == 40'h0);
            if (IoI)
              begin
                case (i)
                  2'b00:
                    begin
                      if (prbs_rxn == 5'd4)
                        lI <= oI;
                      else
                        if (prbs_rxn == 5'd7)
                          lI <= Il;
                        else
                          if (prbs_rxn == 5'd9)
                            lI <= iI;
                          else
                            if (prbs_rxn == 5'd15)
                              lI <= ll;
                            else
                              if (prbs_rxn == 5'd3)
                                lI <= Ol;
                              else
                                lI <= ol;
                    end
                  2'b01:
                    begin
                      if (prbs_rxn == 5'd4)
                        lI <= lo;
                      else
                        if (prbs_rxn == 5'd7)
                          lI <= Oi;
                        else
                          if (prbs_rxn == 5'd9)
                            lI <= oo;
                          else
                            if (prbs_rxn == 5'd15)
                              lI <= Ii;
                            else
                              lI <= io;
                    end
                  2'b10:
                    begin
                      if (prbs_rxn == 5'd4)
                        lI <= oOI;
                      else
                        if (prbs_rxn == 5'd7)
                          lI <= III;
                        else
                          if (prbs_rxn == 5'd9)
                            lI <= iOI;
                          else
                            if (prbs_rxn == 5'd15)
                              lI <= lII;
                            else
                              lI <= OII;
                    end
                  2'b11:
                    begin
                      if (prbs_rxn == 5'd4)
                        lI <= ilI;
                      else
                        if (prbs_rxn == 5'd7)
                          lI <= l0I;
                        else
                          if (prbs_rxn == 5'd9)
                            lI <= O0I;
                          else
                            if (prbs_rxn == 5'd15)
                              lI <= o0I;
                            else
                              lI <= I0I;
                    end
                  default:
                    begin
                      lI <= { 40 { 1'b1 } };
                    end
                endcase
              end
            else
              begin
                if (prbs_rxn == 5'd4)
                  lI <= { lI[25 : 0], loI[4 : 0] };
                else
                  if (prbs_rxn == 5'd7)
                    lI <= { lI[22 : 0], loI[7 : 0] };
                  else
                    if (prbs_rxn == 5'd9)
                      lI <= { lI[20 : 0], loI[9 : 0] };
                    else
                      if (prbs_rxn == 5'd15)
                        lI <= { lI[14 : 0], loI[15 : 0] };
                      else
                        lI <= { lI[10 : 0], loI[19 : 0] };
              end
            ioI <= loI[39 : 0];
            if (!IoI && OoI == 8'hFF)
              IOl <= 8'h00;
            else
              if (IoI && det_err && IOl < 8'hFE)
                IOl <= IOl + 1'b1;
          end
    end
  assign OiI = (ioI[4 : 0] == lI[4 : 0]);
  assign IiI = (ioI[9 : 5] == lI[9 : 5]);
  assign liI = (ioI[19 : 10] == lI[19 : 10]);
  assign OOl = (ioI[39 : 0] == lI[39 : 0]);
  assign oiI = (ioI[7 : 0] == lI[7 : 0]);
  assign iiI = (ioI[15 : 8] == lI[15 : 8]);
  assign det_err = ~OOl;
  reg lIl;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          iOl <= 1'b0;
          OIl <= 1'b0;
          oOl <= 1'b0;
          lOl <= 8'h00;
        end
      else
        begin
          iOl <= lIl;
          OIl <= iOl;
          if (IOl != lOl && oOl == OIl)
            begin
              oOl <= ~oOl;
              lOl <= IOl;
            end
        end
    end
  reg oIl;
  reg iIl;
  always
    @(posedge reg_clk or
      negedge reg_rstn)
    begin
      if (!reg_rstn)
        begin
          oIl <= 1'b0;
          iIl <= 1'b0;
          lIl <= 1'b0;
          prbs_err <= 8'h00;
        end
      else
        begin
          oIl <= oOl;
          iIl <= oIl;
          lIl <= iIl;
          if (lIl != iIl)
            prbs_err <= lOl;
        end
    end
  `ifdef O
    reg[49 : 0] Oll,
                Ill,
                lll;
    reg oll;
    wire[49 : 0] ill = { 50 { 1'b1 } };
    always
      @(posedge arxclk or
        negedge arxrstn)
      begin
        if (!arxrstn)
          begin
            Oll <= 50'b0;
            Ill <= 50'b0;
            lll <= 50'b0;
            oll <= 1'b1;
          end
        else
          begin
            if (!IoI && OoI == 8'hFF)
              Oll <= 50'b0;
            else
              if (!oll)
                Oll <= Oll + 1'b1;
            if (IoI && Oll[49 : 1] == ill[49 : 1])
              oll <= 1'b1;
            else
              oll <= 1'b0;
            if (!IoI && OoI == 8'hFF)
              Ill <= 50'b0;
            else
              if (IoI && det_err && IOl < 8'hFE)
                Ill <= Oll;
            if (IOl != lOl && oOl == OIl)
              begin
                lll <= Ill;
              end
          end
      end
    always
      @(posedge reg_clk or
        negedge reg_rstn)
      begin
        if (!reg_rstn)
          begin
            prbs_err_cyc_first <= 50'b0;
            prbs_err_cyc_last <= 50'b0;
          end
        else
          begin
            if (lIl != iIl && lOl == 8'h01)
              prbs_err_cyc_first <= lll;
            if (lIl != iIl)
              prbs_err_cyc_last <= lll;
          end
      end
  `endif
  `ifdef O0l
    reg I0l;
    reg l0l;
    reg o0l;
    reg i0l;
    reg O1l;
    reg I1l;
    always
      @(posedge arxclk or
        negedge arxrstn)
      begin
        if (!arxrstn)
          begin
            I0l <= 1'b0;
            l0l <= 1'b0;
            o0l <= 1'b0;
            i0l <= 1'b0;
            O1l <= 1'b0;
            I1l <= 1'b0;
          end
        else
          begin
            I0l <= custom_sel;
            l0l <= I0l;
            o0l <= custom_chk;
            i0l <= o0l;
            O1l <= custom_auto;
            I1l <= O1l;
          end
      end
    reg[4 : 0] l1l;
    reg[4 : 0] o1l;
    reg[79 : 0] i1l;
    reg Ool;
    wire Iol;
    always
      @(posedge arxclk or
        negedge arxrstn)
      begin
        if (!arxrstn)
          begin
            l1l <= 5'd0;
            o1l <= 5'd19;
            i1l <= 80'h0;
            Ool <= 1'b0;
          end
        else
          begin
            if (!l0l || !II || l1l == o1l)
              l1l <= 5'h0;
            else
              if (Iol)
                l1l <= 5'h1;
              else
                l1l <= l1l + 1'b1;
            o1l <= (prbs_rxn == 5'd4) ? 5'd15 : (prbs_rxn == 5'd7) ? 5'd9 : (prbs_rxn == 5'd9) ? 5'd7 : (prbs_rxn == 5'd15) ? 5'd4 : 5'd3;
            if (!l0l)
              i1l <= 80'h0;
            else
              if (prbs_rxn == 5'd4)
                i1l <= { prbs_in[4 : 0], i1l[79 : 5] };
              else
                if (prbs_rxn == 5'd7)
                  i1l <= { prbs_in[7 : 0], i1l[79 : 8] };
                else
                  if (prbs_rxn == 5'd9)
                    i1l <= { prbs_in[9 : 0], i1l[79 : 10] };
                  else
                    if (prbs_rxn == 5'd15)
                      i1l <= { prbs_in[15 : 0], i1l[79 : 16] };
                    else
                      i1l <= { prbs_in[19 : 0], i1l[79 : 20] };
            Ool <= (i1l == custom_pattern);
          end
      end
    localparam[2 : 0] lol = 3'b000;
    localparam[2 : 0] ool = 3'b001;
    localparam[2 : 0] iol = 3'b010;
    localparam[2 : 0] Oil = 3'b011;
    localparam[2 : 0] Iil = 3'b100;
    localparam[2 : 0] lil = 3'b101;
    reg[2 : 0] oil;
    reg[7 : 0] iil;
    reg[3 : 0] OO0;
    reg IO0;
    always
      @(posedge arxclk or
        negedge arxrstn)
      begin
        if (!arxrstn)
          begin
            oil <= lol;
            IO0 <= 1'b0;
            iil <= 8'h0;
            OO0 <= 4'h0;
          end
        else
          begin
            case (oil)
              lol:
                begin
                  IO0 <= 1'b0;
                  iil <= 8'h0;
                  if (l0l && I1l && II)
                    oil <= ool;
                  else
                    if (i0l && !I1l && II)
                      oil <= iol;
                end
              ool:
                begin
                  IO0 <= 1'b0;
                  iil <= iil + 1'b1;
                  if (iil == 8'hFF)
                    oil <= iol;
                end
              iol:
                begin
                  IO0 <= 1'b0;
                  if (iil[5 : 1] >= o1l || Ool)
                    iil <= 8'h0;
                  else
                    iil <= iil + 1'b1;
                  if (Ool)
                    oil <= Iil;
                  else
                    if (iil[5 : 1] >= o1l)
                      oil <= Oil;
                end
              Oil:
                begin
                  oil <= iol;
                  IO0 <= 1'b1;
                end
              Iil:
                begin
                  if (iil[5 : 1] >= o1l || Ool)
                    iil <= 8'h0;
                  else
                    iil <= iil + 1'b1;
                  if (!l0l)
                    oil <= lol;
                  else
                    if (Ool && l1l == 5'h0)
                      oil <= lil;
                    else
                      if (iil[5 : 1] >= o1l)
                        oil <= iol;
                end
              lil:
                begin
                  if (!l0l)
                    oil <= lol;
                end
              default:
                begin
                  oil <= lol;
                end
            endcase
            if (!i0l)
              OO0 <= 4'h0;
            else
              if (oil == lil && l1l == 5'h0 && OO0 != 4'hF && !Ool)
                OO0 <= OO0 + 1'b1;
          end
      end
    assign Iol = (oil == iol) && Ool;
    reg lO0;
    assign rxskip = IO0 | custom_skip | lO0;
    reg oO0,
        iO0,
        OI0;
    reg II0;
    reg[3 : 0] lI0;
    always
      @(posedge arxclk or
        negedge arxrstn)
      begin
        if (!arxrstn)
          begin
            oO0 <= 1'b0;
            iO0 <= 1'b0;
            OI0 <= 1'b0;
            lI0 <= 4'h0;
          end
        else
          begin
            oO0 <= II0;
            iO0 <= oO0;
            if (OO0 != lI0 && OI0 == iO0)
              begin
                OI0 <= ~OI0;
                lI0 <= OO0;
              end
          end
      end
    reg oI0;
    reg iI0;
    reg[3 : 0] Ol0;
    always
      @(posedge reg_clk or
        negedge reg_rstn)
      begin
        if (!reg_rstn)
          begin
            oI0 <= 1'b0;
            iI0 <= 1'b0;
            II0 <= 1'b0;
            Ol0 <= 4'h0;
          end
        else
          begin
            oI0 <= OI0;
            iI0 <= oI0;
            II0 <= iI0;
            if (II0 != iI0)
              Ol0 <= lI0;
          end
      end
    reg[2 : 0] Il0,
               ll0;
    always
      @(posedge reg_clk or
        negedge reg_rstn)
      begin
        if (!reg_rstn)
          begin
            Il0 <= 3'b0;
            ll0 <= 3'h0;
          end
        else
          begin
            Il0 <= oil;
            ll0 <= Il0;
          end
      end
    assign custom_sync = (ll0 == lil);
    assign custom_err = Ol0;
    assign custom_state = ll0;
  `else
    reg lO0;
    assign rxskip = custom_skip | lO0;
    assign custom_err = 4'h0;
    assign custom_state = 3'h0;
    assign custom_sync = 1'b0;
  `endif
  reg ol0,
      il0;
  wire O00 = atxclk & ~scan_mode;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          ol0 <= 1'b0;
          il0 <= 1'b0;
        end
      else
        begin
          ol0 <= O00;
          il0 <= ol0;
        end
    end
  reg I00,
      l00;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          I00 <= 1'b0;
          l00 <= 1'b0;
        end
      else
        begin
          I00 <= meso_lpbk;
          l00 <= I00;
        end
    end
  localparam[2 : 0] o00 = 3'b000;
  localparam[2 : 0] i00 = 3'b001;
  localparam[2 : 0] O10 = 3'b010;
  localparam[2 : 0] I10 = 3'b011;
  localparam[2 : 0] l10 = 3'b100;
  localparam[2 : 0] o10 = 3'b101;
  reg[2 : 0] i10;
  reg[3 : 0] Oo0;
  always
    @(posedge arxclk or
      negedge arxrstn)
    begin
      if (!arxrstn)
        begin
          i10 <= o00;
          lO0 <= 1'b0;
          Oo0 <= 4'b0000;
        end
      else
        begin
          case (i10)
            o00:
              begin
                lO0 <= 1'b0;
                Oo0 <= 4'b0000;
                if (l00 && II)
                  i10 <= i00;
              end
            i00:
              begin
                lO0 <= 1'b0;
                Oo0 <= Oo0 + 1'b1;
                if (Oo0 == 4'b1111 && !il0)
                  i10 <= l10;
                else
                  if (Oo0 == 4'b1111)
                    i10 <= O10;
              end
            O10:
              begin
                lO0 <= 1'b1;
                Oo0 <= 4'b0000;
                i10 <= i00;
              end
            l10:
              begin
                lO0 <= 1'b1;
                Oo0 <= 4'b0000;
                i10 <= I10;
              end
            I10:
              begin
                lO0 <= 1'b0;
                Oo0 <= Oo0 + 1'b1;
                if (Oo0 == 4'b1111 && il0)
                  i10 <= o10;
                else
                  if (Oo0 == 4'b1111)
                    i10 <= l10;
              end
            o10:
              begin
                lO0 <= 1'b0;
                Oo0 <= 4'b0000;
                if (!l00)
                  i10 <= o00;
              end
            default:
              begin
                i10 <= o00;
              end
          endcase
        end
    end
  reg[2 : 0] Io0,
             lo0;
  always
    @(posedge reg_clk or
      negedge reg_rstn)
    begin
      if (!reg_rstn)
        begin
          Io0 <= 3'b0;
          lo0 <= 3'h0;
        end
      else
        begin
          Io0 <= i10;
          lo0 <= Io0;
        end
    end
  assign meso_sync = (lo0 == o10);
endmodule
