# Import source files
import_files -hdl_source {./src/hdl/FabUART.v}
import_files -hdl_source {./src/hdl/prbs_asic_chk.v}
import_files -hdl_source {./src/hdl/prbs_asic_gen.v}
import_files -hdl_source {./src/hdl/PRBS_chk.v}
import_files -hdl_source {./src/hdl/PRBS_gen.v}


build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CCC_0.tcl
source ./src/components/fifo_cdc.tcl
source ./src/components/INIT_comp.tcl
source ./src/components/OSC_0.tcl
source ./src/components/transmit_pll.tcl
source ./src/components/uart_ip.tcl
source ./src/components/xcvr_ip.tcl
source ./src/components/xcvr_ref_clock.tcl
source ./src/components/reset_sync_rx.tcl
source ./src/components/reset_sync_tx.tcl
source ./src/components/reset_sync_uart.tcl


# Generate SmartDesign Components
source ./src/components/reset_block.tcl
build_design_hierarchy 
source ./src/components/uart_block.tcl
build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
