# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {EMPTY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FULL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}



# Add CDC_FIFO_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CDC_FIFO} -instance_name {CDC_FIFO_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:DATA} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:DATA} -pin_slices {[32:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:DATA} -pin_slices {[33:33]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:DATA} -pin_slices {[34:34]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:Q} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:Q} -pin_slices {[32:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:Q} -pin_slices {[33:33]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CDC_FIFO_0:Q} -pin_slices {[34:34]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CDC_FIFO_0:WE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CDC_FIFO_0:RE} -value {VCC}



# Add DFN1_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_0}



# Add DFN1_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_1}



# Add DFN1_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_2}



# Add DFN1_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_3}



# Add DFN1_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_4}



# Add DFN1_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_5}



# Add DFN1_6 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_6}



# Add DFN1_7 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_7}



# Add INIT_component_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_component} -instance_name {INIT_component_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_component_0:AUTOCALIB_DONE}



# Add pattern_chk_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_chk} -hdl_file {hdl\pattern_chk.v} -instance_name {pattern_chk_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_cnt}



# Add pattern_gen_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_gen} -hdl_file {hdl\pattern_gen.v} -instance_name {pattern_gen_0}



# Add PF_CCC_01_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_01} -instance_name {PF_CCC_01_0}



# Add PF_OSC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_0} -instance_name {PF_OSC_0_0}



# Add PF_TX_PLL_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_0} -instance_name {PF_TX_PLL_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:PLL_LOCK}



# Add PF_XCVR_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_SOS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_STATUS_HI_BER}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}



# Add PF_XCVR_REF_CLK_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}



# Add Reset_Block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Reset_Block} -instance_name {Reset_Block_0}



# Add UART_INTERFACE_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_INTERFACE} -instance_name {UART_INTERFACE_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_INTERFACE_0:connect_o}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:DATA[32:32]" "pattern_chk_0:lock_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:DATA[33:33]" "pattern_chk_0:rx_val_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:DATA[34:34]" "pattern_chk_0:error_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:EMPTY" "EMPTY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:FULL" "FULL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:Q[32:32]" "UART_INTERFACE_0:rx_lock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:Q[33:33]" "UART_INTERFACE_0:rx_val" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:Q[34:34]" "UART_INTERFACE_0:rx_error" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:RCLOCK" "PF_CCC_01_0:OUT0_FABCLK_0" "Reset_Block_0:uart_clk" "UART_INTERFACE_0:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:RRESET_N" "Reset_Block_0:uart_rst_n" "UART_INTERFACE_0:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:WCLOCK" "DFN1_0:CLK" "DFN1_1:CLK" "DFN1_2:CLK" "DFN1_3:CLK" "PF_XCVR_0_0:LANE0_RX_CLK_R" "Reset_Block_0:RX_clk" "pattern_chk_0:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:WRESET_N" "Reset_Block_0:Pattern_chk_rst_n" "pattern_chk_0:nreset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:D" "Reset_Block_0:Start" "UART_INTERFACE_0:start" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:Q" "DFN1_1:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_1:Q" "pattern_chk_0:start" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_2:D" "UART_INTERFACE_0:clear" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_2:Q" "DFN1_3:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_3:Q" "pattern_chk_0:clr_err_counter" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:CLK" "DFN1_5:CLK" "DFN1_6:CLK" "DFN1_7:CLK" "PF_XCVR_0_0:LANE0_TX_CLK_R" "Reset_Block_0:TX_clk" "pattern_gen_0:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:D" "UART_INTERFACE_0:genrate_err" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:Q" "DFN1_7:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_5:D" "PF_XCVR_0_0:LANE0_STATUS_LOCK" "pattern_chk_0:lane_status_lock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_5:Q" "DFN1_6:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_6:Q" "pattern_gen_0:lane_status_lock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_7:Q" "pattern_gen_0:generate_err" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_component_0:BANK_6_VDDI_STATUS" "Reset_Block_0:BANK_x_VDDI_STATUS" "Reset_Block_0:BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_component_0:DEVICE_INIT_DONE" "Reset_Block_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_component_0:FABRIC_POR_N" "Reset_Block_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_component_0:XCVR_INIT_DONE" "PF_XCVR_0_0:CTRL_ARST_N" "PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_0_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_0_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_0_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_0_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_01_0:OUT1_FABCLK_0" "PF_XCVR_0_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_01_0:PLL_LOCK_0" "Reset_Block_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_01_0:REF_CLK_0" "PF_OSC_0_0:RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:REF_CLK" "PF_XCVR_0_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA_VAL" "pattern_chk_0:data_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_HDR_VAL" "pattern_chk_0:hdr_valid" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_READY" "Reset_Block_0:RX_ready" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_VAL" "pattern_chk_0:rx_val" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_STABLE" "Reset_Block_0:TX_clk_stable" "pattern_gen_0:tx_clk_stable" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_SOS" "pattern_gen_0:sos" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_INTERFACE_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Reset_Block_0:Pattern_gen_rst_n" "pattern_gen_0:nreset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_INTERFACE_0:TX" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:DATA[31:0]" "pattern_chk_0:error_count_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CDC_FIFO_0:Q[31:0]" "UART_INTERFACE_0:error_count" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "pattern_chk_0:data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_HDR" "pattern_chk_0:hdr" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_DATA" "pattern_gen_0:dataout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_HDR" "pattern_gen_0:hdr" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:CLKS_TO_XCVR" "PF_XCVR_0_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
