//-------------------------------------------------------------------
//                                                                 
//-------------------------------------------------------------------------
//© 2024 Microchip Technology Inc. and its subsidiaries
//All rights reserved.
//ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//IN ADVANCE IN WRITING.
//-------------------------------------------------------------------------
//
//-------------------------------------------------------------------
// Title        : bit_slip_gen.v
// Created      : November-2017
// Description  : This module implements the generator logic for the 
// 		  counter pattern going to the transmitter side
// Revision     : NA
// Hierarchy    :
//                bit_slip_PMA_top

//                  -- bit_slip_gen.v             <-- This module
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module bit_slip_gen
(
input clk,//input clock
input rst_n,//Reset for logic
input generate_err,//UART input signal for generating bit error
input valid_signal,//denotes symbol alignment
input rx_val_i,//RX_VALID signal from XCVR
output wire  [39:0] data_out//output data
);


//******************************************************************************
//******************** Signal Declaration     **********************************
//******************************************************************************

parameter  g_DATA_WID = 40;

//----------STATE parameter declaration---------

parameter [2:0] STATE_0 = 3'b000;
parameter [2:0] STATE_1 = 3'b001;
parameter [2:0] STATE_2 = 3'b010;
//----------------------------------------------


reg [g_DATA_WID-1:0]s_count_data;
reg [2:0]s_count;

reg generate_err_d1, generate_err_d2;

always@(posedge clk or negedge rst_n)
 begin
  if (rst_n == 1'b0)
  begin
  generate_err_d1 <= 1'b0;
  generate_err_d2 <= 1'b0;
  end
  else
  begin
  generate_err_d1 <= generate_err;
  generate_err_d2 <= generate_err_d1;
  end
end

//****************************************************************************
//******************* K28.5, bit slip and Count generator ********************
//****************************************************************************

always @(posedge clk or negedge rst_n)
 begin
   if(rst_n == 1'b0)
     begin
        s_count_data <= 40'h00000000bc;
	s_count <= 3'b000;
     end
   else
   begin
	case(s_count)
     	STATE_0:
     	begin
        s_count_data <= 40'h00000000bc;
	s_count <= STATE_1;
     	end
	STATE_1:
	begin
		if(valid_signal && rx_val_i)
		begin
			s_count_data <= 40'h0000000000;
			s_count <= STATE_2;
		end
		else
		begin
            		s_count_data <= 40'h00000000bc;
			s_count <= STATE_1;
		end
	end
			
	STATE_2:
  	begin 
   		if(s_count_data < 40'h8000000000)
   		begin   
   			s_count_data <= s_count_data +1;//increment counter
   			s_count <=STATE_2;     
   		end
   		else
   		begin
   			s_count_data <= 40'h0000000000;
   			s_count <=STATE_0;
   		end
  	end
 	default:
  	begin
   		s_count_data <= 40'h0000000000;
   		s_count <=STATE_0;
    end
 endcase   
end	
end

//output data
assign data_out = (generate_err_d2==1'b1) ? 40'h00000000bc : s_count_data;

endmodule

