# Import source files
import_files -hdl_source {./src/hdl/FabUART.v}
import_files -hdl_source {./src/hdl/bit_slip_chk.v}
import_files -hdl_source {./src/hdl/bit_slip_gen.v}
import_files -hdl_source {./src/hdl/bit_slip_shft.v}



build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CCC_0.tcl
source ./src/components/fifo.tcl
source ./src/components/gt_ref_clk.tcl
source ./src/components/init_monitor.tcl
source ./src/components/osc_clk.tcl
source ./src/components/UART_core.tcl
source ./src/components/XCVR_Block.tcl
source ./src/components/transmit_pll.tcl
source ./src/components/Reset_sync_rx_0.tcl
source ./src/components/Reset_sync_tx_0.tcl
source ./src/components/Reset_sync_uart.tcl


# Generate SmartDesign Components
source ./src/components/reset_block.tcl
build_design_hierarchy 
source ./src/components/uart_interface.tcl
build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
