# Import source files
import_files -hdl_source {./src/hdl/FabUART.v}
import_files -hdl_source {./src/hdl/pattern_chk.v}
import_files -hdl_source {./src/hdl/pattern_gen.v}

build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CDC_FIFO.tcl
source ./src/components/COREUART_0.tcl
source ./src/components/INIT_component.tcl
source ./src/components/PF_CCC_01.tcl
source ./src/components/PF_OSC_0.tcl
source ./src/components/PF_TX_PLL_0.tcl
source ./src/components/PF_XCVR_0.tcl
source ./src/components/PF_XCVR_REF_CLK_0.tcl
source ./src/components/Reset_sync_rx.tcl
source ./src/components/Reset_sync_tx.tcl
source ./src/components/Reset_sync_uart.tcl


# Generate SmartDesign Components
source ./src/components/Reset_Block.tcl
build_design_hierarchy 
source ./src/components/UART_INTERFACE.tcl
build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
