# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {EMPTY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FULL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}



# Add bit_slip_chk_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {bit_slip_chk} -hdl_file {hdl\bit_slip_chk.v} -instance_name {bit_slip_chk_0}



# Add bit_slip_gen_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {bit_slip_gen} -hdl_file {hdl\bit_slip_gen.v} -instance_name {bit_slip_gen_0}



# Add bit_slip_shft_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {bit_slip_shft} -hdl_file {hdl\bit_slip_shft.v} -instance_name {bit_slip_shft_0}



# Add CCC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_0} -instance_name {CCC_0_0}



# Add DFN1_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_0}



# Add DFN1_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_1}



# Add DFN1_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_2}



# Add DFN1_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_3}



# Add DFN1_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_4}



# Add DFN1_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_5}



# Add DFN1_7 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_7}



# Add DFN1_8 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {DFN1} -instance_name {DFN1_8}



# Add fifo_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {fifo} -instance_name {fifo_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:DATA} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:DATA} -pin_slices {[32:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:DATA} -pin_slices {[33:33]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:DATA} -pin_slices {[34:34]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:Q} -pin_slices {[31:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:Q} -pin_slices {[32:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:Q} -pin_slices {[33:33]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {fifo_0:Q} -pin_slices {[34:34]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fifo_0:WE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {fifo_0:RE} -value {VCC}



# Add gt_ref_clk_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {gt_ref_clk} -instance_name {gt_ref_clk_0}



# Add init_monitor_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {init_monitor} -instance_name {init_monitor_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {init_monitor_0:AUTOCALIB_DONE}



# Add osc_clk_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {osc_clk} -instance_name {osc_clk_0}



# Add reset_block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_block} -instance_name {reset_block_0}



# Add transmit_pll_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {transmit_pll} -instance_name {transmit_pll_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {transmit_pll_0:PLL_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {transmit_pll_0:CLK_125}



# Add uart_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {uart_interface} -instance_name {uart_interface_0}



# Add XCVR_Block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_Block} -instance_name {XCVR_Block_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {XCVR_Block_0:LANE0_PCS_ARST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {XCVR_Block_0:LANE0_PMA_ARST_N} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_Block_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {XCVR_Block_0:LANE0_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {XCVR_Block_0:LANE0_LOS} -value {GND}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT0_FABCLK_0" "fifo_0:RCLOCK" "reset_block_0:uart_clk" "uart_interface_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT1_FABCLK_0" "XCVR_Block_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_LOCK_0" "reset_block_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:REF_CLK_0" "osc_clk_0:RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:CLK" "DFN1_1:CLK" "DFN1_2:CLK" "DFN1_3:CLK" "XCVR_Block_0:LANE0_RX_CLK_R" "bit_slip_chk_0:clk_i" "bit_slip_shft_0:clk_i" "fifo_0:WCLOCK" "reset_block_0:RX_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:D" "reset_block_0:start" "uart_interface_0:start" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_0:Q" "DFN1_1:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_1:Q" "bit_slip_chk_0:start_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_2:D" "uart_interface_0:clear" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_2:Q" "DFN1_3:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_3:Q" "bit_slip_chk_0:clear_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:CLK" "DFN1_5:CLK" "DFN1_7:CLK" "DFN1_8:CLK" "XCVR_Block_0:LANE0_TX_CLK_R" "bit_slip_gen_0:clk" "reset_block_0:TX_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:D" "uart_interface_0:genrate_err" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_4:Q" "DFN1_5:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_5:Q" "bit_slip_gen_0:generate_err" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_7:D" "bit_slip_chk_0:valid_signal" "bit_slip_shft_0:valid_signal" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_7:Q" "DFN1_8:D" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DFN1_8:Q" "bit_slip_gen_0:valid_signal" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"EMPTY" "fifo_0:EMPTY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FULL" "fifo_0:FULL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "XCVR_Block_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "XCVR_Block_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "XCVR_Block_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "XCVR_Block_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "gt_ref_clk_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "gt_ref_clk_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "uart_interface_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "uart_interface_0:TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:CTRL_ARST_N" "init_monitor_0:XCVR_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_CDR_REF_CLK_0" "gt_ref_clk_0:REF_CLK" "transmit_pll_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_RX_READY" "reset_block_0:RX_ready" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_RX_SLIP" "bit_slip_shft_0:rx_slip_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_RX_VAL" "bit_slip_chk_0:rx_val_i" "bit_slip_gen_0:rx_val_i" "bit_slip_shft_0:rx_val_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_TX_CLK_STABLE" "reset_block_0:TX_clk_stable" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_chk_0:error_o" "fifo_0:DATA[32:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_chk_0:lock_o" "fifo_0:DATA[34:34]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_chk_0:reset_n_i" "bit_slip_shft_0:reset_n_i" "fifo_0:WRESET_N" "reset_block_0:pattern_chk_rst_n" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_chk_0:rx_val_o" "fifo_0:DATA[33:33]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_gen_0:rst_n" "reset_block_0:pattern_gen_rst_n" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"fifo_0:Q[32:32]" "uart_interface_0:RX_ERROR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"fifo_0:Q[33:33]" "uart_interface_0:RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"fifo_0:Q[34:34]" "uart_interface_0:RX_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"fifo_0:RRESET_N" "reset_block_0:uart_rst_n" "uart_interface_0:RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"init_monitor_0:BANK_6_VDDI_STATUS" "reset_block_0:BANK_x_VDDI_STATUS" "reset_block_0:BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"init_monitor_0:DEVICE_INIT_DONE" "reset_block_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"init_monitor_0:FABRIC_POR_N" "reset_block_0:FPGA_POR_N" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_RX_DATA" "bit_slip_chk_0:data_in_i" "bit_slip_shft_0:rx_data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:LANE0_TX_DATA" "bit_slip_gen_0:data_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"bit_slip_chk_0:error_count_o" "fifo_0:DATA[31:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"fifo_0:Q[31:0]" "uart_interface_0:error_count" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"XCVR_Block_0:CLKS_FROM_TXPLL_0" "transmit_pll_0:CLKS_TO_XCVR" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
