///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : LSRAM1Kx18.v
// Created      : November-2017
// Description  : This module invokes PolarFire LSRAM block using RTL inference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- LSRAM_cascaded.v                   
//                    -- LSRAM1Kx18.v                   <-- This module 
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------
module lsram1kx18 #(parameter width = 18,
                              depth = 1024,
                              addr = 10)
                  (input[width - 1 : 0] Din,   //input data
                   input CLK,                  //input clock
                   input WE,                   //write enable
                   input[addr - 1 : 0] WAddr,  //write address
                   input[addr - 1 : 0] RAddr,  //read address
                   output[width - 1 : 0] Dout  //output data
                  )/* synthesis syn_preserve=1 */; //Attribute added to avoid pruning
  reg[width - 1 : 0] ramTmp[0 : depth - 1]/* synthesis syn_ramstyle="rw_check" */;
  reg[addr - 1 : 0] RAddr_Reg;
  
  //Writing/Reading data to/from LSRAM
  always@(posedge CLK)
    begin
      RAddr_Reg <= RAddr;
      if (WE == 1'b1)
        ramTmp[WAddr] <= Din;
    end
  assign Dout = ramTmp[RAddr_Reg];
endmodule
