///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : LSRAM_cascaded.v
// Created      : November-2017
// Description  : This module cascades LSRAM blocks based on user preference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- LSRAM_cascaded.v		   <-- This module	
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module LSRAM_cascaded #(parameter WIDTH = 18, DEPTH = 1024, ADDR = 10, NO_OF_STAGES = 10) 
(
input clk,               // input clock 
input rst,               // reset for logic
input [WIDTH-1: 0] DIN,  // input data
output [WIDTH-1:0] DOUT  //output data
)/* synthesis syn_noprune=1 syn_hier="fixed" */; //Attribute added to avoid pruning

wire [WIDTH-1:0]   REG_ARRAY[0:NO_OF_STAGES-1];
wire [9:0]         WA;
wire [9:0]         RA;
 
//Module for generating write, read enables and addresses for LSRAM blocks
we_ad_gen #(.WIDTH(10)) U2
    (
    .CLK(clk), 
    .RST(rst), 
    .WA(WA), 
    .RA(RA));

//Logic for cascading and instantiating LSRAM blocks
   generate
      begin : LSRAM_CASCADE
         genvar i;
         for (i = 0; i <= NO_OF_STAGES-1; i = i + 1)
         begin : SRAM
            if (i == 0)
            begin : SRAM0
               
               lsram1kx18 #(.width(18), .depth(DEPTH), .addr(ADDR)) U1
                            (
                            .Din(DIN), 
                            .CLK(clk), 
                            .WE(1'b1),
                            .WAddr(WA), 
                            .RAddr(RA), 
                            .Dout(REG_ARRAY[0]));
            end
            if (i != 0)
            begin : SRAM1
               
               lsram1kx18 #(.width(18), .depth(DEPTH), .addr(ADDR)) U1
                            (
                            .Din(REG_ARRAY[i-1]), 
                            .CLK(clk), 
                            .WE(1'b1),
                            .WAddr(WA), 
                            .RAddr(RA), 
                            .Dout(REG_ARRAY[i]));
            end
         end
      end
   endgenerate
 
assign DOUT = REG_ARRAY[NO_OF_STAGES-1];
endmodule

