///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
// 
// © 2022 Microchip Technology Inc. and its subsidiaries
//   All rights reserved.
//  
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title       : Gate_control.v
// Created     : November-2017
// Description : Double flop synchronizer
//               
// Hierarchy   :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- Gate_control.v           		   <-- This module
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

//`timescale <time_units> / <precision>

module Gate_control( clk, rstn, gate_en_in, gate_en_out);
input clk;
input rstn;
input gate_en_in;
output gate_en_out;

//<statements>

reg gate_en_reg1, gate_en_reg2;

always @ (posedge clk or negedge rstn) begin
    if(rstn == 1'b0) begin
        gate_en_reg1 <= 1'b0;
        gate_en_reg2 <= 1'b0;
    end
    else if (gate_en_in) begin 
        gate_en_reg1 <= 1'b1;
        gate_en_reg2 <= gate_en_reg1;
    end
    else begin
        gate_en_reg1 <= 1'b0;
        gate_en_reg2 <= gate_en_reg1;
    end
end

assign gate_en_out = gate_en_reg2;

endmodule

