///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
// 
// © 2022 Microchip Technology Inc. and its subsidiaries
//   All rights reserved.
//  
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------------
// Title       : cnt_up_cascade.v
// Created     : November-2017
// Description : This module instantiates series of counters based 
//                on user preference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- cnt_up_cascade.v		   <-- This module
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module cnt_up_cascade #(parameter WIDTH = 16, NO_OF_STAGES = 10)
( 
   input              CLK,	//input clock
   input              RST,	//reset for logic
   input [WIDTH-1:0]  DIN,	//input data for counter
   output [WIDTH-1:0] DOUT	//output data from counter
)/* synthesis syn_noprune=1 syn_hier="fixed" */; //Attribute added to avoid pruning  
   
   wire [WIDTH-1:0]   REG_ARRAY[0:NO_OF_STAGES*268];
   assign DOUT = REG_ARRAY[NO_OF_STAGES*268];
   
   //Logic for instantiating fabric LUT and flip flop resources  
   generate
      begin : xhdl0
         genvar i;
		 /* synthesis loop_limit 10000 */
         for (i = 0; i <= NO_OF_STAGES*268; i = i + 1)
         begin : F
            if (i == 0)
            begin : F0
               
               cnt_up #(.WIDTH(WIDTH)) U1
                (
                 .CLK(CLK), 
                 .RST(RST), 
                 .DIN(DIN), 
                 .DOUT(REG_ARRAY[0]));
            end
            if (i != 0)
            begin : F1
               
               cnt_up #(.WIDTH(WIDTH)) U2
                (
                 .CLK(CLK), 
                 .RST(RST),
                 .DIN(REG_ARRAY[i - 1]), 
                 .DOUT(REG_ARRAY[i]));
            end
         end
      end
   endgenerate
endmodule
