///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : mult18x18.v
// Created      : November-2017
// Description  : This module invokes PolarFire mathblock using RTL inference 
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- MACC_cascaded.v          
//                    -- mult18x18.v                      <-- This module       
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------
module mult18x18(input signed[17 : 0] in1,      //input data 1 
                 input signed[17 : 0] in2,      //input data 2
                 input signed[17 : 0] in3,      //input data3
                 input clk,                     //input clock
                 input rst,                     //input reset
                 output reg signed[47 : 0] out1 //output data
                )/* synthesis syn_preserve=1 */;
  
  //Attribute added for avoiding pruning of logic
  reg signed[17 : 0] in1_reg;
  reg signed[17 : 0] in2_reg;
  reg signed[17 : 0] in3_reg;
  wire signed[18 : 0] pre_sum;
  assign pre_sum = in1_reg + in2_reg;
  
  // 18*18 multiplier
  always@(posedge clk)
    begin
      if (!rst)
        begin
          in1_reg <= 18'b0;
          in2_reg <= 18'b0;
          in3_reg <= 18'b0;
          out1 <= 48'b0;
        end
      else
        begin
          in1_reg <= in1;
          in2_reg <= in2;
          in3_reg <= in3;
          out1 <= pre_sum * in3_reg;
        end
    end
endmodule
