///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : we_ad_gen.v
// Created      : November-2017
// Description  : This module generates enables, wrtite
//                address and read address for SRAM blocks
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- uSRAM_cascaded.v/LSRAM_cascaded.v                  
//                    -- we_ad_gen.v                                       <-- This module              
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module we_ad_gen(CLK,
                 RST,
                 WE,
                 WA,
                 RA);
  parameter WIDTH = 10;
  input CLK;                  // Input clock
  input RST;                  // Reset for logic
  output WE;                  // Write enable
  output[WIDTH - 1 : 0] WA;   // Write address 
  output[WIDTH - 1 : 0] RA;   // Read address
  
  //Module for generating write address for SRAMs 
  wa_cnt #(.WIDTH(WIDTH)) U1(.CLK(CLK),
                             .RST(RST),
                             .DOUT(WA));
  
  //Module for generating read address for SRAMs
  ra_cnt #(.WIDTH(WIDTH)) U2(.CLK(CLK),
                             .RST(RST),
                             .DOUT(RA));
endmodule
