///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : MACC_cascaded.v
// Created      : November-2017
// Description  : This module cascades LSRAM blocks based on user preference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- MACC_cascaded.v		   <-- This module	
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------


module MACC_cascaded  #(parameter WIDTH = 18, NO_OF_STAGES = 100)
(
input clk,               // input clock 
input rst,               // reset for logic
input [WIDTH-1: 0] DIN1, // input data 1
input [WIDTH-1: 0] DIN2, // input data 2
output [47:0] DOUT,      // output data
output [47:0] DOUT_t     // output data after multiplier
)/* synthesis syn_noprune=1 syn_hier="fixed" */; //Attribute added for avoiding pruning of logic


wire [WIDTH-1:0]   REG_ARRAY1[0:NO_OF_STAGES-1];
wire [WIDTH-1:0]   REG_ARRAY2[0:NO_OF_STAGES-1]; 
wire [11:0]   REG_ARRAY3[0:NO_OF_STAGES];      


//Logic for cascading and instantiating LSRAM blocks
   generate
      begin : MACC_CASCADE
         genvar i;
         for (i = 0; i <= NO_OF_STAGES-1; i = i + 1)
         begin : MACC
            if (i == 0)
            begin : MACC0
               
               mult18x18 U1
                        (
                        .clk(clk), 
                        .rst(rst), 
                        .in1(DIN1), 
                        .in2(DIN2), 
                        .in3(DIN1), 
                        .out1({REG_ARRAY3[0],REG_ARRAY2[0],REG_ARRAY1[0]}));
            end
            if (i != 0)
            begin : MACC1
               
               mult18x18 U2
                        (
                        .clk(clk), 
                        .rst(rst),
                        .in1(REG_ARRAY1[i-1]), 
                        .in2(REG_ARRAY2[i-1]), 
                        .in3(REG_ARRAY1[i-1]), 
                        .out1({REG_ARRAY3[i],REG_ARRAY2[i],REG_ARRAY1[i]}));
            end
         end
      end
   endgenerate
 
assign DOUT = {30'h00000000,(REG_ARRAY1[NO_OF_STAGES-1] & REG_ARRAY2[NO_OF_STAGES-1])};

assign DOUT_t = {30'h00000000,(REG_ARRAY1[4] & REG_ARRAY2[4])};

endmodule






