///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//                                                                
//  © 2022 Microchip Technology Inc. and its subsidiaries
//  All rights reserved.
//                                                                 
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//  ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : ra_cnt.v
// Created      : November-2017
// Description  : This module generates required read address for SRAM blocks
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- uSRAM_cascaded.v/LSRAM_cascaded.v                  
//                    -- we_ad_gen.v    
//                     -- ra_cnt.v                                 <-- This module              
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module wa_cnt(CLK,
              RST,
              DOUT);
  parameter WIDTH = 10;
  input CLK;                  // Input clock
  input RST;                  // Reset for logic
  output[WIDTH - 1 : 0] DOUT; // Output data
  
  
  reg[WIDTH - 1 : 0] CNTVAL;
  
  //Logic for write address generation
  always@(posedge CLK or negedge RST)
    begin: U
      if (RST == 1'b0)
        CNTVAL <= { WIDTH { 1'b0 } };
      else
        CNTVAL <= CNTVAL + 1;
    end
  assign DOUT = CNTVAL;
endmodule
