# Creating SmartDesign XCVR_Top
set sd_name {XCVR_Top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Reset_In} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {lock_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {error_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCS_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PMA_ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {lock_o_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val_o_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {error_o_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IO_IN_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IO_IN_1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IO_IN_2} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_x_VDDI_STATUS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_POR_N} -port_direction {IN}


# Add ccc_50_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {ccc_50} -instance_name {ccc_50_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {ccc_50_0:PLL_LOCK_0}



# Add CORE_ABC_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORE_ABC} -instance_name {CORE_ABC_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE_ABC_0:IO_IN} -pin_slices {[0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE_ABC_0:IO_IN} -pin_slices {[1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE_ABC_0:IO_IN} -pin_slices {[2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE_ABC_0:IO_IN} -pin_slices {[3]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE_ABC_0:IO_IN[3]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORE_ABC_0:IO_IN} -pin_slices {[4]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORE_ABC_0:IO_IN[4]} -value {GND}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PADDR_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PSEL_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PENABLE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PWRITE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PRDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PWDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PREADY_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CORE_ABC_0:APB3master} -pin_names {CORE_ABC_0:PSLVERR_M}



# Add DRI_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DRI_interface} -instance_name {DRI_interface_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DRI_interface_0:PADDR} -pin_slices {[19:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DRI_interface_0:PADDR} -pin_slices {[28:20]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PADDR}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PSEL}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PENABLE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PWRITE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PRDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PWDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PREADY}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {DRI_interface_0:APBS} -pin_names {DRI_interface_0:PSLVERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DRI_interface_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DRI_interface_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DRI_interface_0:BUSERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DRI_interface_0:PSTRB} -value {VCC}



# Add pattern_chk_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_chk} -hdl_file {hdl\pattern_chk.v} -instance_name {pattern_chk_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:start_i} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_0:clear_i} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_0:error_count_o}



# Add pattern_chk_even_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_chk_even} -hdl_file {hdl\pattern_chk_even.v} -instance_name {pattern_chk_even_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_even_0:start_i} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_chk_even_0:clear_i} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {pattern_chk_even_0:error_count_o}



# Add pattern_gen_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_gen} -hdl_file {hdl\pattern_gen.v} -instance_name {pattern_gen_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_gen_0:generate_err_i} -value {GND}



# Add pattern_gen_even_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {pattern_gen_even} -hdl_file {hdl\pattern_gen_even.v} -instance_name {pattern_gen_even_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {pattern_gen_even_0:generate_err_i} -value {GND}



# Add PF_CLK_DIV_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}



# Add PF_XCVR_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_RX_IDLE}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_READY}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_LOS} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_CODE_VIOLATION}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_DISPARITY_ERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_TX_DISPFNC} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_RX_CODE_VIOLATION}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_RX_DISPARITY_ERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE1_TX_DISPFNC} -value {GND}



# Add Reference_clock_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Reference_clock} -instance_name {Reference_clock_0}



# Add rst_sync1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {rst_sync1} -instance_name {rst_sync1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync1_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {rst_sync1_0:PLL_POWERDOWN_B}



# Add rst_sync2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {rst_sync2} -instance_name {rst_sync2_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync2_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync2_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {rst_sync2_0:PLL_POWERDOWN_B}



# Add rst_sync3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {rst_sync3} -instance_name {rst_sync3_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync3_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync3_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {rst_sync3_0:PLL_POWERDOWN_B}



# Add rst_sync_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {rst_sync} -instance_name {rst_sync_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {rst_sync_0:FF_US_RESTORE} -value {GND}



# Add Transmit_PLL_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Transmit_PLL} -instance_name {Transmit_PLL_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transmit_PLL_0:PLL_LOCK}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync1_0:BANK_y_VDDI_STATUS" "rst_sync3_0:BANK_y_VDDI_STATUS" "rst_sync3_0:BANK_x_VDDI_STATUS" "rst_sync1_0:BANK_x_VDDI_STATUS" "BANK_x_VDDI_STATUS" "rst_sync2_0:BANK_x_VDDI_STATUS" "rst_sync2_0:BANK_y_VDDI_STATUS" "rst_sync_0:BANK_y_VDDI_STATUS" "rst_sync_0:BANK_x_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ccc_50_0:OUT0_FABCLK_0" "CORE_ABC_0:PCLK" "DRI_interface_0:PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PENABLE_M" "DRI_interface_0:PENABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PRESETN" "DRI_interface_0:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PSEL_M" "DRI_interface_0:PSEL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PWRITE_M" "DRI_interface_0:PWRITE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PREADY_M" "DRI_interface_0:PREADY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PSLVERR_M" "DRI_interface_0:PSLVERR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"error_o" "pattern_chk_0:error_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"error_o_0" "pattern_chk_even_0:error_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync1_0:FPGA_POR_N" "rst_sync3_0:FPGA_POR_N" "FPGA_POR_N" "rst_sync_0:FPGA_POR_N" "rst_sync2_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync3_0:INIT_DONE" "rst_sync1_0:INIT_DONE" "rst_sync2_0:INIT_DONE" "rst_sync_0:INIT_DONE" "INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:IO_IN[0]" "IO_IN_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:IO_IN[1]" "IO_IN_1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:IO_IN[2]" "IO_IN_2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync1_0:PLL_LOCK" "PF_XCVR_0_0:LANE0_RX_VAL" "LANE0_RX_VAL" "pattern_chk_even_0:rx_val_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RXD_N" "LANE0_RXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RXD_P" "LANE0_RXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TXD_N" "LANE0_TXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TXD_P" "LANE0_TXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_RXD_N" "LANE1_RXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_RXD_P" "LANE1_RXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_TXD_N" "LANE1_TXD_N_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_TXD_P" "LANE1_TXD_P_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"lock_o" "pattern_chk_0:lock_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"lock_o_0" "pattern_chk_even_0:lock_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE1_PCS_ARST_N" "PF_XCVR_0_0:CTRL_ARST_N" "CORE_ABC_0:NSYSRESET" "PCS_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "PF_XCVR_0_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync1_0:CLK" "PF_XCVR_0_0:LANE0_RX_CLK_R" "pattern_chk_even_0:clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_R" "rst_sync_0:CLK" "pattern_gen_0:clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_STABLE" "rst_sync_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync3_0:CLK" "PF_XCVR_0_0:LANE1_RX_CLK_R" "pattern_chk_0:clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync3_0:PLL_LOCK" "PF_XCVR_0_0:LANE1_RX_VAL" "pattern_chk_0:rx_val_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_even_0:clk_i" "PF_XCVR_0_0:LANE1_TX_CLK_R" "rst_sync2_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_TX_CLK_STABLE" "rst_sync2_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_PMA_ARST_N" "PF_XCVR_0_0:LANE1_PMA_ARST_N" "PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ccc_50_0:REF_CLK_0" "PF_CLK_DIV_C0_0:CLK_IN" "REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Reference_clock_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Reference_clock_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Transmit_PLL_0:REF_CLK" "Reference_clock_0:REF_CLK" "PF_XCVR_0_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_0_0:LANE1_CDR_REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync3_0:EXT_RST_N" "rst_sync1_0:EXT_RST_N" "rst_sync2_0:EXT_RST_N" "rst_sync_0:EXT_RST_N" "Reset_In" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync1_0:FABRIC_RESET_N" "pattern_chk_even_0:reset_n_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_even_0:reset_n_i" "rst_sync2_0:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync3_0:FABRIC_RESET_N" "pattern_chk_0:reset_n_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rst_sync_0:FABRIC_RESET_N" "pattern_gen_0:reset_n_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ccc_50_0:PLL_POWERDOWN_N_0" "rst_sync_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rx_val_o" "pattern_chk_0:rx_val_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rx_val_o_0" "pattern_chk_even_0:rx_val_o" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:IO_OUT" "DRI_interface_0:PADDR[28:20]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PADDR_M" "DRI_interface_0:PADDR[19:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PWDATA_M" "DRI_interface_0:PWDATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORE_ABC_0:PRDATA_M" "DRI_interface_0:PRDATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_0:data_out_o" "PF_XCVR_0_0:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_0:Tx_K_Char_o" "PF_XCVR_0_0:LANE0_8B10B_TX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_even_0:data_out_o" "PF_XCVR_0_0:LANE1_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"pattern_gen_even_0:Tx_K_Char_o" "PF_XCVR_0_0:LANE1_8B10B_TX_K" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_8B10B_RX_K" "pattern_chk_even_0:Rx_K_Char_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "pattern_chk_even_0:data_in_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_8B10B_RX_K" "pattern_chk_0:Rx_K_Char_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_RX_DATA" "pattern_chk_0:data_in_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_DRI_SLAVE" "DRI_interface_0:Q2_LANE2_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE1_DRI_SLAVE" "DRI_interface_0:Q2_LANE3_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Transmit_PLL_0:CLKS_TO_XCVR" "PF_XCVR_0_0:CLKS_FROM_TXPLL_0" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign XCVR_Top
generate_component -component_name ${sd_name}
