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//-------------------------------------------------------------------
// Title        : uSRAM64x12.v
// Created      : November-2017
// Description  : This module instantiated polarfire uSRAM blocks using RTL inference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- uSRAM_cascaded.v                 
//                    -- uSRAM64x12.v             <-- This module       
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module uSRAM64x12 #(parameter width = 18,
                              depth = 1024,
                              addr = 6)
                  (input[width - 1 : 0] Din,  // input data 
                   input CLK,                 // input clock
                   input WE,                  // write enable
                   input[addr - 1 : 0] WAddr, // write address
                   input[addr - 1 : 0] RAddr, // read address
                   output[width - 1 : 0] Dout // output data
                  )/* synthesis syn_preserve=1 */;//Attribute added to avoid pruning
  
  
  reg[width - 1 : 0] ramTmp[0 : depth - 1]/* synthesis syn_ramstyle="rw_check" */;
  reg[addr - 1 : 0] RAddr_Reg;
  always@(posedge CLK)
    begin
      RAddr_Reg <= RAddr;
      if (WE == 1'b1)
        ramTmp[WAddr] <= Din;
    end
  assign Dout = ramTmp[RAddr_Reg];
endmodule
