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//-------------------------------------------------------------------
// Title        : uSRAM_cascaded.v
// Created      : November-2017
// Description  : This module cascades uSRAM blocks based on user preference
// Hierarchy    :
//                
//                Top_Level
//                 -- Fabric_LSRAM_USRAM_MACC
//                  -- fabric_logic.v              
//                   -- uSRAM_cascaded.v		   <-- This module	
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------


module uSRAM_cascaded #(parameter WIDTH = 18, DEPTH = 64, ADDR = 6, NO_OF_STAGES = 10) 
(
input clk,                 // Input clock 
input rst_n,               // Reset for logic
input [WIDTH-1:0] DIN,     // Data input
output [WIDTH-1:0] DOUT    // Data output
)/* synthesis syn_noprune=1 syn_hier="fixed" */;

wire [WIDTH-1:0]   REG_ARRAY[0:NO_OF_STAGES-1];

reg WE;
reg [5:0] WA;
reg [5:0] RA;

//Logic for generating write enable and addresses
  always @(posedge clk)
   begin
    if(rst_n == 1'b1)
      begin
        WE <= 1'b1;
        WA <= 'd0;
        RA <= 'd0;
      end
    else
      begin
        WE <= WE + 1'b1;
        if(WE == 1'b1)
        WA <= WA+ 1'b1;
        else
        RA <= RA + 1'b1;
      end
  end

//Logic for cascading and instantiating uSRAM blocks
   generate
      begin : uSRAM_CASCADE
         genvar i;
         for (i = 0; i <= NO_OF_STAGES-1; i = i + 1)
         begin : uSRAM
            if (i == 0)
            begin : uSRAM0
         
               uSRAM64x12 #(.width(12), .depth(DEPTH), .addr(ADDR)) U1
                            (
                            .Din(DIN), 
                            .CLK(clk), 
                            .WE(WE),
                            .WAddr(WA), 
                            .RAddr(RA), 
                            .Dout(REG_ARRAY[0]));
            end
            if (i != 0)
            begin : SRAM1
               
               uSRAM64x12 #(.width(12), .depth(DEPTH), .addr(ADDR)) U1
                            (
                            .Din(REG_ARRAY[i-1]), 
                            .CLK(clk), 
                            .WE(WE),
                            .WAddr(WA), 
                            .RAddr(RA), 
                            .Dout(REG_ARRAY[i]));
            end
         end
      end
   endgenerate
assign DOUT = REG_ARRAY[NO_OF_STAGES-1];

endmodule

