# Import source files
import_files -hdl_source {./src/hdl/cnt_up.v}
import_files -hdl_source {./src/hdl/cnt_up_cascade.v}
import_files -hdl_source {./src/hdl/fabric_logic.v}
import_files -hdl_source {./src/hdl/Gate_control.v}
import_files -hdl_source {./src/hdl/lsram1kx18.v}
import_files -hdl_source {./src/hdl/LSRAM_cascaded.v}
import_files -hdl_source {./src/hdl/MACC_cascaded.v}
import_files -hdl_source {./src/hdl/mult18X18.v}
import_files -hdl_source {./src/hdl/pattern_chk.v}
import_files -hdl_source {./src/hdl/pattern_chk_even.v}
import_files -hdl_source {./src/hdl/pattern_gen.v}
import_files -hdl_source {./src/hdl/pattern_gen_even.v}
import_files -hdl_source {./src/hdl/ra_cnt.v}
import_files -hdl_source {./src/hdl/uSRAM64x18.v}
import_files -hdl_source {./src/hdl/uSRAM_cascaded.v}
import_files -hdl_source {./src/hdl/wa_cnt.v}
import_files -hdl_source {./src/hdl/we_ad_gen.v}


build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/ccc_50.tcl
source ./src/components/CCC_0.tcl
source ./src/components/CORE_ABC.tcl
source ./src/components/DRI_interface.tcl
source ./src/components/INIT_MONITOR.tcl
source ./src/components/OSC_clock_source.tcl
source ./src/components/PF_CLK_DIV_C0.tcl
source ./src/components/PF_XCVR_0.tcl
source ./src/components/Reference_clock.tcl
source ./src/components/reset_sync0.tcl
source ./src/components/reset_sync1.tcl
source ./src/components/reset_sync2.tcl
source ./src/components/reset_sync3.tcl
source ./src/components/rst_sync.tcl
source ./src/components/rst_sync1.tcl
source ./src/components/rst_sync2.tcl
source ./src/components/rst_sync3.tcl
source ./src/components/Transmit_PLL.tcl


# Generate SmartDesign Components
source ./src/components/PolarFire_Fabric.tcl
build_design_hierarchy 
source ./src/components/XCVR_Top.tcl
build_design_hierarchy 
source ./src/components/top.tcl
# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
