# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {DI} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FLASH} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_IN_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_IN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {IFACE} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_0} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {resetn} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {DO} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {UART_TX} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SS} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}


# Add CCC_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_0} -instance_name {CCC_0_0}



# Add COREJTAGDEBUG_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDEBUG_0} -instance_name {COREJTAGDEBUG_0_0}



# Add CoreReset_PF_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreReset_PF_0} -instance_name {CoreReset_PF_0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreReset_PF_0_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreReset_PF_0_0:FF_US_RESTORE} -value {GND}



# Add CORESPI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORESPI_C0} -instance_name {CORESPI_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[1:1]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[2:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[4:4]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[5:5]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[5:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[6:6]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[6:6]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CORESPI_C0_0:SPISS} -pin_slices {[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPISS[7:7]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPIINT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPIRXAVAIL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPITXRFM}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORESPI_C0_0:SPIMODE}



# Add MIV_ESS_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_C0} -instance_name {MIV_ESS_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[0:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_IN[0:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[1:1]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_IN[1:1]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[3:3]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_C0_0:GPIO_INT}



# Add MIV_RV32_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_C0} -instance_name {MIV_RV32_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:JTAG_TDO_DR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32_C0_0:EXT_IRQ} -value {GND}



# Add PF_INIT_MONITOR_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_INIT_MONITOR_0} -instance_name {PF_INIT_MONITOR_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_0_0:AUTOCALIB_DONE}



# Add PF_SPI_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {PF_SPI} -instance_name {PF_SPI_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SPI_0:FAB_SPI_OWNER}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SPI_0:CLK_OE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_SPI_0:SS_OE} -value {VCC}



# Add PF_SYSTEM_SERVICES_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SYSTEM_SERVICES_C0} -instance_name {PF_SYSTEM_SERVICES_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SYSTEM_SERVICES_C0_0:USR_CMD_ERROR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SYSTEM_SERVICES_C0_0:USR_BUSY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SYSTEM_SERVICES_C0_0:SS_BUSY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SYSTEM_SERVICES_C0_0:USR_RDVLD}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_SYSTEM_SERVICES_C0_0:SYSSERV_INIT_REQ}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:OUT0_FABCLK_0" "CORESPI_C0_0:PCLK" "CoreReset_PF_0_0:CLK" "MIV_ESS_C0_0:PCLK" "MIV_RV32_C0_0:CLK" "PF_SYSTEM_SERVICES_C0_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_LOCK_0" "CoreReset_PF_0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:PLL_POWERDOWN_N_0" "CoreReset_PF_0_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_0_0:REF_CLK_0" "REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK" "PF_SPI_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TGT_TCK_0" "MIV_RV32_C0_0:JTAG_TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TGT_TDI_0" "MIV_RV32_C0_0:JTAG_TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TGT_TDO_0" "MIV_RV32_C0_0:JTAG_TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TGT_TMS_0" "MIV_RV32_C0_0:JTAG_TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TGT_TRSTN_0" "MIV_RV32_C0_0:JTAG_TRSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:PRESETN" "CoreReset_PF_0_0:FABRIC_RESET_N" "MIV_ESS_C0_0:PRESETN" "MIV_RV32_C0_0:RESETN" "PF_SYSTEM_SERVICES_C0_0:RESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPICLKI" "PF_SPI_0:CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPIOEN" "PF_SPI_0:D_OE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPISCLKO" "PF_SPI_0:CLK_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPISDI" "PF_SPI_0:D_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPISDO" "PF_SPI_0:D_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPISSI" "PF_SPI_0:SS_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:SPISS[0:0]" "PF_SPI_0:SS_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_PF_0_0:BANK_x_VDDI_STATUS" "CoreReset_PF_0_0:BANK_y_VDDI_STATUS" "PF_INIT_MONITOR_0_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_PF_0_0:EXT_RST_N" "resetn" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_PF_0_0:FPGA_POR_N" "PF_INIT_MONITOR_0_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_PF_0_0:INIT_DONE" "PF_INIT_MONITOR_0_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DI" "PF_SPI_0:DI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DO" "PF_SPI_0:DO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FLASH" "PF_SPI_0:FLASH" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_IN" "MIV_ESS_C0_0:GPIO_IN[2:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_IN_0" "MIV_ESS_C0_0:GPIO_IN[3:3]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IFACE" "PF_SPI_0:IFACE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_RX" "UART_RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:UART_TX" "UART_TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SPI_0:SS" "SS" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "MIV_ESS_C0_0:GPIO_OUT" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORESPI_C0_0:APB_bif" "MIV_ESS_C0_0:APB_4_mTARGET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_0_mINITIATOR" "MIV_RV32_C0_0:APB_INITIATOR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_C0_0:APB_3_mTARGET" "PF_SYSTEM_SERVICES_C0_0:APBSlave" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
