# Import source files

file copy -force "./src/softconsole/application.hex" "./$Prjname/application.hex"

#build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CCC_0.tcl


source ./src/components/COREJTAGDEBUG_0.tcl
source ./src/components/CoreReset_PF_0.tcl
source ./src/components/CORESPI_C0.tcl
source ./src/components/PF_SYSTEM_SERVICES_C0.tcl

source ./src/components/MIV_RV32_C0.tcl
source ./src/components/MIV_ESS_C0.tcl
source ./src/components/PF_INIT_MONITOR_0.tcl



file copy -force "./src/hdl/miv_rv32_subsys_pkg.v" "./$Prjname/component/Microsemi/MiV/MIV_RV32/$MIV_RV32ver/pkg/miv_rv32_subsys_pkg.v"


#Downgrade the DRC check

smartdesign -memory_map_drc_change_error_to_warning true \


# Generate SmartDesign Components

build_design_hierarchy 
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
