
#check the boolean condition 
if { $FHB_ENABLE == 0 } {
  # # Import source files 
import_files -library work -hdl_source ./src/hdl/AXI_IF.v
import_files -library work -hdl_source ./src/hdl/CMD_Decoder.v
import_files -library work -hdl_source ./src/hdl/count_chk.v
import_files -library work -hdl_source ./src/hdl/count.v
import_files -library work -hdl_source ./src/hdl/match_data.v
import_files -library work -hdl_source ./src/hdl/uprom_chk.v
build_design_hierarchy
} else {
import_files -library work -hdl_source ./src/hdl/count_chk.v
import_files -library work -hdl_source ./src/hdl/count.v
import_files -library work -hdl_source ./src/hdl/match_data.v
import_files -library work -hdl_source ./src/hdl/uprom_chk.v
build_design_hierarchy
}


file copy -force "./src/softconsole/sram.hex" "./$Prjname/sram.hex"
file copy -force "./src/softconsole/uprom.mem" "./$Prjname/uprom.mem"


if { $FHB_ENABLE == 0 } {
source ./src/components/AXI_IF.tcl 
build_design_hierarchy
source ./src/components/DDR4_Splash.tcl 
source ./src/components/PF_RESET.tcl 
source ./src/components/DDR4_Interface.tcl 
source ./src/components/DPSRAM.tcl 
source ./src/components/Micro_ROM.tcl 
source ./src/components/URAM.tcl 
source ./src/components/Fabric_Debug.tcl 
source ./src/components/PF_CCC_0.tcl 
source ./src/components/PF_INIT_MON.tcl 
source ./src/components/SMARTBERT_XCVR_CHK.tcl 
source ./src/components/TX_PLL_XCVR_0.tcl 
source ./src/components/XCVR_REF_CLK_0.tcl 
source ./src/components/XCVR_Debug.tcl 
source ./src/components/reset_des_sync.tcl 
source ./src/components/top.tcl 
build_design_hierarchy 
 } else {

source ./src/components/DPSRAM.tcl 
source ./src/components/Micro_ROM.tcl 
source ./src/components/URAM.tcl 
source ./src/components/Fabric_Debug.tcl 
source ./src/components/PF_CCC_0.tcl 
source ./src/components/PF_INIT_MON.tcl 
source ./src/components/SMARTBERT_XCVR_CHK.tcl 
source ./src/components/TX_PLL_XCVR_0.tcl 
source ./src/components/XCVR_REF_CLK_0.tcl 
source ./src/components/XCVR_Debug.tcl 
source ./src/components/reset_des_sync.tcl 
source ./src/components/top.tcl 
build_design_hierarchy

}

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 
#set_option -synth 1 -fhb 1 -physynth 0 -module {top::work} 

set_option -synth 1 -fhb $FHB_ENABLE -physynth 0 -module {top::work} 

build_design_hierarchy 

save_project
puts "Design generated successfully\n"