///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: DDR_debug.v
// File history:
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//      <Revision number>: <Date>: <Comments>
//
// Description: 
//
// <Description here>
//
// Targeted device: <Family::PolarFire> <Die::MPF300TS> <Package::FCG1152>
// Author: <Name>
//
/////////////////////////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/100ps


`include "ddr4.sv"

module FAE_DDR4_Demo_tb;

parameter SYSCLK_PERIOD = 20000;// 50MHZ

wire SYSCLK;
reg REF_CLK;
reg NSYSRESET;

//
wire DDR4_CTRLR_READY;
wire ddr_rd_wrt_err;
//wire MEM_TEST_PASS;
wire INIT_DONE;
//DDR4 
wire        DDR4_ACT_N;
wire        DDR4_CAS_N;
wire        DDR4_CKE;
wire        DDR4_CK;
wire        DDR4_CK_N;
wire        DDR4_CS_N;
wire        DDR4_ODT;
wire        DDR4_RAS_N;
wire        DDR4_RESET_N;
wire        DDR4_WE_N;	
wire [13:0] DDR4_ADDR;
wire [1:0]  DDR4_BA;
wire  [1:0] DDR4_BG; //DDR4_BG

wire [3:0]  DDR40_DM_N;
wire [3:0]  DDR40_DQS;
wire [3:0]  DDR40_DQS_N;
wire [31:0] DDR40_DQ;
//
//wire [1:0]  DDR40_DM_N;
//wire [1:0]  DDR40_DQS;
//wire [1:0]  DDR40_DQS_N;
//wire [15:0] DDR40_DQ;
reg        READ;
reg        WRITE;
wire	   RBUSY;
wire 	   WBUSY;
reg  [31:0] READ_ADDRESS;
reg  [31:0] WRITE_ADDRESS;
reg  [63:0] DATA_IN;
wire [63:0] DATA_OUT;
reg  [3:0] WLEN,RLEN;
wire [3:0] DATA_BURST_NUM;
wire  	   Next_DATA_IN;
wire  	   transactions_complete;

initial
begin
    REF_CLK = 1'b0;
    NSYSRESET = 1'b0;
	WLEN = 4'b0001;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
		//Unclocked;
end


//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always @(REF_CLK)
    #(SYSCLK_PERIOD / 2.0) REF_CLK <= !REF_CLK;
	
	

DDR4_Interface DDR4_Interface_0 (
    // Inputs
    
    .REF_CLK_0(REF_CLK),
    .USER_RST_N(NSYSRESET),
    .INIT_DONE(1'b1),
    
    // Outputs
    .transactions_complete(transactions_complete),
    .CTRLR_READY_DDR4(DDR4_CTRLR_READY ),
    .PLL_LOCK_DDR4( ),
    .CKE(DDR4_CKE),
    .CS_N(DDR4_CS_N),
    .ODT(DDR4_ODT),
    .RAS_N(DDR4_RAS_N),
    .CAS_N(DDR4_CAS_N),
    .WE_N(DDR4_WE_N),
    .ACT_N(DDR4_ACT_N),
    .RESET_N(DDR4_RESET_N),
    .CK0(DDR4_CK),
    .CK0_N(DDR4_CK_N),
    .SHIELD0( ),
    .SHIELD1( ),
    .SHIELD2( ),
    .SHIELD3( ),
    .SYS_CLK(SYSCLK),
    .ddr_rd_wrt_err( ddr_rd_wrt_err),
    .DM_N(DDR40_DM_N ),
    .BG(DDR4_BG),
    .BA(DDR4_BA),
    .A(DDR4_ADDR),

    // Inouts
    .DQ( DDR40_DQ),
    .DQS(DDR40_DQS ),
    .DQS_N(DDR40_DQS_N )

);

// Instantiate DDR4 model
ddr4 ddr4_mem_0 (
	.model_enable(1'b1),
	.reset_n     (DDR4_RESET_N),
	.clk_p       (DDR4_CK),
	.clk_n       (DDR4_CK_N),	
	.cke         (DDR4_CKE),
	.cs_n        (DDR4_CS_N),
	.act_n       (DDR4_ACT_N),
	.ras_n       (DDR4_RAS_N ),
	.cas_n       (DDR4_CAS_N),
	.we_n        (DDR4_WE_N),
	.sa          (DDR4_ADDR),//[13:0]),
	.ba          (DDR4_BA),
    .bg          (DDR4_BG),
	.dm          (DDR40_DM_N[0]),
	.dq          (DDR40_DQ[7:0]),	
	.dqs         (DDR40_DQS[0]),
	.dqs_n       (DDR40_DQS_N[0]),
	.odt         (DDR4_ODT),	
    .ten         (),
    .sa17        (),
    .par_in      (),
    .mem_alert_n ()
);

ddr4 ddr4_mem_1 (
	.model_enable(1'b1),
	.reset_n     (DDR4_RESET_N),
	.clk_p       (DDR4_CK),
	.clk_n       (DDR4_CK_N),	
	.cke         (DDR4_CKE),
	.cs_n        (DDR4_CS_N),
	.act_n       (DDR4_ACT_N),
	.ras_n       (DDR4_RAS_N ),
	.cas_n       (DDR4_CAS_N),
	.we_n        (DDR4_WE_N),
	.sa          (DDR4_ADDR[13:0]),
	.ba          (DDR4_BA),
    .bg          (DDR4_BG),
	.dm          (DDR40_DM_N[1]),
	.dq          (DDR40_DQ[15:8]),	
	.dqs         (DDR40_DQS[1]),
	.dqs_n       (DDR40_DQS_N[1]),
	.odt         (DDR4_ODT),	
    .ten         (),
    .sa17        (),
    .par_in      (),
    .mem_alert_n ()
);

// Instantiate DDR4 model
ddr4 ddr4_mem_3 (
	.model_enable(1'b1),
	.reset_n     (DDR4_RESET_N),
	.clk_p       (DDR4_CK),
	.clk_n       (DDR4_CK_N),	
	.cke         (DDR4_CKE),
	.cs_n        (DDR4_CS_N),
	.act_n       (DDR4_ACT_N),
	.ras_n       (DDR4_RAS_N ),
	.cas_n       (DDR4_CAS_N),
	.we_n        (DDR4_WE_N),
	.sa          (DDR4_ADDR),//[13:0]),
	.ba          (DDR4_BA),
    .bg          (DDR4_BG),
	.dm          (DDR40_DM_N[2]),
	.dq          (DDR40_DQ[23:16]),	
	.dqs         (DDR40_DQS[2]),
	.dqs_n       (DDR40_DQS_N[2]),
	.odt         (DDR4_ODT),	
    .ten         (),
    .sa17        (),
    .par_in      (),
    .mem_alert_n ()
);

ddr4 ddr4_mem_4 (
	.model_enable(1'b1),
	.reset_n     (DDR4_RESET_N),
	.clk_p       (DDR4_CK),
	.clk_n       (DDR4_CK_N),	
	.cke         (DDR4_CKE),
	.cs_n        (DDR4_CS_N),
	.act_n       (DDR4_ACT_N),
	.ras_n       (DDR4_RAS_N ),
	.cas_n       (DDR4_CAS_N),
	.we_n        (DDR4_WE_N),
	.sa          (DDR4_ADDR[13:0]),
	.ba          (DDR4_BA),
    .bg          (DDR4_BG),
	.dm          (DDR40_DM_N[3]),
	.dq          (DDR40_DQ[31:24]),	
	.dqs         (DDR40_DQS[3]),
	.dqs_n       (DDR40_DQS_N[3]),
	.odt         (DDR4_ODT),	
    .ten         (),
    .sa17        (),
    .par_in      (),
    .mem_alert_n ()
);

////////////////////////////////////////////////////////////////////////
// $stop
////////////////////////////////////////////////////////////////////////
initial 
begin
  #12000000;
  $display("Timeout. Ending simulation.");
  $stop;
end

endmodule