################################################################################################################################################
# © 2024 Microchip Technology Inc. and its subsidiaries
# All rights reserved.
# ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
# ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
# IN ADVANCE IN WRITING
##################################################################################################################################################
# Title        : script.tcl
# Description  : This is the top-level script, which creates the FPGA HW Project. 
#                It invokes all the below TCLs which are required to complete the FPGA design flow.
#         	      -- 1_create_design.tcl: Executes all the required core configuration TCLs with necessary user HDL files to generate the design.
#		          -- 2_constrain_design.tcl: Applies all the necessary constraints for the design.
#		          -- 3_sim_flow.tcl: imports the test bench, other required simulation files and simulate the design.
#		          -- 4_implement_design.tcl : Runs synthesis, place & route, and verify timing design flow steps.
#        		  -- 5_program_design.tcl : Creates and exports the programming job file.              
####################################################################################################################################################

#Checking whether argument passed is valid for FHB_ENABLE
if { $::argc > 0 } {
	set i 1
	foreach arg $::argv {
		if {$arg == "FHB_ENABLE"} {
			set FHB_ENABLE 1
		    puts "FHB_ENABLED command line argument passed:-> FHB is ENABLED"	
		} else {
		    set FHB_ENABLE 0
		    puts "Wrong command line argument passed:-> FHB is DISABLED"
		}

		incr i
	}
} else {
	    puts "no command line argument passed:-> FHB is DISABLED"
	    set FHB_ENABLE 0
}
 
 
# Call common.tcl which contains required cores with the versions numbers to run the TCL scripts 
source ./common/common.tcl

# Set Project name
set Prjname "Libero_Project"

# Set Project Location
set PrjLocation "./$Prjname"

# Device-specific Variables
set die_eval {MPF300TS}
set eval_package {FCG1152}
set eval_part_range {IND}

#variable used in the design
set SimTime 10us
set Effort_Level true
set Repair_Min_Delay true
set Multi_Pass_Layout false

# A common procedure to compute the runtime for each command run in Libero.
# Get tool name from the command
proc run_tool_wrapper { cmd } {
  regexp {run_tool\s+-name\s+\{*(\w*)\}*} $cmd full1 tool;
  puts "Starting $tool command";
  set full_cmd "time \{ $cmd \}";
  set TIME_start [clock seconds];
  set runtime [ eval $full_cmd ];
  set TIME_taken [expr [clock seconds] - $TIME_start];
  puts "\nRUNTIME:$tool=$TIME_taken secs\n";
  set runtime_secs [ expr [lindex $runtime 0]/1000000 ];
  puts "\nRUNTIME_bytime:$tool=$runtime_secs secs\n";
}

# Remove existing project if present
file delete -force ${PrjLocation}

# Create and configure new project
new_project \
    -name "$Prjname" \
    -location "$PrjLocation" \
    -family "PolarFire" \
    -die $die_eval \
    -package $eval_package \
    -die_voltage "1.05" \
    -speed "-1" \
    -part_range $eval_part_range \
    -hdl "VERILOG"

puts "Project created successfully"
 
# Create design
source ./src/1_create_design.tcl

# Constrain design
source ./src/2_constrain_design.tcl

if { $FHB_ENABLE == 0 } {
 
	#Simulation flow
	source ./src/3_sim_flow.tcl

	# # Implement design
	source ./src/4_implement_design.tcl

 } else {
 
	# # Implement design
	source ./src/4_implement_design.tcl
 
 }
# # Program design
source ./src/5_program_design.tcl


#Close project
close_project -save 1