# Import source files
import_files -hdl_source {./src/hdl/binary_to_ascii_apb.v}
import_files -hdl_source {./src/hdl/counter.v}
import_files -hdl_source {./src/hdl/hex_to_ascii.v}


build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CoreAPB3_C0.tcl
source ./src/components/PF_CCC_C0.tcl
source ./src/components/COREABC_C0.tcl
source ./src/components/PF_INIT_MONITOR_C0.tcl
source ./src/components/CORERESET_PF_C1.tcl
source ./src/components/CORERESET_PF_C0.tcl
source ./src/components/PF_SYSTEM_SERVICES_C0.tcl
source ./src/components/PF_TAMPER_C0.tcl
source ./src/components/CoreUARTapb_C0.tcl



# Generate SmartDesign Components
source ./src/components/binary_to_ascii_apb.tcl
source ./src/components/top.tcl

# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
