//////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//Ã‚Â© 2022 Microchip Technology Inc. and its subsidiaries
//All rights reserved.
//ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//IN ADVANCE IN WRITING.
//-------------------------------------------------------------------------
//Title:<DRI_top_tb>
//Created:<June 2018>
//Description:stimulus file for top level module 
//Hierarchy Ã‚Â Ã‚Â :DRI_top_tb--DUT  -- Top_level 
//-------------------------------------------------------------------------

/////////////////////////////////////////////////////////////////////////////////////////////////// 

`timescale 1ns/100ps

module DRI_top_tb;

parameter SYSCLK_PERIOD = 8;// 125MHZ

// Defining the States 
parameter IDLE = 0,
          sw1p25G = 1,
          sw2p5G  = 2,
          sw5G    = 3,
          ccc_out01 = 4,
          ccc_out23 = 5;

reg SYSCLK;
reg NSYSRESET;
reg sw_1_25G;
reg sw_2_5G;
reg sw_5G;
reg sw_out0_out1;
reg sw_out2_out3;
reg [2:0] state;

wire loop_p;
wire loop_n;
wire RX_ready;
wire RX_valid;
wire TX_CLK_Stable;
wire CCC_OUT0;
wire CCC_OUT1;
wire CCC_OUT2;
wire CCC_OUT3;
wire XCVR_RX_CLK;
wire XCVR_TX_CLK;
wire [3:0] Status_LED;

initial
begin
    SYSCLK = 1'b0;
    NSYSRESET = 1'b0;
end

//////////////////////////////////////////////////////////////////////
// Reset Pulse
//////////////////////////////////////////////////////////////////////
initial
begin
    #(SYSCLK_PERIOD * 10 )
        NSYSRESET = 1'b1;
end


//////////////////////////////////////////////////////////////////////
// Clock Driver
//////////////////////////////////////////////////////////////////////
always @(SYSCLK)
    #(SYSCLK_PERIOD / 2.0) SYSCLK <= !SYSCLK;


//////////////////////////////////////////////////////////////////////
// Instantiate Unit Under Test:  Top_level
//////////////////////////////////////////////////////////////////////
top top_0 (
    // Inputs
    .LANE0_RXD_P            (loop_p),
    .LANE0_RXD_N            (loop_n),
    .Switch_1p25G          (sw_1_25G),
    .Switch_2p5G           (sw_2_5G),
    .Switch_5G             (sw_5G),
    .Switch_CCC_OUT0_OUT1   (sw_out0_out1),
    .Switch_CCC_OUT2_OUT3   (sw_out2_out3),
    .REF_CLK_PAD_P          (SYSCLK),
    .REF_CLK_PAD_N          (!SYSCLK),
    // Outputs
    .LANE0_TXD_P            (loop_p),
    .LANE0_TXD_N            (loop_n),
    .LANE0_RX_READY         (RX_ready),
    .LANE0_RX_VAL           (RX_valid),   
    .LANE0_TX_CLK_STABLE    (TX_CLK_Stable),
    .OUT0_FABCLK_0          (CCC_OUT0),
    .OUT1_FABCLK_0          (CCC_OUT1),
    .OUT2_FABCLK_0          (CCC_OUT2),
    .OUT3_FABCLK_0          (CCC_OUT3),
    .RX_CLK_R               (XCVR_RX_CLK),
    .TX_CLK_R               (XCVR_TX_CLK),
    .status                 (Status_LED)

);


//////////////////////////////////////////////////////////////////////
// State Machine Logic - used to generate the Test vectors to 
// reconfigure the XCVR in 1.25G, 2.5G, 5G and reconfigure CCC 
//////////////////////////////////////////////////////////////////////
always @ (posedge SYSCLK or negedge NSYSRESET) begin
    if (!NSYSRESET)begin
        state <= IDLE;
        sw_1_25G <= 1'b0;
        sw_2_5G <= 1'b0;
        sw_5G <= 1'b0;
        sw_out0_out1 <= 1'b0;
        sw_out2_out3 <= 1'b0;
    end
    else begin
        case (state) 
            IDLE :  begin
                        if(RX_valid)
                            state <= sw1p25G;
                        else
                            state <= IDLE;
                    end
            sw1p25G : begin
                       if(RX_valid) begin
                        #10000
                        sw_1_25G <= 1'b1;
                        #2000
                        sw_1_25G <= 1'b0;
                        state <= sw2p5G;
                       end
                       else
                            state <= sw1p25G;
                     end
            sw2p5G : begin
                        if (RX_valid) begin
                        #10000;
                        sw_2_5G <= 1'b1;
                        #2000
                        sw_2_5G <= 1'b0;
                        state <= sw5G;
                        end
                        else 
                            state <= sw2p5G;
                     end
            sw5G : begin
                        if (RX_valid) begin
                        #10000;
                        sw_5G <= 1'b1;
                        #2000
                        sw_5G <= 1'b0;
						#4500
                        state <=  ccc_out01;
                        end
                        else 
                            state <= sw5G;
                     end

            ccc_out01 : begin
                        if (top_0.CCC_Dyn_0.PLL_LOCK_0 == 1'b1) begin
                        #10000;
                        sw_out0_out1 <= 1'b1;
                        #2000
                        sw_out0_out1 <= 1'b0;
                        state <= ccc_out23;
                        end
                        else 
                            state <= ccc_out01;
                     end
            
            ccc_out23 : begin
                        if (top_0.CCC_Dyn_0.PLL_LOCK_0 == 1'b1) begin
                        #5000;
                        sw_out2_out3 <= 1'b1;
                        #2000
                        sw_5G <= 1'b0;
                        sw_out2_out3 <= IDLE;
                        end
                        else 
                            state <= ccc_out23;
                     end
            

            default : begin
                            state <= IDLE;
                        end 
        endcase 
    end
end

//Checking test pass signal stop the simulation
always @(posedge SYSCLK) 
begin
if(!NSYSRESET) begin
$display (" design is in Reset");
end 
else begin 
if(sw_out2_out3) begin
$display (" test completed succesfully");
$finish;
end
end
end 
endmodule

