///////////////////////////////////////////////////////////////////////////////
//-------------------------------------------------------------------------
//© 2022 Microchip Technology Inc. and its subsidiaries
//All rights reserved.
//ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
//ACCORDANCE WITH THE MICROCHIP LICENSE AGREEMENT AND MUST BE APPROVED
//IN ADVANCE IN WRITING.
//-------------------------------------------------------------------------
//Title:<RATE_STATUS>
//Created:<June 2018>
//Description:This module implements LED status as per the Rates selected for XCVR and CCC.
//Hierarchy:Top_level --- Rate_status.v <--- This module
//-------------------------------------------------------------------------

//******************************************************************************
//**************************** Module Declaration ******************************
//******************************************************************************
module RATE_STATUS(input CLK, // Input Clock
                   input NRESETN, // Input Active Low reset
                   input RX_valid, // Transceiver RX Valid 
                   input switch_1_25_G, // Switch for selecting 1.25G XCVR rate 
                   input switch_2_5_G, // Switch for selecting 2.5G XCVR rate 
                   input switch_5_G, // Switch for selecting 5G XCVR rate 
                   input switch_ccc_Out0_Out1, // Switch for changing frequencies of OUT0 and OUT1 of CCC 
                   input switch_ccc_Out2_Out3, // Switch for changing frequencies of OUT2 and OUT3 of CCC
                   output[3 : 0] status // Output LED's Displaying the status 
                  );
reg[3 : 0] status_r;
wire reset_sync_n;                         // internally generated reset
reg [1:0] reset_sync_reg;                  // reset synchronizer
reg  RX_valid_1,RX_valid_2;                // registering valid signal

//reset synchronizer block
always@ (posedge CLK or negedge NRESETN)
begin
  if(!NRESETN)
  begin
    reset_sync_reg [1:0] <= 2'b0;
  end

  else
  begin
    reset_sync_reg[1:0] <= {reset_sync_reg [0], 1'b1};
  end

end

assign reset_sync_n = reset_sync_reg [1];

//registering valid signal
always@(posedge CLK or negedge reset_sync_n)
 begin
  if (reset_sync_n == 1'b0)
  begin
  RX_valid_1 <= 1'b0;
  RX_valid_2 <= 1'b0;
  end
  else
  begin
  RX_valid_1 <= RX_valid;
  RX_valid_2 <= RX_valid_1;
  end
end

  //******************************************************************************
  //************** Logic for selecting the LED's as per Rate Change **************
  //****************************************************************************** 
  always
    @(posedge CLK or
      negedge reset_sync_n)
    begin
      if (reset_sync_n == 1'b0)
        begin
          status_r <= 4'b0000;
        end
      else
        if (RX_valid_2)
          begin
            if (switch_1_25_G)
              status_r <= 4'b0001;
            else
              if (switch_2_5_G)
                status_r <= 4'b0010;
              else
                if (switch_5_G)
                  status_r <= 4'b0100;
                else
                  if (switch_ccc_Out0_Out1)
                    status_r <= 4'b1100;
                  else
                    if (switch_ccc_Out2_Out3)
                      status_r <= 4'b0011;
          end
    end
  assign status = status_r;
endmodule
