# Import source files
import_files -hdl_source {./src/hdl/RATE_STATUS.v}



build_design_hierarchy 

# Create, configure and generate core components
source ./src/components/CCC_50.tcl
source ./src/components/CCC_Dyn.tcl
source ./src/components/CORERESET_PF.tcl
source ./src/components/INIT_MONITOR.tcl
source ./src/components/OSC_160.tcl
source ./src/components/reconfiguration_controller.tcl
source ./src/components/Soft_Processor.tcl
source ./src/components/Transceiver.tcl
source ./src/components/Transmit_PLL_XCVR.tcl
source ./src/components/XCVR_REF_CLK.tcl






# Generate SmartDesign Components
build_design_hierarchy 
source ./src/components/top.tcl
# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
