# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Switch_1p25G} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Switch_2p5G} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Switch_5G} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Switch_CCC_OUT0_OUT1} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {Switch_CCC_OUT2_OUT3} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_VAL} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TX_CLK_STABLE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT0_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT1_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT2_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT3_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX_CLK_R} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX_CLK_R} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {status} -port_direction {OUT} -port_range {[3:0]}


# Add BUFD_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BUFD} -instance_name {BUFD_0}



# Add BUFD_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BUFD} -instance_name {BUFD_1}



# Add CCC_50_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_50} -instance_name {CCC_50_0}



# Add CCC_Dyn_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CCC_Dyn} -instance_name {CCC_Dyn_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CCC_Dyn_0:PLL_LOCK_0}



# Add CoreReset_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreReset} -instance_name {CoreReset_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreReset_0:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreReset_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreReset_0:FF_US_RESTORE} -value {GND}



# Add INIT_MONITOR_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_MONITOR} -instance_name {INIT_MONITOR_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:AUTOCALIB_DONE}



# Add OSC_160_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {OSC_160} -instance_name {OSC_160_0}



# Add RATE_STATUS_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {RATE_STATUS} -hdl_file {hdl\RATE_STATUS.v} -instance_name {RATE_STATUS_0}



# Add reconfiguration_controller_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reconfiguration_controller} -instance_name {reconfiguration_controller_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {reconfiguration_controller_0:PADDR} -pin_slices {[19:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {reconfiguration_controller_0:PADDR} -pin_slices {[28:20]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PADDR}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PSEL}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PENABLE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PWRITE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PRDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PWDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PREADY}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {reconfiguration_controller_0:APBS} -pin_names {reconfiguration_controller_0:PSLVERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {reconfiguration_controller_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {reconfiguration_controller_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {reconfiguration_controller_0:BUSERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reconfiguration_controller_0:PSTRB} -value {VCC}



# Add Soft_Processor_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Soft_Processor} -instance_name {Soft_Processor_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Soft_Processor_0:IO_IN} -pin_slices {[0:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Soft_Processor_0:IO_IN} -pin_slices {[1:1]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Soft_Processor_0:IO_IN} -pin_slices {[2:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Soft_Processor_0:IO_IN} -pin_slices {[3:3]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Soft_Processor_0:IO_IN} -pin_slices {[4:4]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PADDR_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PSEL_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PENABLE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PWRITE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PRDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PWDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PREADY_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {Soft_Processor_0:APB3Initiator} -pin_names {Soft_Processor_0:PSLVERR_M}



# Add Transceiver_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Transceiver} -instance_name {Transceiver_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_RX_IDLE}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_TX_DATA} -value {00000000000000000000000010111100}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_RX_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_RX_CODE_VIOLATION}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_RX_DISPARITY_ERROR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_8B10B_RX_K}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_TX_DISPFNC} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Transceiver_0:LANE0_8B10B_TX_K} -value {0001}



# Add Transmit_PLL_XCVR_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Transmit_PLL_XCVR} -instance_name {Transmit_PLL_XCVR_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transmit_PLL_XCVR_0:PLL_LOCK}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Transmit_PLL_XCVR_0:CLK_125}



# Add XCVR_REF_Clock_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {XCVR_REF_Clock} -instance_name {XCVR_REF_Clock_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BUFD_0:A" "RATE_STATUS_0:CLK" "Transceiver_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BUFD_0:Y" "RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BUFD_1:A" "Transceiver_0:LANE0_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BUFD_1:Y" "TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_50_0:OUT0_FABCLK_0" "CoreReset_0:CLK" "Soft_Processor_0:PCLK" "reconfiguration_controller_0:PCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_50_0:PLL_LOCK_0" "CoreReset_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_50_0:PLL_POWERDOWN_N_0" "CCC_Dyn_0:PLL_POWERDOWN_N_0" "CoreReset_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_50_0:REF_CLK_0" "CCC_Dyn_0:REF_CLK_0" "OSC_160_0:RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_Dyn_0:OUT0_FABCLK_0" "OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_Dyn_0:OUT1_FABCLK_0" "OUT1_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_Dyn_0:OUT2_FABCLK_0" "OUT2_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_Dyn_0:OUT3_FABCLK_0" "OUT3_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_0:BANK_x_VDDI_STATUS" "CoreReset_0:BANK_y_VDDI_STATUS" "INIT_MONITOR_0:BANK_6_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_0:FABRIC_RESET_N" "RATE_STATUS_0:NRESETN" "Soft_Processor_0:NSYSRESET" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_0:FPGA_POR_N" "INIT_MONITOR_0:FABRIC_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreReset_0:INIT_DONE" "INIT_MONITOR_0:DEVICE_INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR_0:XCVR_INIT_DONE" "Transceiver_0:LANE0_PCS_ARST_N" "Transceiver_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "Transceiver_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "Transceiver_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RX_READY" "Transceiver_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RX_VAL" "RATE_STATUS_0:RX_valid" "Transceiver_0:LANE0_RX_VAL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "Transceiver_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "Transceiver_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TX_CLK_STABLE" "Transceiver_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:switch_1_25_G" "Soft_Processor_0:IO_IN[0:0]" "Switch_1p25G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:switch_2_5_G" "Soft_Processor_0:IO_IN[1:1]" "Switch_2p5G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:switch_5_G" "Soft_Processor_0:IO_IN[2:2]" "Switch_5G" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:switch_ccc_Out0_Out1" "Soft_Processor_0:IO_IN[3:3]" "Switch_CCC_OUT0_OUT1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:switch_ccc_Out2_Out3" "Soft_Processor_0:IO_IN[4:4]" "Switch_CCC_OUT2_OUT3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "XCVR_REF_Clock_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "XCVR_REF_Clock_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PENABLE_M" "reconfiguration_controller_0:PENABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PREADY_M" "reconfiguration_controller_0:PREADY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PRESETN" "reconfiguration_controller_0:PRESETN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PSEL_M" "reconfiguration_controller_0:PSEL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PSLVERR_M" "reconfiguration_controller_0:PSLVERR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PWRITE_M" "reconfiguration_controller_0:PWRITE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Transceiver_0:LANE0_CDR_REF_CLK_0" "Transmit_PLL_XCVR_0:REF_CLK" "XCVR_REF_Clock_0:REF_CLK" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"RATE_STATUS_0:status" "status" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:IO_OUT" "reconfiguration_controller_0:PADDR[28:20]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PADDR_M" "reconfiguration_controller_0:PADDR[19:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PRDATA_M" "reconfiguration_controller_0:PRDATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Soft_Processor_0:PWDATA_M" "reconfiguration_controller_0:PWDATA" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CCC_Dyn_0:PLL0_DRI" "reconfiguration_controller_0:PLL0_NW_DRI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Transceiver_0:CLKS_FROM_TXPLL_0" "Transmit_PLL_XCVR_0:CLKS_TO_XCVR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Transceiver_0:LANE0_DRI_SLAVE" "reconfiguration_controller_0:Q2_LANE0_DRI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
