   1              		.file	"main.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0_c2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.comm	MRV_LOCAL_IRQn_Type,4,4
  10              		.section	.text.MRV_enable_local_irq,"ax",@progbits
  11              		.align	1
  13              	MRV_enable_local_irq:
  14              	.LFB12:
  15              		.file 1 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
   1:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
   6:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  10:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  11:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  12:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*=========================================================================*//**
  13:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  15:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  16:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Introduction
  17:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  18:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  25:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  30:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  35:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  39:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  40:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  42:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, see
  43:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-tools/m
  44:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  45:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Core and this document use the following terms:
  46:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  48:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  58:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  59:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  61:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32 preprocessor, macros have been
  62:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted. The HAL is used
  63:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   to target the mentioned platforms by adding the following macros in Project
  64:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Properties > C/C++ Build > Settings > Preprocessor available in the Assembler
  65:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and Compiler settings. The following table shows the macros corresponding to the
  66:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV Core being used in your libero project. By default, the HAL targets v3.1 of
  67:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the IP core and no macros need to be set for this configutation.
  68:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  69:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  70:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-----------------------------|-------------------|
  71:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  72:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  73:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  74:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  75:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  76:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt Handling
  77:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  78:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  79:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  80:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
  81:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  82:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  83:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  84:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  85:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  86:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  87:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  88:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  89:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  90:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  91:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  92:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  93:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  94:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  95:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  96:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  97:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
  98:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
  99:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 100:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 101:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 102:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 103:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 104:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 105:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 106:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 107:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 108:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 109:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 110:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 111:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 112:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 113:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 114:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the value stored in the 
 115:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 116:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handler is as an interrupt service routine.
 117:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 118:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 119:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 120:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 121:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 122:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 123:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 124:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 125:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 126:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32.
 127:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 128:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 129:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 130:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 131:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 132:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 133:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 134:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 135:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 136:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 137:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 138:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 139:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 140:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 141:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 142:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 143:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   unchanged.
 144:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 145:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 146:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Floating Point Interrupt Support
 147:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 148:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 149:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 150:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 151:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Softconsole build settings.
 152:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 153:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   when the ISR does not use FP insturctions and saving the general purpose 
 154:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   register context is sufficient.
 155:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 156:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 157:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 158:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 159:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 160:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 161:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 162:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 163:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 164:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. Refer to the MIV_RV32 v3.1 Handbook for
 165:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   more details.  
 166:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   NOTE: This was previously (MIV_RV32 v3.0) known as OPSRV, which stands for 
 167:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   "Offload Processor Subsystem for RISC-V". See the earlier versions of the 
 168:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook for more details. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 169:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 170:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *//*=========================================================================*/
 171:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 172:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
 173:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 174:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 175:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 176:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 177:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 178:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 179:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 180:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "../../boards/polarfire-video-kit/fpga_design_config/fpga_design_config.h"
 181:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 182:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
 183:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 184:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 185:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
 186:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
 187:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 188:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 189:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 190:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 191:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 192:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 193:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 194:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 195:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 196:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 197:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------------|--------------------------|
 198:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 199:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 200:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 201:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 202:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 203:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 204:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 205:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 206:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 207:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 208:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 209:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 210:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 211:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 212:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine timer interrupt
 213:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 214:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 215:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 216:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 217:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 218:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 219:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME and MTIMECMP
 220:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 221:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 222:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 223:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   possible combinations:
 224:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 225:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 226:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 227:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 228:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 229:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 230:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 231:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 232:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 233:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 234:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 235:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 236:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   core as input.
 237:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 238:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 239:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 240:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 241:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt.
 242:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 243:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 244:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 245:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core design.
 246:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 247:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 248:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 249:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 250:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 251:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 252:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   available internally to the core.
 253:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 254:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 255:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 256:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 257:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 258:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 259:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 260:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 261:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 262:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 263:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 264:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 265:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 266:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 267:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 268:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 269:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 270:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 271:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 272:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 273:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 274:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External IRQ
 275:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 276:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 277:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External Interrupt.
 278:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 279:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 280:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 281:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 282:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 283:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 284:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 285:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 286:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 287:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
 288:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 289:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 290:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 291:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 292:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 293:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 294:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 295:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 296:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 297:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 298:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 299:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 300:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 301:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 302:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 303:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 304:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 305:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 306:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 307:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 308:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 309:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 310:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 311:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 312:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 313:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 314:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 315:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 316:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 317:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIMPID Register
 318:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 319:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 320:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 321:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 322:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 323:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 324:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 325:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 326:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 327:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP core version.
 328:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 329:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 330:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 331:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 332:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 333:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 334:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 335:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 336:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 337:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 338:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 339:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 340:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 341:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 342:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 343:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 344:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 345:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   RISC-V Specification Interrupts
 346:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 347:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 348:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   in the MIE/MIP registers.
 349:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 350:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 351:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 352:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
 353:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, following table shows the 
 354:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt priority order and register description as mentioned in the RISC-V spec.
 355:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 356:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 357:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 358:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 359:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 360:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 361:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 362:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 363:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 364:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 365:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 366:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 367:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 368:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM
 369:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =================================
 370:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When BootROM is enabled, on reset, the core copies data from a memory mapped
 371:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   source memory into a destination memory location and then the core boots from
 372:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the destination memory location. The source start or end addresses and the
 373:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination start address can be provided through GUI inputs. If the 
 374:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reconfigurable option is enabled, then the addresses become software 
 375:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   reconfigurable, which can be used with a soft reset to reboot and run alternative
 376:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   code. The source and destination memory must be a memory mapped location 
 377:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   accessible by the core across the full transfer size.
 378:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 379:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTVEC address - By default, the mtvec.BASE is set at Reset Vector Address + 0x04.
 380:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When the BootROM is enabled, the mtvec.BASE is set at destination address + 0x04.
 381:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When using Reconfigurable BootROM, the MTVEC register needs to be defined 
 382:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and programmed through software.
 383:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 384:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reset Behaviour - With the BootROM feature enabled, upon reset, the PC takes on
 385:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the value of the BootROM dest_addr. When the BootROM is enabled, ensure that the
 386:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   boot code linker script matches the dest_addr, since booting starts from the
 387:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination_addr.
 388:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 389:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM Register Map:
 390:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Name  |  Address  | Description |
 391:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------|-----------|-------------|
 392:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_start_addr     |0xA100| Core copies data beginning here       |
 393:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_end_addr       |0xA104| Last address copied by BootROM        |
 394:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | destination_addr   |0xA108| Destination memory beginning from here|
 395:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 396:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** */
 397:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 398:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_START                    0x0000A100
 399:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_END                      0x0000A104
 400:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_DEST                     0x0000A108
 401:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 402:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 403:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt numbers:
 404:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 405:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 406:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 407:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 408:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 409:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 410:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 411:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 412:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 413:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 414:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 415:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 416:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 417:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 418:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 419:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 420:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 421:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 422:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 423:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 424:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 425:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 426:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 427:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 428:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 429:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 430:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 431:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 432:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 433:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 434:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 435:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 436:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 437:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 438:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 439:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 440:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 441:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 442:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 443:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 444:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 445:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 446:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 447:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 448:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 449:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 450:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 451:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 452:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 453:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 454:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 455:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 456:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 457:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 458:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 459:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 460:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 461:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 462:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 463:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 464:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 465:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 466:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 467:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 468:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 469:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 470:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 471:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 472:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 473:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 474:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 475:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 476:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   */
 477:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 478:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 479:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 480:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 481:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 482:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 483:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 484:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 485:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 486:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 487:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 488:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 489:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 490:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 491:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 492:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 493:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 494:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 495:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 496:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 497:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 498:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 499:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 500:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 501:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 502:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 503:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 504:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 505:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 506:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 507:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 508:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 509:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 510:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 511:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 512:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 513:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 514:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 515:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 516:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 517:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 518:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 519:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 520:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 521:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 522:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 523:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 524:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 525:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 526:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 527:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 528:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 529:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 530:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 531:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 532:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 533:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 534:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 535:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 536:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 537:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 538:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 539:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 540:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 541:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 542:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 543:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 544:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 545:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 546:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 547:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 548:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 549:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 550:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 551:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 552:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 553:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 554:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 555:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 556:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 557:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 558:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 559:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 560:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 561:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 562:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 563:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 564:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 565:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 566:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 567:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 568:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 569:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 570:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 571:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 572:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 573:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 574:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 575:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 576:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 577:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 578:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 579:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 580:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 581:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 582:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 583:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 584:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 585:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 586:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   IP configurator.
 587:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 588:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 589:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 590:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 591:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 592:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 593:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 594:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 595:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 596:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 597:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 598:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 599:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
 600:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 601:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return 
 602:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 603:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 604:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 605:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 606:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 607:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 608:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 609:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 610:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 611:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 612:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 613:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 614:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 615:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 616:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 617:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 618:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 619:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
  16              		.loc 1 619 1
  17              		.cfi_startproc
  18 0000 7971     		addi	sp,sp,-48
  19              		.cfi_def_cfa_offset 48
  20 0002 22D6     		sw	s0,44(sp)
  21              		.cfi_offset 8, -4
  22 0004 0018     		addi	s0,sp,48
  23              		.cfi_def_cfa 8, 0
  24 0006 232EA4FC 		sw	a0,-36(s0)
  25              	.LBB2:
 620:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
  26              		.loc 1 620 5
  27 000a 8327C4FD 		lw	a5,-36(s0)
  28              	 #APP
  29              	# 620 "C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p
   0              	
  30              		csrrs a5, mie, a5
  31              	# 0 "" 2
  32              	 #NO_APP
  33 0012 2326F4FE 		sw	a5,-20(s0)
  34              	.LBE2:
 621:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
  35              		.loc 1 621 1
  36 0016 0100     		nop
  37 0018 3254     		lw	s0,44(sp)
  38              		.cfi_restore 8
  39              		.cfi_def_cfa 2, 48
  40 001a 4561     		addi	sp,sp,48
  41              		.cfi_def_cfa_offset 0
  42 001c 8280     		jr	ra
  43              		.cfi_endproc
  44              	.LFE12:
  46              		.comm	g_10ms_count,4,4
  47              		.globl	timerdone
  48              		.section	.sbss.timerdone,"aw",@nobits
  49              		.align	2
  52              	timerdone:
  53 0000 00000000 		.zero	4
  54              		.comm	g_10ms_count1,4,4
  55              		.comm	g_ms_count,4,4
  56              		.comm	g_i2c_instance_cam1,108,4
  57              		.globl	uart_rx_buff
  58              		.section	.bss.uart_rx_buff,"aw",@nobits
  59              		.align	2
  62              	uart_rx_buff:
  63 0000 00000000 		.zero	23
  63      00000000 
  63      00000000 
  63      00000000 
  63      00000000 
  64              		.comm	g_uart,8,4
  65              		.comm	bayer,2,2
  66              		.section	.sdata.in_gain,"aw"
  67              		.align	1
  70              	in_gain:
  71 0000 5000     		.half	80
  72              		.comm	g_gpio_out,8,4
  73              		.globl	g_state
  74              		.section	.sdata.g_state,"aw"
  75              		.align	2
  78              	g_state:
  79 0000 01000000 		.word	1
  80              		.globl	rx_tmr_done
  81              		.section	.sbss.rx_tmr_done,"aw",@nobits
  82              		.align	2
  85              	rx_tmr_done:
  86 0000 00000000 		.zero	4
  87              		.comm	rx_ms_count1,4,4
  88              		.comm	rx_ms_count,4,4
  89              		.globl	t_ms_count
  90              		.section	.sbss.t_ms_count,"aw",@nobits
  91              		.align	2
  94              	t_ms_count:
  95 0000 00000000 		.zero	4
  96              		.globl	R_constant
  97              		.section	.sdata.R_constant,"aw"
  98              		.align	2
 101              	R_constant:
 102 0000 92000000 		.word	146
 103              		.globl	G_constant
 104              		.section	.sdata.G_constant,"aw"
 105              		.align	2
 108              	G_constant:
 109 0000 7A000000 		.word	122
 110              		.globl	B_constant
 111              		.section	.sdata.B_constant,"aw"
 112              		.align	2
 115              	B_constant:
 116 0000 A5000000 		.word	165
 117              		.globl	second_constant
 118              		.section	.sbss.second_constant,"aw",@nobits
 119              		.align	2
 122              	second_constant:
 123 0000 00000000 		.zero	4
 124              		.globl	i
 125              		.section	.sbss.i,"aw",@nobits
 126              		.align	2
 129              	i:
 130 0000 00000000 		.zero	4
 131              		.globl	process_data
 132              		.section	.sbss.process_data,"aw",@nobits
 133              		.align	2
 136              	process_data:
 137 0000 00000000 		.zero	4
 138              		.section	.text.SysTick_Handler,"ax",@progbits
 139              		.align	1
 140              		.globl	SysTick_Handler
 142              	SysTick_Handler:
 143              	.LFB21:
 144              		.file 2 "../src/application/main.c"
   1:../src/application/main.c **** /*******************************************************************************
   2:../src/application/main.c ****  * (c) Copyright 2016-2017 Microsemi SoC Products Group. All rights reserved.
   3:../src/application/main.c ****  * 
   4:../src/application/main.c ****  * This SoftConsole Video project for MIPI sensor configuration and interfacing with GUI
   5:../src/application/main.c ****  *
   6:../src/application/main.c ****  * Please refer README.TXT in the root folder of this project for more details.
   7:../src/application/main.c ****  */
   8:../src/application/main.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
   9:../src/application/main.c **** #include "drivers/fpga_ip/CoreGPIO/core_gpio.h"
  10:../src/application/main.c **** #include "drivers/fpga_ip/CoreUARTAPB/core_uart_apb.h"
  11:../src/application/main.c **** #include "drivers/fpga_ip/CoreI2C/core_i2c.h"
  12:../src/application/main.c **** #include "drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.h"
  13:../src/application/main.c **** #include "imx334_corei2c/imx334_corei2c.h"
  14:../src/application/main.c **** #include "hdmi_config/hdmi_tx.h"
  15:../src/application/main.c **** #include "dp_cmd_common.h"
  16:../src/application/main.c **** #include "dp_cmd_tx.h"
  17:../src/application/main.c **** #include "dp_cmd_common.h"
  18:../src/application/main.c **** #include "dp_cmd_tx_regs.h"
  19:../src/application/main.c **** #include "dp_cmd_tx.h"
  20:../src/application/main.c **** /* Camera configuration (Data rate, resolution) and pattern generator
  21:../src/application/main.c ****  * can be selected in imx334_corei2c.h file.
  22:../src/application/main.c ****  * */
  23:../src/application/main.c **** 
  24:../src/application/main.c **** #define LED1 GPIO_0
  25:../src/application/main.c **** #define LED2 GPIO_1
  26:../src/application/main.c **** #define LED3 GPIO_2
  27:../src/application/main.c **** #define LED4 GPIO_3
  28:../src/application/main.c **** 
  29:../src/application/main.c **** #define MIPI_TRNG_RST GPIO_4
  30:../src/application/main.c **** 
  31:../src/application/main.c **** 
  32:../src/application/main.c **** // Bayer Configuration
  33:../src/application/main.c **** #define BAYER_ADDR                0x72020000
  34:../src/application/main.c **** 
  35:../src/application/main.c **** // Display Controller Configuration
  36:../src/application/main.c **** #define DC_IP_VER                 0x72040000
  37:../src/application/main.c **** #define DC_IP_EN_DIS              0x72040004
  38:../src/application/main.c **** #define DC_IP_HRES                0x72040008
  39:../src/application/main.c **** #define DC_IP_VRES                0x7204000C
  40:../src/application/main.c **** #define DC_IP_HFP                 0x72040010
  41:../src/application/main.c **** #define DC_IP_HBP                 0x72040014
  42:../src/application/main.c **** #define DC_IP_VFP                 0x72040018
  43:../src/application/main.c **** #define DC_IP_VBP                 0x7204001C
  44:../src/application/main.c **** #define DC_IP_HSW                 0x72040020
  45:../src/application/main.c **** #define DC_IP_VSW                 0x72040024
  46:../src/application/main.c **** 
  47:../src/application/main.c **** // Image Enhancment Configuration
  48:../src/application/main.c **** #define IE_IP_VER                 0x72030000
  49:../src/application/main.c **** #define IE_IP_EN_DIS              0x72030004
  50:../src/application/main.c **** #define IE_R_CONST                0x72030008
  51:../src/application/main.c **** #define IE_G_CONST                0x7203000C
  52:../src/application/main.c **** #define IE_B_CONST                0x72030010
  53:../src/application/main.c **** #define IE_COMMON_CONST           0x72030014
  54:../src/application/main.c **** #define IE_INTENSITY_AVARAGE      0x72030018
  55:../src/application/main.c **** 
  56:../src/application/main.c **** 
  57:../src/application/main.c **** volatile uint32_t g_10ms_count;
  58:../src/application/main.c **** 
  59:../src/application/main.c **** volatile uint32_t timerdone = 0;
  60:../src/application/main.c **** volatile uint32_t g_10ms_count1;
  61:../src/application/main.c **** volatile uint32_t g_ms_count;
  62:../src/application/main.c **** static void gui_handler(void);
  63:../src/application/main.c **** i2c_instance_t g_i2c_instance_cam1;
  64:../src/application/main.c **** uint8_t uart_rx_buff[23]={0};
  65:../src/application/main.c **** UART_instance_t g_uart;
  66:../src/application/main.c **** 
  67:../src/application/main.c **** uint16_t bayer;
  68:../src/application/main.c **** 
  69:../src/application/main.c **** static uint16_t in_gain = 80;
  70:../src/application/main.c **** static void auto_brightness( uint32_t div);
  71:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  72:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  73:../src/application/main.c **** 
  74:../src/application/main.c **** 
  75:../src/application/main.c **** 
  76:../src/application/main.c **** /*----------------------------------------------------
  77:../src/application/main.c **** /*-----------------------------------------------------------------------------
  78:../src/application/main.c ****  * GPIO instance data.
  79:../src/application/main.c ****  */
  80:../src/application/main.c **** 
  81:../src/application/main.c **** gpio_instance_t g_gpio_out;
  82:../src/application/main.c **** 
  83:../src/application/main.c **** /*-----------------------------------------------------------------------------
  84:../src/application/main.c ****  * Global state counter.
  85:../src/application/main.c ****  */
  86:../src/application/main.c **** uint32_t g_state = 1;
  87:../src/application/main.c **** 
  88:../src/application/main.c **** volatile uint32_t rx_tmr_done = 0;
  89:../src/application/main.c **** volatile uint32_t rx_ms_count1;
  90:../src/application/main.c **** volatile uint32_t rx_ms_count;
  91:../src/application/main.c **** 
  92:../src/application/main.c **** uint32_t t_ms_count = 0;
  93:../src/application/main.c **** 
  94:../src/application/main.c **** uint32_t R_constant=146;
  95:../src/application/main.c **** uint32_t G_constant=122;
  96:../src/application/main.c **** uint32_t B_constant=165;
  97:../src/application/main.c **** uint32_t second_constant=0;
  98:../src/application/main.c **** 
  99:../src/application/main.c **** 
 100:../src/application/main.c **** /*-----------------------------------------------------------------------------
 101:../src/application/main.c ****  * UART handler specific.
 102:../src/application/main.c ****  */
 103:../src/application/main.c **** uint32_t i = 0;
 104:../src/application/main.c **** uint32_t process_data = 0;
 105:../src/application/main.c **** 
 106:../src/application/main.c **** /*-----------------------------------------------------------------------------
 107:../src/application/main.c ****  * System Tick interrupt handler
 108:../src/application/main.c ****  */
 109:../src/application/main.c **** void SysTick_Handler(void) {
 145              		.loc 2 109 28
 146              		.cfi_startproc
 147 0000 4111     		addi	sp,sp,-16
 148              		.cfi_def_cfa_offset 16
 149 0002 22C6     		sw	s0,12(sp)
 150              		.cfi_offset 8, -4
 151 0004 0008     		addi	s0,sp,16
 152              		.cfi_def_cfa 8, 0
 110:../src/application/main.c **** 
 111:../src/application/main.c ****     g_state = (~g_state) & 0x01;
 153              		.loc 2 111 26
 154 0006 97070000 		lla	a5,g_state
 154      93870700 
 155 000e 9C43     		lw	a5,0(a5)
 156 0010 858B     		andi	a5,a5,1
 157 0012 93B71700 		seqz	a5,a5
 158 0016 93F7F70F 		andi	a5,a5,0xff
 159 001a 3E87     		mv	a4,a5
 160              		.loc 2 111 13
 161 001c 97070000 		lla	a5,g_state
 161      93870700 
 162 0024 98C3     		sw	a4,0(a5)
 112:../src/application/main.c **** 
 113:../src/application/main.c ****     if(timerdone == 1)
 163              		.loc 2 113 18
 164 0026 97070000 		lla	a5,timerdone
 164      93870700 
 165 002e 9843     		lw	a4,0(a5)
 166              		.loc 2 113 7
 167 0030 8547     		li	a5,1
 168 0032 6310F704 		bne	a4,a5,.L3
 114:../src/application/main.c ****     {
 115:../src/application/main.c ****         g_10ms_count1 += 1;
 169              		.loc 2 115 23
 170 0036 97070000 		lla	a5,g_10ms_count1
 170      93870700 
 171 003e 9C43     		lw	a5,0(a5)
 172 0040 13871700 		addi	a4,a5,1
 173 0044 97070000 		lla	a5,g_10ms_count1
 173      93870700 
 174 004c 98C3     		sw	a4,0(a5)
 116:../src/application/main.c ****         if(g_ms_count <= g_10ms_count1)
 175              		.loc 2 116 23
 176 004e 97070000 		lla	a5,g_ms_count
 176      93870700 
 177 0056 9843     		lw	a4,0(a5)
 178 0058 97070000 		lla	a5,g_10ms_count1
 178      93870700 
 179 0060 9C43     		lw	a5,0(a5)
 180              		.loc 2 116 11
 181 0062 63E8E700 		bgtu	a4,a5,.L3
 117:../src/application/main.c ****             timerdone = 0;
 182              		.loc 2 117 23
 183 0066 97070000 		lla	a5,timerdone
 183      93870700 
 184 006e 23A00700 		sw	zero,0(a5)
 185              	.L3:
 118:../src/application/main.c ****     }
 119:../src/application/main.c **** 
 120:../src/application/main.c ****     if(rx_tmr_done == 1)
 186              		.loc 2 120 20
 187 0072 97070000 		lla	a5,rx_tmr_done
 187      93870700 
 188 007a 9843     		lw	a4,0(a5)
 189              		.loc 2 120 7
 190 007c 8547     		li	a5,1
 191 007e 6316F704 		bne	a4,a5,.L5
 121:../src/application/main.c ****     {
 122:../src/application/main.c ****         rx_ms_count1 += 1;
 192              		.loc 2 122 22
 193 0082 97070000 		lla	a5,rx_ms_count1
 193      93870700 
 194 008a 9C43     		lw	a5,0(a5)
 195 008c 13871700 		addi	a4,a5,1
 196 0090 97070000 		lla	a5,rx_ms_count1
 196      93870700 
 197 0098 98C3     		sw	a4,0(a5)
 123:../src/application/main.c ****         if(rx_ms_count1 >= rx_ms_count){
 198              		.loc 2 123 25
 199 009a 97070000 		lla	a5,rx_ms_count1
 199      93870700 
 200 00a2 9843     		lw	a4,0(a5)
 201 00a4 97070000 		lla	a5,rx_ms_count
 201      93870700 
 202 00ac 9C43     		lw	a5,0(a5)
 203              		.loc 2 123 11
 204 00ae 636EF700 		bltu	a4,a5,.L5
 124:../src/application/main.c ****             rx_tmr_done = 0;
 205              		.loc 2 124 25
 206 00b2 97070000 		lla	a5,rx_tmr_done
 206      93870700 
 207 00ba 23A00700 		sw	zero,0(a5)
 125:../src/application/main.c ****             process_data = 1;
 208              		.loc 2 125 26
 209 00be 97070000 		lla	a5,process_data
 209      93870700 
 210 00c6 0547     		li	a4,1
 211 00c8 98C3     		sw	a4,0(a5)
 212              	.L5:
 126:../src/application/main.c ****         }
 127:../src/application/main.c ****     }
 128:../src/application/main.c **** }
 213              		.loc 2 128 1
 214 00ca 0100     		nop
 215 00cc 3244     		lw	s0,12(sp)
 216              		.cfi_restore 8
 217              		.cfi_def_cfa 2, 16
 218 00ce 4101     		addi	sp,sp,16
 219              		.cfi_def_cfa_offset 0
 220 00d0 8280     		jr	ra
 221              		.cfi_endproc
 222              	.LFE21:
 224              		.section	.text.MSYS_EI0_IRQHandler,"ax",@progbits
 225              		.align	1
 226              		.globl	MSYS_EI0_IRQHandler
 228              	MSYS_EI0_IRQHandler:
 229              	.LFB22:
 129:../src/application/main.c **** 
 130:../src/application/main.c **** uint8_t  MSYS_EI0_IRQHandler(void)
 131:../src/application/main.c **** {
 230              		.loc 2 131 1
 231              		.cfi_startproc
 232 0000 4111     		addi	sp,sp,-16
 233              		.cfi_def_cfa_offset 16
 234 0002 06C6     		sw	ra,12(sp)
 235 0004 22C4     		sw	s0,8(sp)
 236              		.cfi_offset 1, -4
 237              		.cfi_offset 8, -8
 238 0006 0008     		addi	s0,sp,16
 239              		.cfi_def_cfa 8, 0
 132:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
 240              		.loc 2 132 5
 241 0008 17050000 		lla	a0,g_i2c_instance_cam1
 241      13050500 
 242 0010 97000000 		call	I2C_isr
 242      E7800000 
 133:../src/application/main.c ****     return (EXT_IRQ_KEEP_ENABLED);
 243              		.loc 2 133 12
 244 0018 8147     		li	a5,0
 134:../src/application/main.c **** }
 245              		.loc 2 134 1
 246 001a 3E85     		mv	a0,a5
 247 001c B240     		lw	ra,12(sp)
 248              		.cfi_restore 1
 249 001e 2244     		lw	s0,8(sp)
 250              		.cfi_restore 8
 251              		.cfi_def_cfa 2, 16
 252 0020 4101     		addi	sp,sp,16
 253              		.cfi_def_cfa_offset 0
 254 0022 8280     		jr	ra
 255              		.cfi_endproc
 256              	.LFE22:
 258              		.comm	a,4,4
 259              		.section	.text.main,"ax",@progbits
 260              		.align	1
 261              		.globl	main
 263              	main:
 264              	.LFB23:
 135:../src/application/main.c **** 
 136:../src/application/main.c **** /*-----------------------------------------------------------------------------
 137:../src/application/main.c ****  * main
 138:../src/application/main.c ****  */
 139:../src/application/main.c **** uint32_t a;
 140:../src/application/main.c **** 
 141:../src/application/main.c **** int main(int argc, char **argv) {
 265              		.loc 2 141 33
 266              		.cfi_startproc
 267 0000 1971     		addi	sp,sp,-128
 268              		.cfi_def_cfa_offset 128
 269 0002 86DE     		sw	ra,124(sp)
 270 0004 A2DC     		sw	s0,120(sp)
 271              		.cfi_offset 1, -4
 272              		.cfi_offset 8, -8
 273 0006 0001     		addi	s0,sp,128
 274              		.cfi_def_cfa 8, 0
 275 0008 232EA4F8 		sw	a0,-100(s0)
 276 000c 232CB4F8 		sw	a1,-104(s0)
 142:../src/application/main.c ****     volatile  uint32_t counter;
 143:../src/application/main.c ****     uint8_t state;
 144:../src/application/main.c ****     counter = 0;
 277              		.loc 2 144 13
 278 0010 232404FA 		sw	zero,-88(s0)
 145:../src/application/main.c ****     state = 0;
 279              		.loc 2 145 11
 280 0014 A30704FE 		sb	zero,-17(s0)
 146:../src/application/main.c ****     //DISPLAY CONTROLLER PARAMETERS
 147:../src/application/main.c ****     ///////////////////FHD//////////////////////
 148:../src/application/main.c **** #if 0
 149:../src/application/main.c ****     uint32_t PIXEL_MODE=1;//4 PIXEL MODE HRES DEIVIDE BY 4
 150:../src/application/main.c ****     uint32_t BAYER_OFFSET_VALUE=2;
 151:../src/application/main.c ****     uint32_t SPEED_MODE=1;
 152:../src/application/main.c ****     uint32_t HRES=1920;
 153:../src/application/main.c ****     uint32_t VRES=1080;
 154:../src/application/main.c ****     uint32_t HFP=88;
 155:../src/application/main.c ****     uint32_t HSW=44;
 156:../src/application/main.c ****     uint32_t HBP=148;
 157:../src/application/main.c ****     uint32_t VFP=4;
 158:../src/application/main.c ****     uint32_t VSW=5;
 159:../src/application/main.c ****     uint32_t VBP=36;
 160:../src/application/main.c ****     uint32_t VSP=0x00000000;
 161:../src/application/main.c ****     uint32_t LANE_NO=0x00000004;
 162:../src/application/main.c **** #endif
 163:../src/application/main.c ****     ///////////////////4K//////////////////////
 164:../src/application/main.c **** #if 1
 165:../src/application/main.c ****     uint32_t PIXEL_MODE=4;//4 PIXEL MODE HRES DEIVIDE BY 4
 281              		.loc 2 165 14
 282 0018 9147     		li	a5,4
 283 001a 2324F4FE 		sw	a5,-24(s0)
 166:../src/application/main.c ****         uint32_t BAYER_OFFSET_VALUE=0;
 284              		.loc 2 166 18
 285 001e 232204FE 		sw	zero,-28(s0)
 167:../src/application/main.c ****         uint32_t SPEED_MODE=2;
 286              		.loc 2 167 18
 287 0022 8947     		li	a5,2
 288 0024 2320F4FE 		sw	a5,-32(s0)
 168:../src/application/main.c ****         uint32_t HRES=3840;
 289              		.loc 2 168 18
 290 0028 8567     		li	a5,4096
 291 002a 938707F0 		addi	a5,a5,-256
 292 002e 232EF4FC 		sw	a5,-36(s0)
 169:../src/application/main.c ****         uint32_t VRES=2160;
 293              		.loc 2 169 18
 294 0032 8567     		li	a5,4096
 295 0034 93870787 		addi	a5,a5,-1936
 296 0038 232CF4FC 		sw	a5,-40(s0)
 170:../src/application/main.c ****         uint32_t HFP=76;//65;//100;//176;
 297              		.loc 2 170 18
 298 003c 9307C004 		li	a5,76
 299 0040 232AF4FC 		sw	a5,-44(s0)
 171:../src/application/main.c ****         uint32_t HSW=8;
 300              		.loc 2 171 18
 301 0044 A147     		li	a5,8
 302 0046 2328F4FC 		sw	a5,-48(s0)
 172:../src/application/main.c ****         uint32_t HBP=76;//296;
 303              		.loc 2 172 18
 304 004a 9307C004 		li	a5,76
 305 004e 2326F4FC 		sw	a5,-52(s0)
 173:../src/application/main.c ****         uint32_t VFP=54;
 306              		.loc 2 173 18
 307 0052 93076003 		li	a5,54
 308 0056 2324F4FC 		sw	a5,-56(s0)
 174:../src/application/main.c ****         uint32_t VSW=5;
 309              		.loc 2 174 18
 310 005a 9547     		li	a5,5
 311 005c 2322F4FC 		sw	a5,-60(s0)
 175:../src/application/main.c ****         uint32_t VBP=3;
 312              		.loc 2 175 18
 313 0060 8D47     		li	a5,3
 314 0062 2320F4FC 		sw	a5,-64(s0)
 176:../src/application/main.c ****         uint32_t VSP=0x00008000;
 315              		.loc 2 176 18
 316 0066 A167     		li	a5,32768
 317 0068 232EF4FA 		sw	a5,-68(s0)
 177:../src/application/main.c ****         uint32_t LANE_NO=0x00000004;
 318              		.loc 2 177 18
 319 006c 9147     		li	a5,4
 320 006e 232CF4FA 		sw	a5,-72(s0)
 178:../src/application/main.c **** #endif
 179:../src/application/main.c ****         // =========================== DisplayController ================================
 180:../src/application/main.c ****         uint32_t Enable=1;
 321              		.loc 2 180 18
 322 0072 8547     		li	a5,1
 323 0074 232AF4FA 		sw	a5,-76(s0)
 181:../src/application/main.c ****         uint32_t Disable=0;
 324              		.loc 2 181 18
 325 0078 232804FA 		sw	zero,-80(s0)
 182:../src/application/main.c **** 
 183:../src/application/main.c ****         //bayer = 0x00;
 184:../src/application/main.c ****         Enable = 0x01;
 326              		.loc 2 184 16
 327 007c 8547     		li	a5,1
 328 007e 232AF4FA 		sw	a5,-76(s0)
 185:../src/application/main.c ****         Disable = 0x00;
 329              		.loc 2 185 17
 330 0082 232804FA 		sw	zero,-80(s0)
 186:../src/application/main.c **** 
 187:../src/application/main.c ****         axi4litewrite(BAYER_ADDR,BAYER_OFFSET_VALUE);
 331              		.loc 2 187 9
 332 0086 832544FE 		lw	a1,-28(s0)
 333 008a 37050272 		li	a0,1912733696
 334 008e 97000000 		call	axi4litewrite
 334      E7800000 
 188:../src/application/main.c **** 
 189:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Disable); // diabling the IP
 335              		.loc 2 189 9
 336 0096 832504FB 		lw	a1,-80(s0)
 337 009a B7070472 		li	a5,1912864768
 338 009e 13854700 		addi	a0,a5,4
 339 00a2 97000000 		call	axi4litewrite
 339      E7800000 
 190:../src/application/main.c **** 
 191:../src/application/main.c ****         axi4litewrite(DC_IP_HRES,HRES/PIXEL_MODE);
 340              		.loc 2 191 9
 341 00aa 0327C4FD 		lw	a4,-36(s0)
 342 00ae 832784FE 		lw	a5,-24(s0)
 343 00b2 B357F702 		divu	a5,a4,a5
 344 00b6 BE85     		mv	a1,a5
 345 00b8 B7070472 		li	a5,1912864768
 346 00bc 13858700 		addi	a0,a5,8
 347 00c0 97000000 		call	axi4litewrite
 347      E7800000 
 192:../src/application/main.c ****         axi4litewrite(DC_IP_VRES,VRES);
 348              		.loc 2 192 9
 349 00c8 832584FD 		lw	a1,-40(s0)
 350 00cc B7070472 		li	a5,1912864768
 351 00d0 1385C700 		addi	a0,a5,12
 352 00d4 97000000 		call	axi4litewrite
 352      E7800000 
 193:../src/application/main.c ****         axi4litewrite(DC_IP_HFP,HFP/PIXEL_MODE);
 353              		.loc 2 193 9
 354 00dc 032744FD 		lw	a4,-44(s0)
 355 00e0 832784FE 		lw	a5,-24(s0)
 356 00e4 B357F702 		divu	a5,a4,a5
 357 00e8 BE85     		mv	a1,a5
 358 00ea B7070472 		li	a5,1912864768
 359 00ee 13850701 		addi	a0,a5,16
 360 00f2 97000000 		call	axi4litewrite
 360      E7800000 
 194:../src/application/main.c ****         axi4litewrite(DC_IP_HBP,HBP/PIXEL_MODE);
 361              		.loc 2 194 9
 362 00fa 0327C4FC 		lw	a4,-52(s0)
 363 00fe 832784FE 		lw	a5,-24(s0)
 364 0102 B357F702 		divu	a5,a4,a5
 365 0106 BE85     		mv	a1,a5
 366 0108 B7070472 		li	a5,1912864768
 367 010c 13854701 		addi	a0,a5,20
 368 0110 97000000 		call	axi4litewrite
 368      E7800000 
 195:../src/application/main.c ****         axi4litewrite(DC_IP_VFP,VFP);
 369              		.loc 2 195 9
 370 0118 832584FC 		lw	a1,-56(s0)
 371 011c B7070472 		li	a5,1912864768
 372 0120 13858701 		addi	a0,a5,24
 373 0124 97000000 		call	axi4litewrite
 373      E7800000 
 196:../src/application/main.c ****         axi4litewrite(DC_IP_VBP,VBP);
 374              		.loc 2 196 9
 375 012c 832504FC 		lw	a1,-64(s0)
 376 0130 B7070472 		li	a5,1912864768
 377 0134 1385C701 		addi	a0,a5,28
 378 0138 97000000 		call	axi4litewrite
 378      E7800000 
 197:../src/application/main.c ****         axi4litewrite(DC_IP_HSW,HSW/PIXEL_MODE);
 379              		.loc 2 197 9
 380 0140 032704FD 		lw	a4,-48(s0)
 381 0144 832784FE 		lw	a5,-24(s0)
 382 0148 B357F702 		divu	a5,a4,a5
 383 014c BE85     		mv	a1,a5
 384 014e B7070472 		li	a5,1912864768
 385 0152 13850702 		addi	a0,a5,32
 386 0156 97000000 		call	axi4litewrite
 386      E7800000 
 198:../src/application/main.c ****         axi4litewrite(DC_IP_VSW,VSW);
 387              		.loc 2 198 9
 388 015e 832544FC 		lw	a1,-60(s0)
 389 0162 B7070472 		li	a5,1912864768
 390 0166 13854702 		addi	a0,a5,36
 391 016a 97000000 		call	axi4litewrite
 391      E7800000 
 199:../src/application/main.c **** 
 200:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Enable); // Enabling the IP
 392              		.loc 2 200 9
 393 0172 832544FB 		lw	a1,-76(s0)
 394 0176 B7070472 		li	a5,1912864768
 395 017a 13854700 		addi	a0,a5,4
 396 017e 97000000 		call	axi4litewrite
 396      E7800000 
 201:../src/application/main.c **** 
 202:../src/application/main.c **** 
 203:../src/application/main.c ****         axi4litewrite(IE_IP_EN_DIS,Disable); // diabling the IP
 397              		.loc 2 203 9
 398 0186 832504FB 		lw	a1,-80(s0)
 399 018a B7070372 		li	a5,1912799232
 400 018e 13854700 		addi	a0,a5,4
 401 0192 97000000 		call	axi4litewrite
 401      E7800000 
 204:../src/application/main.c **** 
 205:../src/application/main.c ****         axi4litewrite(IE_R_CONST,R_constant);
 402              		.loc 2 205 9
 403 019a 97070000 		lla	a5,R_constant
 403      93870700 
 404 01a2 9C43     		lw	a5,0(a5)
 405 01a4 BE85     		mv	a1,a5
 406 01a6 B7070372 		li	a5,1912799232
 407 01aa 13858700 		addi	a0,a5,8
 408 01ae 97000000 		call	axi4litewrite
 408      E7800000 
 206:../src/application/main.c ****         axi4litewrite(IE_G_CONST,G_constant);
 409              		.loc 2 206 9
 410 01b6 97070000 		lla	a5,G_constant
 410      93870700 
 411 01be 9C43     		lw	a5,0(a5)
 412 01c0 BE85     		mv	a1,a5
 413 01c2 B7070372 		li	a5,1912799232
 414 01c6 1385C700 		addi	a0,a5,12
 415 01ca 97000000 		call	axi4litewrite
 415      E7800000 
 207:../src/application/main.c ****         axi4litewrite(IE_B_CONST,B_constant);
 416              		.loc 2 207 9
 417 01d2 97070000 		lla	a5,B_constant
 417      93870700 
 418 01da 9C43     		lw	a5,0(a5)
 419 01dc BE85     		mv	a1,a5
 420 01de B7070372 		li	a5,1912799232
 421 01e2 13850701 		addi	a0,a5,16
 422 01e6 97000000 		call	axi4litewrite
 422      E7800000 
 208:../src/application/main.c ****         axi4litewrite(IE_COMMON_CONST,second_constant);
 423              		.loc 2 208 9
 424 01ee 97070000 		lla	a5,second_constant
 424      93870700 
 425 01f6 9C43     		lw	a5,0(a5)
 426 01f8 BE85     		mv	a1,a5
 427 01fa B7070372 		li	a5,1912799232
 428 01fe 13854701 		addi	a0,a5,20
 429 0202 97000000 		call	axi4litewrite
 429      E7800000 
 209:../src/application/main.c **** 
 210:../src/application/main.c **** 
 211:../src/application/main.c ****         axi4litewrite(IE_IP_EN_DIS,Enable); // Enabling the IP
 430              		.loc 2 211 9
 431 020a 832544FB 		lw	a1,-76(s0)
 432 020e B7070372 		li	a5,1912799232
 433 0212 13854700 		addi	a0,a5,4
 434 0216 97000000 		call	axi4litewrite
 434      E7800000 
 212:../src/application/main.c **** 
 213:../src/application/main.c ****         //Displaycontroller(HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,PIXEL_MODE/*,BAYER_OFFSET_VALUE*/);
 214:../src/application/main.c **** 
 215:../src/application/main.c ****         uint32_t div = (1920*1080*4);
 435              		.loc 2 215 18
 436 021e B7977E00 		li	a5,8294400
 437 0222 2326F4FA 		sw	a5,-84(s0)
 216:../src/application/main.c **** 
 217:../src/application/main.c ****     GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
 438              		.loc 2 217 5
 439 0226 0946     		li	a2,2
 440 0228 B7450071 		li	a1,1895841792
 441 022c 17050000 		lla	a0,g_gpio_out
 441      13050500 
 442 0234 97000000 		call	GPIO_init
 442      E7800000 
 218:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED1, 1);
 443              		.loc 2 218 5
 444 023c 0546     		li	a2,1
 445 023e 8145     		li	a1,0
 446 0240 17050000 		lla	a0,g_gpio_out
 446      13050500 
 447 0248 97000000 		call	GPIO_set_output
 447      E7800000 
 219:../src/application/main.c **** 
 220:../src/application/main.c ****     MRV_systick_config(SYS_CLK_FREQ / 1000);
 448              		.loc 2 220 5
 449 0250 3165     		li	a0,49152
 450 0252 13050535 		addi	a0,a0,848
 451 0256 8145     		li	a1,0
 452 0258 97000000 		call	MRV_systick_config
 452      E7800000 
 221:../src/application/main.c **** 
 222:../src/application/main.c ****     MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
 453              		.loc 2 222 5
 454 0260 37050001 		li	a0,16777216
 455 0264 97000000 		call	MRV_enable_local_irq
 455      E7800000 
 223:../src/application/main.c **** 
 224:../src/application/main.c ****     HAL_enable_interrupts();
 456              		.loc 2 224 5
 457 026c 97000000 		call	HAL_enable_interrupts
 457      E7800000 
 225:../src/application/main.c **** 
 226:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 0u);
 458              		.loc 2 226 5
 459 0274 0146     		li	a2,0
 460 0276 9145     		li	a1,4
 461 0278 17050000 		lla	a0,g_gpio_out
 461      13050500 
 462 0280 97000000 		call	GPIO_set_output
 462      E7800000 
 227:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED2, 1);
 463              		.loc 2 227 5
 464 0288 0546     		li	a2,1
 465 028a 8545     		li	a1,1
 466 028c 17050000 		lla	a0,g_gpio_out
 466      13050500 
 467 0294 97000000 		call	GPIO_set_output
 467      E7800000 
 228:../src/application/main.c **** 
 229:../src/application/main.c ****     //Camera Initialization
 230:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM1_RST, 1u);
 468              		.loc 2 230 5
 469 029c 0546     		li	a2,1
 470 029e A145     		li	a1,8
 471 02a0 17050000 		lla	a0,g_gpio_out
 471      13050500 
 472 02a8 97000000 		call	GPIO_set_output
 472      E7800000 
 231:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM_CLK_EN, 0u);
 473              		.loc 2 231 5
 474 02b0 0146     		li	a2,0
 475 02b2 A545     		li	a1,9
 476 02b4 17050000 		lla	a0,g_gpio_out
 476      13050500 
 477 02bc 97000000 		call	GPIO_set_output
 477      E7800000 
 232:../src/application/main.c ****     imx334_cam_init();
 478              		.loc 2 232 5
 479 02c4 97000000 		call	imx334_cam_init
 479      E7800000 
 233:../src/application/main.c ****     imx334_cam_reginit(1u);
 480              		.loc 2 233 5
 481 02cc 0545     		li	a0,1
 482 02ce 97000000 		call	imx334_cam_reginit
 482      E7800000 
 234:../src/application/main.c **** 
 235:../src/application/main.c ****     //Setting LED
 236:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED3, 1);
 483              		.loc 2 236 5
 484 02d6 0546     		li	a2,1
 485 02d8 8945     		li	a1,2
 486 02da 17050000 		lla	a0,g_gpio_out
 486      13050500 
 487 02e2 97000000 		call	GPIO_set_output
 487      E7800000 
 237:../src/application/main.c ****     msdelay(1000);
 488              		.loc 2 237 5
 489 02ea 1305803E 		li	a0,1000
 490 02ee 97000000 		call	msdelay
 490      E7800000 
 238:../src/application/main.c **** //    delay_msec(100);
 239:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 1u);
 491              		.loc 2 239 5
 492 02f6 0546     		li	a2,1
 493 02f8 9145     		li	a1,4
 494 02fa 17050000 		lla	a0,g_gpio_out
 494      13050500 
 495 0302 97000000 		call	GPIO_set_output
 495      E7800000 
 240:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED4, 1);
 496              		.loc 2 240 5
 497 030a 0546     		li	a2,1
 498 030c 8D45     		li	a1,3
 499 030e 17050000 		lla	a0,g_gpio_out
 499      13050500 
 500 0316 97000000 		call	GPIO_set_output
 500      E7800000 
 241:../src/application/main.c **** 
 242:../src/application/main.c ****     // =========================== DisplayPort ================================
 243:../src/application/main.c ****     UART_init(&g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, (DATA_8_BITS | NO_PARITY));
 501              		.loc 2 243 5
 502 031e 8546     		li	a3,1
 503 0320 6946     		li	a2,26
 504 0322 B7050071 		li	a1,1895825408
 505 0326 17050000 		lla	a0,g_uart
 505      13050500 
 506 032e 97000000 		call	UART_init
 506      E7800000 
 244:../src/application/main.c ****     DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 507              		.loc 2 244 5
 508 0336 832784FB 		lw	a5,-72(s0)
 509 033a 3EC4     		sw	a5,8(sp)
 510 033c 8327C4FB 		lw	a5,-68(s0)
 511 0340 3EC2     		sw	a5,4(sp)
 512 0342 832744FC 		lw	a5,-60(s0)
 513 0346 3EC0     		sw	a5,0(sp)
 514 0348 832804FD 		lw	a7,-48(s0)
 515 034c 032804FC 		lw	a6,-64(s0)
 516 0350 832784FC 		lw	a5,-56(s0)
 517 0354 0327C4FC 		lw	a4,-52(s0)
 518 0358 832644FD 		lw	a3,-44(s0)
 519 035c 032684FD 		lw	a2,-40(s0)
 520 0360 8325C4FD 		lw	a1,-36(s0)
 521 0364 032504FE 		lw	a0,-32(s0)
 522 0368 97000000 		call	DPSourceInit
 522      E7800000 
 523              	.L12:
 245:../src/application/main.c **** 
 246:../src/application/main.c ****     // ========================================================================
 247:../src/application/main.c **** 
 248:../src/application/main.c ****     do
 249:../src/application/main.c ****     {
 250:../src/application/main.c ****         // ====================================================================
 251:../src/application/main.c ****         // ===================== DisplayPort ==================================
 252:../src/application/main.c ****         // ====================================================================
 253:../src/application/main.c ****         // Check if there is Sink Interrupt
 254:../src/application/main.c ****         DPSourceISR(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 524              		.loc 2 254 9
 525 0370 832784FB 		lw	a5,-72(s0)
 526 0374 3EC4     		sw	a5,8(sp)
 527 0376 8327C4FB 		lw	a5,-68(s0)
 528 037a 3EC2     		sw	a5,4(sp)
 529 037c 832744FC 		lw	a5,-60(s0)
 530 0380 3EC0     		sw	a5,0(sp)
 531 0382 832804FD 		lw	a7,-48(s0)
 532 0386 032804FC 		lw	a6,-64(s0)
 533 038a 832784FC 		lw	a5,-56(s0)
 534 038e 0327C4FC 		lw	a4,-52(s0)
 535 0392 832644FD 		lw	a3,-44(s0)
 536 0396 032684FD 		lw	a2,-40(s0)
 537 039a 8325C4FD 		lw	a1,-36(s0)
 538 039e 032504FE 		lw	a0,-32(s0)
 539 03a2 97000000 		call	DPSourceISR
 539      E7800000 
 255:../src/application/main.c ****         msdelay(30);
 540              		.loc 2 255 9
 541 03aa 7945     		li	a0,30
 542 03ac 97000000 		call	msdelay
 542      E7800000 
 256:../src/application/main.c ****         auto_brightness(div);
 543              		.loc 2 256 9
 544 03b4 0325C4FA 		lw	a0,-84(s0)
 545 03b8 97000000 		call	auto_brightness
 545      E7800000 
 257:../src/application/main.c **** 
 258:../src/application/main.c **** 
 259:../src/application/main.c ****         counter = counter +1;
 546              		.loc 2 259 27
 547 03c0 832784FA 		lw	a5,-88(s0)
 548 03c4 8507     		addi	a5,a5,1
 549              		.loc 2 259 17
 550 03c6 2324F4FA 		sw	a5,-88(s0)
 260:../src/application/main.c ****         if (counter <16){
 551              		.loc 2 260 21
 552 03ca 032784FA 		lw	a4,-88(s0)
 553              		.loc 2 260 12
 554 03ce BD47     		li	a5,15
 555 03d0 63EDE700 		bgtu	a4,a5,.L9
 261:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 556              		.loc 2 261 13
 557 03d4 0146     		li	a2,0
 558 03d6 8145     		li	a1,0
 559 03d8 17050000 		lla	a0,g_gpio_out
 559      13050500 
 560 03e0 97000000 		call	GPIO_set_output
 560      E7800000 
 561 03e8 19A8     		j	.L10
 562              	.L9:
 262:../src/application/main.c ****         }
 263:../src/application/main.c ****         else{
 264:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 1);
 563              		.loc 2 264 13
 564 03ea 0546     		li	a2,1
 565 03ec 8145     		li	a1,0
 566 03ee 17050000 		lla	a0,g_gpio_out
 566      13050500 
 567 03f6 97000000 		call	GPIO_set_output
 567      E7800000 
 568              	.L10:
 265:../src/application/main.c ****         }
 266:../src/application/main.c ****         if (counter ==32){
 569              		.loc 2 266 21
 570 03fe 032784FA 		lw	a4,-88(s0)
 571              		.loc 2 266 12
 572 0402 93070002 		li	a5,32
 573 0406 E315F7F6 		bne	a4,a5,.L12
 267:../src/application/main.c ****             counter =0;
 574              		.loc 2 267 21
 575 040a 232404FA 		sw	zero,-88(s0)
 254:../src/application/main.c ****         msdelay(30);
 576              		.loc 2 254 9
 577 040e 8DB7     		j	.L12
 578              		.cfi_endproc
 579              	.LFE23:
 581              		.section	.text.auto_brightness,"ax",@progbits
 582              		.align	1
 584              	auto_brightness:
 585              	.LFB24:
 268:../src/application/main.c ****         }
 269:../src/application/main.c **** 
 270:../src/application/main.c ****     } while (1);
 271:../src/application/main.c **** 
 272:../src/application/main.c **** 
 273:../src/application/main.c ****     return 0;
 274:../src/application/main.c **** }
 275:../src/application/main.c **** 
 276:../src/application/main.c **** /**********************************************************/
 277:../src/application/main.c **** /**********************FUNCTION CALLS**********************/
 278:../src/application/main.c **** /**********************************************************/
 279:../src/application/main.c **** void auto_brightness(uint32_t div)
 280:../src/application/main.c **** {
 586              		.loc 2 280 1
 587              		.cfi_startproc
 588 0000 7971     		addi	sp,sp,-48
 589              		.cfi_def_cfa_offset 48
 590 0002 06D6     		sw	ra,44(sp)
 591 0004 22D4     		sw	s0,40(sp)
 592              		.cfi_offset 1, -4
 593              		.cfi_offset 8, -8
 594 0006 0018     		addi	s0,sp,48
 595              		.cfi_def_cfa 8, 0
 596 0008 232EA4FC 		sw	a0,-36(s0)
 281:../src/application/main.c ****     uint32_t total_sum =  (uint32_t)(*(volatile int*) IE_INTENSITY_AVARAGE);
 597              		.loc 2 281 38
 598 000c B7070372 		li	a5,1912799232
 599 0010 E107     		addi	a5,a5,24
 600 0012 9C43     		lw	a5,0(a5)
 601              		.loc 2 281 14
 602 0014 2326F4FE 		sw	a5,-20(s0)
 282:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 603              		.loc 2 282 14
 604 0018 0327C4FE 		lw	a4,-20(s0)
 605 001c 8327C4FD 		lw	a5,-36(s0)
 606 0020 B357F702 		divu	a5,a4,a5
 607 0024 2324F4FE 		sw	a5,-24(s0)
 283:../src/application/main.c **** 
 284:../src/application/main.c ****     gain_cal(total_average);
 608              		.loc 2 284 5
 609 0028 032584FE 		lw	a0,-24(s0)
 610 002c 97000000 		call	gain_cal
 610      E7800000 
 285:../src/application/main.c **** }
 611              		.loc 2 285 1
 612 0034 0100     		nop
 613 0036 B250     		lw	ra,44(sp)
 614              		.cfi_restore 1
 615 0038 2254     		lw	s0,40(sp)
 616              		.cfi_restore 8
 617              		.cfi_def_cfa 2, 48
 618 003a 4561     		addi	sp,sp,48
 619              		.cfi_def_cfa_offset 0
 620 003c 8280     		jr	ra
 621              		.cfi_endproc
 622              	.LFE24:
 624              		.section	.text.gain_cal,"ax",@progbits
 625              		.align	1
 627              	gain_cal:
 628              	.LFB25:
 286:../src/application/main.c **** 
 287:../src/application/main.c **** void gain_cal(uint32_t total_average)
 288:../src/application/main.c **** {
 629              		.loc 2 288 1
 630              		.cfi_startproc
 631 0000 7971     		addi	sp,sp,-48
 632              		.cfi_def_cfa_offset 48
 633 0002 06D6     		sw	ra,44(sp)
 634 0004 22D4     		sw	s0,40(sp)
 635              		.cfi_offset 1, -4
 636              		.cfi_offset 8, -8
 637 0006 0018     		addi	s0,sp,48
 638              		.cfi_def_cfa 8, 0
 639 0008 232EA4FC 		sw	a0,-36(s0)
 289:../src/application/main.c ****     //////////////////////////////////////////////////////
 290:../src/application/main.c ****     const int16_t good_average=100;
 640              		.loc 2 290 19
 641 000c 93074006 		li	a5,100
 642 0010 2316F4FE 		sh	a5,-20(s0)
 291:../src/application/main.c ****     const int16_t hysteresis=4;
 643              		.loc 2 291 19
 644 0014 9147     		li	a5,4
 645 0016 2315F4FE 		sh	a5,-22(s0)
 292:../src/application/main.c ****     int16_t step;
 293:../src/application/main.c ****         if(total_average < (good_average - hysteresis))
 646              		.loc 2 293 42
 647 001a 0317C4FE 		lh	a4,-20(s0)
 648 001e 8317A4FE 		lh	a5,-22(s0)
 649 0022 B307F740 		sub	a5,a4,a5
 650 0026 3E87     		mv	a4,a5
 651              		.loc 2 293 11
 652 0028 8327C4FD 		lw	a5,-36(s0)
 653 002c 63F6E700 		bgeu	a5,a4,.L15
 294:../src/application/main.c ****             step = 1;
 654              		.loc 2 294 18
 655 0030 8547     		li	a5,1
 656 0032 2317F4FE 		sh	a5,-18(s0)
 657 0036 0DA0     		j	.L16
 658              	.L15:
 295:../src/application/main.c ****         else
 296:../src/application/main.c ****             if(total_average > (good_average + hysteresis))
 659              		.loc 2 296 46
 660 0038 0317C4FE 		lh	a4,-20(s0)
 661 003c 8317A4FE 		lh	a5,-22(s0)
 662 0040 BA97     		add	a5,a4,a5
 663 0042 3E87     		mv	a4,a5
 664              		.loc 2 296 15
 665 0044 8327C4FD 		lw	a5,-36(s0)
 666 0048 6376F700 		bleu	a5,a4,.L17
 297:../src/application/main.c ****                 step = -1;
 667              		.loc 2 297 22
 668 004c FD57     		li	a5,-1
 669 004e 2317F4FE 		sh	a5,-18(s0)
 670 0052 19A0     		j	.L16
 671              	.L17:
 298:../src/application/main.c ****             else
 299:../src/application/main.c ****                 step = 0;
 672              		.loc 2 299 22
 673 0054 231704FE 		sh	zero,-18(s0)
 674              	.L16:
 300:../src/application/main.c **** 
 301:../src/application/main.c ****         in_gain = in_gain + step;
 675              		.loc 2 301 27
 676 0058 97070000 		lla	a5,in_gain
 676      93870700 
 677 0060 03D70700 		lhu	a4,0(a5)
 678 0064 8357E4FE 		lhu	a5,-18(s0)
 679 0068 BA97     		add	a5,a4,a5
 680 006a 13970701 		slli	a4,a5,16
 681 006e 4183     		srli	a4,a4,16
 682              		.loc 2 301 17
 683 0070 97070000 		lla	a5,in_gain
 683      93870700 
 684 0078 2390E700 		sh	a4,0(a5)
 302:../src/application/main.c **** 
 303:../src/application/main.c ****         if(in_gain < 5)
 685              		.loc 2 303 20
 686 007c 97070000 		lla	a5,in_gain
 686      93870700 
 687 0084 03D70700 		lhu	a4,0(a5)
 688              		.loc 2 303 11
 689 0088 9147     		li	a5,4
 690 008a 63EAE700 		bgtu	a4,a5,.L18
 304:../src/application/main.c ****             in_gain = 5;
 691              		.loc 2 304 21
 692 008e 97070000 		lla	a5,in_gain
 692      93870700 
 693 0096 1547     		li	a4,5
 694 0098 2390E700 		sh	a4,0(a5)
 695 009c 1DA0     		j	.L19
 696              	.L18:
 305:../src/application/main.c ****         else
 306:../src/application/main.c ****             if(in_gain >= 100)
 697              		.loc 2 306 24
 698 009e 97070000 		lla	a5,in_gain
 698      93870700 
 699 00a6 03D70700 		lhu	a4,0(a5)
 700              		.loc 2 306 15
 701 00aa 93073006 		li	a5,99
 702 00ae 63FAE700 		bleu	a4,a5,.L19
 307:../src/application/main.c ****                 in_gain = 100;
 703              		.loc 2 307 25
 704 00b2 97070000 		lla	a5,in_gain
 704      93870700 
 705 00ba 13074006 		li	a4,100
 706 00be 2390E700 		sh	a4,0(a5)
 707              	.L19:
 308:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 309:../src/application/main.c ****     gain_setting(1u,in_gain);
 708              		.loc 2 309 5
 709 00c2 97070000 		lla	a5,in_gain
 709      93870700 
 710 00ca 83D70700 		lhu	a5,0(a5)
 711 00ce BE85     		mv	a1,a5
 712 00d0 0545     		li	a0,1
 713 00d2 97000000 		call	gain_setting
 713      E7800000 
 310:../src/application/main.c **** }
 714              		.loc 2 310 1
 715 00da 0100     		nop
 716 00dc B250     		lw	ra,44(sp)
 717              		.cfi_restore 1
 718 00de 2254     		lw	s0,40(sp)
 719              		.cfi_restore 8
 720              		.cfi_def_cfa 2, 48
 721 00e0 4561     		addi	sp,sp,48
 722              		.cfi_def_cfa_offset 0
 723 00e2 8280     		jr	ra
 724              		.cfi_endproc
 725              	.LFE25:
 727              		.text
 728              	.Letext0:
 729              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 730              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 731              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 732              		.file 6 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 733              		.file 7 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 734              		.file 8 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 735              		.file 9 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 736              		.file 10 "../src/application/dp_cmd_common.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 main.c
                            *COM*:0000000000000004 MRV_LOCAL_IRQn_Type
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:13     .text.MRV_enable_local_irq:0000000000000000 MRV_enable_local_irq
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:17     .text.MRV_enable_local_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:18     .text.MRV_enable_local_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:19     .text.MRV_enable_local_irq:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:21     .text.MRV_enable_local_irq:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:23     .text.MRV_enable_local_irq:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:27     .text.MRV_enable_local_irq:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:36     .text.MRV_enable_local_irq:0000000000000016 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:38     .text.MRV_enable_local_irq:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:39     .text.MRV_enable_local_irq:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:41     .text.MRV_enable_local_irq:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:43     .text.MRV_enable_local_irq:000000000000001e .L0 
                            *COM*:0000000000000004 g_10ms_count
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:52     .sbss.timerdone:0000000000000000 timerdone
                            *COM*:0000000000000004 g_10ms_count1
                            *COM*:0000000000000004 g_ms_count
                            *COM*:000000000000006c g_i2c_instance_cam1
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:62     .bss.uart_rx_buff:0000000000000000 uart_rx_buff
                            *COM*:0000000000000008 g_uart
                            *COM*:0000000000000002 bayer
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:70     .sdata.in_gain:0000000000000000 in_gain
                            *COM*:0000000000000008 g_gpio_out
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:78     .sdata.g_state:0000000000000000 g_state
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:85     .sbss.rx_tmr_done:0000000000000000 rx_tmr_done
                            *COM*:0000000000000004 rx_ms_count1
                            *COM*:0000000000000004 rx_ms_count
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:94     .sbss.t_ms_count:0000000000000000 t_ms_count
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:101    .sdata.R_constant:0000000000000000 R_constant
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:108    .sdata.G_constant:0000000000000000 G_constant
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:115    .sdata.B_constant:0000000000000000 B_constant
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:122    .sbss.second_constant:0000000000000000 second_constant
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:129    .sbss.i:0000000000000000 i
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:136    .sbss.process_data:0000000000000000 process_data
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:142    .text.SysTick_Handler:0000000000000000 SysTick_Handler
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:146    .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:147    .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:148    .text.SysTick_Handler:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:150    .text.SysTick_Handler:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:152    .text.SysTick_Handler:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:154    .text.SysTick_Handler:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:161    .text.SysTick_Handler:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:164    .text.SysTick_Handler:0000000000000026 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:167    .text.SysTick_Handler:0000000000000030 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:170    .text.SysTick_Handler:0000000000000036 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:176    .text.SysTick_Handler:000000000000004e .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:181    .text.SysTick_Handler:0000000000000062 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:183    .text.SysTick_Handler:0000000000000066 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:187    .text.SysTick_Handler:0000000000000072 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:190    .text.SysTick_Handler:000000000000007c .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:193    .text.SysTick_Handler:0000000000000082 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:199    .text.SysTick_Handler:000000000000009a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:204    .text.SysTick_Handler:00000000000000ae .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:206    .text.SysTick_Handler:00000000000000b2 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:209    .text.SysTick_Handler:00000000000000be .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:214    .text.SysTick_Handler:00000000000000ca .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:216    .text.SysTick_Handler:00000000000000ce .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:217    .text.SysTick_Handler:00000000000000ce .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:219    .text.SysTick_Handler:00000000000000d0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:221    .text.SysTick_Handler:00000000000000d2 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:228    .text.MSYS_EI0_IRQHandler:0000000000000000 MSYS_EI0_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:231    .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:232    .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:233    .text.MSYS_EI0_IRQHandler:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:236    .text.MSYS_EI0_IRQHandler:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:237    .text.MSYS_EI0_IRQHandler:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:239    .text.MSYS_EI0_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:241    .text.MSYS_EI0_IRQHandler:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:244    .text.MSYS_EI0_IRQHandler:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:246    .text.MSYS_EI0_IRQHandler:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:248    .text.MSYS_EI0_IRQHandler:000000000000001e .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:250    .text.MSYS_EI0_IRQHandler:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:251    .text.MSYS_EI0_IRQHandler:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:253    .text.MSYS_EI0_IRQHandler:0000000000000022 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:255    .text.MSYS_EI0_IRQHandler:0000000000000024 .L0 
                            *COM*:0000000000000004 a
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:263    .text.main:0000000000000000 main
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:266    .text.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:267    .text.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:268    .text.main:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:271    .text.main:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:272    .text.main:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:274    .text.main:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:278    .text.main:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:280    .text.main:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:282    .text.main:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:285    .text.main:000000000000001e .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:287    .text.main:0000000000000022 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:290    .text.main:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:294    .text.main:0000000000000032 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:298    .text.main:000000000000003c .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:301    .text.main:0000000000000044 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:304    .text.main:000000000000004a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:307    .text.main:0000000000000052 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:310    .text.main:000000000000005a .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:313    .text.main:0000000000000060 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:316    .text.main:0000000000000066 .L0 
C:\Users\I71825\AppData\Local\Temp\ccpRgUxn.s:319    .text.main:000000000000006c .L0 
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                           .group:0000000000000000 wm4.0.d473863a262a582c4c43723f529345fc
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                           .group:0000000000000000 wm4._intsup.h.10.48bafbb683905c4daa4565a85aeeb264
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                           .group:0000000000000000 wm4.stdint.h.23.d53047a68f4a85177f80b422d52785ed
                           .group:0000000000000000 wm4.miv_rv32_assert.h.10.6dc0136b119630f702b094dacf9c48db
                           .group:0000000000000000 wm4.miv_rv32_subsys.h.12.73d9f7238e23adf36f8969cbd5d67239
                           .group:0000000000000000 wm4.fpga_design_config.h.47.caf23d7587803e1bd2d18a7e46d8c4d1
                           .group:0000000000000000 wm4.miv_rv32_hal.h.264.dd35246e0d861e875b521b0ec48aca8e
                           .group:0000000000000000 wm4.hal_assert.h.11.0d97442599ed1a8280adc0745177f94a
                           .group:0000000000000000 wm4.hal.h.60.4995f3d8011bbbf7274e2247e66f98e1
                           .group:0000000000000000 wm4.core_gpio.h.206.06ec3c8edb17fd9482a2fb7834cf68c9
                           .group:0000000000000000 wm4.core_uart_apb.h.101.daf941b5d81e40fa75b133ba239521dd
                           .group:0000000000000000 wm4.core_i2c.h.437.c512b1d6ed8b9b3986fd890aa54cc67c
                           .group:0000000000000000 wm4.imx334_corei2c.h.18.52c0de8e1b31b6ac0fa363eb7e105e7b
                           .group:0000000000000000 wm4.hdmi_tx.h.19.01dee89dc0d071519c2e070d4a60788a
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UNDEFINED SYMBOLS
I2C_isr
axi4litewrite
GPIO_init
GPIO_set_output
MRV_systick_config
HAL_enable_interrupts
imx334_cam_init
imx334_cam_reginit
msdelay
UART_init
DPSourceInit
DPSourceISR
gain_setting
