#include "dp_cmd_common.h"
#include "dp_cmd_tx_regs.h"
#include "dp_cmd_tx.h"

uint32_t SourceCmdSta = 0x0000000;
uint32_t SourceWrBytes[16] = {0x00000000};
uint32_t SourceCmdTx = 0;
uint32_t seq_rst = 1, tps3_supported =0;
uint32_t timestamp = 0;
uint32_t iter = 1;


void DPSourceTxRdCmd(uint32_t addr,uint32_t lenVal,uint32_t rxByteNum);
void DPSourceTxWrCmd(uint32_t addr,uint32_t lenVal,uint32_t txByteNum);
void link_training(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO);
void update_speed(uint32_t data );
void vsw_pe(uint32_t sw,uint32_t pe);

uint32_t lane_01_cr_done=0;
uint32_t lane_23_cr_done=0;
uint32_t lane_01_eq_done=0;
uint32_t lane_23_eq_done=0;
uint32_t reply_data_vs0=0;
uint32_t reply_data_vs1=0;
uint32_t reply_data_vs2=0;
uint32_t reply_data_vs3=0;
uint32_t reply_data_pe0=0;
uint32_t reply_data_pe1=0;
uint32_t reply_data_pe2=0;
uint32_t reply_data_pe3=0;
uint32_t reply_pe_0=0;
uint32_t reply_pe_1=0;
uint32_t reply_pe_2=0;
uint32_t reply_pe_3=0;
uint32_t reply_sw_0=0;
uint32_t reply_sw_1=0;
uint32_t reply_sw_2=0;
uint32_t reply_sw_3=0;
uint32_t vs=0;
uint32_t pe=0;
uint32_t reply_data_cr_01=0;
uint32_t reply_data_cr_23=0;
uint32_t reply_data_eq_01=0;
uint32_t reply_data_eq_23=0;
uint32_t irq_value;
//DRI
uint32_t MSA_VALUE;
uint32_t SPEED=0;
// ---------------------------------------------------------------------------
// DisplayPort init()
// ---------------------------------------------------------------------------
void DPSourceInit(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO)
{

    update_speed(SPEED_MODE);
    uint32_t rd_data_hpd;
    //hpd_1us_cycles
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_HPD_1US_CYCLES_OFFSET, 0x00000064);
    //DP_TX_HPD_CONNECTED_HIGH_TIME_TH_OFFSET
    write_dp(DP_TX_IP_APB_BASE_ADDRESS,DP_TX_HPD_CONNECTED_HIGH_TIME_TH_OFFSET, 0x000186A0);
    //DP_TX_HPD_DISCONNECTED_LOW_TIME_TH_OFFSET
    write_dp(DP_TX_IP_APB_BASE_ADDRESS,DP_TX_HPD_DISCONNECTED_LOW_TIME_TH_OFFSET, 0x000007d0);
    //DP_TX_HPD_IRQ_TIME_OFFSET
    write_dp(DP_TX_IP_APB_BASE_ADDRESS,DP_TX_HPD_IRQ_TIME_OFFSET, 0x03e801f4);
    //read interrupt
     read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_HPD_CONNECT_STATUS_OFFSET,&rd_data_hpd);
    // aux timeout
     write_dp(DP_TX_IP_APB_BASE_ADDRESS,DP_TX_AUX_REPLY_TIMEOUT_TH_OFFSET, 0x000493e0);

    uint32_t rd_data[4];

    //read interrupt
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_INTERRUPT_OFFSET, &rd_data[0]);
    //AUX_Rx_Reply_Timeout_Error
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_RX_ERROR_STATUS_OFFSET, &rd_data[0]);
    //AUX_Tx_Request_Number
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_REQUEST_NUMBER_OFFSET, &rd_data[1]);
    //AUX_Rx_Reply_Number
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_RX_REPLY_NUMBER_OFFSET, &rd_data[2]);

    //powerup the dp
    SourceWrBytes[0] = 0x00000001;
    DPSourceTxWrCmd(0x00000600,0x00000001,0x00000001); //SET_POWER & SET_DP_PWR_VOLTAGE

    //following call displays without power cycling monitor
    link_training(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);



}

// ---------------------------------------------------------------------------
// DisplayPort config init()
// ---------------------------------------------------------------------------

void config_init(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO)
{
    SourceCmdSta = 0x0000000;
    timestamp = 0;

    DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
    //DP_TX_AUX_TX
    SourceWrBytes[0] = 0x00000001;
    DPSourceTxWrCmd(0x00000600,0x00000001,0x00000001); //SET_POWER & SET_DP_PWR_VOLTAGE
}
// ---------------------------------------------------------------------------
// DisplayPort Source ISR
// ---------------------------------------------------------------------------

void DPSourceISR(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO)
{

    uint32_t SER_1_PMA_L0_DES_RSTPD_R;
    uint32_t SER_1_PMA_L0_SER_RSTPD_R;
    uint32_t SER_1_PMA_L0_DES_CDR_CTRL_2_R;
    uint32_t SER_1_PMA_L0_DES_CDR_CTRL_3_R;
    uint32_t SER_1_PMA_L0_DES_DFEEM_CTRL_1_R;
    uint32_t SER_1_PMA_L0_DES_DFEEM_CTRL_2_R;
    uint32_t SER_1_PMA_L0_DES_DFEEM_CTRL_3_R;
    uint32_t SER_1_PMA_L0_DES_DFE_CTRL_2_R;
    uint32_t SER_1_PMA_L0_DES_EM_CTRL_2_R;
    uint32_t SER_1_PMA_L0_DES_RXPLL_DIV_R;
    uint32_t SER_1_PMA_L0_SER_CLK_CTRL_R;
    uint32_t SER_1_PMA_L0_SERDES_RTL_CTRL_R;
    uint32_t SER_1_PMA_L0_DES_DFE_CAL_CTRL_0_R;
    uint32_t SER_1_PMA_L0_DES_DFE_CAL_CTRL_1_R;
    uint32_t SER_1_PMA_L0_DES_DFE_CAL_CTRL_2_R;
    uint32_t SER_1_PMA_L0_DES_DFE_CAL_CMD_R;
    uint32_t TXPLL_DIV_1;
    uint32_t TXPLL_DIV_2;
    //swing reg
    uint32_t SER_1_PMA_L0_SER_DRV_DATA_CTRL_R;
    uint32_t SER_1_PMA_L0_SER_DRV_CTRL_R;
    uint32_t SER_1_PMA_L0_SER_DRV_CTRL_SEL_R;
    //read interrupt
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_INTERRUPT_OFFSET, &irq_value);

    if(irq_value == 0x00000000)
        return;

    if( (irq_value&0x00000002) > 0x00000000)
    {
        link_training(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
    }
    // -----------------------------------------
    // HPD Event
    // -----------------------------------------
    if( (irq_value&0x00000008) > 0x00000000)
    {
        uint8_t testmsg1[] = {"\n * DisplayPort Source Got HPD IRQ : \n"};
        UART_send(&g_uart,(const uint8_t *)&testmsg1,sizeof(testmsg1));
        SourceCmdSta = 0x0000000;
        config_init(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
    }
    if( (irq_value&0x00000010) > 0x00000000)
    {
        uint8_t testmsg1[] = {"\n * DisplayPort Source Got HPD Connection : \n"};
        UART_send(&g_uart,(const uint8_t *)&testmsg1,sizeof(testmsg1));
        SourceCmdSta = 0x0000000;
        config_init(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
        iter=0;
    }
    if( (irq_value&0x00000020) > 0x00000000)
    {
        uint8_t testmsg1[] = {"\n * DisplayPort Source Got HPD Disconnection : \n"};
        UART_send(&g_uart,(const uint8_t *)&testmsg1,sizeof(testmsg1));
        iter=0;

    }
    //
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_RSTPD, &SER_1_PMA_L0_DES_RSTPD_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SER_RSTPD, &SER_1_PMA_L0_SER_RSTPD_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_CDR_CTRL_2, &SER_1_PMA_L0_DES_CDR_CTRL_2_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_CDR_CTRL_3, &SER_1_PMA_L0_DES_CDR_CTRL_3_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFEEM_CTRL_1, &SER_1_PMA_L0_DES_DFEEM_CTRL_1_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFEEM_CTRL_2, &SER_1_PMA_L0_DES_DFEEM_CTRL_2_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFEEM_CTRL_3, &SER_1_PMA_L0_DES_DFEEM_CTRL_3_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFE_CTRL_2, &SER_1_PMA_L0_DES_DFE_CTRL_2_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_EM_CTRL_2, &SER_1_PMA_L0_DES_EM_CTRL_2_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_RXPLL_DIV, &SER_1_PMA_L0_DES_RXPLL_DIV_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SER_CLK_CTRL, &SER_1_PMA_L0_SER_CLK_CTRL_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SERDES_RTL_CTRL, &SER_1_PMA_L0_SERDES_RTL_CTRL_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFE_CAL_CTRL_0, &SER_1_PMA_L0_DES_DFE_CAL_CTRL_0_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFE_CAL_CTRL_1, &SER_1_PMA_L0_DES_DFE_CAL_CTRL_1_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFE_CAL_CTRL_2, &SER_1_PMA_L0_DES_DFE_CAL_CTRL_2_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_DES_DFE_CAL_CMD, &SER_1_PMA_L0_DES_DFE_CAL_CMD_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_TXPLL_DIV_1, &TXPLL_DIV_1);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_TXPLL_DIV_2, &TXPLL_DIV_2);
    //swing registers
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SER_DRV_DATA_CTRL, &SER_1_PMA_L0_SER_DRV_DATA_CTRL_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SER_DRV_CTRL, &SER_1_PMA_L0_SER_DRV_CTRL_R);
    read_dp(DP_DRI_APB_BASE_ADDRESS, SER_1_PMA_L0_SER_DRV_CTRL_SEL, &SER_1_PMA_L0_SER_DRV_CTRL_SEL_R);
}

void DPSourceTxWrCmd(uint32_t addr,uint32_t lenVal,uint32_t txByteNum)
{
    for(uint32_t idx = 0;idx < txByteNum;idx++)
    {
        write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_WRITING_DATA_OFFSET, SourceWrBytes[idx]);
    }

    uint32_t len = txByteNum - 1;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_ADDRESS_OFFSET, addr);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_LENGTH_OFFSET, len);
    uint32_t txCmdReg = (txByteNum << 16) | (lenVal << 8) | 0x00000008;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_COMMAND_OFFSET, txCmdReg);

    SourceCmdSta++;
    SourceCmdTx = 1;
}


void DPSourceTxI2CWrCmd(uint32_t addr,uint32_t lenVal,uint32_t txByteNum,uint32_t mot)
{
    for(uint32_t idx = 0;idx < txByteNum;idx++)
    {
        write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_WRITING_DATA_OFFSET, SourceWrBytes[idx]);
    }

    uint32_t len = txByteNum - 1;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_ADDRESS_OFFSET, addr);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_LENGTH_OFFSET, len);

    uint32_t txCmdReg = (txByteNum << 16) | (lenVal << 8) | (mot << 2) | 0x00000000;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_COMMAND_OFFSET, txCmdReg);

    SourceCmdSta++;
    SourceCmdTx = 1;
}

void DPSourceTxRdCmd(uint32_t addr,uint32_t lenVal,uint32_t rxByteNum)
{
    uint32_t len = rxByteNum - 1;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_ADDRESS_OFFSET, addr);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_LENGTH_OFFSET, len);

    uint32_t txCmdReg = (lenVal << 8) | 0x00000009;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_COMMAND_OFFSET, txCmdReg);

    SourceCmdSta++;
}
void DPSourceTxI2CRdCmd(uint32_t addr,uint32_t lenVal,uint32_t rxByteNum,uint32_t mot)
{
    uint32_t len = rxByteNum - 1;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_ADDRESS_OFFSET, addr);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_LENGTH_OFFSET, len);

    uint32_t txCmdReg = (lenVal << 8) | (mot << 2) | 0x00000001;
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_TX_COMMAND_OFFSET, txCmdReg);

    SourceCmdSta++;
}


void DPSourceStartVideo(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO)
{
    SourceWrBytes[0] = 0x00000000;
    DPSourceTxWrCmd(0x00000102,0x00000001,0x00000001);

    // --------------------------------------
    //      DPSourceStartVideo();
    // -----------------------------------------
    // DP-TX lane number
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_LANE_NUMBER_OFFSET, LANE_NO);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_LANE_ENABLE_OFFSET, 0x0000000F);

    // DP-TX Video Enable
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_VIDEO_STREAM_ENABLE_OFFSET, 0x00000001);
    if(SPEED_MODE==0)
        {
            MSA_VALUE=0x00075555;
        }
        else if (SPEED_MODE==1)
        {
            MSA_VALUE=0x00046666;
        }
        else if (SPEED_MODE==2)
        {
            MSA_VALUE=0x0003F35F;
        }
    // DP-TX 4K MSA
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_MVID_OFFSET, MSA_VALUE);//0x001f9a1);//0x00023333);//0x0008ccd);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_NVID_OFFSET, 0x00080000);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_HTOTAL_OFFSET, (HRES+HBP+HFP+HSW));
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_VTOTAL_OFFSET, (VRES+VBP+VFP+VSW));
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_HSTART_OFFSET, (HSW+HBP));
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_VSTART_OFFSET, (VSW+VBP));
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_HSYNC_OFFSET, HSW);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_VSYNC_OFFSET, (VSP+VSW));// neg pol
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_MISC0_OFFSET, 0x00000021);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_MISC1_OFFSET, 0x00000000);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_HWIDTH_OFFSET, HRES);
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_MSA_VWIDTH_OFFSET, VRES);
          // ------------------------------------------
    // DP-TX Video Enable
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_VIDEO_STREAM_ENABLE_OFFSET, 0x00000001);
    // Enable Scrambler
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_SCRAMBLER_ENABLE_OFFSET, 0x00000001);
    // Disable TPS
    write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_TRAINING_PATTERN_MODE_OFFSET, 0x00000000);

    // Output data from DP-TX
    write_dp(DP_TX_IP_APB_BASE_ADDRESS1, DP_TX_OUTPUT_DATA_OFFSET, 0x80000000);

    iter++;
    seq_rst = 1;
}

void link_training(uint32_t SPEED_MODE,uint32_t HRES,uint32_t VRES,uint32_t HFP,uint32_t HBP,uint32_t VFP,uint32_t VBP,uint32_t HSW,uint32_t VSW,uint32_t VSP,uint32_t LANE_NO)
{
    // -----------------------------------------
    // Received AUX-Reply
    // -----------------------------------------

    uint32_t reply_bytes;
    read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_RX_REPLY_LENGTH_OFFSET, &reply_bytes);
    for(uint32_t i=0;i<reply_bytes;i++)
    {
        uint32_t reply_data;
        read_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_AUX_RX_REPLY_READING_DATA_OFFSET, &reply_data);
        if(SourceCmdSta == 0x0000000B)
        {
            if(i==3)
            {
                tps3_supported= reply_data&0x40;
                if(tps3_supported)
                    UART_send(&g_uart,"\r\nTPS3 Supported\n\r",sizeof("\r\nTPS3 Supported\n\r"));
                else
                    UART_send(&g_uart,"\r\nTPS3 not Supported\n\r",sizeof("\r\nTPS3 not Supported\n\r"));

            }
        }
         if(SourceCmdSta == 0x00000025 || SourceCmdSta == 0x00000027 )
         {
            if(i==1)
            {
                if(reply_data==0x11)
                    lane_01_cr_done = 0x01;
                else
                    lane_01_cr_done = 0x00;
            }
            if(i==2)
            {
                if(reply_data==0x11)
                    lane_23_cr_done = 0x01;
                else
                    lane_23_cr_done = 0x00;
            }
            if(i==5)
            {
                reply_data_pe1 = reply_data&0xc0;
                reply_data_vs1 = reply_data&0x30;
                reply_data_pe0 = reply_data&0x0c;
                reply_data_vs0 = reply_data&0x03;
                if(reply_data_vs0==0)
                    reply_sw_0 = 0;
                else if (reply_data_vs0==0x1)
                    reply_sw_0 = 1;
                else if (reply_data_vs0==0x2)
                    reply_sw_0 = 2;
                else if (reply_data_vs0==0x3)
                    reply_sw_0 = 7;
                if(reply_data_vs1==0)
                    reply_sw_1 = 0;
                else if (reply_data_vs1==0x10)
                    reply_sw_1 = 1;
                else if (reply_data_vs1==0x20)
                    reply_sw_1 = 2;
                else if (reply_data_vs1==0x30)
                    reply_sw_1 = 7;
                if(reply_data_pe0==0)
                    reply_pe_0 = 0;
                else if (reply_data_pe0==0x4)
                    reply_pe_0 = 1;
                else if (reply_data_pe0==0x8)
                    reply_pe_0 = 2;
                else if (reply_data_pe0==0xc)
                    reply_pe_0 = 7;
                if(reply_data_pe1==0)
                    reply_pe_1 = 0;
                else if (reply_data_pe1==0x40)
                    reply_pe_1 = 1;
                else if (reply_data_pe1==0x80)
                    reply_pe_1 = 2;
                else if (reply_data_pe1==0xc0)
                    reply_pe_1 = 7;
            }
            if(i==6)
            {
                reply_data_pe3 = reply_data&0xc0;
                reply_data_vs3 = reply_data&0x30;
                reply_data_pe2 = reply_data&0x0c;
                reply_data_vs2 = reply_data&0x03;
                if(reply_data_vs2==0)
                    reply_sw_2 = 0;
                else if (reply_data_vs2==0x1)
                    reply_sw_2 = 1;
                else if (reply_data_vs2==0x2)
                    reply_sw_2 = 2;
                else if (reply_data_vs2==0x3)
                    reply_sw_2 = 7;
                if(reply_data_vs3==0)
                    reply_sw_3 = 0;
                else if (reply_data_vs3==0x10)
                    reply_sw_3 = 1;
                else if (reply_data_vs3==0x20)
                    reply_sw_3 = 2;
                else if (reply_data_vs3==0x30)
                    reply_sw_3 = 7;
                if(reply_data_pe2==0)
                    reply_pe_2 = 0;
                else if (reply_data_pe2==0x4)
                    reply_pe_2 = 1;
                else if (reply_data_pe2==0x8)
                    reply_pe_2 = 2;
                else if (reply_data_pe2==0xc)
                    reply_pe_2 = 7;
                if(reply_data_pe3==0)
                    reply_pe_3 = 0;
                else if (reply_data_pe3==0x40)
                    reply_pe_3 = 1;
                else if (reply_data_pe3==0x80)
                    reply_pe_3 = 2;
                else if (reply_data_pe3==0xc0)
                    reply_pe_3 = 7;
                if(LANE_NO==0x4)
                {
                    if(lane_01_cr_done==0x01 && lane_23_cr_done==0x01) // cr done for all lanes goto tps2
                    {
                        SourceCmdSta = 0x00000028;
                    }
                    else
                    {
                        SourceCmdSta = 0x00000025;
                    }
                }
                else
                {
                    if(lane_01_cr_done==0x01) // cr done for all lanes goto tps2
                   {
                       SourceCmdSta = 0x00000028;
                   }
                   else
                   {
                       SourceCmdSta = 0x00000025;
                   }
                }
            }

         }
         if(SourceCmdSta == 0x0000002A )
         {
            if(i==1)
            {
                reply_data_cr_01 = reply_data&0x11;
                reply_data_eq_01 = reply_data;
            }
            if(i==2)
            {
                reply_data_cr_23 = reply_data&0x11;
                reply_data_eq_23 = reply_data;
            }
            if(i==5)
            {
                reply_data_pe1 = reply_data&0xc0;
                reply_data_vs1 = reply_data&0x30;
                reply_data_pe0 = reply_data&0x0c;
                reply_data_vs0 = reply_data&0x03;
                if(reply_data_vs0==0)
                    reply_sw_0 = 0;
                else if (reply_data_vs0==0x1)
                    reply_sw_0 = 1;
                else if (reply_data_vs0==0x2)
                    reply_sw_0 = 2;
                else if (reply_data_vs0==0x3)
                    reply_sw_0 = 7;
                if(reply_data_vs1==0)
                    reply_sw_1 = 0;
                else if (reply_data_vs1==0x10)
                    reply_sw_1 = 1;
                else if (reply_data_vs1==0x20)
                    reply_sw_1 = 2;
                else if (reply_data_vs1==0x30)
                    reply_sw_1 = 7;
                if(reply_data_pe0==0)
                    reply_pe_0 = 0;
                else if (reply_data_pe0==0x4)
                    reply_pe_0 = 1;
                else if (reply_data_pe0==0x8)
                    reply_pe_0 = 2;
                else if (reply_data_pe0==0xc)
                    reply_pe_0 = 7;
                if(reply_data_pe1==0)
                    reply_pe_1 = 0;
                else if (reply_data_pe1==0x40)
                    reply_pe_1 = 1;
                else if (reply_data_pe1==0x80)
                    reply_pe_1 = 2;
                else if (reply_data_pe1==0xc0)
                    reply_pe_0 = 7;
            }
            if(i==6)
            {
                reply_data_pe3 = reply_data&0xc0;
                reply_data_vs3 = reply_data&0x30;
                reply_data_pe2 = reply_data&0x0c;
                reply_data_vs2 = reply_data&0x03;
                if(reply_data_vs2==0)
                    reply_sw_2 = 0;
                else if (reply_data_vs2==0x1)
                    reply_sw_2 = 1;
                else if (reply_data_vs2==0x2)
                    reply_sw_2 = 2;
                else if (reply_data_vs2==0x3)
                    reply_sw_2 = 7;
                if(reply_data_vs3==0)
                    reply_sw_3 = 0;
                else if (reply_data_vs3==0x10)
                    reply_sw_3 = 1;
                else if (reply_data_vs3==0x20)
                    reply_sw_3 = 2;
                else if (reply_data_vs3==0x30)
                    reply_sw_3 = 7;
                if(reply_data_pe2==0)
                    reply_pe_2 = 0;
                else if (reply_data_pe2==0x4)
                    reply_pe_2 = 1;
                else if (reply_data_pe2==0x8)
                    reply_pe_2 = 2;
                else if (reply_data_pe2==0xc)
                    reply_pe_2 = 7;
                if(reply_data_pe3==0)
                    reply_pe_3 = 0;
                else if (reply_data_pe3==0x40)
                    reply_pe_3 = 1;
                else if (reply_data_pe3==0x80)
                    reply_pe_3 = 2;
                else if (reply_data_pe3==0xc0)
                    reply_pe_3 = 7;
            }
            if(SourceCmdSta == 0x0000002A & i==6)
            {
               if(LANE_NO==4)
               {
                if(reply_data_cr_01==0x11 & reply_data_cr_23==0x11)
                {
                    if(reply_data_eq_01==0x77 & reply_data_eq_23 ==0x77)
                    {
                        SourceCmdSta = 0x0000002B;
                    }
                    else
                    {
                        SourceCmdSta = 0x00000028;
                    }
                }
                else
                {
                    SourceCmdSta = 0x00000025;
                }
               }
               else
               {
                   if(reply_data_cr_01==0x11 )
                      {
                          if(reply_data_eq_01==0x77 )
                          {
                              SourceCmdSta = 0x0000002B;
                          }
                          else
                          {
                              SourceCmdSta = 0x00000028;
                          }
                      }
                      else
                      {
                          SourceCmdSta = 0x00000025;
                      }
               }
            }
         }
    }

    if(SourceCmdSta == 0x00000001)
    {
        DPSourceTxRdCmd(0x00000200,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000002)
    {
        DPSourceTxRdCmd(0x00000000,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000003)
    {
        DPSourceTxRdCmd(0x00000500,0x00000001,0x0000000B);
    }
    else if(SourceCmdSta == 0x00000004)
    {
        DPSourceTxRdCmd(0x00000600,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000005)
    {
        SourceWrBytes[0] = 0x00000001;
        DPSourceTxWrCmd(0x00000600,0x00000001,0x00000001); //SET_POWER & SET_DP_PWR_VOLTAGE
    }
    else if(SourceCmdSta == 0x00000006)
    {
       SourceWrBytes[0] = 0x00000080;
        DPSourceTxWrCmd(0x00000300,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000007)
    {
       SourceWrBytes[0] = 0x00000034;
        DPSourceTxWrCmd(0x00000301,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000008)
    {
       SourceWrBytes[0] = 0x00000028;
        DPSourceTxWrCmd(0x00000302,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x00000009)
    {
       DPSourceTxRdCmd(0x0000000E,0x00000001,0x00000001);
    }
    else if(SourceCmdSta == 0x0000000A)
    {
       DPSourceTxRdCmd(0x00000000,0x00000001,0x0000000E);
    }
    else if(SourceCmdSta == 0x0000000B)
    {
       DPSourceTxRdCmd(0x00000080,0x00000001,0x00000004);
    }
    else if(SourceCmdSta == 0x0000000C)
    {
        SourceWrBytes[0] = 0x00000000;
        DPSourceTxI2CWrCmd(0x00000050,0x00000001,0x00000001,0x00000001);  //0x00043 to 0x00053 -- Reserved
    }
    else if(SourceCmdSta >= 0x000000D && SourceCmdSta <= 0x00000014)
    {
        DPSourceTxI2CRdCmd(0x00000050,0x00000001,0x00000010,0x00000001);
    }
    else if(SourceCmdSta == 0x0000015)
    {
        SourceWrBytes[0] = 0x00000080;
        DPSourceTxI2CWrCmd(0x00000050,0x00000001,0x00000001,0x00000001);
    }
    else if(SourceCmdSta >= 0x0000016 && SourceCmdSta <= 0x0000001C)
    {
        DPSourceTxI2CRdCmd(0x00000050,0x00000001,0x00000010,0x00000001);
    }
    else if(SourceCmdSta == 0x0000001D)
    {
        DPSourceTxI2CRdCmd(0x00000050,0x00000001,0x00000010,0x00000000);
    }
    else if(SourceCmdSta == 0x0000001E)
    {
        SourceWrBytes[0] = 0x00000000;
        DPSourceTxWrCmd(0x00000111,0x00000001,0x00000001); //00111h MSTM_CTRL
        //1 = UFP shall transmit audio/visual data in Multi-Stream Transport (MST) mode.
    }
    else if(SourceCmdSta == 0x0000001F)
    {
        SourceWrBytes[0] = 0x00000000;
        DPSourceTxWrCmd(0x00000107,0x00000001,0x00000001); //DOWNSPREAD_CTRL
    }
    else if(SourceCmdSta == 0x00000020)
    {
        SourceWrBytes[0] = 0x00000001;
        DPSourceTxWrCmd(0x00000600,0x00000001,0x00000001); //SET_POWER & SET_DP_PWR_VOLTAGE
    }
    else if(SourceCmdSta == 0x00000021)
    {
        SourceWrBytes[0] = 0x00000020;
        DPSourceTxWrCmd(0x00000102,0x00000001,0x00000001); //TRAINING_PATTERN_SET
        //01b = Link Training Pattern Sequence 1.

    }
    else if(SourceCmdSta == 0x00000022)
    {
        if(SPEED_MODE==0)
            {
                SPEED=0x00000006;
            }
            else if (SPEED_MODE==1)
            {
                SPEED=0x0000000A;
            }
            else if (SPEED_MODE==2)
            {
                SPEED=0x00000014;
            }
        SourceWrBytes[0] = SPEED;  //2.7Gbps   //0x00000014;
        //HBR2 - Main-Link Bandwidth Setting = Value × 0.27Gbps/lane = 5.4Gbps/lane
        SourceWrBytes[1] = LANE_NO;
        DPSourceTxWrCmd(0x00000100,0x00000001,0x00000002);//LINK_BW_SET
    }
    else if(SourceCmdSta == 0x00000023)
    {

        // Disable Scrambler
         write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_SCRAMBLER_ENABLE_OFFSET, 0x00000000);
         write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_TRAINING_PATTERN_MODE_OFFSET, 0x00000001);  //TPS1

        SourceWrBytes[0] = 0x00000021;//TRAINING_PATTERN_SET
        //initialsing with voltage sw & pe
        if(reply_data_vs0==0)
                   vs = 0;
               else if (reply_data_vs0==0x1)
                   vs = 1;
               else if (reply_data_vs0==0x2)
                   vs = 2;
               else if (reply_data_vs0==0x3)
                   vs = 3;

               if(reply_data_pe0==0)
                   pe = 0;
               else if (reply_data_pe0==0x4)
                   pe = 1;
               else if (reply_data_pe0==0x8)
                   pe = 2;
               else if (reply_data_pe0==0xc)
                   pe = 3;

                if(vs==0 && pe==0)
                    vsw_pe(0x0,0x0);
                else if (vs==0 && pe==1)
                    vsw_pe(0x0,0x1);
                else if (vs==0 && pe==2)
                    vsw_pe(0x0,0x2);
                else if (vs==1 && pe==0)
                    vsw_pe(0x1,0x0);
                else if (vs==1 && pe==1)
                    vsw_pe(0x1,0x1);
                else if (vs==1 && pe==2)
                    vsw_pe(0x1,0x2);
                else if (vs==2 && pe==0)
                    vsw_pe(0x2,0x0);
                else if (vs==2 && pe==1)
                    vsw_pe(0x2,0x1);
                else if (vs==2 && pe==2)
                    vsw_pe(0x2,0x2);
                else if (vs==3 && pe==0)
                    vsw_pe(0x3,0x0);
                else if (vs==3 && pe==1)
                    vsw_pe(0x3,0x1);
                else if (vs==3 && pe==2)
                    vsw_pe(0x3,0x2);
                else
                    vsw_pe(0x3,0x3);


        SourceWrBytes[1] = 0x00000000;//TRAINING_LANE0_SET
        SourceWrBytes[2] = 0x00000000;
        SourceWrBytes[3] = 0x00000000;
        SourceWrBytes[4] = 0x00000000;
        DPSourceTxWrCmd(0x00000102,0x00000001,0x00000005);

    }
    else if(SourceCmdSta == 0x00000024)
    {

        //delay_msec(10);
        msdelay(10);
        DPSourceTxRdCmd(0x00000202,0x00000001,0x00000006);
        //Lane 0 and Lane 1 Status
    }
    else if(SourceCmdSta == 0x00000025)
    {

        SourceWrBytes[0] = 0x00000021;
        if(reply_data_vs0==0)
           vs = 0;
       else if (reply_data_vs0==0x1)
           vs = 1;
       else if (reply_data_vs0==0x2)
           vs = 2;
       else if (reply_data_vs0==0x3)
           vs = 3;

       if(reply_data_pe0==0)
           pe = 0;
       else if (reply_data_pe0==0x4)
           pe = 1;
       else if (reply_data_pe0==0x8)
           pe = 2;
       else if (reply_data_pe0==0xc)
           pe = 3;

        if(vs==0 && pe==0)
            vsw_pe(0x0,0x0);
        else if (vs==0 && pe==1)
            vsw_pe(0x0,0x1);
        else if (vs==0 && pe==2)
            vsw_pe(0x0,0x2);
        else if (vs==1 && pe==0)
            vsw_pe(0x1,0x0);
        else if (vs==1 && pe==1)
            vsw_pe(0x1,0x1);
        else if (vs==1 && pe==2)
            vsw_pe(0x1,0x2);
        else if (vs==2 && pe==0)
            vsw_pe(0x2,0x0);
        else if (vs==2 && pe==1)
            vsw_pe(0x2,0x1);
        else if (vs==2 && pe==2)
            vsw_pe(0x2,0x2);
        else if (vs==3 && pe==0)
            vsw_pe(0x3,0x0);
        else if (vs==3 && pe==1)
            vsw_pe(0x3,0x1);
        else if (vs==3 && pe==2)
            vsw_pe(0x3,0x2);
        else
            vsw_pe(0x3,0x3);

        if(LANE_NO==4)
        {
        if(reply_sw_0==reply_sw_1&&reply_sw_1==reply_sw_2&&reply_sw_2==reply_sw_3&&reply_sw_3==reply_sw_0)
        {
            SourceWrBytes[1] = ((reply_pe_0*8)+reply_sw_0);
           SourceWrBytes[2] = ((reply_pe_1*8)+reply_sw_1);
           SourceWrBytes[3] = ((reply_pe_2*8)+reply_sw_2);
           SourceWrBytes[4] = ((reply_pe_3*8)+reply_sw_3);
           DPSourceTxWrCmd(0x00000102,0x00000001,0x00000005);
        }

        else
            {
                DPSourceTxRdCmd(0x00000202,0x00000001,0x00000006);
                SourceCmdSta = 0x00000001;
                irq_value = 0x00000008;
            }
        }
        else
        {
            if(reply_sw_0==reply_sw_1)
            {
                SourceWrBytes[1] = ((reply_pe_0*8)+reply_sw_0);
               SourceWrBytes[2] = ((reply_pe_1*8)+reply_sw_1);
               SourceWrBytes[3] = ((reply_pe_2*8)+reply_sw_2);
               SourceWrBytes[4] = ((reply_pe_3*8)+reply_sw_3);
               DPSourceTxWrCmd(0x00000102,0x00000001,0x00000005);
            }
            else
            {

                DPSourceTxRdCmd(0x00000202,0x00000001,0x00000006);
                if(LANE_NO==4)
                {
                SourceCmdSta = 0x00000001;
                irq_value = 0x00000008;
                }

            }
        }
    }
    else if(SourceCmdSta == 0x00000026)
    {


//        delay_msec(10);
        msdelay(10);
        DPSourceTxRdCmd(0x00000202,0x00000001,0x00000006);
        //Lane 0 and Lane 1 Status
    }
    else if(SourceCmdSta == 0x00000028)
    {
        // ----------- TPS4 ---------------
        // Transmit TPS4
        //write_dp(DP_TX_IP_APB_BASE_ADDRESS1, DP_TX_OUTPUT_DATA_OFFSET, 0x40000000);

        // ----------- TPS3 ---------------
        // Scrambler disable
        write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_SCRAMBLER_ENABLE_OFFSET, 0x00000000);
        if(tps3_supported )
        {
            write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_TRAINING_PATTERN_MODE_OFFSET, 0x00000003);  //TPS3
            SourceWrBytes[0] = 0x00000023;
            UART_send(&g_uart,(const uint8_t *)"Sending tps3\n\r",sizeof("sending tps3\n\r"));
        }
        else
        {
            write_dp(DP_TX_IP_APB_BASE_ADDRESS, DP_TX_TRAINING_PATTERN_MODE_OFFSET, 0x00000002);  //TPS2
            SourceWrBytes[0] = 0x00000022;
            UART_send(&g_uart,(const uint8_t *)"sending tps2\n\r",sizeof("sending tps2\n\r"));
        }
        if(reply_data_vs0==0)
           vs = 0;
       else if (reply_data_vs0==0x1)
           vs = 1;
       else if (reply_data_vs0==0x2)
           vs = 2;
       else if (reply_data_vs0==0x3)
           vs = 3;

       if(reply_data_pe0==0)
           pe = 0;
       else if (reply_data_pe0==0x4)
           pe = 1;
       else if (reply_data_pe0==0x8)
           pe = 2;
       else if (reply_data_pe0==0xc)
           pe = 3;
#if 1
        if(vs==0 && pe==0)
            vsw_pe(0x0,0x0);
        else if (vs==0 && pe==1)
            vsw_pe(0x0,0x1);
        else if (vs==0 && pe==2)
            vsw_pe(0x0,0x2);
        else if (vs==1 && pe==0)
            vsw_pe(0x1,0x0);
        else if (vs==1 && pe==1)
            vsw_pe(0x1,0x1);
        else if (vs==1 && pe==2)
            vsw_pe(0x1,0x2);
        else if (vs==2 && pe==0)
            vsw_pe(0x2,0x0);
        else if (vs==2 && pe==1)
            vsw_pe(0x2,0x1);
        else if (vs==2 && pe==2)
            vsw_pe(0x2,0x2);
        else if (vs==3 && pe==0)
            vsw_pe(0x3,0x0);
        else if (vs==3 && pe==1)
            vsw_pe(0x3,0x1);
        else if (vs==3 && pe==2)
            vsw_pe(0x3,0x2);
        else
            vsw_pe(0x3,0x3);
#endif
        SourceWrBytes[1]  =  ((reply_pe_0*8)+reply_sw_0);
        SourceWrBytes[2]  =  ((reply_pe_1*8)+reply_sw_1);
         SourceWrBytes[3] = ((reply_pe_2*8)+reply_sw_2);
        SourceWrBytes[4]  =  ((reply_pe_3*8)+reply_sw_3);
        DPSourceTxWrCmd(0x00000102,0x00000001,0x00000005);
    }
    else if(SourceCmdSta == 0x00000029)
    {
//        delay_msec(100);
        msdelay(100);
        DPSourceTxRdCmd(0x00000202,0x00000001,0x00000006);
    }
    else if(SourceCmdSta == 0x0000002B)
    {
//        delay_msec(100);
        msdelay(100);
        DPSourceStartVideo(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
    }
}



//DRI
void update_speed(uint32_t data )
{

    if (data == 0x01) //2.7G
    {
#if 0
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_3, 0x40100);//DES_CDR_CTRL_3//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CTRL_2, 0x4000005);//DES_DFE_CTRL_2//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_EM_CTRL_2, 0x5);//DES_EM_CTRL_2//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RXPLL_DIV, 0x420c);//DES_RXPLL_DIV//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_CLK_CTRL, 0x75);//SER_CLK_CTRL//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_0, 0xff3f0715);//DES_DFE_CAL_CTRL_0//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_1, 0x101481d);//DES_DFE_CAL_CTRL_1//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_2, 0x400010);//DES_DFE_CAL_CTRL_1//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_1,0x180014 );//TXPLL_DIV_1//IN PMA cmn
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_2,0x100000 );//TXPLL_DIV_2//IN PMA cmn
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
# endif
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_1,0x14000C );//TXPLL_DIV_1//IN PMA cmn
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_2,0x1000000 );//TXPLL_DIV_2//IN PMA cmn


        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE

    }
    else if(data == 0x00) //1.62G
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_1,0x180008 );//TXPLL_DIV_1//IN PMA cmn
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_2,0x2000000 );//TXPLL_DIV_2//IN PMA cmn


        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
    }
    else //5.4 gbps
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_2, 0xf15);//DES_CDR_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_CDR_CTRL_3, 0x0);//DES_CDR_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_1, 0x15);//DES_DFEEM_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_2, 0x0);//DES_DFEEM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFEEM_CTRL_3, 0x0);//DES_DFEEM_CTRL_3//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CTRL_2, 0x0);//DES_DFE_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_EM_CTRL_2, 0x0);//DES_EM_CTRL_2//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RXPLL_DIV, 0x2219);//DES_RXPLL_DIV//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_CLK_CTRL, 0x71);//SER_CLK_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SERDES_RTL_CTRL, 0x0);//SERDES_RTL_CTRL//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_0, 0x64100702);//DES_DFE_CAL_CTRL_0//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_1, 0x1034018);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CTRL_2, 0x800000);//DES_DFE_CAL_CTRL_1//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_DFE_CAL_CMD, 0x00);//DES_DFE_CAL_CMD//IN PMA LANE

       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_1,0x280016 );//TXPLL_DIV_1//IN PMA cmn
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_TXPLL_DIV_2,0x1000000 );//TXPLL_DIV_2//IN PMA cmn

        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
       write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
    }

}
//voltage swing and pre emphasis
void vsw_pe(uint32_t sw,uint32_t pe)
{
    write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x33);//DES_RSTPD//  IN PMA LANE
           write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
           write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
           write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
           write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x3);//SER_RSTPD// IN PMA LANE
    if (sw == 0x00 && pe == 0x00)
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x25);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x25);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x25);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x25);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if(sw == 0x00 && pe == 0x01)
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0xd);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0xd);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0xd);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0xd);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x00 && pe == 0x02)
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x4d);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x4d);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x4d);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x4d);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x01 && pe == 0x00 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x21);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x21);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x21);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x21);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x01 && pe == 0x01 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x9);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x9);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x9);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x9);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x01 && pe == 0x02 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x49);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x49);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x49);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x49);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x02 && pe == 0x00 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x36FFFFEC);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x36FFFFEC);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x36FFFFEC);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x36FFFFEC);
    }
    else if (sw == 0x02 && pe == 0x01 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x5);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x5);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x5);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x5);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x02 && pe == 0x02 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x45);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x45);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x45);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x45);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x03 && pe == 0x00 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x56FFFFED);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x56FFFFED);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x56FFFFED);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0xAAAA);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x56FFFFED);
    }
    else if (sw == 0x03 && pe == 0x01 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x1);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x1);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x1);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x1);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else if (sw == 0x03 && pe == 0x02 )
    {
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x41);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x41);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x41);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x41);
        write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);
    }
    else
        {
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_DATA_CTRL, 0x0);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL_SEL, 0x41);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_DRV_CTRL, 0x11000000);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_DATA_CTRL, 0x0);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL_SEL, 0x41);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_DRV_CTRL, 0x11000000);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_DATA_CTRL, 0x0);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL_SEL, 0x41);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_DRV_CTRL, 0x11000000);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_DATA_CTRL, 0x0);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL_SEL, 0x41);
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_DRV_CTRL, 0x11000000);

        }

            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_DES_RSTPD, 0x1);//DES_RSTPD//  IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L0_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L1_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L2_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE
            write_dp(DP_DRI_APB_BASE_ADDRESS,SER_1_PMA_L3_SER_RSTPD, 0x30);//SER_RSTPD// IN PMA LANE

}
