   1              		.file	"miv_rv32_hal.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0_c2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.MRV_read_mtime,"ax",@progbits
  10              		.align	1
  12              	MRV_read_mtime:
  13              	.LFB18:
  14              		.file 1 "../src/platform/miv_rv32_hal/miv_rv32_hal.h"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * 
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*=========================================================================*//**
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Introduction
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, see
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-tools/m
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIV_RV32 Core and this document use the following terms:
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ==============================================================================
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32 preprocessor, macros have been
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted. The HAL is used
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   to target the mentioned platforms by adding the following macros in Project
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Properties > C/C++ Build > Settings > Preprocessor available in the Assembler
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   and Compiler settings. The following table shows the macros corresponding to the
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV Core being used in your libero project. By default, the HAL targets v3.1 of
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the IP core and no macros need to be set for this configutation.
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-----------------------------|-------------------|
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt Handling
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   configurator.
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the value stored in the 
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   handler is as an interrupt service routine.
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32.
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****    
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   unchanged.
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Floating Point Interrupt Support
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Softconsole build settings.
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   when the ISR does not use FP insturctions and saving the general purpose 
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   register context is sufficient.
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. Refer to the MIV_RV32 v3.1 Handbook for
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   more details.  
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   NOTE: This was previously (MIV_RV32 v3.0) known as OPSRV, which stands for 
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   "Offload Processor Subsystem for RISC-V". See the earlier versions of the 
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   handbook for more details. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *//*=========================================================================*/
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define RISCV_HAL_H
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "../../boards/polarfire-video-kit/fpga_design_config/fpga_design_config.h"
 181:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "hw_platform.h"
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 185:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef __cplusplus
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** extern "C" {
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 194:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****    
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------------|--------------------------|
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine timer interrupt
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTIME and MTIMECMP
 220:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   possible combinations:
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 228:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   core as input.
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt.
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32 core design.
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   available internally to the core.
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   --------------------------------
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   External IRQ
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   External Interrupt.
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|--------|----------------|
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_DELTA                     5
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 307:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIMPID Register
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Soft IP core version.
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (0u)
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (0u)
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   RISC-V Specification Interrupts
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =======================================
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   in the MIE/MIP registers.
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, following table shows the 
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt priority order and register description as mentioned in the RISC-V spec.
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |-------------------|--------|----------------|
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 365:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 366:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 367:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 368:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   BootROM
 369:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   =================================
 370:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When BootROM is enabled, on reset, the core copies data from a memory mapped
 371:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   source memory into a destination memory location and then the core boots from
 372:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the destination memory location. The source start or end addresses and the
 373:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   destination start address can be provided through GUI inputs. If the 
 374:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Reconfigurable option is enabled, then the addresses become software 
 375:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   reconfigurable, which can be used with a soft reset to reboot and run alternative
 376:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   code. The source and destination memory must be a memory mapped location 
 377:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   accessible by the core across the full transfer size.
 378:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 379:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MTVEC address - By default, the mtvec.BASE is set at Reset Vector Address + 0x04.
 380:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When the BootROM is enabled, the mtvec.BASE is set at destination address + 0x04.
 381:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When using Reconfigurable BootROM, the MTVEC register needs to be defined 
 382:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   and programmed through software.
 383:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 384:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Reset Behaviour - With the BootROM feature enabled, upon reset, the PC takes on
 385:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the value of the BootROM dest_addr. When the BootROM is enabled, ensure that the
 386:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   boot code linker script matches the dest_addr, since booting starts from the
 387:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   destination_addr.
 388:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 389:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   BootROM Register Map:
 390:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |  Name  |  Address  | Description |
 391:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   |--------|-----------|-------------|
 392:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | src_start_addr     |0xA100| Core copies data beginning here       |
 393:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | src_end_addr       |0xA104| Last address copied by BootROM        |
 394:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   | destination_addr   |0xA108| Destination memory beginning from here|
 395:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 396:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** */
 397:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 398:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define BOOTROM_START                    0x0000A100
 399:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define BOOTROM_END                      0x0000A104
 400:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define BOOTROM_DEST                     0x0000A108
 401:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 402:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 403:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt numbers:
 404:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 405:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 406:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** enum
 407:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 408:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 409:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 411:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 412:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 414:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 415:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 416:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 417:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 418:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 419:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 420:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 421:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 422:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 423:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 424:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 425:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 426:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 427:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 428:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 429:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 430:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 431:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 432:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 433:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 434:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 435:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 436:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 437:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 438:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 439:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 440:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 441:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 442:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 443:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 444:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 445:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 446:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 447:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 448:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 449:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 450:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 451:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 452:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 453:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 454:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 455:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 456:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 457:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 458:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 459:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 460:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 461:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 462:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 463:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 464:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 465:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 466:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 467:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 468:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 469:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 470:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 471:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 472:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 473:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 474:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 475:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 476:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   */
 477:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 478:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 479:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     uint32_t temp;
 480:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 481:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 482:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "sw x31, %0"
 483:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"=m" (temp));
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 485:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ volatile (
 486:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x1;"
 487:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x1, x31;"
 488:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 489:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x2;"
 490:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x2, x31;"
 491:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 492:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x3;"
 493:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x3, x31;"
 494:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 495:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x4;"
 496:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x4, x31;"
 497:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 498:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x5;"
 499:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x5, x31;"
 500:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 501:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x6;"
 502:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x6, x31;"
 503:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 504:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x7;"
 505:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x7, x31;"
 506:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 507:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x8;"
 508:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x8, x31;"
 509:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 510:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x9;"
 511:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x9, x31;"
 512:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 513:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x10;"
 514:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x10, x31;"
 515:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 516:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x11;"
 517:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x11, x31;"
 518:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 519:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x12;"
 520:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x12, x31;"
 521:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 522:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x13;"
 523:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x13, x31;"
 524:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 525:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x14;"
 526:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x14, x31;"
 527:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 528:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x15;"
 529:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x15, x31;"
 530:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 531:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x16;"
 532:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x16, x31;"
 533:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 534:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x17;"
 535:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x17, x31;"
 536:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 537:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x18;"
 538:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x18, x31;"
 539:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 540:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x19;"
 541:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x19, x31;"
 542:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 543:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x20;"
 544:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x20, x31;"
 545:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 546:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x21;"
 547:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x21, x31;"
 548:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 549:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x22;"
 550:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x22, x31;"
 551:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 552:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x23;"
 553:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x23, x31;"
 554:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 555:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x24;"
 556:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x24, x31;"
 557:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 558:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x25;"
 559:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x25, x31;"
 560:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 561:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x26;"
 562:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x26, x31;"
 563:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 564:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x27;"
 565:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x27, x31;"
 566:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 567:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x28;"
 568:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x28, x31;"
 569:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 570:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x29;"
 571:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x29, x31;"
 572:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 573:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x30;"
 574:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x30, x31;");
 575:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 576:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 577:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "lw x31, %0;"
 578:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :
 579:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"m" (temp));
 580:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 581:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 582:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 583:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 584:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 585:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 586:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   IP configurator.
 587:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 588:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 589:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 590:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 591:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 592:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 593:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 594:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 595:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 596:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 597:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 598:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 599:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   configurator.
 600:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 601:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return 
 602:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 603:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 604:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 605:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 606:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 607:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 608:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 609:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 610:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 611:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 612:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 613:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 614:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 615:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 616:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 617:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 618:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 619:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 620:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, mask);
 621:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 622:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 623:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 624:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_disable_local_irq() function disables the local interrupts. It takes a 
 625:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 626:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   interrupt bit in the MIE register is disabled.
 627:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   
 628:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MRV_disable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 629:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                          MRV32_MSYS_EIE0_IRQn |
 630:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                          MRV32_MSYS_SUBSYS_IRQn);
 631:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 632:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 633:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 634:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mie, mask);
 635:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 636:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /* MIV_LEGACY_RV32 */ 
 637:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 638:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 639:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_enable_interrupts() function enables all interrupts by setting the
 640:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 641:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 642:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 643:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 644:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 645:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 646:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 647:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 648:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_interrupts(void)
 649:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
 651:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 652:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 653:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 654:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_disable_interrupts() function disables all interrupts by clearing the
 655:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   machine mode interrupt enable bit in MSTATUS register.
 656:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 657:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 658:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 659:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 660:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 661:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 662:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_disable_interrupts(void)
 663:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 664:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MPIE);
 665:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MIE);
 666:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 667:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 668:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 669:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_read_mtvec_base() function reads the mtvec base value, which is the 
 670:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   address used when an interrupt/trap occurs. In the mtvec register, [31:2] is the 
 671:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   BASE address. NOTE: The BASE address must be aligned on a 4B boundary.
 672:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 673:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 674:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The function does not take any parameters.
 675:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 676:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 677:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The function returns the value of the BASE field [31:2] as an unsigned 32-bit 
 678:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   value.
 679:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 680:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 681:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_LEGACY_RV32
 682:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_v3_0
 683:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline uint32_t MRV_read_mtvec_base (void)
 684:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 685:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     uint32_t mtvec_addr_base = read_csr(mtvec);
 686:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     return mtvec_addr_base & MTVEC_BASE_ADDR_MASK;
 687:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 688:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 689:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 690:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_set_mtvec_base() function takes the mtvec_base address as a unsigned int 
 691:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   and writes the value into the BASE field [31:2] in the mtvec CSR, MODE[1:0] 
 692:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   is Read-only. BASE is 4B aligned, so the lowest 2 bits of mtvec_base are 
 693:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   ignored.
 694:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 695:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param mtvec_base
 696:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Any legal value is passed into the function, and it is used as the trap_entry 
 697:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   for interrupts. The PC jumps to this address provided when an interrupt occurs. 
 698:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   In case of vectored interrupts, the address value mentioned in the vector 
 699:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   table under the MIE Register Map is updated to the value passed to this 
 700:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   function parameter.
 701:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 702:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 703:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 704:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 705:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_set_mtvec_base (uint32_t mtvec_base)
 706:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 707:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     mtvec_base = mtvec_base & MTVEC_BASE_ADDR_MASK;
 708:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     write_csr(mtvec, mtvec_base);
 709:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 710:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_RV32_v3_0*/
 711:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /*MIV_LEGACY_RV32*/
 712:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 713:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 714:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_read_mtime() function returns the current MTIME register value.
 715:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 716:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline uint64_t MRV_read_mtime(void)
 717:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
  15              		.loc 1 717 1
  16              		.cfi_startproc
 718:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t hi = 0u;
  17              		.loc 1 718 5
 717:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t hi = 0u;
  18              		.loc 1 717 1 is_stmt 0
  19 0000 4111     		addi	sp,sp,-16
  20              		.cfi_def_cfa_offset 16
  21              		.loc 1 718 23
  22 0002 02C4     		sw	zero,8(sp)
 719:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t lo = 0u;
  23              		.loc 1 719 5 is_stmt 1
  24              		.loc 1 719 23 is_stmt 0
  25 0004 02C6     		sw	zero,12(sp)
 720:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 721:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
 722:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****      * returned value could be wrong. */
 723:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     do {
 724:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****         hi = MTIMEH;
  26              		.loc 1 724 14
  27 0006 B7C70002 		li	a5,33603584
  28              	.L2:
 723:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****         hi = MTIMEH;
  29              		.loc 1 723 5 is_stmt 1 discriminator 1
  30              		.loc 1 724 9 discriminator 1
  31              		.loc 1 724 14 is_stmt 0 discriminator 1
  32 000a 83A6C7FF 		lw	a3,-4(a5)
  33              		.loc 1 724 12 discriminator 1
  34 000e 36C4     		sw	a3,8(sp)
 725:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****         lo = MTIME;
  35              		.loc 1 725 9 is_stmt 1 discriminator 1
  36              		.loc 1 725 14 is_stmt 0 discriminator 1
  37 0010 83A687FF 		lw	a3,-8(a5)
  38              		.loc 1 725 12 discriminator 1
  39 0014 36C6     		sw	a3,12(sp)
 726:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     } while(hi != MTIMEH);
  40              		.loc 1 726 19 discriminator 1
  41 0016 03A6C7FF 		lw	a2,-4(a5)
  42              		.loc 1 726 16 discriminator 1
  43 001a A246     		lw	a3,8(sp)
  44              		.loc 1 726 5 discriminator 1
  45 001c E317D6FE 		bne	a2,a3,.L2
 727:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 728:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     return((((uint64_t)MTIMEH) << 32u) | lo);
  46              		.loc 1 728 5 is_stmt 1
  47              		.loc 1 728 24 is_stmt 0
  48 0020 83A5C7FF 		lw	a1,-4(a5)
  49              		.loc 1 728 40
  50 0024 3245     		lw	a0,12(sp)
 729:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
  51              		.loc 1 729 1
  52 0026 4101     		addi	sp,sp,16
  53              		.cfi_def_cfa_offset 0
  54 0028 8280     		jr	ra
  55              		.cfi_endproc
  56              	.LFE18:
  58              		.section	.text.MRV_systick_config,"ax",@progbits
  59              		.align	1
  60              		.globl	MRV_systick_config
  62              	MRV_systick_config:
  63              	.LFB21:
  64              		.file 2 "../src/platform/miv_rv32_hal/miv_rv32_hal.c"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @file miv_rv32_hal.c
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @brief Implementation of Hardware Abstraction Layer for Mi-V soft processors
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include <unistd.h>
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include "miv_rv32_hal.h"
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef __cplusplus
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern "C" {
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define SUCCESS                       0U
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define ERROR                         1U
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MASK_32BIT                    0xFFFFFFFFu
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *  Write in a sequence recommended by privileged spec to avoid spurious
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupts
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****    # New comparand is in a1:a0.
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     li t0, -1
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw t0, mtimecmp # No smaller than old value.
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a1, mtimecmp+4 # No smaller than new value.
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a0, mtimecmp # New value.
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMECMP
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)         MTIMECMPH = MASK_32BIT; \
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMP  = value & MASK_32BIT;\
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMPH =  (value >> 32u) & MASK_32BIT;
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMER
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)            MTIME  = value & MASK_32BIT;\
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMEH = (value >> 32u) & MASK_32BIT;
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void Software_IRQHandler(void);
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MTIME_PRESCALER                 100UL
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t Invalid_IRQHandler(void);
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_1_IRQHandler(void);
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_2_IRQHandler(void);
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_3_IRQHandler(void);
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_4_IRQHandler(void);
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_5_IRQHandler(void);
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_6_IRQHandler(void);
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_7_IRQHandler(void);
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_8_IRQHandler(void);
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_9_IRQHandler(void);
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_10_IRQHandler(void);
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_11_IRQHandler(void);
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_12_IRQHandler(void);
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_13_IRQHandler(void);
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_14_IRQHandler(void);
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_15_IRQHandler(void);
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_16_IRQHandler(void);
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_17_IRQHandler(void);
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_18_IRQHandler(void);
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_19_IRQHandler(void);
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_20_IRQHandler(void);
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_21_IRQHandler(void);
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_22_IRQHandler(void);
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_23_IRQHandler(void);
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_24_IRQHandler(void);
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_25_IRQHandler(void);
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_26_IRQHandler(void);
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_27_IRQHandler(void);
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_28_IRQHandler(void);
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_29_IRQHandler(void);
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_30_IRQHandler(void);
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_31_IRQHandler(void);
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for external interrupts.
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t (* const mrv_ext_irq_handler_table[32])(void) =
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Invalid_IRQHandler,
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_1_IRQHandler,
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_2_IRQHandler,
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_3_IRQHandler,
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_4_IRQHandler,
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_5_IRQHandler,
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_6_IRQHandler,
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_7_IRQHandler,
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_8_IRQHandler,
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_9_IRQHandler,
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_10_IRQHandler,
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_11_IRQHandler,
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_12_IRQHandler,
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_13_IRQHandler,
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_14_IRQHandler,
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_15_IRQHandler,
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_16_IRQHandler,
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_17_IRQHandler,
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_18_IRQHandler,
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_19_IRQHandler,
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_20_IRQHandler,
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_21_IRQHandler,
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_22_IRQHandler,
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_23_IRQHandler,
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_24_IRQHandler,
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_25_IRQHandler,
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_26_IRQHandler,
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_27_IRQHandler,
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_28_IRQHandler,
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_29_IRQHandler,
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_30_IRQHandler,
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_31_IRQHandler
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** };
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Interrupt handlers as mapped into the MIE register of the MIV_RV32
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void Reserved_IRQHandler(void);
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void External_IRQHandler(void);
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGEUI_IRQHandler(void);
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGECI_IRQHandler(void);
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI0_IRQHandler(void);
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI1_IRQHandler(void);
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI2_IRQHandler(void);
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI3_IRQHandler(void);
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI4_IRQHandler(void);
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI5_IRQHandler(void);
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void SUBSYS_IRQHandler(void);
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI6_IRQHandler(void);
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI7_IRQHandler(void);
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void SUBSYSR_IRQHandler(void); // @suppress("Unused function declaration")
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /*MIV_RV32_V3_0*/
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif  /* MIV_LEGACY_RV32 */
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Increment value for the mtimecmp register in order to achieve a system tick
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupt as specified through the MRV_systick_config() function.
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_increment = 0U;
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_cmp_value = 0U;
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Configure the machine timer to generate an interrupt.
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint32_t MRV_systick_config(uint64_t ticks)
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  65              		.loc 2 163 1 is_stmt 1
  66              		.cfi_startproc
  67              	.LVL0:
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t ret_val = ERROR;
  68              		.loc 2 164 5
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
  69              		.loc 2 165 5
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  70              		.loc 2 166 5
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t ret_val = ERROR;
  71              		.loc 2 163 1 is_stmt 0
  72 0000 4111     		addi	sp,sp,-16
  73              		.cfi_def_cfa_offset 16
  74 0002 22C4     		sw	s0,8(sp)
  75              		.loc 2 166 25
  76 0004 0147     		li	a4,0
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  77              		.loc 2 167 25
  78 0006 97070000 		lla	a5,.LANCHOR1
  78      93870700 
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t ret_val = ERROR;
  79              		.loc 2 163 1
  80 000e 06C6     		sw	ra,12(sp)
  81              		.cfi_offset 8, -8
  82              		.cfi_offset 1, -4
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  83              		.loc 2 166 25
  84 0010 17040000 		lla	s0,.LANCHOR0
  84      13040400 
  85 0018 8146     		li	a3,0
  86              		.loc 2 167 25
  87 001a D8C3     		sw	a4,4(a5)
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_increment = 0U;
  88              		.loc 2 166 25
  89 001c 58C0     		sw	a4,4(s0)
  90              		.loc 2 167 5 is_stmt 1
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while (remainder >= MTIME_PRESCALER)
  91              		.loc 2 169 5
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  92              		.loc 2 167 25 is_stmt 0
  93 001e 94C3     		sw	a3,0(a5)
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = 0U;
  94              		.loc 2 166 25
  95 0020 14C0     		sw	a3,0(s0)
  96              		.loc 2 169 11
  97 0022 8147     		li	a5,0
  98 0024 0147     		li	a4,0
  99 0026 0146     		li	a2,0
 100              		.loc 2 169 25
 101 0028 37580002 		li	a6,33574912
 102              	.LVL1:
 103              	.L6:
 104 002c 93881700 		addi	a7,a5,1
 105 0030 03230800 		lw	t1,0(a6)
 106 0034 B3B6F800 		sltu	a3,a7,a5
 107 0038 BA96     		add	a3,a3,a4
 108              		.loc 2 169 11
 109 003a A5E5     		bne	a1,zero,.L7
 110 003c 63736506 		bleu	t1,a0,.L7
 111 0040 09CA     		beq	a2,zero,.L9
 112 0042 97060000 		sw	a5,.LANCHOR0,a3
 112      23A0F600 
 113 004a 97070000 		sw	a4,.LANCHOR0+4,a5
 113      23A0E700 
 114              	.L9:
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         remainder -= MTIME_PRESCALER;
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = g_systick_increment + MRV_read_mtime();
 115              		.loc 2 175 5 is_stmt 1
 116              		.loc 2 175 49 is_stmt 0
 117 0052 97000000 		call	MRV_read_mtime
 117      E7800000 
 118              	.LVL2:
 119              		.loc 2 175 47
 120 005a 1C40     		lw	a5,0(s0)
 121 005c 5440     		lw	a3,4(s0)
 122 005e 3307F500 		add	a4,a0,a5
 123 0062 3335A700 		sltu	a0,a4,a0
 124 0066 B695     		add	a1,a1,a3
 125 0068 AA95     		add	a1,a0,a1
 126              		.loc 2 175 25
 127 006a 17060000 		sw	a4,.LANCHOR1,a2
 127      2320E600 
 128 0072 17060000 		sw	a1,.LANCHOR1+4,a2
 128      2320B600 
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (g_systick_increment > 0U)
 129              		.loc 2 177 5 is_stmt 1
 130              		.loc 2 177 8 is_stmt 0
 131 007a D58F     		or	a5,a5,a3
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
 132              		.loc 2 164 14
 133 007c 0545     		li	a0,1
 134              		.loc 2 177 8
 135 007e 91CF     		beq	a5,zero,.L5
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         WRITE_MTIMECMP(g_systick_cmp_value);
 136              		.loc 2 179 9 is_stmt 1
 137 0080 B7470002 		li	a5,33570816
 138 0084 FD56     		li	a3,-1
 139 0086 D4C3     		sw	a3,4(a5)
 140              		.loc 2 179 9
 141 0088 98C3     		sw	a4,0(a5)
 142              		.loc 2 179 9
 143 008a CCC3     		sw	a1,4(a5)
 144              		.loc 2 179 44
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
 145              		.loc 2 180 9
 146              	.LBB6:
 147              		.loc 2 180 9
 148              		.loc 2 180 9
 149 008c 93070008 		li	a5,128
 150              	 #APP
 151              	# 180 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 181              	        MRV_enable_interrupts();
 152              		csrrs a5, mie, a5
 153              	# 0 "" 2
 154              	.LVL3:
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
 155              		.loc 2 180 9
 156              	 #NO_APP
 157              	.LBE6:
 158              		.loc 2 181 9
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 159              		.loc 1 650 5
 160              	.LBB7:
 161              	.LBB8:
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 162              		.loc 1 650 5
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 163              		.loc 1 650 5
 164              	 #APP
 165              	# 650 "../src/platform/miv_rv32_hal/miv_rv32_hal.h" 1
 166              		csrrs a5, mstatus, 8
 167              	# 0 "" 2
 168              	.LVL4:
 650:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 169              		.loc 1 650 5
 170              	 #NO_APP
 171              	.LBE8:
 172              	.LBE7:
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         ret_val = SUCCESS;
 173              		.loc 2 182 9
 174              		.loc 2 182 17 is_stmt 0
 175 0098 0145     		li	a0,0
 176              	.LVL5:
 177              	.L5:
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 185:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     return ret_val;
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 178              		.loc 2 186 1
 179 009a B240     		lw	ra,12(sp)
 180              		.cfi_remember_state
 181              		.cfi_restore 1
 182 009c 2244     		lw	s0,8(sp)
 183              		.cfi_restore 8
 184 009e 4101     		addi	sp,sp,16
 185              		.cfi_def_cfa_offset 0
 186 00a0 8280     		jr	ra
 187              	.LVL6:
 188              	.L7:
 189              		.cfi_restore_state
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 190              		.loc 2 171 9 is_stmt 1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 191              		.loc 2 171 22 is_stmt 0
 192 00a2 83270800 		lw	a5,0(a6)
 193 00a6 0546     		li	a2,1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 194              		.loc 2 171 19
 195 00a8 B307F540 		sub	a5,a0,a5
 196 00ac 3337F500 		sgtu	a4,a5,a0
 197 00b0 998D     		sub	a1,a1,a4
 198              	.LVL7:
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 199              		.loc 2 172 9 is_stmt 1
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 200              		.loc 2 171 19 is_stmt 0
 201 00b2 3E85     		mv	a0,a5
 202 00b4 3687     		mv	a4,a3
 203 00b6 C687     		mv	a5,a7
 204              	.LVL8:
 205 00b8 95BF     		j	.L6
 206              		.cfi_endproc
 207              	.LFE21:
 209              		.section	.text.handle_m_timer_interrupt,"ax",@progbits
 210              		.align	1
 211              		.globl	handle_m_timer_interrupt
 213              	handle_m_timer_interrupt:
 214              	.LFB22:
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for machine timer interrupts.
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_timer_interrupt(void)
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 215              		.loc 2 192 1 is_stmt 1
 216              		.cfi_startproc
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 217              		.loc 2 193 5
 218              	.LBB9:
 219              		.loc 2 193 5
 220              		.loc 2 193 5
 221              	.LBE9:
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 222              		.loc 2 192 1 is_stmt 0
 223 0000 4111     		addi	sp,sp,-16
 224              		.cfi_def_cfa_offset 16
 225 0002 06C6     		sw	ra,12(sp)
 226              		.cfi_offset 1, -4
 227              	.LBB10:
 228              		.loc 2 193 5
 229 0004 93070008 		li	a5,128
 230              	 #APP
 231              	# 193 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 194              	
 232              		csrrc a5, mie, a5
 233              	# 0 "" 2
 234              	.LVL9:
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 235              		.loc 2 193 5 is_stmt 1
 236              	 #NO_APP
 237              	.LBE10:
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mtime_at_irq = MRV_read_mtime();
 238              		.loc 2 195 5
 239              		.loc 2 195 29 is_stmt 0
 240 000c 97000000 		call	MRV_read_mtime
 240      E7800000 
 241              	.LVL10:
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     static volatile uint32_t d_tick = 0u;
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
 242              		.loc 2 201 5 is_stmt 1
 243 0014 97070000 		lla	a5,.LANCHOR1
 243      93870700 
 244 001c 9843     		lw	a4,0(a5)
 245              		.loc 2 201 47 is_stmt 0
 246 001e 13065500 		addi	a2,a0,5
 247 0022 DC43     		lw	a5,4(a5)
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 248              		.loc 2 202 51
 249 0024 97060000 		lla	a3,.LANCHOR0
 249      93860600 
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 250              		.loc 2 201 47
 251 002c 3335A600 		sltu	a0,a2,a0
 252              	.LVL11:
 253              		.loc 2 202 51
 254 0030 03A80600 		lw	a6,0(a3)
 255 0034 83A84600 		lw	a7,4(a3)
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 256              		.loc 2 201 47
 257 0038 AA95     		add	a1,a0,a1
 258              	.LVL12:
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 259              		.loc 2 201 10
 260 003a 8146     		li	a3,0
 261              	.L20:
 262 003c 63E0B704 		bgtu	a1,a5,.L21
 263 0040 6394F500 		bne	a1,a5,.L24
 264 0044 636CC702 		bgtu	a2,a4,.L21
 265              	.L24:
 266 0048 89CA     		beq	a3,zero,.L23
 267 004a 97060000 		sw	a4,.LANCHOR1,a3
 267      23A0E600 
 268 0052 97060000 		sw	a5,.LANCHOR1+4,a3
 268      23A0F600 
 269              	.L23:
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         d_tick += 1;
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /***************************************************************************//**
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     /*
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Note: If d_tick > 1 it means, that a system timer interrupt has been 
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * missed.
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Please ensure that interrupt handlers are as short as possible to prevent
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * them stopping other interrupts from being handled. For example, if a
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * system timer interrupt occurs during a software interrupt, the system
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * timer interrupt will not be handled until the software interrupt handling
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * is complete. If the software interrupt handling time is more than one 
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * systick interval, it will result in d_tick > 1.
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * If you are running the program using the debugger and halt the CPU at a 
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * breakpoint, MTIME will continue to increment and interrupts will be 
 220:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * missed; resulting in d_tick > 1.
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      */
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     WRITE_MTIMECMP(g_systick_cmp_value);
 270              		.loc 2 223 5 is_stmt 1
 271 005a B7460002 		li	a3,33570816
 272 005e 7D56     		li	a2,-1
 273 0060 D0C2     		sw	a2,4(a3)
 274              		.loc 2 223 5
 275 0062 98C2     		sw	a4,0(a3)
 276              		.loc 2 223 5
 277 0064 DCC2     		sw	a5,4(a3)
 278              		.loc 2 223 40
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SysTick_Handler();
 279              		.loc 2 225 5
 280 0066 97000000 		call	SysTick_Handler
 280      E7800000 
 281              	.LVL13:
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 282              		.loc 2 227 5
 283              	.LBB11:
 284              		.loc 2 227 5
 285              		.loc 2 227 5
 286 006e 93070008 		li	a5,128
 287              	 #APP
 288              	# 227 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 228              	}
 289              		csrrs a5, mie, a5
 290              	# 0 "" 2
 291              	.LVL14:
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 292              		.loc 2 227 5
 293              	 #NO_APP
 294              	.LBE11:
 295              		.loc 2 228 1 is_stmt 0
 296 0076 B240     		lw	ra,12(sp)
 297              		.cfi_remember_state
 298              		.cfi_restore 1
 299 0078 4101     		addi	sp,sp,16
 300              		.cfi_def_cfa_offset 0
 301 007a 8280     		jr	ra
 302              	.L21:
 303              		.cfi_restore_state
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 304              		.loc 2 202 9 is_stmt 1
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 305              		.loc 2 202 51 is_stmt 0
 306 007c B3060701 		add	a3,a4,a6
 307 0080 33B5E600 		sltu	a0,a3,a4
 308 0084 C697     		add	a5,a5,a7
 309 0086 3687     		mv	a4,a3
 310 0088 AA97     		add	a5,a0,a5
 311 008a 8546     		li	a3,1
 312 008c 45BF     		j	.L20
 313              		.cfi_endproc
 314              	.LFE22:
 316              		.section	.text.handle_m_soft_interrupt,"ax",@progbits
 317              		.align	1
 318              		.globl	handle_m_soft_interrupt
 320              	handle_m_soft_interrupt:
 321              	.LFB23:
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_soft_interrupt(void)
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 322              		.loc 2 231 1 is_stmt 1
 323              		.cfi_startproc
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 324              		.loc 2 232 5
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 325              		.loc 2 231 1 is_stmt 0
 326 0000 4111     		addi	sp,sp,-16
 327              		.cfi_def_cfa_offset 16
 328 0002 06C6     		sw	ra,12(sp)
 329              		.cfi_offset 1, -4
 330              		.loc 2 232 5
 331 0004 97000000 		call	Software_IRQHandler
 331      E7800000 
 332              	.LVL15:
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MRV_clear_soft_irq();
 333              		.loc 2 233 5 is_stmt 1
 334              	.LBB14:
 335              	.LBB15:
 730:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 731:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 732:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_raise_soft_irq() function raises a synchronous software interrupt
 733:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   by writing into the MSIP register.
 734:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 735:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 736:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 737:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 738:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 739:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 740:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_raise_soft_irq(void)
 741:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 742:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, MIP_MSIP);       /* Enable software interrupt bit */
 743:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 744:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 745:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* You need to make sure that the global interrupt is enabled */
 746:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x01;   /* raise soft interrupt */
 747:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 748:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Raise soft IRQ on MIV_RV32 processor */
 749:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     SUBSYS->soft_reg |= SUBSYS_SOFT_IRQ;
 750:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 751:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 752:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 753:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 754:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV_clear_soft_irq() function clears a synchronous software interrupt
 755:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   by clearing the MSIP register.
 756:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @param
 757:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not take any parameters.
 758:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 759:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   @return
 760:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   This function does not return any value.
 761:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 762:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_clear_soft_irq(void)
 763:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 764:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 765:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x00u;   /* clear soft interrupt */
 766:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 767:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Clear soft IRQ on MIV_RV32 processor */
 768:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
 336              		.loc 1 768 5
 337              		.loc 1 768 22 is_stmt 0
 338 000c 1967     		li	a4,24576
 339 000e 1C53     		lw	a5,32(a4)
 340              	.LBE15:
 341              	.LBE14:
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 342              		.loc 2 234 1
 343 0010 B240     		lw	ra,12(sp)
 344              		.cfi_restore 1
 345              	.LBB17:
 346              	.LBB16:
 347              		.loc 1 768 22
 348 0012 F59B     		andi	a5,a5,-3
 349 0014 1CD3     		sw	a5,32(a4)
 350              	.LBE16:
 351              	.LBE17:
 352              		.loc 2 234 1
 353 0016 4101     		addi	sp,sp,16
 354              		.cfi_def_cfa_offset 0
 355 0018 8280     		jr	ra
 356              		.cfi_endproc
 357              	.LFE23:
 359              		.section	.text.handle_local_ei_interrupts,"ax",@progbits
 360              		.align	1
 361              		.globl	handle_local_ei_interrupts
 363              	handle_local_ei_interrupts:
 364              	.LFB24:
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for software interrupts.
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_ext_interrupt(void)
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     unsigned long hart_id = read_csr(mhartid);
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t int_num  = PLIC->TARGET[hart_id].CLAIM_COMPLETE;
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint8_t disable = EXT_IRQ_KEEP_ENABLED;
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (0u !=int_num)
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         disable = mrv_ext_irq_handler_table[int_num]();
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         PLIC->TARGET[hart_id].CLAIM_COMPLETE = int_num;
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if(EXT_IRQ_DISABLE == disable)
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             MRV_PLIC_disable_irq((IRQn_Type)int_num);
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * MSYS local interrupts table
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void (* const local_irq_handler_table[16])(void) =
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_V3_0
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGEUI_IRQHandler,
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGECI_IRQHandler,
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYSR_IRQHandler,
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYS_IRQHandler,
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI0_IRQHandler,
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI1_IRQHandler,
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI2_IRQHandler,
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI3_IRQHandler,
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI4_IRQHandler,
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI5_IRQHandler,
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI6_IRQHandler,
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI7_IRQHandler
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGEUI_IRQHandler,
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MGECI_IRQHandler,
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,    
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI0_IRQHandler,
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI1_IRQHandler,
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI2_IRQHandler,
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI3_IRQHandler,
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI4_IRQHandler,
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MSYS_EI5_IRQHandler,
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SUBSYS_IRQHandler,
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reserved_IRQHandler,
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** };
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Jump to interrupt table containing local interrupts
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_local_ei_interrupts(uint8_t irq_no)
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 365              		.loc 2 305 1 is_stmt 1
 366              		.cfi_startproc
 367              	.LVL16:
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mhart_id = read_csr(mhartid);
 368              		.loc 2 306 5
 369              	.LBB18:
 370              		.loc 2 306 25
 371              		.loc 2 306 25
 372              	 #APP
 373              	# 306 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 307              	    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
 374              		csrr a5, mhartid
 375              	# 0 "" 2
 376              	.LVL17:
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mhart_id = read_csr(mhartid);
 377              		.loc 2 306 25
 378              	 #NO_APP
 379              	.LBE18:
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
 380              		.loc 2 310 5
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     (*local_irq_handler_table[ei_no])();
 381              		.loc 2 311 5
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     (*local_irq_handler_table[ei_no])();
 382              		.loc 2 310 13 is_stmt 0
 383 0004 4115     		addi	a0,a0,-16
 384              	.LVL18:
 385              		.loc 2 311 6
 386 0006 1375F50F 		andi	a0,a0,0xff
 387 000a 0A05     		slli	a0,a0,2
 388 000c 97070000 		lla	a5,.LANCHOR2
 388      93870700 
 389 0014 3E95     		add	a0,a5,a0
 390 0016 03230500 		lw	t1,0(a0)
 391 001a 0283     		jr	t1
 392              	.LVL19:
 393              		.cfi_endproc
 394              	.LFE24:
 396              		.section	.text.handle_trap,"ax",@progbits
 397              		.align	1
 398              		.globl	handle_trap
 400              	handle_trap:
 401              	.LFB25:
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /* MIV_LEGACY_RV32 */
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Trap handler. This function is invoked in the non-vectored mode.
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_trap(uintptr_t mcause, uintptr_t mepc)
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {   
 402              		.loc 2 320 1 is_stmt 1
 403              		.cfi_startproc
 404              	.LVL20:
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 405              		.loc 2 321 5
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (is_interrupt)
 406              		.loc 2 323 5
 407              		.loc 2 323 8 is_stmt 0
 408 0000 63590504 		bge	a0,zero,.L33
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_LEGACY_RV32
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL
 409              		.loc 2 326 9 is_stmt 1
 410              		.loc 2 326 38 is_stmt 0
 411 0004 B7070080 		li	a5,-2147483648
 412 0008 13C707FF 		xori	a4,a5,-16
 413 000c 698F     		and	a4,a0,a4
 414              		.loc 2 326 12
 415 000e 19CB     		beq	a4,zero,.L34
 416              		.loc 2 326 88 discriminator 1
 417 0010 93C707FE 		xori	a5,a5,-32
 418 0014 E98F     		and	a5,a0,a5
 419              		.loc 2 326 60 discriminator 1
 420 0016 99E7     		bne	a5,zero,.L34
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
 421              		.loc 2 328 13 is_stmt 1
 422 0018 1375F50F 		andi	a0,a0,0xff
 423              	.LVL21:
 424 001c 17030000 		tail	handle_local_ei_interrupts
 424      67000300 
 425              	.LVL22:
 426              	.L34:
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
 427              		.loc 2 330 14
 428              		.loc 2 330 26 is_stmt 0
 429 0024 0605     		slli	a0,a0,1
 430              	.LVL23:
 431 0026 0581     		srli	a0,a0,1
 432              		.loc 2 330 17
 433 0028 AD47     		li	a5,11
 434 002a 6316F500 		bne	a0,a5,.L35
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_LEGACY_RV32
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             External_IRQHandler();
 435              		.loc 2 336 13 is_stmt 1
 436 002e 17030000 		tail	External_IRQHandler
 436      67000300 
 437              	.LVL24:
 438              	.L35:
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_ext_interrupt();
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
 439              		.loc 2 341 14
 440              		.loc 2 341 17 is_stmt 0
 441 0036 8D47     		li	a5,3
 442 0038 6316F500 		bne	a0,a5,.L36
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_soft_interrupt();
 443              		.loc 2 343 13 is_stmt 1
 444 003c 17030000 		tail	handle_m_soft_interrupt
 444      67000300 
 445              	.LVL25:
 446              	.L36:
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
 447              		.loc 2 345 14
 448              		.loc 2 345 17 is_stmt 0
 449 0044 9D47     		li	a5,7
 450 0046 631DF500 		bne	a0,a5,.L32
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             handle_m_timer_interrupt();
 451              		.loc 2 347 13 is_stmt 1
 452 004a 17030000 		tail	handle_m_timer_interrupt
 452      67000300 
 453              	.LVL26:
 454              	.L33:
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /*
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Arguments supplied to this function are mcause, mepc (exception PC) and
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          stack pointer.
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Based on privileged-isa specification mcause values and meanings are:
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          0 Instruction address misaligned (mtval/mtval is the address)
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          1 Instruction access fault       (mtval/mtval is the address)
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          2 Illegal instruction            (mtval/mtval contains the
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                            offending instruction opcode)
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          3 Breakpoint
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          4 Load address misaligned        (mtval/mtval is the address)
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          5 Load address fault             (mtval/mtval is the address)
 365:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          6 Store/AMO address fault        (mtval/mtval is the address)
 366:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          7 Store/AMO access fault         (mtval/mtval is the address)
 367:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          8 Environment call from U-mode
 368:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          9 Environment call from S-mode
 369:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          A Environment call from M-mode
 370:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          B Instruction page fault
 371:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          C Load page fault                (mtval/mtval is the address)
 372:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          E Store page fault               (mtval/mtval is the address)
 373:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 374:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # Please note: mtval is the newer name for register mbadaddr
 375:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # If you get a compile failure here, use the older name.
 376:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # At this point, both are supported in latest compiler, older compiler
 377:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # versions only support mbadaddr.
 378:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # See: https://github.com/riscv/riscv-gcc/issues/133
 379:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         */
 380:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 381:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* interrupt pending */
 382:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mip      = read_csr(mip);
 383:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 384:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* additional info and meaning depends on mcause */
 385:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtval = read_csr(mtval);
 386:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 387:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* trap vector */
 388:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtvec    = read_csr(mtvec);
 389:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 390:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* temporary, sometimes might hold temporary value of a0 */
 391:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mscratch = read_csr(mscratch);
 392:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 393:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* status contains many smaller fields: */
 394:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mstatus  = read_csr(mstatus);
 395:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 396:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* PC value when the exception was taken*/
 397:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mmepc  = read_csr(mepc);
 398:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 399:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /* breakpoint */
 400:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         __asm__("ebreak");
 401:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 402:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         _exit(1 + mcause);
 455              		.loc 2 402 9
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 456              		.loc 2 320 1 is_stmt 0
 457 0052 4111     		addi	sp,sp,-16
 458              		.cfi_def_cfa_offset 16
 459              		.loc 2 402 9
 460 0054 0505     		addi	a0,a0,1
 461              	.LVL27:
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t is_interrupt = mcause & MCAUSE_INT;
 462              		.loc 2 320 1
 463 0056 06C6     		sw	ra,12(sp)
 464              		.cfi_offset 1, -4
 465              		.loc 2 402 9
 466 0058 97000000 		call	_exit
 466      E7800000 
 467              	.LVL28:
 468              	.L32:
 469              		.cfi_def_cfa_offset 0
 470              		.cfi_restore 1
 471 0060 8280     		ret
 472              		.cfi_endproc
 473              	.LFE25:
 475              		.section	.text.MRV_BootROM_reconfigure,"ax",@progbits
 476              		.align	1
 477              		.globl	MRV_BootROM_reconfigure
 479              	MRV_BootROM_reconfigure:
 480              	.LFB26:
 403:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif  /* NDEBUG */
 404:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 405:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 406:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 407:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Reconfigure the BootROM source and destination addresses
 408:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** */
 409:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void MRV_BootROM_reconfigure(uint32_t start_addr, uint32_t end_addr, uint32_t destination_addr)
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 481              		.loc 2 410 1 is_stmt 1
 482              		.cfi_startproc
 483              	.LVL29:
 411:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_START, start_addr);
 484              		.loc 2 411 5
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_START, start_addr);
 485              		.loc 2 410 1 is_stmt 0
 486 0000 0111     		addi	sp,sp,-32
 487              		.cfi_def_cfa_offset 32
 488 0002 22CC     		sw	s0,24(sp)
 489              		.cfi_offset 8, -8
 490              		.loc 2 411 5
 491 0004 2964     		li	s0,40960
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_START, start_addr);
 492              		.loc 2 410 1
 493 0006 26CA     		sw	s1,20(sp)
 494              		.cfi_offset 9, -12
 495 0008 AE84     		mv	s1,a1
 496              		.loc 2 411 5
 497 000a AA85     		mv	a1,a0
 498              	.LVL30:
 499 000c 13050410 		addi	a0,s0,256
 500              	.LVL31:
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_START, start_addr);
 501              		.loc 2 410 1
 502 0010 06CE     		sw	ra,28(sp)
 503              		.cfi_offset 1, -4
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_START, start_addr);
 504              		.loc 2 410 1
 505 0012 32C6     		sw	a2,12(sp)
 506              		.loc 2 411 5
 507 0014 97000000 		call	HW_set_32bit_reg
 507      E7800000 
 508              	.LVL32:
 412:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_END, end_addr);
 509              		.loc 2 412 5 is_stmt 1
 510 001c A685     		mv	a1,s1
 511 001e 13054410 		addi	a0,s0,260
 512 0022 97000000 		call	HW_set_32bit_reg
 512      E7800000 
 513              	.LVL33:
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_DEST, destination_addr);
 514              		.loc 2 413 5
 515 002a 3246     		lw	a2,12(sp)
 516 002c 13058410 		addi	a0,s0,264
 414:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 415:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 517              		.loc 2 415 1 is_stmt 0
 518 0030 6244     		lw	s0,24(sp)
 519              		.cfi_restore 8
 520 0032 F240     		lw	ra,28(sp)
 521              		.cfi_restore 1
 522 0034 D244     		lw	s1,20(sp)
 523              		.cfi_restore 9
 524              	.LVL34:
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_DEST, destination_addr);
 525              		.loc 2 413 5
 526 0036 B285     		mv	a1,a2
 527              		.loc 2 415 1
 528 0038 0561     		addi	sp,sp,32
 529              		.cfi_def_cfa_offset 0
 530              	.LVL35:
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     HW_set_32bit_reg(BOOTROM_DEST, destination_addr);
 531              		.loc 2 413 5
 532 003a 17030000 		tail	HW_set_32bit_reg
 532      67000300 
 533              	.LVL36:
 534              		.cfi_endproc
 535              	.LFE26:
 537              		.globl	local_irq_handler_table
 538              		.comm	MRV_LOCAL_IRQn_Type,4,4
 539              		.section	.rodata.local_irq_handler_table,"a"
 540              		.align	2
 541              		.set	.LANCHOR2,. + 0
 544              	local_irq_handler_table:
 545 0000 00000000 		.word	MGEUI_IRQHandler
 546 0004 00000000 		.word	MGECI_IRQHandler
 547 0008 00000000 		.word	Reserved_IRQHandler
 548 000c 00000000 		.word	Reserved_IRQHandler
 549 0010 00000000 		.word	Reserved_IRQHandler
 550 0014 00000000 		.word	Reserved_IRQHandler
 551 0018 00000000 		.word	SUBSYSR_IRQHandler
 552 001c 00000000 		.word	SUBSYS_IRQHandler
 553 0020 00000000 		.word	MSYS_EI0_IRQHandler
 554 0024 00000000 		.word	MSYS_EI1_IRQHandler
 555 0028 00000000 		.word	MSYS_EI2_IRQHandler
 556 002c 00000000 		.word	MSYS_EI3_IRQHandler
 557 0030 00000000 		.word	MSYS_EI4_IRQHandler
 558 0034 00000000 		.word	MSYS_EI5_IRQHandler
 559 0038 00000000 		.word	MSYS_EI6_IRQHandler
 560 003c 00000000 		.word	MSYS_EI7_IRQHandler
 561              		.section	.sbss.g_systick_cmp_value,"aw",@nobits
 562              		.align	3
 563              		.set	.LANCHOR1,. + 0
 566              	g_systick_cmp_value:
 567 0000 00000000 		.zero	8
 567      00000000 
 568              		.section	.sbss.g_systick_increment,"aw",@nobits
 569              		.align	3
 570              		.set	.LANCHOR0,. + 0
 573              	g_systick_increment:
 574 0000 00000000 		.zero	8
 574      00000000 
 575              		.text
 576              	.Letext0:
 577              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 578              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 579              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 580              		.file 6 "../src/platform/miv_rv32_hal/miv_rv32_subsys.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 miv_rv32_hal.c
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:12     .text.MRV_read_mtime:0000000000000000 MRV_read_mtime
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:16     .text.MRV_read_mtime:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:17     .text.MRV_read_mtime:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:18     .text.MRV_read_mtime:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:19     .text.MRV_read_mtime:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:20     .text.MRV_read_mtime:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:22     .text.MRV_read_mtime:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:24     .text.MRV_read_mtime:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:25     .text.MRV_read_mtime:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:27     .text.MRV_read_mtime:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:30     .text.MRV_read_mtime:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:31     .text.MRV_read_mtime:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:32     .text.MRV_read_mtime:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:34     .text.MRV_read_mtime:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:36     .text.MRV_read_mtime:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:37     .text.MRV_read_mtime:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:39     .text.MRV_read_mtime:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:41     .text.MRV_read_mtime:0000000000000016 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:43     .text.MRV_read_mtime:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:45     .text.MRV_read_mtime:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:47     .text.MRV_read_mtime:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:48     .text.MRV_read_mtime:0000000000000020 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:50     .text.MRV_read_mtime:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:52     .text.MRV_read_mtime:0000000000000026 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:53     .text.MRV_read_mtime:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:55     .text.MRV_read_mtime:000000000000002a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:62     .text.MRV_systick_config:0000000000000000 MRV_systick_config
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:66     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:68     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:69     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:70     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:71     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:72     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:73     .text.MRV_systick_config:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:76     .text.MRV_systick_config:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:78     .text.MRV_systick_config:0000000000000006 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:80     .text.MRV_systick_config:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:81     .text.MRV_systick_config:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:82     .text.MRV_systick_config:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:84     .text.MRV_systick_config:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:87     .text.MRV_systick_config:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:89     .text.MRV_systick_config:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:91     .text.MRV_systick_config:000000000000001e .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:92     .text.MRV_systick_config:000000000000001e .L0 
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:93     .text.MRV_systick_config:000000000000001e .L0 
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C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:187    .text.MRV_systick_config:00000000000000a2 .LVL6
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C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:582    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:218    .text.handle_m_timer_interrupt:0000000000000000 .LBB9
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:221    .text.handle_m_timer_interrupt:0000000000000000 .LBE9
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:227    .text.handle_m_timer_interrupt:0000000000000004 .LBB10
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:237    .text.handle_m_timer_interrupt:000000000000000c .LBE10
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:341    .text.handle_m_soft_interrupt:0000000000000010 .LBE14
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:345    .text.handle_m_soft_interrupt:0000000000000012 .LBB17
C:\Users\I71825\AppData\Local\Temp\ccx1qPop.s:351    .text.handle_m_soft_interrupt:0000000000000016 .LBE17

UNDEFINED SYMBOLS
SysTick_Handler
Software_IRQHandler
External_IRQHandler
_exit
HW_set_32bit_reg
MGEUI_IRQHandler
MGECI_IRQHandler
Reserved_IRQHandler
SUBSYSR_IRQHandler
SUBSYS_IRQHandler
MSYS_EI0_IRQHandler
MSYS_EI1_IRQHandler
MSYS_EI2_IRQHandler
MSYS_EI3_IRQHandler
MSYS_EI4_IRQHandler
MSYS_EI5_IRQHandler
MSYS_EI6_IRQHandler
MSYS_EI7_IRQHandler
