/*
 * dp_cmd_tx_regs.h
 *
 *  Created on: Mar 8, 2022
 *      Author: I63238
 */

#ifndef DP_CMD_TX_REGS_H_
#define DP_CMD_TX_REGS_H_

#define DP_TX_IP_APB_BASE_ADDRESS1                         0x7000A000
#define DP_TX_OUTPUT_DATA_OFFSET                           0x0000
#define DP_TX_OUTPUT_DATA_OFFSET1                          0x0004

#define DP_TX_IP_APB_BASE_ADDRESS                          0x70001000
#define DP_TX_IP_APB_DC_BASE_ADDRESS                       0x70002000
//DISPLAY CONTROLLER
#define DC_HRES_OFFSET                   0x0000
#define DC_VRES_OFFSET                   0x0004
#define DC_HFP_OFFSET                   0x0008
#define DC_HBP_OFFSET                   0x000C
#define DC_VFP_OFFSET                   0x0010
#define DC_VBP_OFFSET                   0x0014
#define DC_HSW_OFFSET                   0x0018
#define DC_VSW_OFFSET                   0x001C
#define BAYER_OFFSET                   0x0020


#define DP_TX_VIDEO_STREAM_ENABLE_OFFSET                   0x0000
#define DP_TX_YCBCR422_MODE_ENABLE_OFFSET                  0x0004
#define DP_TX_LANE_NUMBER_OFFSET                           0x0008
#define DP_TX_LANE_ENABLE_OFFSET                           0x000C
#define DP_TX_SCRAMBLER_ENABLE_OFFSET                      0x0010
#define DP_TX_INTERLANE_SKEW_ENABLE_OFFSET                 0x0014
#define DP_TX_TRAINING_PATTERN_MODE_OFFSET                 0x0018
#define DP_TX_ENHANCED_BS_ENABLE_OFFSET                    0x001C
#define DP_TX_FIFO_STATUS_OFFSET                           0x0020
#define DP_TX_VIDEO_FRAME_NUMBER_OFFSET                    0x0024
#define DP_TX_VIDEO_LINE_NUMBER_OFFSET                     0x0028

#define DP_TX_MSA_MVID_OFFSET                              0x00C0
#define DP_TX_MSA_NVID_OFFSET                              0x00C4
#define DP_TX_MSA_HTOTAL_OFFSET                            0x00C8
#define DP_TX_MSA_VTOTAL_OFFSET                            0x00CC
#define DP_TX_MSA_HSTART_OFFSET                            0x00D0
#define DP_TX_MSA_VSTART_OFFSET                            0x00D4
#define DP_TX_MSA_HSYNC_OFFSET                             0x00D8
#define DP_TX_MSA_VSYNC_OFFSET                             0x00DC
#define DP_TX_MSA_MISC0_OFFSET                             0x00E0
#define DP_TX_MSA_MISC1_OFFSET                             0x00E4
#define DP_TX_MSA_HWIDTH_OFFSET                            0x00E8
#define DP_TX_MSA_VWIDTH_OFFSET                            0x00EC

#define DP_TX_AUX_TX_COMMAND_OFFSET                        0x0100
#define DP_TX_AUX_TX_ADDRESS_OFFSET                        0x0104
#define DP_TX_AUX_TX_LENGTH_OFFSET                         0x0108
#define DP_TX_AUX_TX_WRITING_DATA_OFFSET                   0x010C
#define DP_TX_AUX_REPLY_TIMEOUT_TH_OFFSET                  0x0110
#define DP_TX_AUX_TX_BIT_WIDTH_OFFSET                      0x0114
#define DP_TX_AUX_TX_PRECHARGE_BIT_NUMBER_OFFSET           0x0118
#define DP_TX_AUX_TX_REQUEST_NUMBER_OFFSET                 0x011C
#define DP_TX_AUX_RX_REPLY_NUMBER_OFFSET                   0x0120
#define DP_TX_AUX_RX_REPLY_READING_DATA_OFFSET             0x0124
#define DP_TX_AUX_RX_ERROR_STATUS_OFFSET                   0x0128
#define DP_TX_AUX_RX_REPLY_LENGTH_OFFSET                   0x012C

#define DP_TX_HPD_1US_CYCLES_OFFSET                        0x0140
#define DP_TX_HPD_CONNECTED_HIGH_TIME_TH_OFFSET            0x0144
#define DP_TX_HPD_DISCONNECTED_LOW_TIME_TH_OFFSET          0x0148
#define DP_TX_HPD_IRQ_TIME_OFFSET                          0x014C
#define DP_TX_HPD_CONNECT_STATUS_OFFSET                    0x0150
#define DP_TX_HPD_IRQ_OFFSET                               0x0154

#define DP_TX_INTERRUPT_TOTALINTERRUPTMASK_OFFSET          0x0180
#define DP_TX_INTERRUPT_MASK_OFFSET                        0x0184
#define DP_TX_INTERRUPT_OFFSET                             0x0188

//sai for dri address
#define DP_DRI_APB_BASE_ADDRESS                            0x70000000
// XVCR Register Offsets
#define SER_1_PMA_L0_DES_RSTPD              0x0108104c
#define SER_1_PMA_L0_SER_RSTPD              0x01081078
#define SER_1_PMA_L0_DES_CDR_CTRL_2         0x01081008
#define SER_1_PMA_L0_DES_CDR_CTRL_3         0x0108100C
#define SER_1_PMA_L0_DES_DFEEM_CTRL_1       0x01081010
#define SER_1_PMA_L0_DES_DFEEM_CTRL_2       0x01081014
#define SER_1_PMA_L0_DES_DFEEM_CTRL_3       0x01081018
#define SER_1_PMA_L0_DES_DFE_CTRL_2         0x01081024
#define SER_1_PMA_L0_DES_EM_CTRL_2          0x0108102C
#define SER_1_PMA_L0_DES_RXPLL_DIV          0x01081040
#define SER_1_PMA_L0_SER_CLK_CTRL           0x01081074
#define SER_1_PMA_L0_SERDES_RTL_CTRL        0x010810C0
#define SER_1_PMA_L0_DES_DFE_CAL_CTRL_0     0x010810D0
#define SER_1_PMA_L0_DES_DFE_CAL_CTRL_1     0x010810D4
#define SER_1_PMA_L0_DES_DFE_CAL_CTRL_2     0x010810D8
#define SER_1_PMA_L0_DES_DFE_CAL_CMD        0x010810DC
#define SER_1_TXPLL_DIV_1                   0x01090010
#define SER_1_TXPLL_DIV_2                   0x01090014
//lane 0 swing

#define SER_1_PMA_L0_SER_DRV_DATA_CTRL      0x01081098
#define SER_1_PMA_L0_SER_DRV_CTRL           0x0108109C
#define SER_1_PMA_L0_SER_DRV_CTRL_SEL       0x010810A0
//lane1
#define SER_1_PMA_L1_DES_RSTPD              0x0108204c
#define SER_1_PMA_L1_SER_RSTPD              0x01082078
#define SER_1_PMA_L1_DES_CDR_CTRL_2         0x01082008
#define SER_1_PMA_L1_DES_CDR_CTRL_3         0x0108200C
#define SER_1_PMA_L1_DES_DFEEM_CTRL_1       0x01082010
#define SER_1_PMA_L1_DES_DFEEM_CTRL_2       0x01082014
#define SER_1_PMA_L1_DES_DFEEM_CTRL_3       0x01082018
#define SER_1_PMA_L1_DES_DFE_CTRL_2         0x01082024
#define SER_1_PMA_L1_DES_EM_CTRL_2          0x0108202C
#define SER_1_PMA_L1_DES_RXPLL_DIV          0x01082040
#define SER_1_PMA_L1_SER_CLK_CTRL           0x01082074
#define SER_1_PMA_L1_SERDES_RTL_CTRL        0x010820C0
#define SER_1_PMA_L1_DES_DFE_CAL_CTRL_0     0x010820D0
#define SER_1_PMA_L1_DES_DFE_CAL_CTRL_1     0x010820D4
#define SER_1_PMA_L1_DES_DFE_CAL_CTRL_2     0x010820D8
#define SER_1_PMA_L1_DES_DFE_CAL_CMD        0x010820DC
//lane 1 swing

#define SER_1_PMA_L1_SER_DRV_DATA_CTRL      0x01081098
#define SER_1_PMA_L1_SER_DRV_CTRL           0x0108109C
#define SER_1_PMA_L1_SER_DRV_CTRL_SEL       0x010810A0
//lane2
#define SER_1_PMA_L2_DES_RSTPD              0x0108404c
#define SER_1_PMA_L2_SER_RSTPD              0x01084078
#define SER_1_PMA_L2_DES_CDR_CTRL_2         0x01084008
#define SER_1_PMA_L2_DES_CDR_CTRL_3         0x0108400C
#define SER_1_PMA_L2_DES_DFEEM_CTRL_1       0x01084010
#define SER_1_PMA_L2_DES_DFEEM_CTRL_2       0x01084014
#define SER_1_PMA_L2_DES_DFEEM_CTRL_3       0x01084018
#define SER_1_PMA_L2_DES_DFE_CTRL_2         0x01084024
#define SER_1_PMA_L2_DES_EM_CTRL_2          0x0108402C
#define SER_1_PMA_L2_DES_RXPLL_DIV          0x01084040
#define SER_1_PMA_L2_SER_CLK_CTRL           0x01084074
#define SER_1_PMA_L2_SERDES_RTL_CTRL        0x010840C0
#define SER_1_PMA_L2_DES_DFE_CAL_CTRL_0     0x010840D0
#define SER_1_PMA_L2_DES_DFE_CAL_CTRL_1     0x010840D4
#define SER_1_PMA_L2_DES_DFE_CAL_CTRL_2     0x010840D8
#define SER_1_PMA_L2_DES_DFE_CAL_CMD        0x010840DC
//lane 2 swing

#define SER_1_PMA_L2_SER_DRV_DATA_CTRL      0x01081098
#define SER_1_PMA_L2_SER_DRV_CTRL           0x0108109C
#define SER_1_PMA_L2_SER_DRV_CTRL_SEL       0x010810A0
//lane3
#define SER_1_PMA_L3_DES_RSTPD              0x0108804c
#define SER_1_PMA_L3_SER_RSTPD              0x01088078
#define SER_1_PMA_L3_DES_CDR_CTRL_2         0x01088008
#define SER_1_PMA_L3_DES_CDR_CTRL_3         0x0108800C
#define SER_1_PMA_L3_DES_DFEEM_CTRL_1       0x01088010
#define SER_1_PMA_L3_DES_DFEEM_CTRL_2       0x01088014
#define SER_1_PMA_L3_DES_DFEEM_CTRL_3       0x01088018
#define SER_1_PMA_L3_DES_DFE_CTRL_2         0x01088024
#define SER_1_PMA_L3_DES_EM_CTRL_2          0x0108802C
#define SER_1_PMA_L3_DES_RXPLL_DIV          0x01088040
#define SER_1_PMA_L3_SER_CLK_CTRL           0x01088074
#define SER_1_PMA_L3_SERDES_RTL_CTRL        0x010880C0
#define SER_1_PMA_L3_DES_DFE_CAL_CTRL_0     0x010880D0
#define SER_1_PMA_L3_DES_DFE_CAL_CTRL_1     0x010880D4
#define SER_1_PMA_L3_DES_DFE_CAL_CTRL_2     0x010880D8
#define SER_1_PMA_L3_DES_DFE_CAL_CMD        0x010880DC
//lane 3 swing

#define SER_1_PMA_L3_SER_DRV_DATA_CTRL      0x01081098
#define SER_1_PMA_L3_SER_DRV_CTRL           0x0108109C
#define SER_1_PMA_L3_SER_DRV_CTRL_SEL       0x010810A0
#endif /* DP_CMD_TX_REGS_H_ */
