   1              		.file	"main.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0_c2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.SysTick_Handler,"ax",@progbits
  10              		.align	1
  11              		.globl	SysTick_Handler
  13              	SysTick_Handler:
  14              	.LFB21:
  15              		.file 1 "../src/application/main.c"
   1:../src/application/main.c **** /*******************************************************************************
   2:../src/application/main.c ****  * (c) Copyright 2016-2017 Microsemi SoC Products Group. All rights reserved.
   3:../src/application/main.c ****  * 
   4:../src/application/main.c ****  * This SoftConsole Video project for MIPI sensor configuration and interfacing with GUI
   5:../src/application/main.c ****  *
   6:../src/application/main.c ****  * Please refer README.TXT in the root folder of this project for more details.
   7:../src/application/main.c ****  */
   8:../src/application/main.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
   9:../src/application/main.c **** #include "drivers/fpga_ip/CoreGPIO/core_gpio.h"
  10:../src/application/main.c **** #include "drivers/fpga_ip/CoreUARTAPB/core_uart_apb.h"
  11:../src/application/main.c **** #include "drivers/fpga_ip/CoreI2C/core_i2c.h"
  12:../src/application/main.c **** #include "drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.h"
  13:../src/application/main.c **** #include "imx334_corei2c/imx334_corei2c.h"
  14:../src/application/main.c **** #include "hdmi_config/hdmi_tx.h"
  15:../src/application/main.c **** #include "dp_cmd_common.h"
  16:../src/application/main.c **** #include "dp_cmd_tx.h"
  17:../src/application/main.c **** #include "dp_cmd_common.h"
  18:../src/application/main.c **** #include "dp_cmd_tx_regs.h"
  19:../src/application/main.c **** #include "dp_cmd_tx.h"
  20:../src/application/main.c **** /* Camera configuration (Data rate, resolution) and pattern generator
  21:../src/application/main.c ****  * can be selected in imx334_corei2c.h file.
  22:../src/application/main.c ****  * */
  23:../src/application/main.c **** 
  24:../src/application/main.c **** #define LED1 GPIO_0
  25:../src/application/main.c **** #define LED2 GPIO_1
  26:../src/application/main.c **** #define LED3 GPIO_2
  27:../src/application/main.c **** #define LED4 GPIO_3
  28:../src/application/main.c **** 
  29:../src/application/main.c **** #define MIPI_TRNG_RST GPIO_4
  30:../src/application/main.c **** 
  31:../src/application/main.c **** 
  32:../src/application/main.c **** // Bayer Configuration
  33:../src/application/main.c **** #define BAYER_ADDR                0x72020000
  34:../src/application/main.c **** 
  35:../src/application/main.c **** // Display Controller Configuration
  36:../src/application/main.c **** #define DC_IP_VER                 0x72040000
  37:../src/application/main.c **** #define DC_IP_EN_DIS              0x72040004
  38:../src/application/main.c **** #define DC_IP_HRES                0x72040008
  39:../src/application/main.c **** #define DC_IP_VRES                0x7204000C
  40:../src/application/main.c **** #define DC_IP_HFP                 0x72040010
  41:../src/application/main.c **** #define DC_IP_HBP                 0x72040014
  42:../src/application/main.c **** #define DC_IP_VFP                 0x72040018
  43:../src/application/main.c **** #define DC_IP_VBP                 0x7204001C
  44:../src/application/main.c **** #define DC_IP_HSW                 0x72040020
  45:../src/application/main.c **** #define DC_IP_VSW                 0x72040024
  46:../src/application/main.c **** 
  47:../src/application/main.c **** // Image Enhancment Configuration
  48:../src/application/main.c **** #define IE_IP_VER                 0x72030000
  49:../src/application/main.c **** #define IE_IP_EN_DIS              0x72030004
  50:../src/application/main.c **** #define IE_R_CONST                0x72030008
  51:../src/application/main.c **** #define IE_G_CONST                0x7203000C
  52:../src/application/main.c **** #define IE_B_CONST                0x72030010
  53:../src/application/main.c **** #define IE_COMMON_CONST           0x72030014
  54:../src/application/main.c **** #define IE_INTENSITY_AVARAGE      0x72030018
  55:../src/application/main.c **** 
  56:../src/application/main.c **** 
  57:../src/application/main.c **** volatile uint32_t g_10ms_count;
  58:../src/application/main.c **** 
  59:../src/application/main.c **** volatile uint32_t timerdone = 0;
  60:../src/application/main.c **** volatile uint32_t g_10ms_count1;
  61:../src/application/main.c **** volatile uint32_t g_ms_count;
  62:../src/application/main.c **** static void gui_handler(void);
  63:../src/application/main.c **** i2c_instance_t g_i2c_instance_cam1;
  64:../src/application/main.c **** uint8_t uart_rx_buff[23]={0};
  65:../src/application/main.c **** UART_instance_t g_uart;
  66:../src/application/main.c **** 
  67:../src/application/main.c **** uint16_t bayer;
  68:../src/application/main.c **** 
  69:../src/application/main.c **** static uint16_t in_gain = 80;
  70:../src/application/main.c **** static void auto_brightness( uint32_t div);
  71:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  72:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  73:../src/application/main.c **** 
  74:../src/application/main.c **** 
  75:../src/application/main.c **** 
  76:../src/application/main.c **** /*----------------------------------------------------
  77:../src/application/main.c **** /*-----------------------------------------------------------------------------
  78:../src/application/main.c ****  * GPIO instance data.
  79:../src/application/main.c ****  */
  80:../src/application/main.c **** 
  81:../src/application/main.c **** gpio_instance_t g_gpio_out;
  82:../src/application/main.c **** 
  83:../src/application/main.c **** /*-----------------------------------------------------------------------------
  84:../src/application/main.c ****  * Global state counter.
  85:../src/application/main.c ****  */
  86:../src/application/main.c **** uint32_t g_state = 1;
  87:../src/application/main.c **** 
  88:../src/application/main.c **** volatile uint32_t rx_tmr_done = 0;
  89:../src/application/main.c **** volatile uint32_t rx_ms_count1;
  90:../src/application/main.c **** volatile uint32_t rx_ms_count;
  91:../src/application/main.c **** 
  92:../src/application/main.c **** uint32_t t_ms_count = 0;
  93:../src/application/main.c **** 
  94:../src/application/main.c **** 
  95:../src/application/main.c **** /*-----------------------------------------------------------------------------
  96:../src/application/main.c ****  * UART handler specific.
  97:../src/application/main.c ****  */
  98:../src/application/main.c **** uint32_t i = 0;
  99:../src/application/main.c **** uint32_t process_data = 0;
 100:../src/application/main.c **** 
 101:../src/application/main.c **** /*-----------------------------------------------------------------------------
 102:../src/application/main.c ****  * System Tick interrupt handler
 103:../src/application/main.c ****  */
 104:../src/application/main.c **** void SysTick_Handler(void) {
  16              		.loc 1 104 28
  17              		.cfi_startproc
 105:../src/application/main.c **** 
 106:../src/application/main.c ****     g_state = (~g_state) & 0x01;
  18              		.loc 1 106 5
  19              		.loc 1 106 13 is_stmt 0
  20 0000 97070000 		lla	a5,.LANCHOR0
  20      93870700 
  21 0008 9C43     		lw	a5,0(a5)
  22 000a 93C7F7FF 		not	a5,a5
  23 000e 858B     		andi	a5,a5,1
  24 0010 17070000 		sw	a5,.LANCHOR0,a4
  24      2320F700 
 107:../src/application/main.c **** 
 108:../src/application/main.c ****     if(timerdone == 1)
  25              		.loc 1 108 5 is_stmt 1
  26              		.loc 1 108 18 is_stmt 0
  27 0018 97070000 		lla	a5,.LANCHOR1
  27      93870700 
  28 0020 9843     		lw	a4,0(a5)
  29              		.loc 1 108 7
  30 0022 8547     		li	a5,1
  31 0024 6318F702 		bne	a4,a5,.L3
 109:../src/application/main.c ****     {
 110:../src/application/main.c ****         g_10ms_count1 += 1;
  32              		.loc 1 110 9 is_stmt 1
  33              		.loc 1 110 23 is_stmt 0
  34 0028 17070000 		lla	a4,g_10ms_count1
  34      13070700 
  35 0030 1C43     		lw	a5,0(a4)
  36 0032 8507     		addi	a5,a5,1
  37 0034 97060000 		sw	a5,g_10ms_count1,a3
  37      23A0F600 
 111:../src/application/main.c ****         if(g_ms_count <= g_10ms_count1)
  38              		.loc 1 111 9 is_stmt 1
  39              		.loc 1 111 23 is_stmt 0
  40 003c 97070000 		lla	a5,g_ms_count
  40      93870700 
  41 0044 9443     		lw	a3,0(a5)
  42 0046 1C43     		lw	a5,0(a4)
  43              		.loc 1 111 11
  44 0048 63E6D700 		bgtu	a3,a5,.L3
 112:../src/application/main.c ****             timerdone = 0;
  45              		.loc 1 112 13 is_stmt 1
  46              		.loc 1 112 23 is_stmt 0
  47 004c 97070000 		sw	zero,.LANCHOR1,a5
  47      23A00700 
  48              	.L3:
 113:../src/application/main.c ****     }
 114:../src/application/main.c **** 
 115:../src/application/main.c ****     if(rx_tmr_done == 1)
  49              		.loc 1 115 5 is_stmt 1
  50              		.loc 1 115 20 is_stmt 0
  51 0054 97070000 		lla	a5,.LANCHOR2
  51      93870700 
  52 005c 9843     		lw	a4,0(a5)
  53              		.loc 1 115 7
  54 005e 8547     		li	a5,1
  55 0060 631CF702 		bne	a4,a5,.L1
 116:../src/application/main.c ****     {
 117:../src/application/main.c ****         rx_ms_count1 += 1;
  56              		.loc 1 117 9 is_stmt 1
  57              		.loc 1 117 22 is_stmt 0
  58 0064 97060000 		lla	a3,rx_ms_count1
  58      93860600 
  59 006c 9C42     		lw	a5,0(a3)
  60 006e 8507     		addi	a5,a5,1
  61 0070 17060000 		sw	a5,rx_ms_count1,a2
  61      2320F600 
 118:../src/application/main.c ****         if(rx_ms_count1 >= rx_ms_count){
  62              		.loc 1 118 9 is_stmt 1
  63              		.loc 1 118 25 is_stmt 0
  64 0078 97070000 		lla	a5,rx_ms_count
  64      93870700 
  65 0080 9442     		lw	a3,0(a3)
  66 0082 9C43     		lw	a5,0(a5)
  67              		.loc 1 118 11
  68 0084 63EAF600 		bltu	a3,a5,.L1
 119:../src/application/main.c ****             rx_tmr_done = 0;
  69              		.loc 1 119 13 is_stmt 1
  70              		.loc 1 119 25 is_stmt 0
  71 0088 97070000 		sw	zero,.LANCHOR2,a5
  71      23A00700 
 120:../src/application/main.c ****             process_data = 1;
  72              		.loc 1 120 13 is_stmt 1
  73              		.loc 1 120 26 is_stmt 0
  74 0090 97070000 		sw	a4,.LANCHOR3,a5
  74      23A0E700 
  75              	.L1:
 121:../src/application/main.c ****         }
 122:../src/application/main.c ****     }
 123:../src/application/main.c **** }
  76              		.loc 1 123 1
  77 0098 8280     		ret
  78              		.cfi_endproc
  79              	.LFE21:
  81              		.section	.text.MSYS_EI0_IRQHandler,"ax",@progbits
  82              		.align	1
  83              		.globl	MSYS_EI0_IRQHandler
  85              	MSYS_EI0_IRQHandler:
  86              	.LFB22:
 124:../src/application/main.c **** 
 125:../src/application/main.c **** uint8_t  MSYS_EI0_IRQHandler(void)
 126:../src/application/main.c **** {
  87              		.loc 1 126 1 is_stmt 1
  88              		.cfi_startproc
 127:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  89              		.loc 1 127 5
 126:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  90              		.loc 1 126 1 is_stmt 0
  91 0000 4111     		addi	sp,sp,-16
  92              		.cfi_def_cfa_offset 16
  93              		.loc 1 127 5
  94 0002 17050000 		lla	a0,g_i2c_instance_cam1
  94      13050500 
 126:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  95              		.loc 1 126 1
  96 000a 06C6     		sw	ra,12(sp)
  97              		.cfi_offset 1, -4
  98              		.loc 1 127 5
  99 000c 97000000 		call	I2C_isr
  99      E7800000 
 100              	.LVL0:
 128:../src/application/main.c ****     return (EXT_IRQ_KEEP_ENABLED);
 101              		.loc 1 128 5 is_stmt 1
 129:../src/application/main.c **** }
 102              		.loc 1 129 1 is_stmt 0
 103 0014 B240     		lw	ra,12(sp)
 104              		.cfi_restore 1
 105 0016 0145     		li	a0,0
 106 0018 4101     		addi	sp,sp,16
 107              		.cfi_def_cfa_offset 0
 108 001a 8280     		jr	ra
 109              		.cfi_endproc
 110              	.LFE22:
 112              		.section	.text.startup.main,"ax",@progbits
 113              		.align	1
 114              		.globl	main
 116              	main:
 117              	.LFB23:
 130:../src/application/main.c **** 
 131:../src/application/main.c **** /*-----------------------------------------------------------------------------
 132:../src/application/main.c ****  * main
 133:../src/application/main.c ****  */
 134:../src/application/main.c **** uint32_t a;
 135:../src/application/main.c **** 
 136:../src/application/main.c **** int main(int argc, char **argv) {
 118              		.loc 1 136 33 is_stmt 1
 119              		.cfi_startproc
 120              	.LVL1:
 137:../src/application/main.c ****     volatile  uint32_t counter;
 121              		.loc 1 137 5
 138:../src/application/main.c ****     uint8_t state;
 122              		.loc 1 138 5
 139:../src/application/main.c ****     counter = 0;
 123              		.loc 1 139 5
 136:../src/application/main.c ****     volatile  uint32_t counter;
 124              		.loc 1 136 33 is_stmt 0
 125 0000 3971     		addi	sp,sp,-64
 126              		.cfi_def_cfa_offset 64
 140:../src/application/main.c ****     state = 0;
 141:../src/application/main.c ****     //DISPLAY CONTROLLER PARAMETERS
 142:../src/application/main.c ****     ///////////////////FHD//////////////////////
 143:../src/application/main.c **** #if 0
 144:../src/application/main.c ****     uint32_t PIXEL_MODE=1;//4 PIXEL MODE HRES DEIVIDE BY 4
 145:../src/application/main.c ****     uint32_t BAYER_OFFSET_VALUE=2;
 146:../src/application/main.c ****     uint32_t SPEED_MODE=1;
 147:../src/application/main.c ****     uint32_t HRES=1920;
 148:../src/application/main.c ****     uint32_t VRES=1080;
 149:../src/application/main.c ****     uint32_t HFP=88;
 150:../src/application/main.c ****     uint32_t HSW=44;
 151:../src/application/main.c ****     uint32_t HBP=148;
 152:../src/application/main.c ****     uint32_t VFP=4;
 153:../src/application/main.c ****     uint32_t VSW=5;
 154:../src/application/main.c ****     uint32_t VBP=36;
 155:../src/application/main.c ****     uint32_t VSP=0x00000000;
 156:../src/application/main.c ****     uint32_t LANE_NO=0x00000004;
 157:../src/application/main.c **** #endif
 158:../src/application/main.c ****     ///////////////////4K//////////////////////
 159:../src/application/main.c **** #if 1
 160:../src/application/main.c ****     uint32_t PIXEL_MODE=4;//4 PIXEL MODE HRES DEIVIDE BY 4
 161:../src/application/main.c ****         uint32_t BAYER_OFFSET_VALUE=0;
 162:../src/application/main.c ****         uint32_t SPEED_MODE=2;
 163:../src/application/main.c ****         uint32_t HRES=3840;
 164:../src/application/main.c ****         uint32_t VRES=2160;
 165:../src/application/main.c ****         uint32_t HFP=76;//65;//100;//176;
 166:../src/application/main.c ****         uint32_t HSW=8;
 167:../src/application/main.c ****         uint32_t HBP=76;//296;
 168:../src/application/main.c ****         uint32_t VFP=54;
 169:../src/application/main.c ****         uint32_t VSW=5;
 170:../src/application/main.c ****         uint32_t VBP=3;
 171:../src/application/main.c ****         uint32_t VSP=0x00008000;
 172:../src/application/main.c ****         uint32_t LANE_NO=0x00000004;
 173:../src/application/main.c **** #endif
 174:../src/application/main.c ****         // =========================== DisplayController ================================
 175:../src/application/main.c ****         uint32_t Enable=1;
 176:../src/application/main.c ****         uint32_t Disable=0;
 177:../src/application/main.c **** 
 178:../src/application/main.c ****         //bayer = 0x00;
 179:../src/application/main.c ****         Enable = 0x01;
 180:../src/application/main.c ****         Disable = 0x00;
 181:../src/application/main.c **** 
 182:../src/application/main.c ****         axi4litewrite(BAYER_ADDR,BAYER_OFFSET_VALUE);
 127              		.loc 1 182 9
 128 0002 8145     		li	a1,0
 129              	.LVL2:
 130 0004 37050272 		li	a0,1912733696
 131              	.LVL3:
 136:../src/application/main.c ****     volatile  uint32_t counter;
 132              		.loc 1 136 33
 133 0008 06DE     		sw	ra,60(sp)
 134 000a 22DC     		sw	s0,56(sp)
 135 000c 26DA     		sw	s1,52(sp)
 136              		.cfi_offset 1, -4
 137              		.cfi_offset 8, -8
 138              		.cfi_offset 9, -12
 183:../src/application/main.c **** 
 184:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Disable); // diabling the IP
 139              		.loc 1 184 9
 140 000e 37040472 		li	s0,1912864768
 136:../src/application/main.c ****     volatile  uint32_t counter;
 141              		.loc 1 136 33
 142 0012 4AD8     		sw	s2,48(sp)
 143 0014 4ED6     		sw	s3,44(sp)
 144 0016 52D4     		sw	s4,40(sp)
 145 0018 56D2     		sw	s5,36(sp)
 146              		.cfi_offset 18, -16
 147              		.cfi_offset 19, -20
 148              		.cfi_offset 20, -24
 149              		.cfi_offset 21, -28
 139:../src/application/main.c ****     state = 0;
 150              		.loc 1 139 13
 151 001a 02CE     		sw	zero,28(sp)
 140:../src/application/main.c ****     //DISPLAY CONTROLLER PARAMETERS
 152              		.loc 1 140 5 is_stmt 1
 153              	.LVL4:
 160:../src/application/main.c ****         uint32_t BAYER_OFFSET_VALUE=0;
 154              		.loc 1 160 5
 161:../src/application/main.c ****         uint32_t SPEED_MODE=2;
 155              		.loc 1 161 9
 162:../src/application/main.c ****         uint32_t HRES=3840;
 156              		.loc 1 162 9
 163:../src/application/main.c ****         uint32_t VRES=2160;
 157              		.loc 1 163 9
 164:../src/application/main.c ****         uint32_t HFP=76;//65;//100;//176;
 158              		.loc 1 164 9
 165:../src/application/main.c ****         uint32_t HSW=8;
 159              		.loc 1 165 9
 166:../src/application/main.c ****         uint32_t HBP=76;//296;
 160              		.loc 1 166 9
 167:../src/application/main.c ****         uint32_t VFP=54;
 161              		.loc 1 167 9
 168:../src/application/main.c ****         uint32_t VSW=5;
 162              		.loc 1 168 9
 169:../src/application/main.c ****         uint32_t VBP=3;
 163              		.loc 1 169 9
 170:../src/application/main.c ****         uint32_t VSP=0x00008000;
 164              		.loc 1 170 9
 171:../src/application/main.c ****         uint32_t LANE_NO=0x00000004;
 165              		.loc 1 171 9
 172:../src/application/main.c **** #endif
 166              		.loc 1 172 9
 175:../src/application/main.c ****         uint32_t Disable=0;
 167              		.loc 1 175 9
 176:../src/application/main.c **** 
 168              		.loc 1 176 9
 179:../src/application/main.c ****         Disable = 0x00;
 169              		.loc 1 179 9
 180:../src/application/main.c **** 
 170              		.loc 1 180 9
 182:../src/application/main.c **** 
 171              		.loc 1 182 9
 172 001c 97000000 		call	axi4litewrite
 172      E7800000 
 173              	.LVL5:
 174              		.loc 1 184 9
 175 0024 13054400 		addi	a0,s0,4
 176 0028 8145     		li	a1,0
 177 002a 97000000 		call	axi4litewrite
 177      E7800000 
 178              	.LVL6:
 185:../src/application/main.c **** 
 186:../src/application/main.c ****         axi4litewrite(DC_IP_HRES,HRES/PIXEL_MODE);
 179              		.loc 1 186 9
 180 0032 13058400 		addi	a0,s0,8
 181 0036 9305003C 		li	a1,960
 182 003a 97000000 		call	axi4litewrite
 182      E7800000 
 183              	.LVL7:
 187:../src/application/main.c ****         axi4litewrite(DC_IP_VRES,VRES);
 184              		.loc 1 187 9
 185 0042 8564     		li	s1,4096
 186 0044 93850487 		addi	a1,s1,-1936
 187 0048 1305C400 		addi	a0,s0,12
 188 004c 97000000 		call	axi4litewrite
 188      E7800000 
 189              	.LVL8:
 188:../src/application/main.c ****         axi4litewrite(DC_IP_HFP,HFP/PIXEL_MODE);
 190              		.loc 1 188 9
 191 0054 13050401 		addi	a0,s0,16
 192 0058 CD45     		li	a1,19
 193 005a 97000000 		call	axi4litewrite
 193      E7800000 
 194              	.LVL9:
 189:../src/application/main.c ****         axi4litewrite(DC_IP_HBP,HBP/PIXEL_MODE);
 195              		.loc 1 189 9
 196 0062 13054401 		addi	a0,s0,20
 197 0066 CD45     		li	a1,19
 198 0068 97000000 		call	axi4litewrite
 198      E7800000 
 199              	.LVL10:
 190:../src/application/main.c ****         axi4litewrite(DC_IP_VFP,VFP);
 200              		.loc 1 190 9
 201 0070 13058401 		addi	a0,s0,24
 202 0074 93056003 		li	a1,54
 203 0078 97000000 		call	axi4litewrite
 203      E7800000 
 204              	.LVL11:
 191:../src/application/main.c ****         axi4litewrite(DC_IP_VBP,VBP);
 205              		.loc 1 191 9
 206 0080 1305C401 		addi	a0,s0,28
 207 0084 8D45     		li	a1,3
 208 0086 97000000 		call	axi4litewrite
 208      E7800000 
 209              	.LVL12:
 192:../src/application/main.c ****         axi4litewrite(DC_IP_HSW,HSW/PIXEL_MODE);
 210              		.loc 1 192 9
 211 008e 13050402 		addi	a0,s0,32
 212 0092 8945     		li	a1,2
 213 0094 97000000 		call	axi4litewrite
 213      E7800000 
 214              	.LVL13:
 193:../src/application/main.c ****         axi4litewrite(DC_IP_VSW,VSW);
 215              		.loc 1 193 9
 216 009c 13054402 		addi	a0,s0,36
 217 00a0 9545     		li	a1,5
 218 00a2 97000000 		call	axi4litewrite
 218      E7800000 
 219              	.LVL14:
 194:../src/application/main.c **** 
 195:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Enable); // Enabling the IP
 220              		.loc 1 195 9
 221 00aa 13054400 		addi	a0,s0,4
 222 00ae 8545     		li	a1,1
 223 00b0 97000000 		call	axi4litewrite
 223      E7800000 
 224              	.LVL15:
 196:../src/application/main.c **** 
 197:../src/application/main.c ****         //Displaycontroller(HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,PIXEL_MODE/*,BAYER_OFFSET_VALUE*/);
 198:../src/application/main.c **** 
 199:../src/application/main.c ****         uint32_t div = (HRES*VRES*2);
 225              		.loc 1 199 9
 200:../src/application/main.c **** 
 201:../src/application/main.c ****     GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
 226              		.loc 1 201 5
 227 00b8 0946     		li	a2,2
 228 00ba B7450071 		li	a1,1895841792
 229 00be 17050000 		lla	a0,g_gpio_out
 229      13050500 
 230 00c6 97000000 		call	GPIO_init
 230      E7800000 
 231              	.LVL16:
 202:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED1, 1);
 232              		.loc 1 202 5
 233 00ce 0546     		li	a2,1
 234 00d0 8145     		li	a1,0
 235 00d2 17050000 		lla	a0,g_gpio_out
 235      13050500 
 236 00da 97000000 		call	GPIO_set_output
 236      E7800000 
 237              	.LVL17:
 203:../src/application/main.c **** 
 204:../src/application/main.c ****     MRV_systick_config(SYS_CLK_FREQ / 1000);
 238              		.loc 1 204 5
 239 00e2 3165     		li	a0,49152
 240 00e4 8145     		li	a1,0
 241 00e6 13050535 		addi	a0,a0,848
 242 00ea 97000000 		call	MRV_systick_config
 242      E7800000 
 243              	.LVL18:
 205:../src/application/main.c **** 
 206:../src/application/main.c ****     MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
 244              		.loc 1 206 5
 245              		.file 2 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
   1:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
   6:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  10:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  11:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  12:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*=========================================================================*//**
  13:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  15:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  16:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Introduction
  17:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  18:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  25:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  30:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  35:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  39:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  40:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  42:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, see
  43:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-tools/m
  44:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  45:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Core and this document use the following terms:
  46:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  48:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  58:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  59:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  61:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32 preprocessor, macros have been
  62:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted. The HAL is used
  63:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   to target the mentioned platforms by adding the following macros in Project
  64:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Properties > C/C++ Build > Settings > Preprocessor available in the Assembler
  65:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and Compiler settings. The following table shows the macros corresponding to the
  66:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV Core being used in your libero project. By default, the HAL targets v3.1 of
  67:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the IP core and no macros need to be set for this configutation.
  68:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  69:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  70:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-----------------------------|-------------------|
  71:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  72:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  73:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  74:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  75:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  76:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt Handling
  77:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  78:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  79:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  80:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
  81:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  82:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  83:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  84:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  85:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  86:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  87:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  88:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  89:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  90:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  91:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  92:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  93:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  94:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  95:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  96:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  97:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
  98:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
  99:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 100:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 101:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 102:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 103:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 104:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 105:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 106:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 107:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 108:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 109:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 110:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 111:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 112:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 113:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 114:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the value stored in the 
 115:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 116:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handler is as an interrupt service routine.
 117:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 118:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 119:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 120:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 121:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 122:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 123:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 124:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 125:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 126:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32.
 127:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 128:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 129:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 130:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 131:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 132:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 133:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 134:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 135:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 136:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 137:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 138:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 139:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 140:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 141:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 142:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 143:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   unchanged.
 144:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 145:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 146:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Floating Point Interrupt Support
 147:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 148:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 149:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 150:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 151:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Softconsole build settings.
 152:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 153:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   when the ISR does not use FP insturctions and saving the general purpose 
 154:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   register context is sufficient.
 155:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 156:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 157:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 158:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 159:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 160:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 161:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 162:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 163:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 164:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. Refer to the MIV_RV32 v3.1 Handbook for
 165:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   more details.  
 166:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   NOTE: This was previously (MIV_RV32 v3.0) known as OPSRV, which stands for 
 167:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   "Offload Processor Subsystem for RISC-V". See the earlier versions of the 
 168:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook for more details. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 169:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 170:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *//*=========================================================================*/
 171:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 172:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
 173:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 174:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 175:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 176:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 177:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 178:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 179:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 180:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "../../boards/polarfire-video-kit/fpga_design_config/fpga_design_config.h"
 181:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 182:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
 183:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 184:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 185:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
 186:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
 187:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 188:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 189:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 190:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 191:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 192:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 193:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 194:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 195:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 196:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 197:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------------|--------------------------|
 198:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 199:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 200:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 201:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 202:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 203:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 204:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 205:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 206:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 207:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 208:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 209:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 210:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 211:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 212:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine timer interrupt
 213:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 214:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 215:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 216:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 217:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 218:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 219:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME and MTIMECMP
 220:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 221:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 222:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 223:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   possible combinations:
 224:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 225:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 226:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 227:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 228:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 229:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 230:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 231:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 232:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 233:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 234:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 235:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 236:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   core as input.
 237:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 238:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 239:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 240:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 241:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt.
 242:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 243:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 244:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 245:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core design.
 246:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 247:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 248:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 249:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 250:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 251:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 252:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   available internally to the core.
 253:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 254:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 255:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 256:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 257:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 258:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 259:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 260:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 261:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 262:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 263:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 264:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 265:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 266:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 267:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 268:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 269:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 270:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 271:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 272:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 273:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 274:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External IRQ
 275:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 276:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 277:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External Interrupt.
 278:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 279:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 280:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 281:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 282:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 283:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 284:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 285:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 286:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 287:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
 288:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 289:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 290:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 291:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 292:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 293:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 294:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 295:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 296:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 297:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 298:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 299:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 300:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 301:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 302:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 303:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 304:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 305:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 306:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 307:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 308:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 309:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 310:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 311:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 312:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 313:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 314:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 315:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 316:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 317:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIMPID Register
 318:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 319:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 320:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 321:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 322:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 323:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 324:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 325:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 326:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 327:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP core version.
 328:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 329:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 330:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 331:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 332:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 333:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 334:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 335:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 336:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 337:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 338:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 339:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 340:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 341:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 342:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 343:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 344:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 345:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   RISC-V Specification Interrupts
 346:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 347:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 348:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   in the MIE/MIP registers.
 349:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 350:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 351:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 352:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
 353:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, following table shows the 
 354:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt priority order and register description as mentioned in the RISC-V spec.
 355:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 356:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 357:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 358:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 359:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 360:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 361:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 362:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 363:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 364:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 365:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 366:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 367:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 368:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM
 369:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =================================
 370:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When BootROM is enabled, on reset, the core copies data from a memory mapped
 371:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   source memory into a destination memory location and then the core boots from
 372:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the destination memory location. The source start or end addresses and the
 373:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination start address can be provided through GUI inputs. If the 
 374:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reconfigurable option is enabled, then the addresses become software 
 375:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   reconfigurable, which can be used with a soft reset to reboot and run alternative
 376:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   code. The source and destination memory must be a memory mapped location 
 377:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   accessible by the core across the full transfer size.
 378:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 379:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTVEC address - By default, the mtvec.BASE is set at Reset Vector Address + 0x04.
 380:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When the BootROM is enabled, the mtvec.BASE is set at destination address + 0x04.
 381:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When using Reconfigurable BootROM, the MTVEC register needs to be defined 
 382:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and programmed through software.
 383:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 384:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reset Behaviour - With the BootROM feature enabled, upon reset, the PC takes on
 385:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the value of the BootROM dest_addr. When the BootROM is enabled, ensure that the
 386:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   boot code linker script matches the dest_addr, since booting starts from the
 387:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination_addr.
 388:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 389:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM Register Map:
 390:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Name  |  Address  | Description |
 391:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------|-----------|-------------|
 392:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_start_addr     |0xA100| Core copies data beginning here       |
 393:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_end_addr       |0xA104| Last address copied by BootROM        |
 394:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | destination_addr   |0xA108| Destination memory beginning from here|
 395:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 396:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** */
 397:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 398:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_START                    0x0000A100
 399:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_END                      0x0000A104
 400:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_DEST                     0x0000A108
 401:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 402:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 403:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt numbers:
 404:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 405:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 406:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 407:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 408:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 409:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 410:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 411:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 412:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 413:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 414:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 415:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 416:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 417:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 418:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 419:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 420:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 421:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 422:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 423:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 424:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 425:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 426:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 427:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 428:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 429:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 430:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 431:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 432:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 433:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 434:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 435:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 436:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 437:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 438:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 439:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 440:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 441:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 442:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 443:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 444:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 445:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 446:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 447:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 448:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 449:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 450:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 451:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 452:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 453:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 454:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 455:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 456:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 457:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 458:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 459:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 460:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 461:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 462:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 463:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 464:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 465:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 466:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 467:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 468:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 469:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 470:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 471:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 472:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 473:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 474:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 475:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 476:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   */
 477:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 478:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 479:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 480:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 481:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 482:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 483:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 484:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 485:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 486:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 487:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 488:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 489:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 490:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 491:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 492:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 493:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 494:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 495:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 496:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 497:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 498:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 499:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 500:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 501:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 502:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 503:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 504:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 505:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 506:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 507:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 508:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 509:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 510:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 511:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 512:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 513:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 514:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 515:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 516:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 517:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 518:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 519:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 520:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 521:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 522:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 523:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 524:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 525:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 526:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 527:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 528:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 529:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 530:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 531:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 532:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 533:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 534:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 535:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 536:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 537:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 538:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 539:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 540:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 541:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 542:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 543:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 544:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 545:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 546:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 547:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 548:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 549:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 550:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 551:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 552:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 553:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 554:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 555:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 556:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 557:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 558:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 559:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 560:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 561:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 562:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 563:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 564:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 565:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 566:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 567:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 568:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 569:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 570:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 571:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 572:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 573:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 574:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 575:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 576:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 577:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 578:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 579:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 580:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 581:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 582:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 583:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 584:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 585:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 586:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   IP configurator.
 587:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 588:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 589:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 590:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 591:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 592:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 593:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 594:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 595:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 596:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 597:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 598:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 599:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
 600:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 601:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return 
 602:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 603:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 604:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 605:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 606:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 607:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 608:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 609:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 610:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 611:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 612:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 613:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 614:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 615:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 616:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 617:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 618:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 619:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 620:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
 246              		.loc 2 620 5
 247              	.LBB11:
 248              	.LBB12:
 249              		.loc 2 620 5
 250              		.loc 2 620 5
 251 00f2 B7070001 		li	a5,16777216
 252              	 #APP
 253              	# 620 "C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p
   0              	
 254              		csrrs a5, mie, a5
 255              	# 0 "" 2
 256              	.LVL19:
 257              		.loc 2 620 5
 258              	 #NO_APP
 259              	.LBE12:
 260              	.LBE11:
 207:../src/application/main.c **** 
 208:../src/application/main.c ****     HAL_enable_interrupts();
 261              		.loc 1 208 5
 262 00fa 97000000 		call	HAL_enable_interrupts
 262      E7800000 
 263              	.LVL20:
 209:../src/application/main.c **** 
 210:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 0u);
 264              		.loc 1 210 5
 265 0102 0146     		li	a2,0
 266 0104 9145     		li	a1,4
 267 0106 17050000 		lla	a0,g_gpio_out
 267      13050500 
 268 010e 97000000 		call	GPIO_set_output
 268      E7800000 
 269              	.LVL21:
 211:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED2, 1);
 270              		.loc 1 211 5
 271 0116 0546     		li	a2,1
 272 0118 8545     		li	a1,1
 273 011a 17050000 		lla	a0,g_gpio_out
 273      13050500 
 274 0122 97000000 		call	GPIO_set_output
 274      E7800000 
 275              	.LVL22:
 212:../src/application/main.c **** 
 213:../src/application/main.c ****     //Camera Initialization
 214:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM1_RST, 1u);
 276              		.loc 1 214 5
 277 012a 0546     		li	a2,1
 278 012c A145     		li	a1,8
 279 012e 17050000 		lla	a0,g_gpio_out
 279      13050500 
 280 0136 97000000 		call	GPIO_set_output
 280      E7800000 
 281              	.LVL23:
 215:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM_CLK_EN, 0u);
 282              		.loc 1 215 5
 283 013e 0146     		li	a2,0
 284 0140 A545     		li	a1,9
 285 0142 17050000 		lla	a0,g_gpio_out
 285      13050500 
 286 014a 97000000 		call	GPIO_set_output
 286      E7800000 
 287              	.LVL24:
 216:../src/application/main.c ****     imx334_cam_init();
 288              		.loc 1 216 5
 289 0152 97000000 		call	imx334_cam_init
 289      E7800000 
 290              	.LVL25:
 217:../src/application/main.c ****     imx334_cam_reginit(1u);
 291              		.loc 1 217 5
 292 015a 0545     		li	a0,1
 293 015c 97000000 		call	imx334_cam_reginit
 293      E7800000 
 294              	.LVL26:
 218:../src/application/main.c **** 
 219:../src/application/main.c ****     //Setting LED
 220:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED3, 1);
 295              		.loc 1 220 5
 296 0164 0546     		li	a2,1
 297 0166 8945     		li	a1,2
 298 0168 17050000 		lla	a0,g_gpio_out
 298      13050500 
 299 0170 97000000 		call	GPIO_set_output
 299      E7800000 
 300              	.LVL27:
 221:../src/application/main.c ****     msdelay(1000);
 301              		.loc 1 221 5
 302 0178 1305803E 		li	a0,1000
 303 017c 97000000 		call	msdelay
 303      E7800000 
 304              	.LVL28:
 222:../src/application/main.c **** //    delay_msec(100);
 223:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 1u);
 305              		.loc 1 223 5
 306 0184 0546     		li	a2,1
 307 0186 9145     		li	a1,4
 308 0188 17050000 		lla	a0,g_gpio_out
 308      13050500 
 309 0190 97000000 		call	GPIO_set_output
 309      E7800000 
 310              	.LVL29:
 224:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED4, 1);
 311              		.loc 1 224 5
 312 0198 0546     		li	a2,1
 313 019a 8D45     		li	a1,3
 314 019c 17050000 		lla	a0,g_gpio_out
 314      13050500 
 315 01a4 97000000 		call	GPIO_set_output
 315      E7800000 
 316              	.LVL30:
 225:../src/application/main.c **** 
 226:../src/application/main.c ****     // =========================== DisplayPort ================================
 227:../src/application/main.c ****     UART_init(&g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, (DATA_8_BITS | NO_PARITY));
 317              		.loc 1 227 5
 318 01ac 8546     		li	a3,1
 319 01ae 6946     		li	a2,26
 320 01b0 B7050071 		li	a1,1895825408
 321 01b4 17050000 		lla	a0,g_uart
 321      13050500 
 322 01bc 97000000 		call	UART_init
 322      E7800000 
 323              	.LVL31:
 228:../src/application/main.c ****     DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 324              		.loc 1 228 5
 325 01c4 9147     		li	a5,4
 326 01c6 3EC4     		sw	a5,8(sp)
 327 01c8 A167     		li	a5,32768
 328 01ca 3EC2     		sw	a5,4(sp)
 329 01cc 9547     		li	a5,5
 330 01ce 3EC0     		sw	a5,0(sp)
 331 01d0 13860487 		addi	a2,s1,-1936
 332 01d4 938504F0 		addi	a1,s1,-256
 333 01d8 A148     		li	a7,8
 334 01da 0D48     		li	a6,3
 335 01dc 93076003 		li	a5,54
 336 01e0 1307C004 		li	a4,76
 337 01e4 9306C004 		li	a3,76
 338 01e8 0945     		li	a0,2
 229:../src/application/main.c **** 
 230:../src/application/main.c ****     // ========================================================================
 231:../src/application/main.c **** 
 232:../src/application/main.c ****     do
 233:../src/application/main.c ****     {
 234:../src/application/main.c ****         // ====================================================================
 235:../src/application/main.c ****         // ===================== DisplayPort ==================================
 236:../src/application/main.c ****         // ====================================================================
 237:../src/application/main.c ****         // Check if there is Sink Interrupt
 238:../src/application/main.c ****         DPSourceISR(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 339              		.loc 1 238 9 is_stmt 0
 340 01ea 138A0487 		addi	s4,s1,-1936
 228:../src/application/main.c ****     DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 341              		.loc 1 228 5
 342 01ee 97000000 		call	DPSourceInit
 342      E7800000 
 343              	.LVL32:
 344              		.loc 1 238 9
 345 01f6 1144     		li	s0,4
 346 01f8 A169     		li	s3,32768
 347 01fa 938404F0 		addi	s1,s1,-256
 348              	.LBB13:
 349              	.LBB14:
 350              	.LBB15:
 351              	.LBB16:
 239:../src/application/main.c ****         msdelay(30);
 240:../src/application/main.c ****                 auto_brightness(div);
 241:../src/application/main.c **** 
 242:../src/application/main.c **** 
 243:../src/application/main.c ****         counter = counter +1;
 244:../src/application/main.c ****         if (counter <16){
 245:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 246:../src/application/main.c ****         }
 247:../src/application/main.c ****         else{
 248:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 1);
 249:../src/application/main.c ****         }
 250:../src/application/main.c ****         if (counter ==32){
 251:../src/application/main.c ****             counter =0;
 252:../src/application/main.c ****         }
 253:../src/application/main.c **** 
 254:../src/application/main.c ****     } while (1);
 255:../src/application/main.c **** 
 256:../src/application/main.c **** 
 257:../src/application/main.c ****     return 0;
 258:../src/application/main.c **** }
 259:../src/application/main.c **** 
 260:../src/application/main.c **** /**********************************************************/
 261:../src/application/main.c **** /**********************FUNCTION CALLS**********************/
 262:../src/application/main.c **** /**********************************************************/
 263:../src/application/main.c **** void auto_brightness(uint32_t div)
 264:../src/application/main.c **** {
 265:../src/application/main.c ****     uint32_t total_sum =  (uint32_t)(*(volatile int*) IE_INTENSITY_AVARAGE);
 266:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 267:../src/application/main.c **** 
 268:../src/application/main.c ****     gain_cal(total_average);
 269:../src/application/main.c **** }
 270:../src/application/main.c **** 
 271:../src/application/main.c **** void gain_cal(uint32_t total_average)
 272:../src/application/main.c **** {
 273:../src/application/main.c ****     //////////////////////////////////////////////////////
 274:../src/application/main.c ****     const int16_t good_average=100;
 275:../src/application/main.c ****     const int16_t hysteresis=4;
 276:../src/application/main.c ****     int16_t step;
 277:../src/application/main.c ****         if(total_average < (good_average - hysteresis))
 278:../src/application/main.c ****             step = 1;
 279:../src/application/main.c ****         else
 280:../src/application/main.c ****             if(total_average > (good_average + hysteresis))
 281:../src/application/main.c ****                 step = -1;
 282:../src/application/main.c ****             else
 283:../src/application/main.c ****                 step = 0;
 284:../src/application/main.c **** 
 285:../src/application/main.c ****         in_gain = in_gain + step;
 352              		.loc 1 285 27
 353 01fe 970A0000 		lla	s5,.LANCHOR4
 353      938A0A00 
 354              	.L18:
 355              	.LBE16:
 356              	.LBE15:
 357              	.LBE14:
 358              	.LBE13:
 238:../src/application/main.c ****         msdelay(30);
 359              		.loc 1 238 9
 360 0206 1549     		li	s2,5
 361              	.L17:
 232:../src/application/main.c ****     {
 362              		.loc 1 232 5 is_stmt 1
 238:../src/application/main.c ****         msdelay(30);
 363              		.loc 1 238 9
 364 0208 93076003 		li	a5,54
 365 020c 1307C004 		li	a4,76
 366 0210 9306C004 		li	a3,76
 367 0214 A148     		li	a7,8
 368 0216 0D48     		li	a6,3
 369 0218 5286     		mv	a2,s4
 370 021a A685     		mv	a1,s1
 371 021c 0945     		li	a0,2
 372 021e 22C4     		sw	s0,8(sp)
 373 0220 4EC2     		sw	s3,4(sp)
 374 0222 4AC0     		sw	s2,0(sp)
 375 0224 97000000 		call	DPSourceISR
 375      E7800000 
 376              	.LVL33:
 239:../src/application/main.c ****         msdelay(30);
 377              		.loc 1 239 9
 378 022c 7945     		li	a0,30
 379 022e 97000000 		call	msdelay
 379      E7800000 
 380              	.LVL34:
 240:../src/application/main.c **** 
 381              		.loc 1 240 17
 382              	.LBB23:
 383              	.LBB21:
 265:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 384              		.loc 1 265 5
 265:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 385              		.loc 1 265 38 is_stmt 0
 386 0236 B7070372 		li	a5,1912799232
 387 023a 984F     		lw	a4,24(a5)
 388              	.LVL35:
 266:../src/application/main.c **** 
 389              		.loc 1 266 5 is_stmt 1
 268:../src/application/main.c **** }
 390              		.loc 1 268 5
 391              	.LBB19:
 392              	.LBB17:
 274:../src/application/main.c ****     const int16_t hysteresis=4;
 393              		.loc 1 274 5
 275:../src/application/main.c ****     int16_t step;
 394              		.loc 1 275 5
 276:../src/application/main.c ****         if(total_average < (good_average - hysteresis))
 395              		.loc 1 276 5
 277:../src/application/main.c ****             step = 1;
 396              		.loc 1 277 9
 277:../src/application/main.c ****             step = 1;
 397              		.loc 1 277 11 is_stmt 0
 398 023c B706EC5E 		li	a3,1592524800
 278:../src/application/main.c ****         else
 399              		.loc 1 278 18
 400 0240 8547     		li	a5,1
 277:../src/application/main.c ****             step = 1;
 401              		.loc 1 277 11
 402 0242 6369D700 		bltu	a4,a3,.L11
 280:../src/application/main.c ****                 step = -1;
 403              		.loc 1 280 13 is_stmt 1
 280:../src/application/main.c ****                 step = -1;
 404              		.loc 1 280 15 is_stmt 0
 405 0246 B727D267 		li	a5,1741824000
 406 024a B337F700 		sltu	a5,a4,a5
 407 024e FD17     		addi	a5,a5,-1
 408 0250 C207     		slli	a5,a5,16
 409 0252 C187     		srai	a5,a5,16
 410              	.L11:
 411              	.LVL36:
 412              		.loc 1 285 9 is_stmt 1
 413              		.loc 1 285 27 is_stmt 0
 414 0254 03D70A00 		lhu	a4,0(s5)
 415              	.LVL37:
 416 0258 BA97     		add	a5,a5,a4
 417              	.LVL38:
 418 025a C207     		slli	a5,a5,16
 419 025c C183     		srli	a5,a5,16
 286:../src/application/main.c **** 
 287:../src/application/main.c ****         if(in_gain < 5)
 420              		.loc 1 287 9 is_stmt 1
 421              		.loc 1 287 11 is_stmt 0
 422 025e 6368F404 		bgtu	a5,s0,.L12
 288:../src/application/main.c ****             in_gain = 5;
 423              		.loc 1 288 13 is_stmt 1
 424              		.loc 1 288 21 is_stmt 0
 425 0262 97070000 		sh	s2,.LANCHOR4,a5
 425      23902701 
 426              	.L13:
 289:../src/application/main.c ****         else
 290:../src/application/main.c ****             if(in_gain >= 100)
 291:../src/application/main.c ****                 in_gain = 100;
 292:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 293:../src/application/main.c ****     gain_setting(1u,in_gain);
 427              		.loc 1 293 5 is_stmt 1
 428 026a 97050000 		lhu	a1,.LANCHOR4
 428      83D50500 
 429 0272 0545     		li	a0,1
 430 0274 97000000 		call	gain_setting
 430      E7800000 
 431              	.LVL39:
 432              	.LBE17:
 433              	.LBE19:
 434              	.LBE21:
 435              	.LBE23:
 243:../src/application/main.c ****         if (counter <16){
 436              		.loc 1 243 9
 243:../src/application/main.c ****         if (counter <16){
 437              		.loc 1 243 27 is_stmt 0
 438 027c F247     		lw	a5,28(sp)
 245:../src/application/main.c ****         }
 439              		.loc 1 245 13
 440 027e 0146     		li	a2,0
 243:../src/application/main.c ****         if (counter <16){
 441              		.loc 1 243 27
 442 0280 8507     		addi	a5,a5,1
 243:../src/application/main.c ****         if (counter <16){
 443              		.loc 1 243 17
 444 0282 3ECE     		sw	a5,28(sp)
 244:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 445              		.loc 1 244 9 is_stmt 1
 244:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 446              		.loc 1 244 21 is_stmt 0
 447 0284 7247     		lw	a4,28(sp)
 244:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 448              		.loc 1 244 12
 449 0286 BD47     		li	a5,15
 450 0288 63F3E700 		bleu	a4,a5,.L23
 248:../src/application/main.c ****         }
 451              		.loc 1 248 13 is_stmt 1
 452 028c 0546     		li	a2,1
 453              	.L23:
 454 028e 8145     		li	a1,0
 455 0290 17050000 		lla	a0,g_gpio_out
 455      13050500 
 456 0298 97000000 		call	GPIO_set_output
 456      E7800000 
 457              	.LVL40:
 250:../src/application/main.c ****             counter =0;
 458              		.loc 1 250 9
 250:../src/application/main.c ****             counter =0;
 459              		.loc 1 250 21 is_stmt 0
 460 02a0 7247     		lw	a4,28(sp)
 250:../src/application/main.c ****             counter =0;
 461              		.loc 1 250 12
 462 02a2 93070002 		li	a5,32
 463 02a6 E311F7F6 		bne	a4,a5,.L17
 251:../src/application/main.c ****         }
 464              		.loc 1 251 13 is_stmt 1
 251:../src/application/main.c ****         }
 465              		.loc 1 251 21 is_stmt 0
 466 02aa 02CE     		sw	zero,28(sp)
 467 02ac A9BF     		j	.L18
 468              	.LVL41:
 469              	.L12:
 470              	.LBB24:
 471              	.LBB22:
 472              	.LBB20:
 473              	.LBB18:
 290:../src/application/main.c ****                 in_gain = 100;
 474              		.loc 1 290 13 is_stmt 1
 290:../src/application/main.c ****                 in_gain = 100;
 475              		.loc 1 290 15 is_stmt 0
 476 02ae 13073006 		li	a4,99
 477 02b2 6367F700 		bgtu	a5,a4,.L14
 478              	.L22:
 291:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 479              		.loc 1 291 25
 480 02b6 17070000 		sh	a5,.LANCHOR4,a4
 480      2310F700 
 481 02be 75B7     		j	.L13
 482              	.L14:
 291:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 483              		.loc 1 291 17 is_stmt 1
 291:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 484              		.loc 1 291 25 is_stmt 0
 485 02c0 93074006 		li	a5,100
 486 02c4 CDBF     		j	.L22
 487              	.LBE18:
 488              	.LBE20:
 489              	.LBE22:
 490              	.LBE24:
 491              		.cfi_endproc
 492              	.LFE23:
 494              		.comm	a,4,4
 495              		.globl	process_data
 496              		.globl	i
 497              		.globl	t_ms_count
 498              		.comm	rx_ms_count,4,4
 499              		.comm	rx_ms_count1,4,4
 500              		.globl	rx_tmr_done
 501              		.globl	g_state
 502              		.comm	g_gpio_out,8,4
 503              		.comm	bayer,2,2
 504              		.comm	g_uart,8,4
 505              		.globl	uart_rx_buff
 506              		.comm	g_i2c_instance_cam1,108,4
 507              		.comm	g_ms_count,4,4
 508              		.comm	g_10ms_count1,4,4
 509              		.globl	timerdone
 510              		.comm	g_10ms_count,4,4
 511              		.comm	MRV_LOCAL_IRQn_Type,4,4
 512              		.section	.bss.uart_rx_buff,"aw",@nobits
 513              		.align	2
 516              	uart_rx_buff:
 517 0000 00000000 		.zero	23
 517      00000000 
 517      00000000 
 517      00000000 
 517      00000000 
 518              		.section	.sbss.i,"aw",@nobits
 519              		.align	2
 522              	i:
 523 0000 00000000 		.zero	4
 524              		.section	.sbss.process_data,"aw",@nobits
 525              		.align	2
 526              		.set	.LANCHOR3,. + 0
 529              	process_data:
 530 0000 00000000 		.zero	4
 531              		.section	.sbss.rx_tmr_done,"aw",@nobits
 532              		.align	2
 533              		.set	.LANCHOR2,. + 0
 536              	rx_tmr_done:
 537 0000 00000000 		.zero	4
 538              		.section	.sbss.t_ms_count,"aw",@nobits
 539              		.align	2
 542              	t_ms_count:
 543 0000 00000000 		.zero	4
 544              		.section	.sbss.timerdone,"aw",@nobits
 545              		.align	2
 546              		.set	.LANCHOR1,. + 0
 549              	timerdone:
 550 0000 00000000 		.zero	4
 551              		.section	.sdata.g_state,"aw"
 552              		.align	2
 553              		.set	.LANCHOR0,. + 0
 556              	g_state:
 557 0000 01000000 		.word	1
 558              		.section	.sdata.in_gain,"aw"
 559              		.align	1
 560              		.set	.LANCHOR4,. + 0
 563              	in_gain:
 564 0000 5000     		.half	80
 565              		.text
 566              	.Letext0:
 567              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 568              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 569              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 570              		.file 6 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 571              		.file 7 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 572              		.file 8 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 573              		.file 9 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 574              		.file 10 "../src/application/dp_cmd_common.h"
 575              		.file 11 "../src/application/imx334_corei2c/imx334_corei2c.h"
 576              		.file 12 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softco
 577              		.file 13 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softco
 578              		.file 14 "../src/application/dp_cmd_tx.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 main.c
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:13     .text.SysTick_Handler:0000000000000000 SysTick_Handler
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:17     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:18     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:19     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:20     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:26     .text.SysTick_Handler:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:27     .text.SysTick_Handler:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:30     .text.SysTick_Handler:0000000000000022 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:33     .text.SysTick_Handler:0000000000000028 .L0 
                            *COM*:0000000000000004 g_10ms_count1
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:34     .text.SysTick_Handler:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:39     .text.SysTick_Handler:000000000000003c .L0 
                            *COM*:0000000000000004 g_ms_count
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:40     .text.SysTick_Handler:000000000000003c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:44     .text.SysTick_Handler:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:46     .text.SysTick_Handler:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:47     .text.SysTick_Handler:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:50     .text.SysTick_Handler:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:51     .text.SysTick_Handler:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:54     .text.SysTick_Handler:000000000000005e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:57     .text.SysTick_Handler:0000000000000064 .L0 
                            *COM*:0000000000000004 rx_ms_count1
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:58     .text.SysTick_Handler:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:63     .text.SysTick_Handler:0000000000000078 .L0 
                            *COM*:0000000000000004 rx_ms_count
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:64     .text.SysTick_Handler:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:68     .text.SysTick_Handler:0000000000000084 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:70     .text.SysTick_Handler:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:71     .text.SysTick_Handler:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:73     .text.SysTick_Handler:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:74     .text.SysTick_Handler:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:77     .text.SysTick_Handler:0000000000000098 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:78     .text.SysTick_Handler:000000000000009a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:85     .text.MSYS_EI0_IRQHandler:0000000000000000 MSYS_EI0_IRQHandler
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:88     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:89     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:90     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:91     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:92     .text.MSYS_EI0_IRQHandler:0000000000000002 .L0 
                            *COM*:000000000000006c g_i2c_instance_cam1
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:94     .text.MSYS_EI0_IRQHandler:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:96     .text.MSYS_EI0_IRQHandler:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:97     .text.MSYS_EI0_IRQHandler:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:99     .text.MSYS_EI0_IRQHandler:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:102    .text.MSYS_EI0_IRQHandler:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:103    .text.MSYS_EI0_IRQHandler:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:104    .text.MSYS_EI0_IRQHandler:0000000000000016 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:107    .text.MSYS_EI0_IRQHandler:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:109    .text.MSYS_EI0_IRQHandler:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:116    .text.startup.main:0000000000000000 main
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:119    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:121    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:122    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:123    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:124    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:125    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:126    .text.startup.main:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:128    .text.startup.main:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:133    .text.startup.main:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:136    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:137    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:138    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:140    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:142    .text.startup.main:0000000000000012 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:146    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:147    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:148    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:149    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:151    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:154    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:155    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:156    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:157    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:158    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:159    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:160    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:161    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:162    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:163    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:164    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:165    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:166    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:167    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:168    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:169    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:170    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:171    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:172    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:175    .text.startup.main:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:180    .text.startup.main:0000000000000032 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:185    .text.startup.main:0000000000000042 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:191    .text.startup.main:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:196    .text.startup.main:0000000000000062 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:201    .text.startup.main:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:206    .text.startup.main:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:211    .text.startup.main:000000000000008e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:216    .text.startup.main:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:221    .text.startup.main:00000000000000aa .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:226    .text.startup.main:00000000000000b8 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:227    .text.startup.main:00000000000000b8 .L0 
                            *COM*:0000000000000008 g_gpio_out
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:233    .text.startup.main:00000000000000ce .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:239    .text.startup.main:00000000000000e2 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:246    .text.startup.main:00000000000000f2 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:249    .text.startup.main:00000000000000f2 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:250    .text.startup.main:00000000000000f2 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:251    .text.startup.main:00000000000000f2 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:261    .text.startup.main:00000000000000fa .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:262    .text.startup.main:00000000000000fa .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:265    .text.startup.main:0000000000000102 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:271    .text.startup.main:0000000000000116 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:277    .text.startup.main:000000000000012a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:283    .text.startup.main:000000000000013e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:289    .text.startup.main:0000000000000152 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:292    .text.startup.main:000000000000015a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:296    .text.startup.main:0000000000000164 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:302    .text.startup.main:0000000000000178 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:306    .text.startup.main:0000000000000184 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:312    .text.startup.main:0000000000000198 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:318    .text.startup.main:00000000000001ac .L0 
                            *COM*:0000000000000008 g_uart
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:325    .text.startup.main:00000000000001c4 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:340    .text.startup.main:00000000000001ea .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:342    .text.startup.main:00000000000001ee .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:345    .text.startup.main:00000000000001f6 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:353    .text.startup.main:00000000000001fe .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:360    .text.startup.main:0000000000000206 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:363    .text.startup.main:0000000000000208 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:364    .text.startup.main:0000000000000208 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:378    .text.startup.main:000000000000022c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:384    .text.startup.main:0000000000000236 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:385    .text.startup.main:0000000000000236 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:386    .text.startup.main:0000000000000236 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:390    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:393    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:394    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:395    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:396    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:397    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:398    .text.startup.main:000000000000023c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:400    .text.startup.main:0000000000000240 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:402    .text.startup.main:0000000000000242 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:404    .text.startup.main:0000000000000246 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:405    .text.startup.main:0000000000000246 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:413    .text.startup.main:0000000000000254 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:414    .text.startup.main:0000000000000254 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:421    .text.startup.main:000000000000025e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:422    .text.startup.main:000000000000025e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:424    .text.startup.main:0000000000000262 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:425    .text.startup.main:0000000000000262 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:428    .text.startup.main:000000000000026a .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:437    .text.startup.main:000000000000027c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:438    .text.startup.main:000000000000027c .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:440    .text.startup.main:000000000000027e .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:442    .text.startup.main:0000000000000280 .L0 
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:444    .text.startup.main:0000000000000282 .L0 
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C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3611   .debug_str:000000000000024f .LASF115
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3715   .debug_str:0000000000000583 .LASF116
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3829   .debug_str:000000000000082a .LASF117
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3885   .debug_str:0000000000000a0f .LASF118
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3703   .debug_str:000000000000053a .LASF119
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3615   .debug_str:0000000000000275 .LASF120
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3743   .debug_str:0000000000000604 .LASF121
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3707   .debug_str:0000000000000556 .LASF122
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3757   .debug_str:0000000000000661 .LASF123
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3841   .debug_str:00000000000008e9 .LASF124
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3913   .debug_str:0000000000000a89 .LASF125
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3631   .debug_str:00000000000002d5 .LASF126
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3789   .debug_str:000000000000071f .LASF127
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3859   .debug_str:000000000000095a .LASF128
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3705   .debug_str:0000000000000549 .LASF129
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3601   .debug_str:0000000000000202 .LASF130
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3539   .debug_str:000000000000006d .LASF131
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3653   .debug_str:0000000000000415 .LASF132
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3819   .debug_str:00000000000007e8 .LASF133
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3785   .debug_str:0000000000000701 .LASF134
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3845   .debug_str:0000000000000903 .LASF135
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3695   .debug_str:0000000000000500 .LASF136
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3565   .debug_str:0000000000000125 .LASF137
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3839   .debug_str:00000000000008e2 .LASF139
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3593   .debug_str:00000000000001d9 .LASF140
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3837   .debug_str:00000000000008d8 .LASF141
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3871   .debug_str:00000000000009af .LASF142
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3857   .debug_str:000000000000094f .LASF143
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3817   .debug_str:00000000000007d4 .LASF144
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3861   .debug_str:0000000000000967 .LASF145
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3523   .debug_str:000000000000000c .LASF146
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3713   .debug_str:000000000000057b .LASF163
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3709   .debug_str:0000000000000568 .LASF147
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3795   .debug_str:0000000000000755 .LASF148
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3521   .debug_str:0000000000000000 .LASF149
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3809   .debug_str:00000000000007a2 .LASF150
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3533   .debug_str:000000000000004d .LASF151
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3585   .debug_str:00000000000001a9 .LASF152
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3831   .debug_str:0000000000000838 .LASF153
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3531   .debug_str:0000000000000044 .LASF157
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3849   .debug_str:000000000000091f .LASF159
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3873   .debug_str:00000000000009bd .LASF154
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3617   .debug_str:0000000000000283 .LASF155
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3765   .debug_str:0000000000000697 .LASF156
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3807   .debug_str:0000000000000792 .LASF158
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3561   .debug_str:0000000000000104 .LASF160
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3909   .debug_str:0000000000000a72 .LASF175
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:117    .text.startup.main:0000000000000000 .LFB23
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:492    .text.startup.main:00000000000002c6 .LFE23
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3883   .debug_str:0000000000000a0a .LASF161
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3391   .debug_loc:0000000000000000 .LLST0
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3847   .debug_str:000000000000091a .LASF162
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3405   .debug_loc:0000000000000021 .LLST1
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3773   .debug_str:00000000000006c5 .LASF164
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3597   .debug_str:00000000000001f3 .LASF165
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3719   .debug_str:000000000000059a .LASF166
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3787   .debug_str:000000000000070c .LASF167
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3545   .debug_str:0000000000000094 .LASF168
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3689   .debug_str:00000000000004e4 .LASF169
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3583   .debug_str:00000000000001a4 .LASF170
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3557   .debug_str:00000000000000e2 .LASF171
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3637   .debug_str:00000000000002f5 .LASF172
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3535   .debug_str:0000000000000059 .LASF173
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3661   .debug_str:0000000000000452 .LASF188
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:247    .text.startup.main:00000000000000f2 .LBB11
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:260    .text.startup.main:00000000000000fa .LBE11
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3419   .debug_loc:0000000000000042 .LLST2
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:248    .text.startup.main:00000000000000f2 .LBB12
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:259    .text.startup.main:00000000000000fa .LBE12
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:348    .text.startup.main:00000000000001fe .LBB13
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3429   .debug_loc:0000000000000058 .LLST3
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3444   .debug_loc:0000000000000080 .LLST4
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3451   .debug_loc:0000000000000093 .LLST5
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:350    .text.startup.main:00000000000001fe .LBB15
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3469   .debug_loc:00000000000000b4 .LLST7
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:431    .text.startup.main:000000000000027c .LVL39
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:173    .text.startup.main:0000000000000024 .LVL5
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:178    .text.startup.main:0000000000000032 .LVL6
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:183    .text.startup.main:0000000000000042 .LVL7
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:189    .text.startup.main:0000000000000054 .LVL8
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:194    .text.startup.main:0000000000000062 .LVL9
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:199    .text.startup.main:0000000000000070 .LVL10
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:204    .text.startup.main:0000000000000080 .LVL11
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:209    .text.startup.main:000000000000008e .LVL12
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:214    .text.startup.main:000000000000009c .LVL13
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:219    .text.startup.main:00000000000000aa .LVL14
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:224    .text.startup.main:00000000000000b8 .LVL15
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:231    .text.startup.main:00000000000000ce .LVL16
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:237    .text.startup.main:00000000000000e2 .LVL17
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:243    .text.startup.main:00000000000000f2 .LVL18
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:263    .text.startup.main:0000000000000102 .LVL20
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:269    .text.startup.main:0000000000000116 .LVL21
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:275    .text.startup.main:000000000000012a .LVL22
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:281    .text.startup.main:000000000000013e .LVL23
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:287    .text.startup.main:0000000000000152 .LVL24
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:290    .text.startup.main:000000000000015a .LVL25
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:294    .text.startup.main:0000000000000164 .LVL26
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:300    .text.startup.main:0000000000000178 .LVL27
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:304    .text.startup.main:0000000000000184 .LVL28
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:310    .text.startup.main:0000000000000198 .LVL29
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:316    .text.startup.main:00000000000001ac .LVL30
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:323    .text.startup.main:00000000000001c4 .LVL31
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:343    .text.startup.main:00000000000001f6 .LVL32
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:376    .text.startup.main:000000000000022c .LVL33
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:380    .text.startup.main:0000000000000236 .LVL34
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:457    .text.startup.main:00000000000002a0 .LVL40
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3805   .debug_str:000000000000078d .LASF174
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3879   .debug_str:00000000000009e6 .LASF176
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:86     .text.MSYS_EI0_IRQHandler:0000000000000000 .LFB22
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:110    .text.MSYS_EI0_IRQHandler:000000000000001c .LFE22
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:100    .text.MSYS_EI0_IRQHandler:0000000000000014 .LVL0
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3801   .debug_str:0000000000000771 .LASF196
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:14     .text.SysTick_Handler:0000000000000000 .LFB21
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:79     .text.SysTick_Handler:000000000000009a .LFE21
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3613   .debug_str:0000000000000260 .LASF177
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3853   .debug_str:0000000000000943 .LASF178
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3633   .debug_str:00000000000002e5 .LASF179
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3591   .debug_str:00000000000001cc .LASF180
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3629   .debug_str:00000000000002c7 .LASF181
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3749   .debug_str:0000000000000631 .LASF182
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3877   .debug_str:00000000000009d6 .LASF183
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3863   .debug_str:0000000000000974 .LASF184
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3573   .debug_str:0000000000000161 .LASF185
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3813   .debug_str:00000000000007b9 .LASF186
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3791   .debug_str:000000000000072d .LASF187
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3811   .debug_str:00000000000007af .LASF189
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3657   .debug_str:0000000000000439 .LASF190
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3843   .debug_str:00000000000008f7 .LASF191
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:3721   .debug_str:00000000000005a5 .LASF192
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:120    .text.startup.main:0000000000000000 .LVL1
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:131    .text.startup.main:0000000000000008 .LVL3
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:129    .text.startup.main:0000000000000004 .LVL2
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:256    .text.startup.main:00000000000000fa .LVL19
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:468    .text.startup.main:00000000000002ae .LVL41
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:388    .text.startup.main:000000000000023c .LVL35
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:415    .text.startup.main:0000000000000258 .LVL37
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:411    .text.startup.main:0000000000000254 .LVL36
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:417    .text.startup.main:000000000000025a .LVL38
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:580    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:358    .text.startup.main:0000000000000206 .LBE13
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:382    .text.startup.main:0000000000000236 .LBB23
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:435    .text.startup.main:000000000000027c .LBE23
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:470    .text.startup.main:00000000000002ae .LBB24
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:490    .text.startup.main:00000000000002c6 .LBE24
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:356    .text.startup.main:0000000000000206 .LBE15
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:391    .text.startup.main:000000000000023c .LBB19
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:433    .text.startup.main:000000000000027c .LBE19
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:472    .text.startup.main:00000000000002ae .LBB20
C:\Users\I71825\AppData\Local\Temp\cc6rz2gF.s:488    .text.startup.main:00000000000002c6 .LBE20

UNDEFINED SYMBOLS
I2C_isr
axi4litewrite
GPIO_init
GPIO_set_output
MRV_systick_config
HAL_enable_interrupts
imx334_cam_init
imx334_cam_reginit
msdelay
UART_init
DPSourceInit
DPSourceISR
gain_setting
