src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.o: \
 ../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c \
 ../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hal.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/cpu_types.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hw_reg_access.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hal_assert.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_hal.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_regs.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_plic.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_assert.h \
 C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_subsys.h \
 c:\work_folder_akhil\q4_2024_2025\display_port_tx_web_release\final\new_miv\softconsole2022p2\miv-rv32-dp-tx\src\boards\polarfire-video-kit\fpga_design_config\fpga_design_config.h

../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hal.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/cpu_types.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hw_reg_access.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/hal/hal_assert.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_hal.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_regs.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_plic.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_assert.h:

C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal/miv_rv32_subsys.h:

c:\work_folder_akhil\q4_2024_2025\display_port_tx_web_release\final\new_miv\softconsole2022p2\miv-rv32-dp-tx\src\boards\polarfire-video-kit\fpga_design_config\fpga_design_config.h:
