   1              		.file	"main.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0_m2p0_c2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.SysTick_Handler,"ax",@progbits
  10              		.align	1
  11              		.globl	SysTick_Handler
  13              	SysTick_Handler:
  14              	.LFB21:
  15              		.file 1 "../src/application/main.c"
   1:../src/application/main.c **** /*******************************************************************************
   2:../src/application/main.c ****  * (c) Copyright 2016-2017 Microsemi SoC Products Group. All rights reserved.
   3:../src/application/main.c ****  * 
   4:../src/application/main.c ****  * This SoftConsole Video project for MIPI sensor configuration and interfacing with GUI
   5:../src/application/main.c ****  *
   6:../src/application/main.c ****  * Please refer README.TXT in the root folder of this project for more details.
   7:../src/application/main.c ****  */
   8:../src/application/main.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
   9:../src/application/main.c **** #include "drivers/fpga_ip/CoreGPIO/core_gpio.h"
  10:../src/application/main.c **** #include "drivers/fpga_ip/CoreUARTAPB/core_uart_apb.h"
  11:../src/application/main.c **** #include "drivers/fpga_ip/CoreI2C/core_i2c.h"
  12:../src/application/main.c **** #include "drivers/fpga_ip/CoreAXI4-Lite/AXI4-Lite.h"
  13:../src/application/main.c **** #include "imx334_corei2c/imx334_corei2c.h"
  14:../src/application/main.c **** #include "hdmi_config/hdmi_tx.h"
  15:../src/application/main.c **** #include "dp_cmd_common.h"
  16:../src/application/main.c **** #include "dp_cmd_tx.h"
  17:../src/application/main.c **** #include "dp_cmd_common.h"
  18:../src/application/main.c **** #include "dp_cmd_tx_regs.h"
  19:../src/application/main.c **** #include "dp_cmd_tx.h"
  20:../src/application/main.c **** /* Camera configuration (Data rate, resolution) and pattern generator
  21:../src/application/main.c ****  * can be selected in imx334_corei2c.h file.
  22:../src/application/main.c ****  * */
  23:../src/application/main.c **** 
  24:../src/application/main.c **** #define LED1 GPIO_0
  25:../src/application/main.c **** #define LED2 GPIO_1
  26:../src/application/main.c **** #define LED3 GPIO_2
  27:../src/application/main.c **** #define LED4 GPIO_3
  28:../src/application/main.c **** 
  29:../src/application/main.c **** #define MIPI_TRNG_RST GPIO_4
  30:../src/application/main.c **** 
  31:../src/application/main.c **** 
  32:../src/application/main.c **** // Bayer Configuration
  33:../src/application/main.c **** #define BAYER_ADDR                0x72020000
  34:../src/application/main.c **** 
  35:../src/application/main.c **** // Display Controller Configuration
  36:../src/application/main.c **** #define DC_IP_VER                 0x72040000
  37:../src/application/main.c **** #define DC_IP_EN_DIS              0x72040004
  38:../src/application/main.c **** #define DC_IP_HRES                0x72040008
  39:../src/application/main.c **** #define DC_IP_VRES                0x7204000C
  40:../src/application/main.c **** #define DC_IP_HFP                 0x72040010
  41:../src/application/main.c **** #define DC_IP_HBP                 0x72040014
  42:../src/application/main.c **** #define DC_IP_VFP                 0x72040018
  43:../src/application/main.c **** #define DC_IP_VBP                 0x7204001C
  44:../src/application/main.c **** #define DC_IP_HSW                 0x72040020
  45:../src/application/main.c **** #define DC_IP_VSW                 0x72040024
  46:../src/application/main.c **** 
  47:../src/application/main.c **** // Image Enhancment Configuration
  48:../src/application/main.c **** #define IE_IP_VER                 0x72030000
  49:../src/application/main.c **** #define IE_IP_EN_DIS              0x72030004
  50:../src/application/main.c **** #define IE_R_CONST                0x72030008
  51:../src/application/main.c **** #define IE_G_CONST                0x7203000C
  52:../src/application/main.c **** #define IE_B_CONST                0x72030010
  53:../src/application/main.c **** #define IE_COMMON_CONST           0x72030014
  54:../src/application/main.c **** #define IE_INTENSITY_AVARAGE      0x72030018
  55:../src/application/main.c **** 
  56:../src/application/main.c **** 
  57:../src/application/main.c **** volatile uint32_t g_10ms_count;
  58:../src/application/main.c **** 
  59:../src/application/main.c **** volatile uint32_t timerdone = 0;
  60:../src/application/main.c **** volatile uint32_t g_10ms_count1;
  61:../src/application/main.c **** volatile uint32_t g_ms_count;
  62:../src/application/main.c **** static void gui_handler(void);
  63:../src/application/main.c **** i2c_instance_t g_i2c_instance_cam1;
  64:../src/application/main.c **** uint8_t uart_rx_buff[23]={0};
  65:../src/application/main.c **** UART_instance_t g_uart;
  66:../src/application/main.c **** 
  67:../src/application/main.c **** uint16_t bayer;
  68:../src/application/main.c **** 
  69:../src/application/main.c **** static uint16_t in_gain = 80;
  70:../src/application/main.c **** static void auto_brightness( uint32_t div);
  71:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  72:../src/application/main.c **** static void gain_cal(uint32_t total_average);
  73:../src/application/main.c **** 
  74:../src/application/main.c **** 
  75:../src/application/main.c **** 
  76:../src/application/main.c **** /*----------------------------------------------------
  77:../src/application/main.c **** /*-----------------------------------------------------------------------------
  78:../src/application/main.c ****  * GPIO instance data.
  79:../src/application/main.c ****  */
  80:../src/application/main.c **** 
  81:../src/application/main.c **** gpio_instance_t g_gpio_out;
  82:../src/application/main.c **** 
  83:../src/application/main.c **** /*-----------------------------------------------------------------------------
  84:../src/application/main.c ****  * Global state counter.
  85:../src/application/main.c ****  */
  86:../src/application/main.c **** uint32_t g_state = 1;
  87:../src/application/main.c **** 
  88:../src/application/main.c **** volatile uint32_t rx_tmr_done = 0;
  89:../src/application/main.c **** volatile uint32_t rx_ms_count1;
  90:../src/application/main.c **** volatile uint32_t rx_ms_count;
  91:../src/application/main.c **** 
  92:../src/application/main.c **** uint32_t t_ms_count = 0;
  93:../src/application/main.c **** 
  94:../src/application/main.c **** uint32_t R_constant=146;
  95:../src/application/main.c **** uint32_t G_constant=122;
  96:../src/application/main.c **** uint32_t B_constant=165;
  97:../src/application/main.c **** uint32_t second_constant=0;
  98:../src/application/main.c **** 
  99:../src/application/main.c **** 
 100:../src/application/main.c **** /*-----------------------------------------------------------------------------
 101:../src/application/main.c ****  * UART handler specific.
 102:../src/application/main.c ****  */
 103:../src/application/main.c **** uint32_t i = 0;
 104:../src/application/main.c **** uint32_t process_data = 0;
 105:../src/application/main.c **** 
 106:../src/application/main.c **** /*-----------------------------------------------------------------------------
 107:../src/application/main.c ****  * System Tick interrupt handler
 108:../src/application/main.c ****  */
 109:../src/application/main.c **** void SysTick_Handler(void) {
  16              		.loc 1 109 28
  17              		.cfi_startproc
 110:../src/application/main.c **** 
 111:../src/application/main.c ****     g_state = (~g_state) & 0x01;
  18              		.loc 1 111 5
  19              		.loc 1 111 13 is_stmt 0
  20 0000 97070000 		lla	a5,.LANCHOR0
  20      93870700 
  21 0008 9C43     		lw	a5,0(a5)
  22 000a 93C7F7FF 		not	a5,a5
  23 000e 858B     		andi	a5,a5,1
  24 0010 17070000 		sw	a5,.LANCHOR0,a4
  24      2320F700 
 112:../src/application/main.c **** 
 113:../src/application/main.c ****     if(timerdone == 1)
  25              		.loc 1 113 5 is_stmt 1
  26              		.loc 1 113 18 is_stmt 0
  27 0018 97070000 		lla	a5,.LANCHOR1
  27      93870700 
  28 0020 9843     		lw	a4,0(a5)
  29              		.loc 1 113 7
  30 0022 8547     		li	a5,1
  31 0024 6318F702 		bne	a4,a5,.L3
 114:../src/application/main.c ****     {
 115:../src/application/main.c ****         g_10ms_count1 += 1;
  32              		.loc 1 115 9 is_stmt 1
  33              		.loc 1 115 23 is_stmt 0
  34 0028 17070000 		lla	a4,g_10ms_count1
  34      13070700 
  35 0030 1C43     		lw	a5,0(a4)
  36 0032 8507     		addi	a5,a5,1
  37 0034 97060000 		sw	a5,g_10ms_count1,a3
  37      23A0F600 
 116:../src/application/main.c ****         if(g_ms_count <= g_10ms_count1)
  38              		.loc 1 116 9 is_stmt 1
  39              		.loc 1 116 23 is_stmt 0
  40 003c 97070000 		lla	a5,g_ms_count
  40      93870700 
  41 0044 9443     		lw	a3,0(a5)
  42 0046 1C43     		lw	a5,0(a4)
  43              		.loc 1 116 11
  44 0048 63E6D700 		bgtu	a3,a5,.L3
 117:../src/application/main.c ****             timerdone = 0;
  45              		.loc 1 117 13 is_stmt 1
  46              		.loc 1 117 23 is_stmt 0
  47 004c 97070000 		sw	zero,.LANCHOR1,a5
  47      23A00700 
  48              	.L3:
 118:../src/application/main.c ****     }
 119:../src/application/main.c **** 
 120:../src/application/main.c ****     if(rx_tmr_done == 1)
  49              		.loc 1 120 5 is_stmt 1
  50              		.loc 1 120 20 is_stmt 0
  51 0054 97070000 		lla	a5,.LANCHOR2
  51      93870700 
  52 005c 9843     		lw	a4,0(a5)
  53              		.loc 1 120 7
  54 005e 8547     		li	a5,1
  55 0060 631CF702 		bne	a4,a5,.L1
 121:../src/application/main.c ****     {
 122:../src/application/main.c ****         rx_ms_count1 += 1;
  56              		.loc 1 122 9 is_stmt 1
  57              		.loc 1 122 22 is_stmt 0
  58 0064 97060000 		lla	a3,rx_ms_count1
  58      93860600 
  59 006c 9C42     		lw	a5,0(a3)
  60 006e 8507     		addi	a5,a5,1
  61 0070 17060000 		sw	a5,rx_ms_count1,a2
  61      2320F600 
 123:../src/application/main.c ****         if(rx_ms_count1 >= rx_ms_count){
  62              		.loc 1 123 9 is_stmt 1
  63              		.loc 1 123 25 is_stmt 0
  64 0078 97070000 		lla	a5,rx_ms_count
  64      93870700 
  65 0080 9442     		lw	a3,0(a3)
  66 0082 9C43     		lw	a5,0(a5)
  67              		.loc 1 123 11
  68 0084 63EAF600 		bltu	a3,a5,.L1
 124:../src/application/main.c ****             rx_tmr_done = 0;
  69              		.loc 1 124 13 is_stmt 1
  70              		.loc 1 124 25 is_stmt 0
  71 0088 97070000 		sw	zero,.LANCHOR2,a5
  71      23A00700 
 125:../src/application/main.c ****             process_data = 1;
  72              		.loc 1 125 13 is_stmt 1
  73              		.loc 1 125 26 is_stmt 0
  74 0090 97070000 		sw	a4,.LANCHOR3,a5
  74      23A0E700 
  75              	.L1:
 126:../src/application/main.c ****         }
 127:../src/application/main.c ****     }
 128:../src/application/main.c **** }
  76              		.loc 1 128 1
  77 0098 8280     		ret
  78              		.cfi_endproc
  79              	.LFE21:
  81              		.section	.text.MSYS_EI0_IRQHandler,"ax",@progbits
  82              		.align	1
  83              		.globl	MSYS_EI0_IRQHandler
  85              	MSYS_EI0_IRQHandler:
  86              	.LFB22:
 129:../src/application/main.c **** 
 130:../src/application/main.c **** uint8_t  MSYS_EI0_IRQHandler(void)
 131:../src/application/main.c **** {
  87              		.loc 1 131 1 is_stmt 1
  88              		.cfi_startproc
 132:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  89              		.loc 1 132 5
 131:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  90              		.loc 1 131 1 is_stmt 0
  91 0000 4111     		addi	sp,sp,-16
  92              		.cfi_def_cfa_offset 16
  93              		.loc 1 132 5
  94 0002 17050000 		lla	a0,g_i2c_instance_cam1
  94      13050500 
 131:../src/application/main.c ****     I2C_isr(&g_i2c_instance_cam1);
  95              		.loc 1 131 1
  96 000a 06C6     		sw	ra,12(sp)
  97              		.cfi_offset 1, -4
  98              		.loc 1 132 5
  99 000c 97000000 		call	I2C_isr
  99      E7800000 
 100              	.LVL0:
 133:../src/application/main.c ****     return (EXT_IRQ_KEEP_ENABLED);
 101              		.loc 1 133 5 is_stmt 1
 134:../src/application/main.c **** }
 102              		.loc 1 134 1 is_stmt 0
 103 0014 B240     		lw	ra,12(sp)
 104              		.cfi_restore 1
 105 0016 0145     		li	a0,0
 106 0018 4101     		addi	sp,sp,16
 107              		.cfi_def_cfa_offset 0
 108 001a 8280     		jr	ra
 109              		.cfi_endproc
 110              	.LFE22:
 112              		.section	.text.startup.main,"ax",@progbits
 113              		.align	1
 114              		.globl	main
 116              	main:
 117              	.LFB23:
 135:../src/application/main.c **** 
 136:../src/application/main.c **** /*-----------------------------------------------------------------------------
 137:../src/application/main.c ****  * main
 138:../src/application/main.c ****  */
 139:../src/application/main.c **** uint32_t a;
 140:../src/application/main.c **** 
 141:../src/application/main.c **** int main(int argc, char **argv) {
 118              		.loc 1 141 33 is_stmt 1
 119              		.cfi_startproc
 120              	.LVL1:
 142:../src/application/main.c ****     volatile  uint32_t counter;
 121              		.loc 1 142 5
 143:../src/application/main.c ****     uint8_t state;
 122              		.loc 1 143 5
 144:../src/application/main.c ****     counter = 0;
 123              		.loc 1 144 5
 141:../src/application/main.c ****     volatile  uint32_t counter;
 124              		.loc 1 141 33 is_stmt 0
 125 0000 3971     		addi	sp,sp,-64
 126              		.cfi_def_cfa_offset 64
 145:../src/application/main.c ****     state = 0;
 146:../src/application/main.c ****     //DISPLAY CONTROLLER PARAMETERS
 147:../src/application/main.c ****     ///////////////////FHD//////////////////////
 148:../src/application/main.c **** #if 0
 149:../src/application/main.c ****     uint32_t PIXEL_MODE=1;//4 PIXEL MODE HRES DEIVIDE BY 4
 150:../src/application/main.c ****     uint32_t BAYER_OFFSET_VALUE=2;
 151:../src/application/main.c ****     uint32_t SPEED_MODE=1;
 152:../src/application/main.c ****     uint32_t HRES=1920;
 153:../src/application/main.c ****     uint32_t VRES=1080;
 154:../src/application/main.c ****     uint32_t HFP=88;
 155:../src/application/main.c ****     uint32_t HSW=44;
 156:../src/application/main.c ****     uint32_t HBP=148;
 157:../src/application/main.c ****     uint32_t VFP=4;
 158:../src/application/main.c ****     uint32_t VSW=5;
 159:../src/application/main.c ****     uint32_t VBP=36;
 160:../src/application/main.c ****     uint32_t VSP=0x00000000;
 161:../src/application/main.c ****     uint32_t LANE_NO=0x00000004;
 162:../src/application/main.c **** #endif
 163:../src/application/main.c ****     ///////////////////4K//////////////////////
 164:../src/application/main.c **** #if 1
 165:../src/application/main.c ****     uint32_t PIXEL_MODE=4;//4 PIXEL MODE HRES DEIVIDE BY 4
 166:../src/application/main.c ****         uint32_t BAYER_OFFSET_VALUE=0;
 167:../src/application/main.c ****         uint32_t SPEED_MODE=2;
 168:../src/application/main.c ****         uint32_t HRES=3840;
 169:../src/application/main.c ****         uint32_t VRES=2160;
 170:../src/application/main.c ****         uint32_t HFP=76;//65;//100;//176;
 171:../src/application/main.c ****         uint32_t HSW=8;
 172:../src/application/main.c ****         uint32_t HBP=76;//296;
 173:../src/application/main.c ****         uint32_t VFP=54;
 174:../src/application/main.c ****         uint32_t VSW=5;
 175:../src/application/main.c ****         uint32_t VBP=3;
 176:../src/application/main.c ****         uint32_t VSP=0x00008000;
 177:../src/application/main.c ****         uint32_t LANE_NO=0x00000004;
 178:../src/application/main.c **** #endif
 179:../src/application/main.c ****         // =========================== DisplayController ================================
 180:../src/application/main.c ****         uint32_t Enable=1;
 181:../src/application/main.c ****         uint32_t Disable=0;
 182:../src/application/main.c **** 
 183:../src/application/main.c ****         //bayer = 0x00;
 184:../src/application/main.c ****         Enable = 0x01;
 185:../src/application/main.c ****         Disable = 0x00;
 186:../src/application/main.c **** 
 187:../src/application/main.c ****         axi4litewrite(BAYER_ADDR,BAYER_OFFSET_VALUE);
 127              		.loc 1 187 9
 128 0002 8145     		li	a1,0
 129              	.LVL2:
 130 0004 37050272 		li	a0,1912733696
 131              	.LVL3:
 141:../src/application/main.c ****     volatile  uint32_t counter;
 132              		.loc 1 141 33
 133 0008 06DE     		sw	ra,60(sp)
 134 000a 22DC     		sw	s0,56(sp)
 135 000c 26DA     		sw	s1,52(sp)
 136              		.cfi_offset 1, -4
 137              		.cfi_offset 8, -8
 138              		.cfi_offset 9, -12
 188:../src/application/main.c **** 
 189:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Disable); // diabling the IP
 139              		.loc 1 189 9
 140 000e 37040472 		li	s0,1912864768
 141:../src/application/main.c ****     volatile  uint32_t counter;
 141              		.loc 1 141 33
 142 0012 4AD8     		sw	s2,48(sp)
 143 0014 4ED6     		sw	s3,44(sp)
 144 0016 52D4     		sw	s4,40(sp)
 145 0018 56D2     		sw	s5,36(sp)
 146              		.cfi_offset 18, -16
 147              		.cfi_offset 19, -20
 148              		.cfi_offset 20, -24
 149              		.cfi_offset 21, -28
 144:../src/application/main.c ****     state = 0;
 150              		.loc 1 144 13
 151 001a 02CE     		sw	zero,28(sp)
 145:../src/application/main.c ****     //DISPLAY CONTROLLER PARAMETERS
 152              		.loc 1 145 5 is_stmt 1
 153              	.LVL4:
 165:../src/application/main.c ****         uint32_t BAYER_OFFSET_VALUE=0;
 154              		.loc 1 165 5
 166:../src/application/main.c ****         uint32_t SPEED_MODE=2;
 155              		.loc 1 166 9
 167:../src/application/main.c ****         uint32_t HRES=3840;
 156              		.loc 1 167 9
 168:../src/application/main.c ****         uint32_t VRES=2160;
 157              		.loc 1 168 9
 169:../src/application/main.c ****         uint32_t HFP=76;//65;//100;//176;
 158              		.loc 1 169 9
 170:../src/application/main.c ****         uint32_t HSW=8;
 159              		.loc 1 170 9
 171:../src/application/main.c ****         uint32_t HBP=76;//296;
 160              		.loc 1 171 9
 172:../src/application/main.c ****         uint32_t VFP=54;
 161              		.loc 1 172 9
 173:../src/application/main.c ****         uint32_t VSW=5;
 162              		.loc 1 173 9
 174:../src/application/main.c ****         uint32_t VBP=3;
 163              		.loc 1 174 9
 175:../src/application/main.c ****         uint32_t VSP=0x00008000;
 164              		.loc 1 175 9
 176:../src/application/main.c ****         uint32_t LANE_NO=0x00000004;
 165              		.loc 1 176 9
 177:../src/application/main.c **** #endif
 166              		.loc 1 177 9
 180:../src/application/main.c ****         uint32_t Disable=0;
 167              		.loc 1 180 9
 181:../src/application/main.c **** 
 168              		.loc 1 181 9
 184:../src/application/main.c ****         Disable = 0x00;
 169              		.loc 1 184 9
 185:../src/application/main.c **** 
 170              		.loc 1 185 9
 187:../src/application/main.c **** 
 171              		.loc 1 187 9
 172 001c 97000000 		call	axi4litewrite
 172      E7800000 
 173              	.LVL5:
 174              		.loc 1 189 9
 175 0024 13054400 		addi	a0,s0,4
 176 0028 8145     		li	a1,0
 177 002a 97000000 		call	axi4litewrite
 177      E7800000 
 178              	.LVL6:
 190:../src/application/main.c **** 
 191:../src/application/main.c ****         axi4litewrite(DC_IP_HRES,HRES/PIXEL_MODE);
 179              		.loc 1 191 9
 180 0032 13058400 		addi	a0,s0,8
 181 0036 9305003C 		li	a1,960
 182 003a 97000000 		call	axi4litewrite
 182      E7800000 
 183              	.LVL7:
 192:../src/application/main.c ****         axi4litewrite(DC_IP_VRES,VRES);
 184              		.loc 1 192 9
 185 0042 8564     		li	s1,4096
 186 0044 93850487 		addi	a1,s1,-1936
 187 0048 1305C400 		addi	a0,s0,12
 188 004c 97000000 		call	axi4litewrite
 188      E7800000 
 189              	.LVL8:
 193:../src/application/main.c ****         axi4litewrite(DC_IP_HFP,HFP/PIXEL_MODE);
 190              		.loc 1 193 9
 191 0054 13050401 		addi	a0,s0,16
 192 0058 CD45     		li	a1,19
 193 005a 97000000 		call	axi4litewrite
 193      E7800000 
 194              	.LVL9:
 194:../src/application/main.c ****         axi4litewrite(DC_IP_HBP,HBP/PIXEL_MODE);
 195              		.loc 1 194 9
 196 0062 13054401 		addi	a0,s0,20
 197 0066 CD45     		li	a1,19
 198 0068 97000000 		call	axi4litewrite
 198      E7800000 
 199              	.LVL10:
 195:../src/application/main.c ****         axi4litewrite(DC_IP_VFP,VFP);
 200              		.loc 1 195 9
 201 0070 13058401 		addi	a0,s0,24
 202 0074 93056003 		li	a1,54
 203 0078 97000000 		call	axi4litewrite
 203      E7800000 
 204              	.LVL11:
 196:../src/application/main.c ****         axi4litewrite(DC_IP_VBP,VBP);
 205              		.loc 1 196 9
 206 0080 1305C401 		addi	a0,s0,28
 207 0084 8D45     		li	a1,3
 208 0086 97000000 		call	axi4litewrite
 208      E7800000 
 209              	.LVL12:
 197:../src/application/main.c ****         axi4litewrite(DC_IP_HSW,HSW/PIXEL_MODE);
 210              		.loc 1 197 9
 211 008e 13050402 		addi	a0,s0,32
 212 0092 8945     		li	a1,2
 213 0094 97000000 		call	axi4litewrite
 213      E7800000 
 214              	.LVL13:
 198:../src/application/main.c ****         axi4litewrite(DC_IP_VSW,VSW);
 215              		.loc 1 198 9
 216 009c 13054402 		addi	a0,s0,36
 217 00a0 9545     		li	a1,5
 218 00a2 97000000 		call	axi4litewrite
 218      E7800000 
 219              	.LVL14:
 199:../src/application/main.c **** 
 200:../src/application/main.c ****         axi4litewrite(DC_IP_EN_DIS,Enable); // Enabling the IP
 220              		.loc 1 200 9
 221 00aa 13054400 		addi	a0,s0,4
 222 00ae 8545     		li	a1,1
 201:../src/application/main.c **** 
 202:../src/application/main.c **** 
 203:../src/application/main.c ****         axi4litewrite(IE_IP_EN_DIS,Disable); // diabling the IP
 223              		.loc 1 203 9 is_stmt 0
 224 00b0 37040372 		li	s0,1912799232
 200:../src/application/main.c **** 
 225              		.loc 1 200 9
 226 00b4 97000000 		call	axi4litewrite
 226      E7800000 
 227              	.LVL15:
 228              		.loc 1 203 9 is_stmt 1
 229 00bc 13054400 		addi	a0,s0,4
 230 00c0 8145     		li	a1,0
 231 00c2 97000000 		call	axi4litewrite
 231      E7800000 
 232              	.LVL16:
 204:../src/application/main.c **** 
 205:../src/application/main.c ****         axi4litewrite(IE_R_CONST,R_constant);
 233              		.loc 1 205 9
 234 00ca 97070000 		lla	a5,.LANCHOR4
 234      93870700 
 235 00d2 8C43     		lw	a1,0(a5)
 236 00d4 13058400 		addi	a0,s0,8
 237 00d8 97000000 		call	axi4litewrite
 237      E7800000 
 238              	.LVL17:
 206:../src/application/main.c ****         axi4litewrite(IE_G_CONST,G_constant);
 239              		.loc 1 206 9
 240 00e0 97070000 		lla	a5,.LANCHOR5
 240      93870700 
 241 00e8 8C43     		lw	a1,0(a5)
 242 00ea 1305C400 		addi	a0,s0,12
 243 00ee 97000000 		call	axi4litewrite
 243      E7800000 
 244              	.LVL18:
 207:../src/application/main.c ****         axi4litewrite(IE_B_CONST,B_constant);
 245              		.loc 1 207 9
 246 00f6 97070000 		lla	a5,.LANCHOR6
 246      93870700 
 247 00fe 8C43     		lw	a1,0(a5)
 248 0100 13050401 		addi	a0,s0,16
 249 0104 97000000 		call	axi4litewrite
 249      E7800000 
 250              	.LVL19:
 208:../src/application/main.c ****         axi4litewrite(IE_COMMON_CONST,second_constant);
 251              		.loc 1 208 9
 252 010c 97070000 		lla	a5,.LANCHOR7
 252      93870700 
 253 0114 8C43     		lw	a1,0(a5)
 254 0116 13054401 		addi	a0,s0,20
 255 011a 97000000 		call	axi4litewrite
 255      E7800000 
 256              	.LVL20:
 209:../src/application/main.c **** 
 210:../src/application/main.c **** 
 211:../src/application/main.c ****         axi4litewrite(IE_IP_EN_DIS,Enable); // Enabling the IP
 257              		.loc 1 211 9
 258 0122 13054400 		addi	a0,s0,4
 259 0126 8545     		li	a1,1
 260 0128 97000000 		call	axi4litewrite
 260      E7800000 
 261              	.LVL21:
 212:../src/application/main.c **** 
 213:../src/application/main.c ****         //Displaycontroller(HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,PIXEL_MODE/*,BAYER_OFFSET_VALUE*/);
 214:../src/application/main.c **** 
 215:../src/application/main.c ****         uint32_t div = (1920*1080*2);
 262              		.loc 1 215 9
 216:../src/application/main.c **** 
 217:../src/application/main.c ****     GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
 263              		.loc 1 217 5
 264 0130 0946     		li	a2,2
 265 0132 B7450071 		li	a1,1895841792
 266 0136 17050000 		lla	a0,g_gpio_out
 266      13050500 
 267 013e 97000000 		call	GPIO_init
 267      E7800000 
 268              	.LVL22:
 218:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED1, 1);
 269              		.loc 1 218 5
 270 0146 0546     		li	a2,1
 271 0148 8145     		li	a1,0
 272 014a 17050000 		lla	a0,g_gpio_out
 272      13050500 
 273 0152 97000000 		call	GPIO_set_output
 273      E7800000 
 274              	.LVL23:
 219:../src/application/main.c **** 
 220:../src/application/main.c ****     MRV_systick_config(SYS_CLK_FREQ / 1000);
 275              		.loc 1 220 5
 276 015a 3165     		li	a0,49152
 277 015c 8145     		li	a1,0
 278 015e 13050535 		addi	a0,a0,848
 279 0162 97000000 		call	MRV_systick_config
 279      E7800000 
 280              	.LVL24:
 221:../src/application/main.c **** 
 222:../src/application/main.c ****     MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
 281              		.loc 1 222 5
 282              		.file 2 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
   1:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
   6:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
   7:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
   8:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
   9:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  10:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  11:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  12:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*=========================================================================*//**
  13:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @mainpage MIV_RV32 Hardware Abstraction Layer
  14:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  15:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  16:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Introduction
  17:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  18:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This document describes the Hardware Abstraction Layer (HAL) for the MIV_RV32 
  19:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP Core. This release of the HAL corresponds to the Soft IP core MIV_RV32
  20:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   v3.1 release. It also supports earlier versions of the MIV_RV32 as well as the 
  21:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   legacy RV32 IP cores.
  22:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The preprocessor macros provided with the MIV_RV32 HAL are used to customize 
  23:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   it to target the Soft Processor IP version being used in your project.
  24:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  25:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term "MIV_RV32" represents following two cores:    
  26:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32 v3.0 and later (the latest and greatest Mi-V soft processor)      
  27:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMC v2.1 (MIV_RV32 v3.0 is a drop in replacement for this core)
  28:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   It is highly recommended to migrate your design to MIV_RV32 v3.1
  29:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  30:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The term, Legacy RV32 IP cores, represents following IP cores:    
  31:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AHB     
  32:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMA_L1_AXI     
  33:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MIV_RV32IMAF_L1_AHB
  34:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  35:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These legacy RV32 IP cores are deprecated. It is highly recommended to migrate
  36:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   your designs to MIV_RV32 v3.1 (and subsequent IP releases) for the latest 
  37:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   enhancements, bug fixes, and support.
  38:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  39:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  40:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 V3.1
  41:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  42:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This is the latest release of the MIV_RV32 Soft IP core. For more details, see
  43:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 User [Guide](https://www.microchip.com/en-us/products/fpgas-and-plds/ip-core-tools/m
  44:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  45:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Core and this document use the following terms:
  46:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  48:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - SUBSYS - Processor Subsystem for RISC-V
  49:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - OPSRV - Offload Processor Subsystem for RISC-V
  50:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - GPR - General Purpose Registers
  51:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGECIE - Machine GPR ECC Correctable Interrupt Enable
  52:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MGEUIE - Machine GPR ECC Uncorrectable Interrupt Enable
  53:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MTIE - Machine Timer Interrupt Enable
  54:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MEIE - Machine External Interrupt Enable
  55:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - MSIE - Machine Software Interrupt Enable
  56:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     - ISR - Interrupt Service Routine
  57:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  58:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  59:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Customizing MIV_RV32 HAL
  60:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ==============================================================================
  61:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To use the HAL with older releases of MIV_RV32 preprocessor, macros have been
  62:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   provided. Using these macros, any of the IP version is targeted. The HAL is used
  63:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   to target the mentioned platforms by adding the following macros in Project
  64:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Properties > C/C++ Build > Settings > Preprocessor available in the Assembler
  65:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and Compiler settings. The following table shows the macros corresponding to the
  66:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV Core being used in your libero project. By default, the HAL targets v3.1 of
  67:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the IP core and no macros need to be set for this configutation.
  68:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  69:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Libero MI-V Soft IP Version | SoftConsole Macro |
  70:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-----------------------------|-------------------|
  71:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.1       |  no macro required  |
  72:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       MIV_RV32 v3.0       |    MIV_CORE_V3_0    |
  73:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |     Legacy RV32 Cores     |    MIV_LEGACY_RV32  |
  74:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  75:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  76:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt Handling
  77:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
  78:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE Register is defined as a enum in the HAL, and the table below is used 
  79:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   as a reference when the vectored interrupts are enabled in the GUI core
  80:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
  81:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
  82:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIE register is a RISC-V Control and Status Register (CSR), which stands
  83:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   for the Machine Interrupt Enable. This is used to enable the machine mode
  84:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupts in the MIV_RV32 hart. Refer to the RISC-V Priv spec for more details.
  85:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  86:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table shows the trap entry addresses when an interrupt occurs and
  87:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the vectored interrupts are enabled in the GUI configurator.
  88:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
  89:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Interrupt Enable | Vector Address |
  90:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
  91:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |     MSYS_IE7     |  mtvec.BASE + 0x7C   |
  92:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     MSYS_IE6     |  mtvec.BASE + 0x78   |
  93:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        29         |     MSYS_IE5     |  mtvec.BASE + 0x74   |
  94:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        28         |     MSYS_IE4     |  mtvec.BASE + 0x70   |
  95:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        27         |     MSYS_IE3     |  mtvec.BASE + 0x6C   |
  96:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        26         |     MSYS_IE2     |  mtvec.BASE + 0x68   |
  97:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        25         |     MSYS_IE1     |  mtvec.BASE + 0x64   |
  98:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        24         |     MSYS_IE0     |  mtvec.BASE + 0x60   |
  99:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    SUBSYS_EI     |  mtvec.BASE + 0x5C   |
 100:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |     SUBSYSR      |  mtvec.BASE + 0x58   |
 101:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        17         |      MGECIE      |  mtvec.BASE + 0x44   |
 102:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        16         |      MGEUIE      |  mtvec.BASE + 0x40   |
 103:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        11         |       MEIE       |  mtvec.BASE + 0x2C   |
 104:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         7         |       MTIE       |  mtvec.BASE + 0x1C   |
 105:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |         3         |       MSIE       |  mtvec.BASE + 0x0C   |
 106:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 107:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 108:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For changes in MIE register map, see the [MIE Register Map for MIV_RV32 v3.0]
 109:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (#mie-register-map-for-miv_rv32-v3.0) section. 
 110:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 111:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYSR is currently not being used by the core and is Reserved for future use.
 112:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 113:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The mtvec.BASE field corresponds to the bits [31:2], where mtvec stands for 
 114:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Machine Trap Vector, and all traps set the PC to the value stored in the 
 115:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mtvec.BASE field when in Non-Vectored mode. In this case, a generic trap 
 116:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handler is as an interrupt service routine.
 117:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 118:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When Vectored interrupts are enabled, use this formula to calculate the trap
 119:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   address: (mtvec.BASE + 4*cause), where cause comes from the mcause CSR. The 
 120:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mcause register is written with a code indicating the event that caused the trap.
 121:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For more details, see the RISC-V priv specification. 
 122:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 123:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIV_RV32 Soft IP core does not contain a Platfrom Level Interrup Controller 
 124:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   (PLIC). It is advised to use the PLIC contained within the MIV_ESS sub-system.
 125:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Connect the PLIC interrupt output of the MIV_ESS to the EXT_IRQ pin on the 
 126:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32.
 127:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 128:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The following table is the MIE register map for the MIV_RV32 Core V3.0. It only
 129:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   highlights the differences between the V3.0 and V3.1 of the core.
 130:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 131:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 132:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIE Register Map for MIV_RV32 V3.0 
 133:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 134:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 135:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MIE Register Bit  | Target Interrupt | Vector Address |
 136:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|------------------|----------------|
 137:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        31         |    Not in use    |   top table   |
 138:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        30         |     SUBSYS_EI    |  addr + 0x78   |
 139:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        23         |    Not in use    |   Not in use   |
 140:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |        22         |    Not in use    |   Not in use   |
 141:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 142:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Other interrupt bit postions like the MGEUIE and MSYS_IE5 to MSYS_IE0 remain 
 143:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   unchanged.
 144:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 145:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 146:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Floating Point Interrupt Support
 147:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 148:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When an interrupt is taken and Floating Point instructions are used in the 
 149:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ISR, the floating point register context must be saved to resume the application
 150:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   correctly. To use this feature, enable the provided macro in the 
 151:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Softconsole build settings.
 152:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This feature is turned off by default as it adds overhead which is not required 
 153:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   when the ISR does not use FP insturctions and saving the general purpose 
 154:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   register context is sufficient.
 155:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 156:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |       Macro Name       |                    Definition                     |
 157:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------------------------|-------------------------------------------------|
 158:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |    MIV_FP_CONTEXT_SAVE   |     Define to save the FP register file         |
 159:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 160:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 161:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 162:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS - SubSystem for RISC-V
 163:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 164:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS stands for SubSystem for RISC-V. Refer to the MIV_RV32 v3.1 Handbook for
 165:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   more details.  
 166:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   NOTE: This was previously (MIV_RV32 v3.0) known as OPSRV, which stands for 
 167:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   "Offload Processor Subsystem for RISC-V". See the earlier versions of the 
 168:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook for more details. The MIV_RV32 HAL now uses SUBSYS instead of OPSRV.
 169:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 170:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *//*=========================================================================*/
 171:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
 172:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
 173:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 174:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
 175:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
 176:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
 177:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_subsys.h"
 178:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 179:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
 180:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "../../boards/polarfire-video-kit/fpga_design_config/fpga_design_config.h"
 181:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 182:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
 183:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
 184:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 185:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
 186:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
 187:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 188:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 189:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   SUBSYS Backwards Compatibility 
 190:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 191:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   For application code using the older macro names and API functions, these macros
 192:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   act as a compatibility layer and applications which use OPSRV API features work 
 193:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   due to these macro definitions. However, it is adviced to update your
 194:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   application code to use the SUBSYS macros and API functions.
 195:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****    
 196:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |      Macro Name         |       Now Called         |
 197:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------------|--------------------------|
 198:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_CE_IRQ    | SUBSYS_TCM_ECC_CE_IRQ    | 
 199:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_TCM_ECC_UCE_IRQ   | SUBSYS_TCM_ECC_UCE_IRQ   | 
 200:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_AXI_WR_RESP_IRQ   | SUBSYS_AXI_WR_RESP_IRQ   | 
 201:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_MSYS_OPSRV_IRQn   | MRV32_SUBSYS_IRQn        | 
 202:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_enable_irq  | MRV32_subsys_enable_irq  | 
 203:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_disable_irq | MRV32_subsys_disable_irq | 
 204:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_opsrv_clear_irq   | MRV32_subsys_clear_irq   | 
 205:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | OPSRV_IRQHandler        | SUBSYS_IRQHandler        |
 206:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 207:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 208:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 209:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME Timer Interrupt Constants
 210:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 211:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These values contain the register addresses for the registers used by the 
 212:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   machine timer interrupt
 213:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 214:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME_PRESCALER is not defined on the MIV_RV32IMC v2.0 and v2.1. By using this
 215:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   definition the system crashes. For those core, use the following definition:
 216:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 217:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   #define MTIME_PRESCALER              100u
 218:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 219:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTIME and MTIMECMP
 220:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 221:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core offers flexibility in terms of generating MTIME and MTIMECMP 
 222:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internal to the core or using external time reference. There four
 223:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   possible combinations:
 224:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 225:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ enabled Generate the MTIME and MTIMECMP
 226:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   registers internally. (The only combination available on legacy RV32 cores)
 227:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 228:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME enabled and Internal MTIME IRQ disabled Generate the MTIME 
 229:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internally and have a timer interrupt input to the core as external pin. In 
 230:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this case, 1 pin port will be available on MIV_RV32 for timer interrupt.
 231:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 232:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - When the internal MTIME is disabled, and the Internal MTIME IRQ is enabled, the
 233:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   system generates the time value externally and generates the mtimecmp and 
 234:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt internally (for example, a multiprocessor system with a shared time 
 235:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   between all cores). In this case, a 64-bit port is available on the MIV_RV32 
 236:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   core as input.
 237:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 238:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   - Internal MTIME and Internal MTIME IRQ disabled Generate both the time and 
 239:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   timer interrupts externally. In this case a 64 bit port will be available on 
 240:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the MIV_RV32 core as input, and a 1 pin port will be available for timer 
 241:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt.
 242:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 243:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   To handle all these combinations in the firmware, the following constants must 
 244:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   be defined in accordance with the configuration that you have made on your 
 245:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32 core design.
 246:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 247:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMER
 248:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 249:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means that the MTIME register is not available internal to 
 250:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core. In this case, a 64 bit port will be available on the MIV_RV32 core as
 251:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   input. When this macro is not defined, it means that the MTIME register is 
 252:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   available internally to the core.
 253:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 254:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32_EXT_TIMECMP
 255:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   --------------------------------
 256:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When defined, it means the MTIMECMP register is not available internally to 
 257:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the core and the Timer interrupt input to the core comes as an external pin. 
 258:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When this macro is not defined it means the that MTIMECMP register exists 
 259:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   internal to the core and that the timer interrupt is generated internally.
 260:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 261:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** NOTE: All these macros must not be defined if you are using a MIV_RV32 core.
 262:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 263:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 264:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ                SUBSYS_TCM_ECC_CE_IRQ
 265:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ               SUBSYS_TCM_ECC_UCE_IRQ
 266:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ               SUBSYS_AXI_WR_RESP_IRQ
 267:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn               MRV32_SUBSYS_IRQn
 268:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_enable_irq              MRV32_subsys_enable_irq
 269:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_disable_irq             MRV32_subsys_disable_irq
 270:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_opsrv_clear_irq               MRV32_subsys_clear_irq
 271:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_IRQHandler                    SUBSYS_IRQHandler
 272:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 273:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 274:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External IRQ
 275:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 276:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Return value from External IRQ handler. This is used to disable the
 277:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   External Interrupt.
 278:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 279:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 280:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 281:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_KEEP_ENABLED  |    0    |  Keep external interrupts enabled |
 282:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | EXT_IRQ_DISABLE       |    1    |  Disable external interrupts      |
 283:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 284:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
 285:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
 286:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 287:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
 288:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 289:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
 290:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
 291:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
 292:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
 293:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
 294:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 295:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 296:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
 297:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else /* MIV_LEGACY_RV32 */
 298:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 299:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
 300:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
 301:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 302:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 303:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 304:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 305:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 306:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 307:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 308:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 309:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 310:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 311:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 312:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 313:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 314:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 315:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 316:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 317:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIMPID Register
 318:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MIMPID register is a RISC-V Control and Status Register In the v3.0 of 
 319:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MIV_RV32, the value of `MIMPID = 0x000540AD`. In the v3.1 of MIV_RV32, the 
 320:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   value if `MIMPID = 0xE5010301` corresponding to (E)mbedded (5)ystem(01) core 
 321:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   version (03).(01) this terminology will be followed in the subsequent releases 
 322:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the core read the csr value and store it in a varible which may be used to 
 323:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   check the MIV_RV32 core version during runtime.
 324:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 325:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Future releases of the core will increment the 03 and 01 as major and minor 
 326:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   releases respectively and the register can be read at runtime to find the 
 327:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Soft IP core version.
 328:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 329:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Core Version  |  Register  |  Value  |  Notes  |
 330:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |----------------|------------|---------|---------|
 331:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.1  |  mimpid |   0xE5010301  | implimentation ID |
 332:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  MIV_RV32 V3.0  |  mimpid |   0x000540AD  | implimentation ID |
 333:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 334:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MIMPID                          read_csr(mimpid)
 335:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 336:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*Used as a mask to read and write to mte mtvec.BASE address*/
 337:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTVEC_BASE_ADDR_MASK            0xFFFFFFFC
 338:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 339:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 340:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 341:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 342:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 343:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 344:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 345:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   RISC-V Specification Interrupts
 346:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =======================================
 347:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   These definitions are provided for easy identification of the interrupt
 348:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   in the MIE/MIP registers.
 349:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Apart from the standard software, timer, and external interrupts, the names
 350:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   of the additional interrupts correspond to the names as used in the MIV_RV32
 351:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   handbook. Please refer the MIV_RV32 handbook for more details.
 352:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  
 353:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   All the interrups, provided by the MIV_RV32 core, following table shows the 
 354:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt priority order and register description as mentioned in the RISC-V spec.
 355:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 356:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | Macro Name  | Value |  Description|
 357:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |-------------------|--------|----------------|
 358:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_SOFT_IRQn   | MIE_3_IRQn  |  Software interrupt enable  |
 359:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_TIMER_IRQn  | MIE_7_IRQn  |  Timer interrupt enable     |
 360:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | MRV32_EXT_IRQn    | MIE_11_IRQn |  External interrupt enable  |
 361:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 362:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 363:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 364:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 365:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 366:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 367:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*-------------------------------------------------------------------------*//**
 368:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM
 369:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   =================================
 370:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When BootROM is enabled, on reset, the core copies data from a memory mapped
 371:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   source memory into a destination memory location and then the core boots from
 372:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the destination memory location. The source start or end addresses and the
 373:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination start address can be provided through GUI inputs. If the 
 374:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reconfigurable option is enabled, then the addresses become software 
 375:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   reconfigurable, which can be used with a soft reset to reboot and run alternative
 376:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   code. The source and destination memory must be a memory mapped location 
 377:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   accessible by the core across the full transfer size.
 378:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 379:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MTVEC address - By default, the mtvec.BASE is set at Reset Vector Address + 0x04.
 380:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When the BootROM is enabled, the mtvec.BASE is set at destination address + 0x04.
 381:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When using Reconfigurable BootROM, the MTVEC register needs to be defined 
 382:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   and programmed through software.
 383:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 384:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Reset Behaviour - With the BootROM feature enabled, upon reset, the PC takes on
 385:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the value of the BootROM dest_addr. When the BootROM is enabled, ensure that the
 386:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   boot code linker script matches the dest_addr, since booting starts from the
 387:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   destination_addr.
 388:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 389:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   BootROM Register Map:
 390:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |  Name  |  Address  | Description |
 391:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   |--------|-----------|-------------|
 392:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_start_addr     |0xA100| Core copies data beginning here       |
 393:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | src_end_addr       |0xA104| Last address copied by BootROM        |
 394:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   | destination_addr   |0xA108| Destination memory beginning from here|
 395:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 396:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** */
 397:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 398:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_START                    0x0000A100
 399:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_END                      0x0000A104
 400:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define BOOTROM_DEST                     0x0000A108
 401:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 402:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 403:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt numbers:
 404:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This enum represents the interrupt enable bits in the MIE register.
 405:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 406:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 407:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 408:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 409:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 410:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 411:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE 0xC*/
 412:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 413:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 414:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 415:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE 0x1C*/
 416:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 417:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 418:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 419:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE 0x2C*/
 420:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 421:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 422:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 423:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 424:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE ECC Uncorrectable 0x40*/
 425:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE ECC Correctable 0x44*/
 426:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 427:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 428:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 429:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 430:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),        /*SUBSYSR 0x58 (R)eserved*/        
 431:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),        /*SUBSYS_IE 0x5C for MIV_RV32 v3.1*/      
 432:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_IE0 0x60*/
 433:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_IE1 0x64*/
 434:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_IE2 0x68*/
 435:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_IE3 0x6C*/
 436:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_IE4 0x70*/        
 437:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_IE5 0x74*/
 438:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u),        /*MSYS_IE6 0x78, read comment below*/
 439:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_31_IRQn =  (0x01u<<31u)         /*MSYS_IE7 0x7C*/
 440:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 441:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 442:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 443:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 444:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 445:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 446:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 447:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 448:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 449:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 450:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_V3_0 /*For MIV_RV32 v3.1*/
 451:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYSR_IRQn              MIE_22_IRQn
 452:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_23_IRQn
 453:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE6_IRQn            MIE_30_IRQn
 454:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE7_IRQn            MIE_31_IRQn
 455:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 456:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SUBSYS_IRQn               MIE_30_IRQn
 457:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /*MIV_RV32_V3_0*/
 458:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 459:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*--------------------------------Public APIs---------------------------------*/
 460:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 461:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 462:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() function clears single bit ECC errors on the 
 463:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   GPRs. The ECC block does not write back corrected data to memory. Hence, when 
 464:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   ECC is enabled for the GPRs and if that data has a single bit error then the 
 465:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   data coming out of the ECC block is corrected and will not have the error, but 
 466:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data source will still have the error. Therefore, if data has a single bit
 467:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error, then the corrected data must be written back to prevent the single bit
 468:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error from becoming a double bit error. Clear the pending interrupt bit after 
 469:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   this using MRV32_mgeci_clear_irq() function to complete the ECC error handling.
 470:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 471:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @param
 472:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not take any parameters.
 473:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 474:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 475:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This functions returns the CORE_GPR_DED_RESET_REG bit value.
 476:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   */
 477:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 478:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 479:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 480:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 481:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 482:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 483:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 484:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 485:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 486:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 487:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 488:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 489:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 490:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 491:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 492:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 493:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 494:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 495:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 496:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 497:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 498:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 499:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 500:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 501:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 502:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 503:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 504:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 505:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 506:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 507:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 508:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 509:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 510:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 511:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 512:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 513:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 514:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 515:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 516:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 517:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 518:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 519:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 520:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 521:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 522:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 523:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 524:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 525:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 526:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 527:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 528:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 529:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 530:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 531:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 532:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 533:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 534:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 535:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 536:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 537:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 538:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 539:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 540:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 541:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 542:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 543:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 544:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 545:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 546:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 547:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 548:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 549:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 550:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 551:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 552:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 553:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 554:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 555:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 556:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 557:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 558:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 559:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 560:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 561:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 562:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 563:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 564:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 565:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 566:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 567:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 568:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 569:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 570:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 571:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 572:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 573:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 574:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 575:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 576:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 577:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 578:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 579:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 580:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 581:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 582:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 583:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 584:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeui_clear_irq() function clears the GPR ECC Uncorrectable 
 585:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Interrupt. MGEUI interrupt is available only when ECC is enabled in the MIV_RV32 
 586:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   IP configurator.
 587:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 588:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return
 589:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 590:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 591:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(void)
 592:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 593:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 594:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 595:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 596:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 597:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_mgeci_clear_irq() function clears the GPR ECC Correctable Interrupt
 598:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MGECI interrupt is available only when ECC is enabled in the MIV_RV32 IP 
 599:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   configurator.
 600:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 601:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   @return 
 602:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   This function does not return any value.
 603:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 604:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(void)
 605:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 606:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 607:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 608:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 609:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 610:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV_enable_local_irq() function enables the local interrupts. It takes a 
 611:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   mask value as input. For each set bit in the mask value, the corresponding 
 612:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   interrupt bit in the MIE register is enabled.
 613:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   
 614:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_enable_local_irq( MRV32_SOFT_IRQn | MRV32_TIMER_IRQn | MRV32_EXT_IRQn |
 615:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 616:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_SUBSYS_IRQn);                
 617:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 618:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 619:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 620:C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p2\miv-rv32-dp-tx\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
 283              		.loc 2 620 5
 284              	.LBB11:
 285              	.LBB12:
 286              		.loc 2 620 5
 287              		.loc 2 620 5
 288 016a B7070001 		li	a5,16777216
 289              	 #APP
 290              	# 620 "C:\Work_Folder_Akhil\Q4_2024_2025\Display_Port_TX_web_release\Final\NEW_MIV\softconsole2022p
   0              	
 291              		csrrs a5, mie, a5
 292              	# 0 "" 2
 293              	.LVL25:
 294              		.loc 2 620 5
 295              	 #NO_APP
 296              	.LBE12:
 297              	.LBE11:
 223:../src/application/main.c **** 
 224:../src/application/main.c ****     HAL_enable_interrupts();
 298              		.loc 1 224 5
 299 0172 97000000 		call	HAL_enable_interrupts
 299      E7800000 
 300              	.LVL26:
 225:../src/application/main.c **** 
 226:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 0u);
 301              		.loc 1 226 5
 302 017a 0146     		li	a2,0
 303 017c 9145     		li	a1,4
 304 017e 17050000 		lla	a0,g_gpio_out
 304      13050500 
 305 0186 97000000 		call	GPIO_set_output
 305      E7800000 
 306              	.LVL27:
 227:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED2, 1);
 307              		.loc 1 227 5
 308 018e 0546     		li	a2,1
 309 0190 8545     		li	a1,1
 310 0192 17050000 		lla	a0,g_gpio_out
 310      13050500 
 311 019a 97000000 		call	GPIO_set_output
 311      E7800000 
 312              	.LVL28:
 228:../src/application/main.c **** 
 229:../src/application/main.c ****     //Camera Initialization
 230:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM1_RST, 1u);
 313              		.loc 1 230 5
 314 01a2 0546     		li	a2,1
 315 01a4 A145     		li	a1,8
 316 01a6 17050000 		lla	a0,g_gpio_out
 316      13050500 
 317 01ae 97000000 		call	GPIO_set_output
 317      E7800000 
 318              	.LVL29:
 231:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, CAM_CLK_EN, 0u);
 319              		.loc 1 231 5
 320 01b6 0146     		li	a2,0
 321 01b8 A545     		li	a1,9
 322 01ba 17050000 		lla	a0,g_gpio_out
 322      13050500 
 323 01c2 97000000 		call	GPIO_set_output
 323      E7800000 
 324              	.LVL30:
 232:../src/application/main.c ****     imx334_cam_init();
 325              		.loc 1 232 5
 326 01ca 97000000 		call	imx334_cam_init
 326      E7800000 
 327              	.LVL31:
 233:../src/application/main.c ****     imx334_cam_reginit(1u);
 328              		.loc 1 233 5
 329 01d2 0545     		li	a0,1
 330 01d4 97000000 		call	imx334_cam_reginit
 330      E7800000 
 331              	.LVL32:
 234:../src/application/main.c **** 
 235:../src/application/main.c ****     //Setting LED
 236:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED3, 1);
 332              		.loc 1 236 5
 333 01dc 0546     		li	a2,1
 334 01de 8945     		li	a1,2
 335 01e0 17050000 		lla	a0,g_gpio_out
 335      13050500 
 336 01e8 97000000 		call	GPIO_set_output
 336      E7800000 
 337              	.LVL33:
 237:../src/application/main.c ****     msdelay(1000);
 338              		.loc 1 237 5
 339 01f0 1305803E 		li	a0,1000
 340 01f4 97000000 		call	msdelay
 340      E7800000 
 341              	.LVL34:
 238:../src/application/main.c **** //    delay_msec(100);
 239:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, MIPI_TRNG_RST, 1u);
 342              		.loc 1 239 5
 343 01fc 0546     		li	a2,1
 344 01fe 9145     		li	a1,4
 345 0200 17050000 		lla	a0,g_gpio_out
 345      13050500 
 346 0208 97000000 		call	GPIO_set_output
 346      E7800000 
 347              	.LVL35:
 240:../src/application/main.c ****     GPIO_set_output(&g_gpio_out, LED4, 1);
 348              		.loc 1 240 5
 349 0210 0546     		li	a2,1
 350 0212 8D45     		li	a1,3
 351 0214 17050000 		lla	a0,g_gpio_out
 351      13050500 
 352 021c 97000000 		call	GPIO_set_output
 352      E7800000 
 353              	.LVL36:
 241:../src/application/main.c **** 
 242:../src/application/main.c ****     // =========================== DisplayPort ================================
 243:../src/application/main.c ****     UART_init(&g_uart, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, (DATA_8_BITS | NO_PARITY));
 354              		.loc 1 243 5
 355 0224 8546     		li	a3,1
 356 0226 6946     		li	a2,26
 357 0228 B7050071 		li	a1,1895825408
 358 022c 17050000 		lla	a0,g_uart
 358      13050500 
 359 0234 97000000 		call	UART_init
 359      E7800000 
 360              	.LVL37:
 244:../src/application/main.c ****     DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 361              		.loc 1 244 5
 362 023c 9147     		li	a5,4
 363 023e 3EC4     		sw	a5,8(sp)
 364 0240 A167     		li	a5,32768
 365 0242 3EC2     		sw	a5,4(sp)
 366 0244 9547     		li	a5,5
 367 0246 3EC0     		sw	a5,0(sp)
 368 0248 A148     		li	a7,8
 369 024a 0D48     		li	a6,3
 370 024c 93076003 		li	a5,54
 371 0250 1307C004 		li	a4,76
 372 0254 9306C004 		li	a3,76
 373 0258 13860487 		addi	a2,s1,-1936
 374 025c 938504F0 		addi	a1,s1,-256
 375 0260 0945     		li	a0,2
 376              	.LBB13:
 377              	.LBB14:
 378              	.LBB15:
 379              	.LBB16:
 245:../src/application/main.c **** 
 246:../src/application/main.c ****     // ========================================================================
 247:../src/application/main.c **** 
 248:../src/application/main.c ****     do
 249:../src/application/main.c ****     {
 250:../src/application/main.c ****         // ====================================================================
 251:../src/application/main.c ****         // ===================== DisplayPort ==================================
 252:../src/application/main.c ****         // ====================================================================
 253:../src/application/main.c ****         // Check if there is Sink Interrupt
 254:../src/application/main.c ****         DPSourceISR(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 255:../src/application/main.c ****         msdelay(30);
 256:../src/application/main.c ****         auto_brightness(div);
 257:../src/application/main.c **** 
 258:../src/application/main.c **** 
 259:../src/application/main.c ****         counter = counter +1;
 260:../src/application/main.c ****         if (counter <16){
 261:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 262:../src/application/main.c ****         }
 263:../src/application/main.c ****         else{
 264:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 1);
 265:../src/application/main.c ****         }
 266:../src/application/main.c ****         if (counter ==32){
 267:../src/application/main.c ****             counter =0;
 268:../src/application/main.c ****         }
 269:../src/application/main.c **** 
 270:../src/application/main.c ****     } while (1);
 271:../src/application/main.c **** 
 272:../src/application/main.c **** 
 273:../src/application/main.c ****     return 0;
 274:../src/application/main.c **** }
 275:../src/application/main.c **** 
 276:../src/application/main.c **** /**********************************************************/
 277:../src/application/main.c **** /**********************FUNCTION CALLS**********************/
 278:../src/application/main.c **** /**********************************************************/
 279:../src/application/main.c **** void auto_brightness(uint32_t div)
 280:../src/application/main.c **** {
 281:../src/application/main.c ****     uint32_t total_sum =  (uint32_t)(*(volatile int*) IE_INTENSITY_AVARAGE);
 282:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 283:../src/application/main.c **** 
 284:../src/application/main.c ****     gain_cal(total_average);
 285:../src/application/main.c **** }
 286:../src/application/main.c **** 
 287:../src/application/main.c **** void gain_cal(uint32_t total_average)
 288:../src/application/main.c **** {
 289:../src/application/main.c ****     //////////////////////////////////////////////////////
 290:../src/application/main.c ****     const int16_t good_average=100;
 291:../src/application/main.c ****     const int16_t hysteresis=4;
 292:../src/application/main.c ****     int16_t step;
 293:../src/application/main.c ****         if(total_average < (good_average - hysteresis))
 294:../src/application/main.c ****             step = 1;
 295:../src/application/main.c ****         else
 296:../src/application/main.c ****             if(total_average > (good_average + hysteresis))
 380              		.loc 1 296 15 is_stmt 0
 381 0262 3794F419 		li	s0,435458048
 382              	.LBE16:
 383              	.LBE15:
 384              	.LBE14:
 385              	.LBE13:
 244:../src/application/main.c ****     DPSourceInit(SPEED_MODE,HRES,VRES,HFP,HBP,VFP,VBP,HSW,VSW,VSP,LANE_NO);
 386              		.loc 1 244 5
 387 0266 97000000 		call	DPSourceInit
 387      E7800000 
 388              	.LVL38:
 254:../src/application/main.c ****         msdelay(30);
 389              		.loc 1 254 9
 390 026e 138A0487 		addi	s4,s1,-1936
 391              	.LBB26:
 392              	.LBB23:
 393              	.LBB20:
 394              	.LBB17:
 395              		.loc 1 296 15
 396 0272 13040480 		addi	s0,s0,-2048
 297:../src/application/main.c ****                 step = -1;
 298:../src/application/main.c ****             else
 299:../src/application/main.c ****                 step = 0;
 300:../src/application/main.c **** 
 301:../src/application/main.c ****         in_gain = in_gain + step;
 397              		.loc 1 301 27
 398 0276 97090000 		lla	s3,.LANCHOR8
 398      93890900 
 399              	.L18:
 400              	.LBE17:
 401              	.LBE20:
 402              	.LBE23:
 403              	.LBE26:
 254:../src/application/main.c ****         msdelay(30);
 404              		.loc 1 254 9
 405 027e 1149     		li	s2,4
 406 0280 A16A     		li	s5,32768
 407              	.L17:
 248:../src/application/main.c ****     {
 408              		.loc 1 248 5 is_stmt 1
 254:../src/application/main.c ****         msdelay(30);
 409              		.loc 1 254 9
 410 0282 9547     		li	a5,5
 411 0284 1307C004 		li	a4,76
 412 0288 9306C004 		li	a3,76
 413 028c 3EC0     		sw	a5,0(sp)
 414 028e A148     		li	a7,8
 415 0290 93076003 		li	a5,54
 416 0294 0D48     		li	a6,3
 417 0296 5286     		mv	a2,s4
 418 0298 938504F0 		addi	a1,s1,-256
 419 029c 0945     		li	a0,2
 420 029e 4AC4     		sw	s2,8(sp)
 421 02a0 56C2     		sw	s5,4(sp)
 422 02a2 97000000 		call	DPSourceISR
 422      E7800000 
 423              	.LVL39:
 255:../src/application/main.c ****         auto_brightness(div);
 424              		.loc 1 255 9
 425 02aa 7945     		li	a0,30
 426 02ac 97000000 		call	msdelay
 426      E7800000 
 427              	.LVL40:
 256:../src/application/main.c **** 
 428              		.loc 1 256 9
 429              	.LBB27:
 430              	.LBB24:
 281:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 431              		.loc 1 281 5
 281:../src/application/main.c ****     uint32_t total_average = total_sum/div;
 432              		.loc 1 281 38 is_stmt 0
 433 02b4 B7070372 		li	a5,1912799232
 434 02b8 984F     		lw	a4,24(a5)
 435              	.LVL41:
 282:../src/application/main.c **** 
 436              		.loc 1 282 5 is_stmt 1
 284:../src/application/main.c **** }
 437              		.loc 1 284 5
 438              	.LBB21:
 439              	.LBB18:
 290:../src/application/main.c ****     const int16_t hysteresis=4;
 440              		.loc 1 290 5
 291:../src/application/main.c ****     int16_t step;
 441              		.loc 1 291 5
 292:../src/application/main.c ****         if(total_average < (good_average - hysteresis))
 442              		.loc 1 292 5
 293:../src/application/main.c ****             step = 1;
 443              		.loc 1 293 9
 293:../src/application/main.c ****             step = 1;
 444              		.loc 1 293 11 is_stmt 0
 445 02ba B706BB17 		li	a3,398131200
 294:../src/application/main.c ****         else
 446              		.loc 1 294 18
 447 02be 8547     		li	a5,1
 293:../src/application/main.c ****             step = 1;
 448              		.loc 1 293 11
 449 02c0 6367D700 		bltu	a4,a3,.L11
 296:../src/application/main.c ****                 step = -1;
 450              		.loc 1 296 13 is_stmt 1
 296:../src/application/main.c ****                 step = -1;
 451              		.loc 1 296 15 is_stmt 0
 452 02c4 B3378700 		sltu	a5,a4,s0
 453 02c8 FD17     		addi	a5,a5,-1
 454 02ca C207     		slli	a5,a5,16
 455 02cc C187     		srai	a5,a5,16
 456              	.L11:
 457              	.LVL42:
 458              		.loc 1 301 9 is_stmt 1
 459              		.loc 1 301 27 is_stmt 0
 460 02ce 03D70900 		lhu	a4,0(s3)
 461              	.LVL43:
 462 02d2 BA97     		add	a5,a5,a4
 463              	.LVL44:
 464 02d4 C207     		slli	a5,a5,16
 465 02d6 C183     		srli	a5,a5,16
 302:../src/application/main.c **** 
 303:../src/application/main.c ****         if(in_gain < 5)
 466              		.loc 1 303 9 is_stmt 1
 467              		.loc 1 303 11 is_stmt 0
 468 02d8 6369F904 		bgtu	a5,s2,.L12
 304:../src/application/main.c ****             in_gain = 5;
 469              		.loc 1 304 13 is_stmt 1
 470              		.loc 1 304 21 is_stmt 0
 471 02dc 9547     		li	a5,5
 472              	.L22:
 305:../src/application/main.c ****         else
 306:../src/application/main.c ****             if(in_gain >= 100)
 307:../src/application/main.c ****                 in_gain = 100;
 473              		.loc 1 307 25
 474 02de 17070000 		sh	a5,.LANCHOR8,a4
 474      2310F700 
 308:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 309:../src/application/main.c ****     gain_setting(1u,in_gain);
 475              		.loc 1 309 5 is_stmt 1
 476 02e6 97050000 		lhu	a1,.LANCHOR8
 476      83D50500 
 477 02ee 0545     		li	a0,1
 478 02f0 97000000 		call	gain_setting
 478      E7800000 
 479              	.LVL45:
 480              	.LBE18:
 481              	.LBE21:
 482              	.LBE24:
 483              	.LBE27:
 259:../src/application/main.c ****         if (counter <16){
 484              		.loc 1 259 9
 259:../src/application/main.c ****         if (counter <16){
 485              		.loc 1 259 27 is_stmt 0
 486 02f8 F247     		lw	a5,28(sp)
 261:../src/application/main.c ****         }
 487              		.loc 1 261 13
 488 02fa 0146     		li	a2,0
 259:../src/application/main.c ****         if (counter <16){
 489              		.loc 1 259 27
 490 02fc 8507     		addi	a5,a5,1
 259:../src/application/main.c ****         if (counter <16){
 491              		.loc 1 259 17
 492 02fe 3ECE     		sw	a5,28(sp)
 260:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 493              		.loc 1 260 9 is_stmt 1
 260:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 494              		.loc 1 260 21 is_stmt 0
 495 0300 7247     		lw	a4,28(sp)
 260:../src/application/main.c ****             GPIO_set_output(&g_gpio_out, LED1, 0);
 496              		.loc 1 260 12
 497 0302 BD47     		li	a5,15
 498 0304 63F3E700 		bleu	a4,a5,.L23
 264:../src/application/main.c ****         }
 499              		.loc 1 264 13 is_stmt 1
 500 0308 0546     		li	a2,1
 501              	.L23:
 502 030a 8145     		li	a1,0
 503 030c 17050000 		lla	a0,g_gpio_out
 503      13050500 
 504 0314 97000000 		call	GPIO_set_output
 504      E7800000 
 505              	.LVL46:
 266:../src/application/main.c ****             counter =0;
 506              		.loc 1 266 9
 266:../src/application/main.c ****             counter =0;
 507              		.loc 1 266 21 is_stmt 0
 508 031c 7247     		lw	a4,28(sp)
 266:../src/application/main.c ****             counter =0;
 509              		.loc 1 266 12
 510 031e 93070002 		li	a5,32
 511 0322 E310F7F6 		bne	a4,a5,.L17
 267:../src/application/main.c ****         }
 512              		.loc 1 267 13 is_stmt 1
 267:../src/application/main.c ****         }
 513              		.loc 1 267 21 is_stmt 0
 514 0326 02CE     		sw	zero,28(sp)
 515 0328 99BF     		j	.L18
 516              	.LVL47:
 517              	.L12:
 518              	.LBB28:
 519              	.LBB25:
 520              	.LBB22:
 521              	.LBB19:
 306:../src/application/main.c ****                 in_gain = 100;
 522              		.loc 1 306 13 is_stmt 1
 306:../src/application/main.c ****                 in_gain = 100;
 523              		.loc 1 306 15 is_stmt 0
 524 032a 13073006 		li	a4,99
 525 032e E378F7FA 		bleu	a5,a4,.L22
 307:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 526              		.loc 1 307 17 is_stmt 1
 307:../src/application/main.c ****     ///////////////////////////////////////////////////////////
 527              		.loc 1 307 25 is_stmt 0
 528 0332 93074006 		li	a5,100
 529 0336 65B7     		j	.L22
 530              	.LBE19:
 531              	.LBE22:
 532              	.LBE25:
 533              	.LBE28:
 534              		.cfi_endproc
 535              	.LFE23:
 537              		.comm	a,4,4
 538              		.globl	process_data
 539              		.globl	i
 540              		.globl	second_constant
 541              		.globl	B_constant
 542              		.globl	G_constant
 543              		.globl	R_constant
 544              		.globl	t_ms_count
 545              		.comm	rx_ms_count,4,4
 546              		.comm	rx_ms_count1,4,4
 547              		.globl	rx_tmr_done
 548              		.globl	g_state
 549              		.comm	g_gpio_out,8,4
 550              		.comm	bayer,2,2
 551              		.comm	g_uart,8,4
 552              		.globl	uart_rx_buff
 553              		.comm	g_i2c_instance_cam1,108,4
 554              		.comm	g_ms_count,4,4
 555              		.comm	g_10ms_count1,4,4
 556              		.globl	timerdone
 557              		.comm	g_10ms_count,4,4
 558              		.comm	MRV_LOCAL_IRQn_Type,4,4
 559              		.section	.bss.uart_rx_buff,"aw",@nobits
 560              		.align	2
 563              	uart_rx_buff:
 564 0000 00000000 		.zero	23
 564      00000000 
 564      00000000 
 564      00000000 
 564      00000000 
 565              		.section	.sbss.i,"aw",@nobits
 566              		.align	2
 569              	i:
 570 0000 00000000 		.zero	4
 571              		.section	.sbss.process_data,"aw",@nobits
 572              		.align	2
 573              		.set	.LANCHOR3,. + 0
 576              	process_data:
 577 0000 00000000 		.zero	4
 578              		.section	.sbss.rx_tmr_done,"aw",@nobits
 579              		.align	2
 580              		.set	.LANCHOR2,. + 0
 583              	rx_tmr_done:
 584 0000 00000000 		.zero	4
 585              		.section	.sbss.second_constant,"aw",@nobits
 586              		.align	2
 587              		.set	.LANCHOR7,. + 0
 590              	second_constant:
 591 0000 00000000 		.zero	4
 592              		.section	.sbss.t_ms_count,"aw",@nobits
 593              		.align	2
 596              	t_ms_count:
 597 0000 00000000 		.zero	4
 598              		.section	.sbss.timerdone,"aw",@nobits
 599              		.align	2
 600              		.set	.LANCHOR1,. + 0
 603              	timerdone:
 604 0000 00000000 		.zero	4
 605              		.section	.sdata.B_constant,"aw"
 606              		.align	2
 607              		.set	.LANCHOR6,. + 0
 610              	B_constant:
 611 0000 A5000000 		.word	165
 612              		.section	.sdata.G_constant,"aw"
 613              		.align	2
 614              		.set	.LANCHOR5,. + 0
 617              	G_constant:
 618 0000 7A000000 		.word	122
 619              		.section	.sdata.R_constant,"aw"
 620              		.align	2
 621              		.set	.LANCHOR4,. + 0
 624              	R_constant:
 625 0000 92000000 		.word	146
 626              		.section	.sdata.g_state,"aw"
 627              		.align	2
 628              		.set	.LANCHOR0,. + 0
 631              	g_state:
 632 0000 01000000 		.word	1
 633              		.section	.sdata.in_gain,"aw"
 634              		.align	1
 635              		.set	.LANCHOR8,. + 0
 638              	in_gain:
 639 0000 5000     		.half	80
 640              		.text
 641              	.Letext0:
 642              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 643              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 644              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 645              		.file 6 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 646              		.file 7 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 647              		.file 8 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 648              		.file 9 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softcon
 649              		.file 10 "../src/application/dp_cmd_common.h"
 650              		.file 11 "../src/application/imx334_corei2c/imx334_corei2c.h"
 651              		.file 12 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softco
 652              		.file 13 "C:\\Work_Folder_Akhil\\Q4_2024_2025\\Display_Port_TX_web_release\\Final\\NEW_MIV\\softco
 653              		.file 14 "../src/application/dp_cmd_tx.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 main.c
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:13     .text.SysTick_Handler:0000000000000000 SysTick_Handler
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:17     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:18     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:19     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:20     .text.SysTick_Handler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:26     .text.SysTick_Handler:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:27     .text.SysTick_Handler:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:30     .text.SysTick_Handler:0000000000000022 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:33     .text.SysTick_Handler:0000000000000028 .L0 
                            *COM*:0000000000000004 g_10ms_count1
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:34     .text.SysTick_Handler:0000000000000028 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:39     .text.SysTick_Handler:000000000000003c .L0 
                            *COM*:0000000000000004 g_ms_count
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:40     .text.SysTick_Handler:000000000000003c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:44     .text.SysTick_Handler:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:46     .text.SysTick_Handler:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:47     .text.SysTick_Handler:000000000000004c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:50     .text.SysTick_Handler:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:51     .text.SysTick_Handler:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:54     .text.SysTick_Handler:000000000000005e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:57     .text.SysTick_Handler:0000000000000064 .L0 
                            *COM*:0000000000000004 rx_ms_count1
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:58     .text.SysTick_Handler:0000000000000064 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:63     .text.SysTick_Handler:0000000000000078 .L0 
                            *COM*:0000000000000004 rx_ms_count
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:64     .text.SysTick_Handler:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:68     .text.SysTick_Handler:0000000000000084 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:70     .text.SysTick_Handler:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:71     .text.SysTick_Handler:0000000000000088 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:73     .text.SysTick_Handler:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:74     .text.SysTick_Handler:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:77     .text.SysTick_Handler:0000000000000098 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:78     .text.SysTick_Handler:000000000000009a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:85     .text.MSYS_EI0_IRQHandler:0000000000000000 MSYS_EI0_IRQHandler
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:88     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:89     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:90     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:91     .text.MSYS_EI0_IRQHandler:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:92     .text.MSYS_EI0_IRQHandler:0000000000000002 .L0 
                            *COM*:000000000000006c g_i2c_instance_cam1
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:94     .text.MSYS_EI0_IRQHandler:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:96     .text.MSYS_EI0_IRQHandler:000000000000000a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:97     .text.MSYS_EI0_IRQHandler:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:99     .text.MSYS_EI0_IRQHandler:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:102    .text.MSYS_EI0_IRQHandler:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:103    .text.MSYS_EI0_IRQHandler:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:104    .text.MSYS_EI0_IRQHandler:0000000000000016 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:107    .text.MSYS_EI0_IRQHandler:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:109    .text.MSYS_EI0_IRQHandler:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:116    .text.startup.main:0000000000000000 main
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:119    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:121    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:122    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:123    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:124    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:125    .text.startup.main:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:126    .text.startup.main:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:128    .text.startup.main:0000000000000002 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:133    .text.startup.main:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:136    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:137    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:138    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:140    .text.startup.main:000000000000000e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:142    .text.startup.main:0000000000000012 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:146    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:147    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:148    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:149    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:151    .text.startup.main:000000000000001a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:154    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:155    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:156    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:157    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:158    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:159    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:160    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:161    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:162    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:163    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:164    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:165    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:166    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:167    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:168    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:169    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:170    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:171    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:172    .text.startup.main:000000000000001c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:175    .text.startup.main:0000000000000024 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:180    .text.startup.main:0000000000000032 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:185    .text.startup.main:0000000000000042 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:191    .text.startup.main:0000000000000054 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:196    .text.startup.main:0000000000000062 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:201    .text.startup.main:0000000000000070 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:206    .text.startup.main:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:211    .text.startup.main:000000000000008e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:216    .text.startup.main:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:221    .text.startup.main:00000000000000aa .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:224    .text.startup.main:00000000000000b0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:226    .text.startup.main:00000000000000b4 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:229    .text.startup.main:00000000000000bc .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:234    .text.startup.main:00000000000000ca .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:240    .text.startup.main:00000000000000e0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:246    .text.startup.main:00000000000000f6 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:252    .text.startup.main:000000000000010c .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:258    .text.startup.main:0000000000000122 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:263    .text.startup.main:0000000000000130 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:264    .text.startup.main:0000000000000130 .L0 
                            *COM*:0000000000000008 g_gpio_out
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:270    .text.startup.main:0000000000000146 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:276    .text.startup.main:000000000000015a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:283    .text.startup.main:000000000000016a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:286    .text.startup.main:000000000000016a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:287    .text.startup.main:000000000000016a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:288    .text.startup.main:000000000000016a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:298    .text.startup.main:0000000000000172 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:299    .text.startup.main:0000000000000172 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:302    .text.startup.main:000000000000017a .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:308    .text.startup.main:000000000000018e .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:314    .text.startup.main:00000000000001a2 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:320    .text.startup.main:00000000000001b6 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:326    .text.startup.main:00000000000001ca .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:329    .text.startup.main:00000000000001d2 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:333    .text.startup.main:00000000000001dc .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:339    .text.startup.main:00000000000001f0 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:343    .text.startup.main:00000000000001fc .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:349    .text.startup.main:0000000000000210 .L0 
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:355    .text.startup.main:0000000000000224 .L0 
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C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:117    .text.startup.main:0000000000000000 .LFB23
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:535    .text.startup.main:0000000000000338 .LFE23
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C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3579   .debug_loc:0000000000000000 .LLST0
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C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3593   .debug_loc:0000000000000021 .LLST1
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C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:297    .text.startup.main:0000000000000172 .LBE11
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3607   .debug_loc:0000000000000042 .LLST2
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:285    .text.startup.main:000000000000016a .LBB12
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:296    .text.startup.main:0000000000000172 .LBE12
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:376    .text.startup.main:0000000000000262 .LBB13
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3617   .debug_loc:0000000000000058 .LLST3
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C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:378    .text.startup.main:0000000000000262 .LBB15
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3657   .debug_loc:00000000000000b4 .LLST7
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:479    .text.startup.main:00000000000002f8 .LVL45
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:173    .text.startup.main:0000000000000024 .LVL5
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:178    .text.startup.main:0000000000000032 .LVL6
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:183    .text.startup.main:0000000000000042 .LVL7
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:189    .text.startup.main:0000000000000054 .LVL8
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:194    .text.startup.main:0000000000000062 .LVL9
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:199    .text.startup.main:0000000000000070 .LVL10
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:204    .text.startup.main:0000000000000080 .LVL11
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:209    .text.startup.main:000000000000008e .LVL12
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:214    .text.startup.main:000000000000009c .LVL13
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:219    .text.startup.main:00000000000000aa .LVL14
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:227    .text.startup.main:00000000000000bc .LVL15
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:232    .text.startup.main:00000000000000ca .LVL16
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:238    .text.startup.main:00000000000000e0 .LVL17
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:244    .text.startup.main:00000000000000f6 .LVL18
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:250    .text.startup.main:000000000000010c .LVL19
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:256    .text.startup.main:0000000000000122 .LVL20
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:261    .text.startup.main:0000000000000130 .LVL21
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:268    .text.startup.main:0000000000000146 .LVL22
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:274    .text.startup.main:000000000000015a .LVL23
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:280    .text.startup.main:000000000000016a .LVL24
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:300    .text.startup.main:000000000000017a .LVL26
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:306    .text.startup.main:000000000000018e .LVL27
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:312    .text.startup.main:00000000000001a2 .LVL28
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:318    .text.startup.main:00000000000001b6 .LVL29
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:324    .text.startup.main:00000000000001ca .LVL30
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:327    .text.startup.main:00000000000001d2 .LVL31
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:331    .text.startup.main:00000000000001dc .LVL32
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:337    .text.startup.main:00000000000001f0 .LVL33
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:341    .text.startup.main:00000000000001fc .LVL34
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:347    .text.startup.main:0000000000000210 .LVL35
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:353    .text.startup.main:0000000000000224 .LVL36
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:360    .text.startup.main:000000000000023c .LVL37
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:388    .text.startup.main:000000000000026e .LVL38
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:423    .text.startup.main:00000000000002aa .LVL39
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:427    .text.startup.main:00000000000002b4 .LVL40
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:505    .text.startup.main:000000000000031c .LVL46
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4005   .debug_str:00000000000007be .LASF178
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4079   .debug_str:0000000000000a17 .LASF180
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:86     .text.MSYS_EI0_IRQHandler:0000000000000000 .LFB22
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:110    .text.MSYS_EI0_IRQHandler:000000000000001c .LFE22
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:100    .text.MSYS_EI0_IRQHandler:0000000000000014 .LVL0
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4001   .debug_str:00000000000007a2 .LASF200
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:14     .text.SysTick_Handler:0000000000000000 .LFB21
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:79     .text.SysTick_Handler:000000000000009a .LFE21
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3807   .debug_str:0000000000000268 .LASF181
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4053   .debug_str:0000000000000974 .LASF182
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3827   .debug_str:00000000000002ed .LASF183
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3785   .debug_str:00000000000001d4 .LASF184
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3823   .debug_str:00000000000002cf .LASF185
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3945   .debug_str:0000000000000647 .LASF186
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4077   .debug_str:0000000000000a07 .LASF187
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4063   .debug_str:00000000000009a5 .LASF188
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3767   .debug_str:0000000000000169 .LASF189
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4013   .debug_str:00000000000007ea .LASF190
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3991   .debug_str:000000000000075e .LASF191
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4011   .debug_str:00000000000007e0 .LASF193
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3851   .debug_str:0000000000000441 .LASF194
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:4043   .debug_str:0000000000000928 .LASF195
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:3917   .debug_str:00000000000005bb .LASF196
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:120    .text.startup.main:0000000000000000 .LVL1
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:131    .text.startup.main:0000000000000008 .LVL3
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:129    .text.startup.main:0000000000000004 .LVL2
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:293    .text.startup.main:0000000000000172 .LVL25
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:516    .text.startup.main:000000000000032a .LVL47
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:435    .text.startup.main:00000000000002ba .LVL41
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:461    .text.startup.main:00000000000002d2 .LVL43
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:457    .text.startup.main:00000000000002ce .LVL42
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:463    .text.startup.main:00000000000002d4 .LVL44
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:655    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:385    .text.startup.main:0000000000000266 .LBE13
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:391    .text.startup.main:0000000000000272 .LBB26
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:403    .text.startup.main:000000000000027e .LBE26
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:429    .text.startup.main:00000000000002b4 .LBB27
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:483    .text.startup.main:00000000000002f8 .LBE27
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:518    .text.startup.main:000000000000032a .LBB28
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:533    .text.startup.main:0000000000000338 .LBE28
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:383    .text.startup.main:0000000000000266 .LBE15
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:393    .text.startup.main:0000000000000272 .LBB20
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:401    .text.startup.main:000000000000027e .LBE20
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:438    .text.startup.main:00000000000002ba .LBB21
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:481    .text.startup.main:00000000000002f8 .LBE21
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:520    .text.startup.main:000000000000032a .LBB22
C:\Users\I71825\AppData\Local\Temp\ccbdAFpP.s:531    .text.startup.main:0000000000000338 .LBE22

UNDEFINED SYMBOLS
I2C_isr
axi4litewrite
GPIO_init
GPIO_set_output
MRV_systick_config
HAL_enable_interrupts
imx334_cam_init
imx334_cam_reginit
msdelay
UART_init
DPSourceInit
DPSourceISR
gain_setting
