   1              	# 1 "../src/platform/hal/hw_reg_access.S"
   1              	/***************************************************************************//**
   0              	
   0              	
   0              	
   2              	 * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3              	 *
   4              	 * SPDX-License-Identifier: MIT
   5              	 *
   6              	 * @file hw_reg_access.S
   7              	 * @author Microchip FPGA Embedded Systems Solutions
   8              	 * @brief Hardware registers access functions.
   9              	 * The implementation of these function is platform and toolchain specific.
  10              	 * The functions declared here are implemented using assembler as part of the
  11              	 * processor/toolchain specific HAL. This implementation is for the combination
  12              	 * of the 32 bit RISC-V processors and GNU tool chain.
  13              	 *
  14              	 */
  15              	
  16              	.section .text
  17              	    .globl HW_set_32bit_reg
  18              	    .globl HW_get_32bit_reg
  19              	    .globl HW_set_32bit_reg_field
  20              	    .globl HW_get_32bit_reg_field
  21              	    .globl HW_set_16bit_reg
  22              	    .globl HW_get_16bit_reg
  23              	    .globl HW_set_16bit_reg_field
  24              	    .globl HW_get_16bit_reg_field
  25              	    .globl HW_set_8bit_reg
  26              	    .globl HW_get_8bit_reg
  27              	    .globl HW_set_8bit_reg_field
  28              	    .globl HW_get_8bit_reg_field
  29              	
  30              	
  31              	/***************************************************************************//**
  32              	 * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
  33              	 * register.
  34              	 *
  35              	 * a0:   addr_t reg_addr
  36              	 * a1:   uint32_t value
  37              	 */
  38              	HW_set_32bit_reg:
  39 0000 0CC1     	    sw a1, 0(a0)
  40 0002 8280     	    ret
  41              	
  42              	/***************************************************************************//**
  43              	 * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
  44              	 * register.
  45              	 *
  46              	 * a0:   addr_t reg_addr
  47              	
  48              	 * @return          32 bits value read from the peripheral register.
  49              	 */
  50              	HW_get_32bit_reg:
  51 0004 0841     	    lw a0, 0(a0)
  52 0006 8280     	    ret
  53              	
  54              	/***************************************************************************//**
  55              	 * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits
  56              	 * wide peripheral register.
  57              	 *
  58              	 * a0:   addr_t reg_addr
  59              	 * a1:   int_fast8_t shift
  60              	 * a2:   uint32_t mask
  61              	 * a3:   uint32_t value
  62              	 */
  63              	HW_set_32bit_reg_field:
  64 0008 368E     	    mv t3, a3
  65 000a 331EBE00 	    sll t3, t3, a1
  66 000e 337ECE00 	    and  t3, t3, a2
  67 0012 03230500 	    lw t1, 0(a0)
  68 0016 B283     	    mv t2, a2
  69 0018 93C3F3FF 	    not t2, t2
  70 001c 33737300 	    and t1, t1, t2
  71 0020 3363C301 	    or t1, t1, t3
  72 0024 23206500 	    sw t1, 0(a0)
  73 0028 8280     	    ret
  74              	
  75              	/***************************************************************************//**
  76              	 * HW_get_32bit_reg_field is used to read the content of a field out of a
  77              	 * 32 bits wide peripheral register.
  78              	 *
  79              	 * a0:   addr_t reg_addr
  80              	 * a1:   int_fast8_t shift
  81              	 * a2:   uint32_t mask
  82              	 *
  83              	 * @return          32 bits value containing the register field value specified
  84              	 *                  as parameter.
  85              	 */
  86              	HW_get_32bit_reg_field:
  87 002a 0841     	    lw a0, 0(a0)
  88 002c 718D     	    and a0, a0, a2
  89 002e 3355B500 	    srl a0, a0, a1
  90 0032 8280     	    ret
  91              	
  92              	/***************************************************************************//**
  93              	 * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
  94              	 * register.
  95              	 *
  96              	 * a0:   addr_t reg_addr
  97              	 * a1:   uint_fast16_t value
  98              	 */
  99              	HW_set_16bit_reg:
 100 0034 2310B500 	    sh a1, 0(a0)
 101 0038 8280     	    ret
 102              	
 103              	/***************************************************************************//**
 104              	 * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
 105              	 * register.
 106              	 *
 107              	 * a0:   addr_t reg_addr
 108              	
 109              	 * @return          16 bits value read from the peripheral register.
 110              	 */
 111              	HW_get_16bit_reg:
 112 003a 03150500 	    lh a0, (a0)
 113 003e 8280     	    ret
 114              	
 115              	/***************************************************************************//**
 116              	 * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits
 117              	 * wide peripheral register.
 118              	 *
 119              	 * a0:   addr_t reg_addr
 120              	 * a1:   int_fast8_t shift
 121              	 * a2:   uint_fast16_t mask
 122              	 * a3:   uint_fast16_t value
 123              	 * @param value     Value to be written in the specified field.
 124              	 */
 125              	HW_set_16bit_reg_field:
 126 0040 368E     	    mv t3, a3
 127 0042 331EBE00 	    sll t3, t3, a1
 128 0046 337ECE00 	    and  t3, t3, a2
 129 004a 03130500 	    lh t1, 0(a0)
 130 004e B283     	    mv t2, a2
 131 0050 93C3F3FF 	    not t2, t2
 132 0054 33737300 	    and t1, t1, t2
 133 0058 3363C301 	    or t1, t1, t3
 134 005c 23106500 	    sh t1, 0(a0)
 135 0060 8280     	    ret
 136              	
 137              	/***************************************************************************//**
 138              	 * HW_get_16bit_reg_field is used to read the content of a field from a
 139              	 * 16 bits wide peripheral register.
 140              	 *
 141              	 * a0:   addr_t reg_addr
 142              	 * a1:   int_fast8_t shift
 143              	 * a2:   uint_fast16_t mask
 144              	 *
 145              	 * @return          16 bits value containing the register field value specified
 146              	 *                  as parameter.
 147              	 */
 148              	HW_get_16bit_reg_field:
 149 0062 03150500 	    lh a0, 0(a0)
 150 0066 718D     	    and a0, a0, a2
 151 0068 3355B500 	    srl a0, a0, a1
 152 006c 8280     	    ret
 153              	
 154              	/***************************************************************************//**
 155              	 * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
 156              	 * register.
 157              	 *
 158              	 * a0:   addr_t reg_addr
 159              	 * a1:   uint_fast8_t value
 160              	 */
 161              	HW_set_8bit_reg:
 162 006e 2300B500 	    sb a1, 0(a0)
 163 0072 8280     	    ret
 164              	
 165              	/***************************************************************************//**
 166              	 * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
 167              	 * register.
 168              	 *
 169              	 * a0:   addr_t reg_addr
 170              	
 171              	 * @return          8 bits value read from the peripheral register.
 172              	 */
 173              	HW_get_8bit_reg:
 174 0074 03050500 	    lb a0, 0(a0)
 175 0078 8280     	    ret
 176              	
 177              	/***************************************************************************//**
 178              	 * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits
 179              	 * wide peripheral register.
 180              	 *
 181              	 * a0:   addr_t reg_addr,
 182              	 * a1:   int_fast8_t shift
 183              	 * a2:   uint_fast8_t mask
 184              	 * a3:   uint_fast8_t value
 185              	 */
 186              	HW_set_8bit_reg_field:
 187 007a 368E     	    mv t3, a3
 188 007c 331EBE00 	    sll t3, t3, a1
 189 0080 337ECE00 	    and  t3, t3, a2
 190 0084 03030500 	    lb t1, 0(a0)
 191 0088 B283     	    mv t2, a2
 192 008a 93C3F3FF 	    not t2, t2
 193 008e 33737300 	    and t1, t1, t2
 194 0092 3363C301 	    or t1, t1, t3
 195 0096 23006500 	    sb t1, 0(a0)
 196 009a 8280     	    ret
 197              	
 198              	/***************************************************************************//**
 199              	 * HW_get_8bit_reg_field is used to read the content of a field from a
 200              	 * 8 bits wide peripheral register.
 201              	 *
 202              	 * a0:   addr_t reg_addr
 203              	 * a1:   int_fast8_t shift
 204              	 * a2:   uint_fast8_t mask
 205              	 *
 206              	 * @return          8 bits value containing the register field value specified
 207              	 *                  as parameter.
 208              	 */
 209              	HW_get_8bit_reg_field:
 210 009c 03050500 	    lb a0, 0(a0)
 211 00a0 718D     	    and a0, a0, a2
 212 00a2 3355B500 	    srl a0, a0, a1
 213 00a6 8280     	    ret
 214              	
 215              	.end
DEFINED SYMBOLS
../src/platform/hal/hw_reg_access.S:38     .text:0000000000000000 HW_set_32bit_reg
../src/platform/hal/hw_reg_access.S:50     .text:0000000000000004 HW_get_32bit_reg
../src/platform/hal/hw_reg_access.S:63     .text:0000000000000008 HW_set_32bit_reg_field
../src/platform/hal/hw_reg_access.S:86     .text:000000000000002a HW_get_32bit_reg_field
../src/platform/hal/hw_reg_access.S:99     .text:0000000000000034 HW_set_16bit_reg
../src/platform/hal/hw_reg_access.S:111    .text:000000000000003a HW_get_16bit_reg
../src/platform/hal/hw_reg_access.S:125    .text:0000000000000040 HW_set_16bit_reg_field
../src/platform/hal/hw_reg_access.S:148    .text:0000000000000062 HW_get_16bit_reg_field
../src/platform/hal/hw_reg_access.S:161    .text:000000000000006e HW_set_8bit_reg
../src/platform/hal/hw_reg_access.S:173    .text:0000000000000074 HW_get_8bit_reg
../src/platform/hal/hw_reg_access.S:186    .text:000000000000007a HW_set_8bit_reg_field
../src/platform/hal/hw_reg_access.S:209    .text:000000000000009c HW_get_8bit_reg_field
../src/platform/hal/hw_reg_access.S:39     .text:0000000000000000 .L0 
../src/platform/hal/hw_reg_access.S:40     .text:0000000000000002 .L0 
../src/platform/hal/hw_reg_access.S:51     .text:0000000000000004 .L0 
../src/platform/hal/hw_reg_access.S:52     .text:0000000000000006 .L0 
../src/platform/hal/hw_reg_access.S:64     .text:0000000000000008 .L0 
../src/platform/hal/hw_reg_access.S:65     .text:000000000000000a .L0 
../src/platform/hal/hw_reg_access.S:66     .text:000000000000000e .L0 
../src/platform/hal/hw_reg_access.S:67     .text:0000000000000012 .L0 
../src/platform/hal/hw_reg_access.S:68     .text:0000000000000016 .L0 
../src/platform/hal/hw_reg_access.S:69     .text:0000000000000018 .L0 
../src/platform/hal/hw_reg_access.S:70     .text:000000000000001c .L0 
../src/platform/hal/hw_reg_access.S:71     .text:0000000000000020 .L0 
../src/platform/hal/hw_reg_access.S:72     .text:0000000000000024 .L0 
../src/platform/hal/hw_reg_access.S:73     .text:0000000000000028 .L0 
../src/platform/hal/hw_reg_access.S:87     .text:000000000000002a .L0 
../src/platform/hal/hw_reg_access.S:88     .text:000000000000002c .L0 
../src/platform/hal/hw_reg_access.S:89     .text:000000000000002e .L0 
../src/platform/hal/hw_reg_access.S:90     .text:0000000000000032 .L0 
../src/platform/hal/hw_reg_access.S:100    .text:0000000000000034 .L0 
../src/platform/hal/hw_reg_access.S:101    .text:0000000000000038 .L0 
../src/platform/hal/hw_reg_access.S:112    .text:000000000000003a .L0 
../src/platform/hal/hw_reg_access.S:113    .text:000000000000003e .L0 
../src/platform/hal/hw_reg_access.S:126    .text:0000000000000040 .L0 
../src/platform/hal/hw_reg_access.S:127    .text:0000000000000042 .L0 
../src/platform/hal/hw_reg_access.S:128    .text:0000000000000046 .L0 
../src/platform/hal/hw_reg_access.S:129    .text:000000000000004a .L0 
../src/platform/hal/hw_reg_access.S:130    .text:000000000000004e .L0 
../src/platform/hal/hw_reg_access.S:131    .text:0000000000000050 .L0 
../src/platform/hal/hw_reg_access.S:132    .text:0000000000000054 .L0 
../src/platform/hal/hw_reg_access.S:133    .text:0000000000000058 .L0 
../src/platform/hal/hw_reg_access.S:134    .text:000000000000005c .L0 
../src/platform/hal/hw_reg_access.S:135    .text:0000000000000060 .L0 
../src/platform/hal/hw_reg_access.S:149    .text:0000000000000062 .L0 
../src/platform/hal/hw_reg_access.S:150    .text:0000000000000066 .L0 
../src/platform/hal/hw_reg_access.S:151    .text:0000000000000068 .L0 
../src/platform/hal/hw_reg_access.S:152    .text:000000000000006c .L0 
../src/platform/hal/hw_reg_access.S:162    .text:000000000000006e .L0 
../src/platform/hal/hw_reg_access.S:163    .text:0000000000000072 .L0 
../src/platform/hal/hw_reg_access.S:174    .text:0000000000000074 .L0 
../src/platform/hal/hw_reg_access.S:175    .text:0000000000000078 .L0 
../src/platform/hal/hw_reg_access.S:187    .text:000000000000007a .L0 
../src/platform/hal/hw_reg_access.S:188    .text:000000000000007c .L0 
../src/platform/hal/hw_reg_access.S:189    .text:0000000000000080 .L0 
../src/platform/hal/hw_reg_access.S:190    .text:0000000000000084 .L0 
../src/platform/hal/hw_reg_access.S:191    .text:0000000000000088 .L0 
../src/platform/hal/hw_reg_access.S:192    .text:000000000000008a .L0 
../src/platform/hal/hw_reg_access.S:193    .text:000000000000008e .L0 
../src/platform/hal/hw_reg_access.S:194    .text:0000000000000092 .L0 
../src/platform/hal/hw_reg_access.S:195    .text:0000000000000096 .L0 
../src/platform/hal/hw_reg_access.S:196    .text:000000000000009a .L0 
../src/platform/hal/hw_reg_access.S:210    .text:000000000000009c .L0 
../src/platform/hal/hw_reg_access.S:211    .text:00000000000000a0 .L0 
../src/platform/hal/hw_reg_access.S:212    .text:00000000000000a2 .L0 
../src/platform/hal/hw_reg_access.S:213    .text:00000000000000a6 .L0 
../src/platform/hal/hw_reg_access.S:215    .text:00000000000000a8 .L0 
                            .text:0000000000000000 .L0 
../src/platform/hal/hw_reg_access.S:215    .text:00000000000000a8 .L0 
                       .debug_str:0000000000000000 .L0 
                       .debug_str:0000000000000024 .L0 
                       .debug_str:00000000000000a4 .L0 

NO UNDEFINED SYMBOLS
