src/application/slvs_ec_corei2c/slvs_ec_corei2c.o: \
 ../src/application/slvs_ec_corei2c/slvs_ec_corei2c.c \
 ../src/application/slvs_ec_corei2c/slvs_ec_corei2c.h \
 c:\d\g5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform\drivers\fpga_ip\corei2c\core_i2c.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hal.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/cpu_types.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hw_reg_access.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hal_assert.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/drivers/fpga_ip/CoreGPIO/core_gpio.h \
 C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\boards/polarfire-cxp-device-kit/miv-rv32-design/fpga_design_config/fpga_design_config.h

../src/application/slvs_ec_corei2c/slvs_ec_corei2c.h:

c:\d\g5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform\drivers\fpga_ip\corei2c\core_i2c.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hal.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/cpu_types.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hw_reg_access.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/hal/hal_assert.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\platform/drivers/fpga_ip/CoreGPIO/core_gpio.h:

C:\D\G5\coaxpress\slvs2cxp\libero\tcl\mpf_an4053_v2025p2_df\softconsole2022p2\miv-rv32i-cxp-device\src\boards/polarfire-cxp-device-kit/miv-rv32-design/fpga_design_config/fpga_design_config.h:
