   1              		.file	"miv_rv32_hal.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.MRV_systick_config,"ax",@progbits
  10              		.align	2
  11              		.globl	MRV_systick_config
  13              	MRV_systick_config:
  14              	.LFB18:
  15              		.file 1 "../src/platform/miv_rv32_hal/miv_rv32_hal.c"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @file miv_rv32_hal.c
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * @brief Implementation of Hardware Abstraction Layer for Mi-V soft processors
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include <unistd.h>
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #include "miv_rv32_hal.h"
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef __cplusplus
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern "C" {
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define SUCCESS                       0U
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define ERROR                         1U
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MASK_32BIT                    0xFFFFFFFFu
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *  Write in a sequence recommended by privileged spec to avoid spurious
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupts
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****    # New comparand is in a1:a0.
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     li t0, -1
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw t0, mtimecmp # No smaller than old value.
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a1, mtimecmp+4 # No smaller than new value.
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     sw a0, mtimecmp # New value.
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMECMP
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)         MTIMECMPH = MASK_32BIT; \
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMP  = value & MASK_32BIT;\
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMECMPH =  (value >> 32u) & MASK_32BIT;
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIMECMP(value)
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_RV32_EXT_TIMER
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)            MTIME  = value & MASK_32BIT;\
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                       MTIMEH = (value >> 32u) & MASK_32BIT;
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define WRITE_MTIME(value)
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void Software_IRQHandler(void);
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #define MTIME_PRESCALER                 100UL
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  *
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t Invalid_IRQHandler(void);
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_1_IRQHandler(void);
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_2_IRQHandler(void);
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_3_IRQHandler(void);
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_4_IRQHandler(void);
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_5_IRQHandler(void);
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_6_IRQHandler(void);
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_7_IRQHandler(void);
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_8_IRQHandler(void);
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_9_IRQHandler(void);
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_10_IRQHandler(void);
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_11_IRQHandler(void);
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_12_IRQHandler(void);
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_13_IRQHandler(void);
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_14_IRQHandler(void);
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_15_IRQHandler(void);
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_16_IRQHandler(void);
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_17_IRQHandler(void);
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_18_IRQHandler(void);
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_19_IRQHandler(void);
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_20_IRQHandler(void);
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_21_IRQHandler(void);
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_22_IRQHandler(void);
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_23_IRQHandler(void);
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_24_IRQHandler(void);
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_25_IRQHandler(void);
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_26_IRQHandler(void);
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_27_IRQHandler(void);
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_28_IRQHandler(void);
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_29_IRQHandler(void);
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_30_IRQHandler(void);
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t External_31_IRQHandler(void);
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for external interrupts.
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint8_t (* const ext_irq_handler_table[32])(void) =
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Invalid_IRQHandler,
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_1_IRQHandler,
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_2_IRQHandler,
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_3_IRQHandler,
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_4_IRQHandler,
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_5_IRQHandler,
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_6_IRQHandler,
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_7_IRQHandler,
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_8_IRQHandler,
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_9_IRQHandler,
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_10_IRQHandler,
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_11_IRQHandler,
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_12_IRQHandler,
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_13_IRQHandler,
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_14_IRQHandler,
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_15_IRQHandler,
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_16_IRQHandler,
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_17_IRQHandler,
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_18_IRQHandler,
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_19_IRQHandler,
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_20_IRQHandler,
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_21_IRQHandler,
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_22_IRQHandler,
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_23_IRQHandler,
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_24_IRQHandler,
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_25_IRQHandler,
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_26_IRQHandler,
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_27_IRQHandler,
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_28_IRQHandler,
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_29_IRQHandler,
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_30_IRQHandler,
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     External_31_IRQHandler
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** };
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Interrupt handlers as mapped into the MIE register of the MIV_RV32
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void External_IRQHandler(void);
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGEUI_IRQHandler(void);
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MGECI_IRQHandler(void);
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI0_IRQHandler(void);
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI1_IRQHandler(void);
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI2_IRQHandler(void);
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI3_IRQHandler(void);
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI4_IRQHandler(void);
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void MSYS_EI5_IRQHandler(void);
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** extern void OPSRV_IRQHandler(void);
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif  /* MIV_LEGACY_RV32 */
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Increment value for the mtimecmp register in order to achieve a system tick
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * interrupt as specified through the MRV_systick_config() function.
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_increment = 0U;
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** static uint64_t g_systick_cmp_value = 0U;
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Configure the machine timer to generate an interrupt.
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** uint32_t MRV_systick_config(uint64_t ticks)
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
  16              		.loc 1 156 1
  17              		.cfi_startproc
  18              	.LVL0:
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t ret_val = ERROR;
  19              		.loc 1 157 5
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
  20              		.loc 1 158 5
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while (remainder >= MTIME_PRESCALER)
  21              		.loc 1 160 5
  22 0000 97070000 		lla	a5,.LANCHOR0
  22      93870700 
  23 0008 83A60700 		lw	a3,0(a5)
  24 000c 03A64700 		lw	a2,4(a5)
  25              		.loc 1 160 11 is_stmt 0
  26 0010 93080000 		li	a7,0
  27 0014 13870700 		mv	a4,a5
  28              		.loc 1 160 25
  29 0018 37530002 		li	t1,33574912
  30              	.LVL1:
  31              	.L2:
  32 001c 138E1600 		addi	t3,a3,1
  33 0020 83270300 		lw	a5,0(t1)
  34 0024 3338DE00 		sltu	a6,t3,a3
  35 0028 3308C800 		add	a6,a6,a2
  36              		.loc 1 160 11
  37 002c 639E0506 		bne	a1,zero,.L3
  38 0030 637CF506 		bleu	a5,a0,.L3
  39 0034 638A0800 		beq	a7,zero,.L5
  40 0038 97070000 		sw	a3,.LANCHOR0,a5
  40      23A0D700 
  41 0040 97070000 		sw	a2,.LANCHOR0+4,a5
  41      23A0C700 
  42              	.L5:
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         remainder -= MTIME_PRESCALER;
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     g_systick_cmp_value = g_systick_increment + MTIME;
  43              		.loc 1 166 5 is_stmt 1
  44              		.loc 1 166 49 is_stmt 0
  45 0048 B7C70002 		li	a5,33603584
  46 004c 83A787FF 		lw	a5,-8(a5)
  47              		.loc 1 166 47
  48 0050 83260700 		lw	a3,0(a4)
  49 0054 03274700 		lw	a4,4(a4)
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t remainder = ticks;
  50              		.loc 1 157 14
  51 0058 13051000 		li	a0,1
  52              	.LVL2:
  53              		.loc 1 166 47
  54 005c 3386D700 		add	a2,a5,a3
  55 0060 B337F600 		sltu	a5,a2,a5
  56 0064 B387E700 		add	a5,a5,a4
  57              		.loc 1 166 25
  58 0068 97050000 		sw	a2,.LANCHOR1,a1
  58      23A0C500 
  59 0070 97050000 		sw	a5,.LANCHOR1+4,a1
  59      23A0F500 
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (g_systick_increment > 0U)
  60              		.loc 1 168 5 is_stmt 1
  61              		.loc 1 168 8 is_stmt 0
  62 0078 B3E6E600 		or	a3,a3,a4
  63 007c 63840602 		beq	a3,zero,.L1
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         WRITE_MTIMECMP(g_systick_cmp_value);
  64              		.loc 1 170 9 is_stmt 1
  65 0080 37470002 		li	a4,33570816
  66 0084 9306F0FF 		li	a3,-1
  67 0088 2322D700 		sw	a3,4(a4)
  68              		.loc 1 170 9
  69 008c 2320C700 		sw	a2,0(a4)
  70              		.loc 1 170 9
  71 0090 2322F700 		sw	a5,4(a4)
  72              		.loc 1 170 44
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
  73              		.loc 1 171 9
  74              	.LBB6:
  75              		.loc 1 171 9
  76              		.loc 1 171 9
  77 0094 93070008 		li	a5,128
  78              	 #APP
  79              	# 171 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 172              	        MRV_enable_interrupts();
  80              		csrrs a5, mie, a5
  81              	# 0 "" 2
  82              	.LVL3:
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         set_csr(mie, MIP_MTIP);
  83              		.loc 1 171 9
  84              	 #NO_APP
  85              	.LBE6:
  86              		.loc 1 172 9
  87              		.file 2 "../src/platform/miv_rv32_hal/miv_rv32_hal.h"
   1:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*******************************************************************************
   2:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
   4:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
   6:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * of this software and associated documentation files (the "Software"), to
   8:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * deal in the Software without restriction, including without limitation the
   9:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
  10:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * sell copies of the Software, and to permit persons to whom the Software is
  11:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * furnished to do so, subject to the following conditions:
  12:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  13:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The above copyright notice and this permission notice shall be included in
  14:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * all copies or substantial portions of the Software.
  15:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  16:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * IN THE SOFTWARE.
  23:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * 
  24:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @file miv_rv32_hal.h
  25:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
  26:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
  27:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  28:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  29:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  30:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef RISCV_HAL_H
  31:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define RISCV_HAL_H
  32:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  33:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_regs.h"
  34:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_plic.h"
  35:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "miv_rv32_assert.h"
  36:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  37:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
  38:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "fpga_design_config/fpga_design_config.h"
  39:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
  40:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #include "hw_platform.h"
  41:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
  42:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  43:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef __cplusplus
  44:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** extern "C" {
  45:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
  46:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  47:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
  48:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Return value from External IRQ handler. This will be used to disable the
  49:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * External interrupt.
  50:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  51:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
  52:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
  53:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  54:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
  55:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * System tick handler. This handler function gets called when the Machine
  56:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * timer interrupt asserts. An implementation of this function should be
  57:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * provided by the application to implement the application specific machine
  58:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * timer interrupt handling. If application does not provide such implementation
  59:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * the weakly linked handler stub function implemented in riscv_hal_stubs.c gets
  60:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * linked.
  61:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  62:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** void SysTick_Handler(void);
  63:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  64:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
  65:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * System timer tick configuration.
  66:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Configures the machine timer to generate a system tick interrupt at regular
  67:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * intervals.
  68:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Takes the number of system clock ticks between interrupts.
  69:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  70:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Though this function can take any valid ticks value as parameter, we expect
  71:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * that, for all practical purposes, a small tick value (to generate periodic 
  72:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * interrupts every few miliseconds) will be passed. If you need to generate
  73:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * periodic events in the range of seconds or more, you may use the SysTick_Handler()
  74:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * to further count the number of interrupts and hence the larger time intervals.
  75:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  *
  76:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Returns 0 if successful.
  77:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Returns 1 if the interrupt interval cannot be achieved.
  78:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
  79:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** uint32_t MRV_systick_config(uint64_t ticks);
  80:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  81:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_DELTA                     5
  82:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  83:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
  84:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
  85:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
  86:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
  87:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
  88:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
  89:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  90:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  91:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
  92:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  93:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
  94:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  95:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  96:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
  97:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
  98:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* OPSRV stands for "Offload Processor Subsystem for RISC-V" (OPSRV) on the
  99:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * MIV_RV32 IP core. Please see the handbook for more details. */
 100:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 101:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* TCM ECC correctable error irq enable mask value */
 102:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ            0x01u
 103:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 104:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* TCMECC uncorrectable error irq enable */
 105:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ           0x02u
 106:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 107:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* AXI write response error irq enable */
 108:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ           0x10u
 109:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 110:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV_BASE_ADDR                 0x00006000UL
 111:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 112:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** typedef struct
 113:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 114:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t cfg;          	/*Parity is not being supported by MIV_RV32 v3.0*/
 115:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t reserved0[3];
 116:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t irq_en;           /*offset 0x10*/
 117:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t irq_pend;
 118:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t reserved1[2];
 119:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     volatile uint32_t soft_reg;         /*offset 0x20*/
 120:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** } OPSRV_Type;
 121:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 122:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define OPSRV                           ((OPSRV_Type *)OPSRV_BASE_ADDR)
 123:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 124:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 125:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 126:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 127:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 128:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 129:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 130:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 131:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 132:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* On MIV_RV32IMC v2.0 and v2.1 MTIME_PRESCALER is not defined and using this
 133:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * definition will result in crash. For those core use the definition as below
 134:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * #define MTIME_PRESCALER              100u
 135:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 136:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 137:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 138:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 139:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 140:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 141:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 142:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIME                           (0u)
 143:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MTIMEH                          (0u)
 144:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 145:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 146:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /* These definitions are provided for convenient identification of the interrupts
 147:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * in the MIE/MIP registers.
 148:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Apart from the standard software, timer and external interrupts, the names
 149:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * of the additional interrupts correspond to the names as used in the MIV_RV32
 150:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * handbook. Please refer the MIV_RV32 handbook for more details.
 151:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * */
 152:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 153:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 154:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 155:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 156:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /*==============================================================================
 157:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Interrupt numbers:
 158:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * This enum represents the interrupt enable bits in the MIE register.
 159:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 160:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** enum
 161:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 164:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 165:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE*/
 166:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 167:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 168:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 169:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE*/
 170:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 171:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 172:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE*/
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE*/
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE*/
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 181:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),
 185:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_EIE0*/
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_EIE1*/
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_EIE2*/
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_EIE3*/
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_EIE4*/
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_EIE5*/
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u)         /*OPSRV_IRQ_IE*/
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 194:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn           MIE_30_IRQn
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     Enable OPSRV interrupt. Parameter takes logical OR of following values
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_opsrv_enable_irq(uint32_t irq_mask)
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->irq_en = irq_mask;
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     Disable OPSRV interrupt. Parameter takes logical OR of following values
 220:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_opsrv_disable_irq(uint32_t irq_mask)
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->irq_en &= ~irq_mask;
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 228:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     Clear OPSRV interrupt. Parameter takes logical OR of following values
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_opsrv_clear_irq(uint32_t irq_mask)
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->irq_pend |= irq_mask;
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV32_is_gpr_ded() returns the core_gpr_ded_reset_reg bit value.
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * When ECC is enabled, the core_gpr_ded_reset_reg is set when the core was
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * reset due to GPR DED error.
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline uint32_t MRV32_is_gpr_ded(void)
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     return((OPSRV->soft_reg & 0x04u) >> 0x02u);
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV32_clear_gpr_ded() can be used to clear the
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * core_gpr_ded_reset_reg bit. When ECC is enabled, the core_gpr_ded_reset_reg
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * is set when the core was previously reset due to GPR DED error.
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ded(void)
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x04u;
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   When ECC is enabled for the GPRs and if that data has a single bit error then
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   the data coming out of the ECC block will be corrected and will not have the
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   error but the data source will still have the error.
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The ECC block does not write back corrected data to memory.
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Therefore, if data has a single bit error, then the corrected data should be 
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   written back to prevent the single bit error from becoming a double bit error.
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() can be used for that.
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   Clear the pending interrupt bit after this using MRV32_mgeci_clear_irq()
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   function to complete the ECC error handling.
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     uint32_t temp;
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "sw x31, %0"
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"=m" (temp));
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ volatile (
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x1;"
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x1, x31;"
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x2;"
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x2, x31;"
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x3;"
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x3, x31;"
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x4;"
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x4, x31;"
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x5;"
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x5, x31;"
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x6;"
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x6, x31;"
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x7;"
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x7, x31;"
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x8;"
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x8, x31;"
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x9;"
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x9, x31;"
 307:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x10;"
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x10, x31;"
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x11;"
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x11, x31;"
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x12;"
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x12, x31;"
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x13;"
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x13, x31;"
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x14;"
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x14, x31;"
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x15;"
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x15, x31;"
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x16;"
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x16, x31;"
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x17;"
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x17, x31;"
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x18;"
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x18, x31;"
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x19;"
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x19, x31;"
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x20;"
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x20, x31;"
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x21;"
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x21, x31;"
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x22;"
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x22, x31;"
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x23;"
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x23, x31;"
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x24;"
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x24, x31;"
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x25;"
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x25, x31;"
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x26;"
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x26, x31;"
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x27;"
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x27, x31;"
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x28;"
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x28, x31;"
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 365:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x29;"
 366:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x29, x31;"
 367:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 368:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x31, x30;"
 369:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "mv x30, x31;");
 370:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 371:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     __asm__ __volatile__ (
 372:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             "lw x31, %0;"
 373:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :
 374:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****             :"m" (temp));
 375:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 376:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 377:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 378:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV32_enable_parity_check() is used to enable parity check on
 379:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * the TCM and it's interface transactions. This feature is not available on
 380:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * MIV_RV32 v3.0.100 soft processor core.
 381:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 382:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_enable_parity_check(void)
 383:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 384:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->cfg |= 0x01u;
 385:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 386:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 387:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 388:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV32_disable_parity_check() is used to disable parity check on
 389:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * the TCM and it's interface transactions.
 390:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 391:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_disable_parity_check(void)
 392:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 393:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->cfg &= ~0x01u;
 394:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 395:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 396:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 397:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV32_cpu_soft_reset() is used to cause a soft cpu reset on
 398:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * the MIV_RV32 soft processor core.
 399:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 400:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_cpu_soft_reset(void)
 401:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 402:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x01u;
 403:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 404:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 405:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 406:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     Clear GPR ECC Uncorrectable interrupt. MGEUI interrupt is available only when
 407:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 408:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 409:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(uint32_t irq_mask)
 410:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 411:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 412:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 413:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 414:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 415:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     Clear GPR ECC correctable interrupt. MGECI interrupt is available only when
 416:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 417:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 418:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(uint32_t irq_mask)
 419:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 420:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 421:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 422:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 423:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 424:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Enable interrupts.
 425:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 426:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is enabled.
 427:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 428:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  MRV_enable_local_irq(MRV32_SOFT_IRQn  |
 429:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                       MRV32_TIMER_IRQn |
 430:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                       MRV32_EXT_IRQn   |
 431:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                       MRV32_MSYS_EIE0_IRQn |
 432:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                       MRV32_MSYS_OPSRV_IRQn);
 433:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 434:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 435:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 436:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, mask);
 437:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 438:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 439:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 440:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * Disable interrupts.
 441:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 442:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is disabled.
 443:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 444:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****   MRV_disable_local_irq(MRV32_SOFT_IRQn  |
 445:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_TIMER_IRQn |
 446:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_EXT_IRQn   |
 447:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 448:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****                         MRV32_MSYS_OPSRV_IRQn);
 449:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 450:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 451:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 452:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     clear_csr(mie, mask);
 453:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 454:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 455:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif /* MIV_LEGACY_RV32 */
 456:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 457:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 458:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV_raise_soft_irq() raises a synchronous software interrupt
 459:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * by writing into the MSIP register.
 460:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 461:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_raise_soft_irq(void)
 462:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 463:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mie, MIP_MSIP);       /* Enable software interrupt bit */
 464:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 465:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 466:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* You need to make sure that the global interrupt is enabled */
 467:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x01;   /* raise soft interrupt */
 468:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 469:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Raise soft IRQ on MIV_RV32 processor */
 470:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->soft_reg |= (1u << 1u);
 471:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 472:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 473:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 474:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 475:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV_clear_soft_irq() clears a synchronous software interrupt
 476:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * by clearing the MSIP register.
 477:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 478:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_clear_soft_irq(void)
 479:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 480:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 481:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     MSIP = 0x00u;   /* clear soft interrupt */
 482:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #else
 483:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     /* Clear soft IRQ on MIV_RV32 processor */
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     OPSRV->soft_reg &= ~(1u << 1u);
 485:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 486:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** }
 487:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** 
 488:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** /***************************************************************************//**
 489:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * The function MRV_enable_interrupts() enables all interrupts setting the
 490:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  * machine mode interrupt enable bit in MSTATUS register.
 491:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****  */
 492:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** static inline void MRV_enable_interrupts(void)
 493:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** {
 494:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
  88              		.loc 2 494 5
  89              	.LBB7:
  90              	.LBB8:
  91              		.loc 2 494 5
  92              		.loc 2 494 5
  93              	 #APP
  94              	# 494 "../src/platform/miv_rv32_hal/miv_rv32_hal.h" 1
 495              	}
  95              		csrrs a5, mstatus, 8
  96              	# 0 "" 2
  97              	.LVL4:
 494:../src/platform/miv_rv32_hal/miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
  98              		.loc 2 494 5
  99              	 #NO_APP
 100              	.LBE8:
 101              	.LBE7:
 173:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         ret_val = SUCCESS;
 102              		.loc 1 173 9
 103              		.loc 1 173 17 is_stmt 0
 104 00a0 13050000 		li	a0,0
 105              	.LVL5:
 106              	.L1:
 174:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 175:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 176:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     return ret_val;
 177:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 107              		.loc 1 177 1
 108 00a4 67800000 		ret
 109              	.LVL6:
 110              	.L3:
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 111              		.loc 1 162 9 is_stmt 1
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 112              		.loc 1 162 22 is_stmt 0
 113 00a8 83270300 		lw	a5,0(t1)
 114 00ac 93081000 		li	a7,1
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 115              		.loc 1 162 19
 116 00b0 13060800 		mv	a2,a6
 117 00b4 B307F540 		sub	a5,a0,a5
 118 00b8 B336F500 		sgtu	a3,a5,a0
 119 00bc B385D540 		sub	a1,a1,a3
 120              	.LVL7:
 163:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 121              		.loc 1 163 9 is_stmt 1
 162:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_increment++;
 122              		.loc 1 162 19 is_stmt 0
 123 00c0 13850700 		mv	a0,a5
 124 00c4 93060E00 		mv	a3,t3
 125 00c8 6FF05FF5 		j	.L2
 126              		.cfi_endproc
 127              	.LFE18:
 129              		.section	.text.handle_m_timer_interrupt,"ax",@progbits
 130              		.align	2
 131              		.globl	handle_m_timer_interrupt
 133              	handle_m_timer_interrupt:
 134              	.LFB19:
 178:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 179:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 180:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for machine timer interrupts.
 181:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 182:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_timer_interrupt(void)
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 135              		.loc 1 183 1 is_stmt 1
 136              		.cfi_startproc
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 137              		.loc 1 184 5
 138              	.LBB9:
 139              		.loc 1 184 5
 140              		.loc 1 184 5
 141              	.LBE9:
 183:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 142              		.loc 1 183 1 is_stmt 0
 143 0000 130101FF 		addi	sp,sp,-16
 144              		.cfi_def_cfa_offset 16
 145 0004 23261100 		sw	ra,12(sp)
 146              		.cfi_offset 1, -4
 147              	.LBB10:
 148              		.loc 1 184 5
 149 0008 93070008 		li	a5,128
 150              	 #APP
 151              	# 184 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 185              	
 152              		csrrc a5, mie, a5
 153              	# 0 "" 2
 154              	.LVL8:
 184:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     clear_csr(mie, MIP_MTIP);
 155              		.loc 1 184 5 is_stmt 1
 156              	 #NO_APP
 157              	.LBE10:
 186:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint64_t mtime_at_irq = MTIME;
 158              		.loc 1 186 5
 159              		.loc 1 186 29 is_stmt 0
 160 0010 B7C70002 		li	a5,33603584
 161 0014 83A687FF 		lw	a3,-8(a5)
 162              	.LVL9:
 187:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 188:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 189:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     static volatile uint32_t d_tick = 0u;
 190:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 191:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
 163              		.loc 1 192 5 is_stmt 1
 164 0018 97070000 		lla	a5,.LANCHOR1
 164      93870700 
 165 0020 03A70700 		lw	a4,0(a5)
 166 0024 83A74700 		lw	a5,4(a5)
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 167              		.loc 1 193 51 is_stmt 0
 168 0028 17060000 		lla	a2,.LANCHOR0
 168      13060600 
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 169              		.loc 1 192 47
 170 0030 93855600 		addi	a1,a3,5
 171              		.loc 1 193 51
 172 0034 03250600 		lw	a0,0(a2)
 173 0038 03284600 		lw	a6,4(a2)
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 174              		.loc 1 192 47
 175 003c B3B6D500 		sltu	a3,a1,a3
 176              	.LVL10:
 192:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
 177              		.loc 1 192 10
 178 0040 13060000 		li	a2,0
 179              	.L15:
 180 0044 63E8D704 		bgtu	a3,a5,.L16
 181 0048 6394F600 		bne	a3,a5,.L19
 182 004c 6364B704 		bgtu	a1,a4,.L16
 183              	.L19:
 184 0050 630A0600 		beq	a2,zero,.L18
 185 0054 97060000 		sw	a4,.LANCHOR1,a3
 185      23A0E600 
 186 005c 97060000 		sw	a5,.LANCHOR1+4,a3
 186      23A0F600 
 187              	.L18:
 194:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 195:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 196:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         d_tick += 1;
 197:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 198:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 199:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 200:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     /*
 201:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Note: If d_tick > 1 it means, that a system timer interrupt has been missed.
 202:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      *
 203:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * Please ensure that interrupt handlers are as short as possible to prevent
 204:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * them stopping other interrupts from being handled. For example, if a
 205:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * system timer interrupt occurs during a software interrupt, the system
 206:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * timer interrupt will not be handled until the software interrupt handling
 207:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * is complete. If the software interrupt handling time is more than one systick
 208:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * interval, it will result in d_tick > 1.
 209:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      *
 210:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * If you are running the program using the debugger and halt the CPU at a breakpoint,
 211:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * MTIME will continue to increment and interrupts will be missed; resulting
 212:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      * in d_tick > 1.
 213:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****      */
 214:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 215:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     WRITE_MTIMECMP(g_systick_cmp_value);
 188              		.loc 1 215 5 is_stmt 1
 189 0064 B7460002 		li	a3,33570816
 190 0068 1306F0FF 		li	a2,-1
 191 006c 23A2C600 		sw	a2,4(a3)
 192              		.loc 1 215 5
 193 0070 23A0E600 		sw	a4,0(a3)
 194              		.loc 1 215 5
 195 0074 23A2F600 		sw	a5,4(a3)
 196              		.loc 1 215 40
 216:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 217:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     SysTick_Handler();
 197              		.loc 1 217 5
 198 0078 97000000 		call	SysTick_Handler
 198      E7800000 
 199              	.LVL11:
 218:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 200              		.loc 1 219 5
 201              	.LBB11:
 202              		.loc 1 219 5
 203              		.loc 1 219 5
 204 0080 93070008 		li	a5,128
 205              	 #APP
 206              	# 219 "../src/platform/miv_rv32_hal/miv_rv32_hal.c" 1
 220              	}
 207              		csrrs a5, mie, a5
 208              	# 0 "" 2
 209              	.LVL12:
 219:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     set_csr(mie, MIP_MTIP);
 210              		.loc 1 219 5
 211              	 #NO_APP
 212              	.LBE11:
 213              		.loc 1 220 1 is_stmt 0
 214 0088 8320C100 		lw	ra,12(sp)
 215              		.cfi_remember_state
 216              		.cfi_restore 1
 217 008c 13010101 		addi	sp,sp,16
 218              		.cfi_def_cfa_offset 0
 219 0090 67800000 		jr	ra
 220              	.LVL13:
 221              	.L16:
 222              		.cfi_restore_state
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 223              		.loc 1 193 9 is_stmt 1
 193:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 224              		.loc 1 193 51 is_stmt 0
 225 0094 3306A700 		add	a2,a4,a0
 226 0098 B338E600 		sltu	a7,a2,a4
 227 009c B3870701 		add	a5,a5,a6
 228 00a0 13070600 		mv	a4,a2
 229 00a4 B387F800 		add	a5,a7,a5
 230 00a8 13061000 		li	a2,1
 231 00ac 6FF09FF9 		j	.L15
 232              		.cfi_endproc
 233              	.LFE19:
 235              		.section	.text.handle_m_soft_interrupt,"ax",@progbits
 236              		.align	2
 237              		.globl	handle_m_soft_interrupt
 239              	handle_m_soft_interrupt:
 240              	.LFB20:
 221:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 222:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 223:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * RISC-V interrupt handler for software interrupts.
 224:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 225:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
 226:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_ext_interrupt(void)
 227:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 228:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     unsigned long hart_id = read_csr(mhartid);
 229:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint32_t int_num  = PLIC->TARGET[hart_id].CLAIM_COMPLETE;
 230:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     uint8_t disable = EXT_IRQ_KEEP_ENABLED;
 231:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 232:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if (0u !=int_num)
 233:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 234:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         disable = ext_irq_handler_table[int_num]();
 235:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 236:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         PLIC->TARGET[hart_id].CLAIM_COMPLETE = int_num;
 237:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 238:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         if(EXT_IRQ_DISABLE == disable)
 239:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         {
 240:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****             MRV_PLIC_disable_irq((IRQn_Type)int_num);
 241:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         }
 242:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 243:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 244:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /* MIV_LEGACY_RV32 */
 245:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 246:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_m_soft_interrupt(void)
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 241              		.loc 1 247 1 is_stmt 1
 242              		.cfi_startproc
 248:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 243              		.loc 1 248 5
 247:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     Software_IRQHandler();
 244              		.loc 1 247 1 is_stmt 0
 245 0000 130101FF 		addi	sp,sp,-16
 246              		.cfi_def_cfa_offset 16
 247 0004 23261100 		sw	ra,12(sp)
 248              		.cfi_offset 1, -4
 249              		.loc 1 248 5
 250 0008 97000000 		call	Software_IRQHandler
 250      E7800000 
 251              	.LVL14:
 249:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     MRV_clear_soft_irq();
 252              		.loc 1 249 5 is_stmt 1
 253              	.LBB14:
 254              	.LBB15:
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 255              		.loc 2 484 5
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 256              		.loc 2 484 21 is_stmt 0
 257 0010 37670000 		li	a4,24576
 258 0014 83270702 		lw	a5,32(a4)
 259              	.LBE15:
 260              	.LBE14:
 250:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** }
 261              		.loc 1 250 1
 262 0018 8320C100 		lw	ra,12(sp)
 263              		.cfi_restore 1
 264              	.LBB17:
 265              	.LBB16:
 484:../src/platform/miv_rv32_hal/miv_rv32_hal.h **** #endif
 266              		.loc 2 484 21
 267 001c 93F7D7FF 		andi	a5,a5,-3
 268 0020 2320F702 		sw	a5,32(a4)
 269              	.LBE16:
 270              	.LBE17:
 271              		.loc 1 250 1
 272 0024 13010101 		addi	sp,sp,16
 273              		.cfi_def_cfa_offset 0
 274 0028 67800000 		jr	ra
 275              		.cfi_endproc
 276              	.LFE20:
 278              		.section	.text.handle_trap,"ax",@progbits
 279              		.align	2
 280              		.globl	handle_trap
 282              	handle_trap:
 283              	.LFB21:
 251:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 252:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** /*------------------------------------------------------------------------------
 253:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  * Trap handler. This function is invoked in the non-vectored mode.
 254:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****  */
 255:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** void handle_trap(uintptr_t mcause, uintptr_t mepc)
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** {
 284              		.loc 1 256 1 is_stmt 1
 285              		.cfi_startproc
 286              	.LVL15:
 257:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
 287              		.loc 1 257 5
 288              		.loc 1 257 8 is_stmt 0
 289 0000 6356050C 		bge	a0,zero,.L27
 290              		.loc 1 257 43 discriminator 1
 291 0004 93171500 		slli	a5,a0,1
 292 0008 93D71700 		srli	a5,a5,1
 293              		.loc 1 257 31 discriminator 1
 294 000c 13073000 		li	a4,3
 295 0010 6396E700 		bne	a5,a4,.L28
 258:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 259:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         handle_m_soft_interrupt();
 296              		.loc 1 259 9 is_stmt 1
 297 0014 17030000 		tail	handle_m_soft_interrupt
 297      67000300 
 298              	.LVL16:
 299              	.L28:
 260:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 261:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER))
 300              		.loc 1 261 10 discriminator 1
 301              		.loc 1 261 36 is_stmt 0 discriminator 1
 302 001c 13077000 		li	a4,7
 303 0020 6396E700 		bne	a5,a4,.L29
 262:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 263:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         handle_m_timer_interrupt();
 304              		.loc 1 263 9 is_stmt 1
 305 0024 17030000 		tail	handle_m_timer_interrupt
 305      67000300 
 306              	.LVL17:
 307              	.L29:
 264:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 265:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT))
 308              		.loc 1 265 10 discriminator 1
 309              		.loc 1 265 36 is_stmt 0 discriminator 1
 310 002c 1307B000 		li	a4,11
 311 0030 6396E700 		bne	a5,a4,.L30
 266:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 267:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifdef MIV_LEGACY_RV32
 268:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         handle_m_ext_interrupt();
 269:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 270:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         External_IRQHandler();
 312              		.loc 1 270 9 is_stmt 1
 313 0034 17030000 		tail	External_IRQHandler
 313      67000300 
 314              	.LVL18:
 315              	.L30:
 271:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif
 272:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 273:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef MIV_LEGACY_RV32
 274:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI0))
 316              		.loc 1 274 10 discriminator 1
 317              		.loc 1 274 36 is_stmt 0 discriminator 1
 318 003c 13078001 		li	a4,24
 319 0040 6396E700 		bne	a5,a4,.L31
 275:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 276:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI0_IRQHandler();
 320              		.loc 1 276 9 is_stmt 1
 321 0044 17030000 		tail	MSYS_EI0_IRQHandler
 321      67000300 
 322              	.LVL19:
 323              	.L31:
 277:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 278:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI1))
 324              		.loc 1 278 10 discriminator 1
 325              		.loc 1 278 36 is_stmt 0 discriminator 1
 326 004c 13079001 		li	a4,25
 327 0050 6396E700 		bne	a5,a4,.L32
 279:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 280:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI1_IRQHandler();
 328              		.loc 1 280 9 is_stmt 1
 329 0054 17030000 		tail	MSYS_EI1_IRQHandler
 329      67000300 
 330              	.LVL20:
 331              	.L32:
 281:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 282:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI2))
 332              		.loc 1 282 10 discriminator 1
 333              		.loc 1 282 36 is_stmt 0 discriminator 1
 334 005c 1307A001 		li	a4,26
 335 0060 6396E700 		bne	a5,a4,.L33
 283:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 284:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI2_IRQHandler();
 336              		.loc 1 284 9 is_stmt 1
 337 0064 17030000 		tail	MSYS_EI2_IRQHandler
 337      67000300 
 338              	.LVL21:
 339              	.L33:
 285:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 286:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI3))
 340              		.loc 1 286 10 discriminator 1
 341              		.loc 1 286 36 is_stmt 0 discriminator 1
 342 006c 1307B001 		li	a4,27
 343 0070 6396E700 		bne	a5,a4,.L34
 287:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 288:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI3_IRQHandler();
 344              		.loc 1 288 9 is_stmt 1
 345 0074 17030000 		tail	MSYS_EI3_IRQHandler
 345      67000300 
 346              	.LVL22:
 347              	.L34:
 289:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 290:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI4))
 348              		.loc 1 290 10 discriminator 1
 349              		.loc 1 290 36 is_stmt 0 discriminator 1
 350 007c 1307C001 		li	a4,28
 351 0080 6396E700 		bne	a5,a4,.L35
 291:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 292:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI4_IRQHandler();
 352              		.loc 1 292 9 is_stmt 1
 353 0084 17030000 		tail	MSYS_EI4_IRQHandler
 353      67000300 
 354              	.LVL23:
 355              	.L35:
 293:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 294:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MSYS_EI5))
 356              		.loc 1 294 10 discriminator 1
 357              		.loc 1 294 36 is_stmt 0 discriminator 1
 358 008c 1307D001 		li	a4,29
 359 0090 6396E700 		bne	a5,a4,.L36
 295:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 296:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MSYS_EI5_IRQHandler();
 360              		.loc 1 296 9 is_stmt 1
 361 0094 17030000 		tail	MSYS_EI5_IRQHandler
 361      67000300 
 362              	.LVL24:
 363              	.L36:
 297:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 298:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == OPSRV_REG))
 364              		.loc 1 298 10 discriminator 1
 365              		.loc 1 298 36 is_stmt 0 discriminator 1
 366 009c 1307E001 		li	a4,30
 367 00a0 6396E700 		bne	a5,a4,.L37
 299:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 300:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         OPSRV_IRQHandler();
 368              		.loc 1 300 9 is_stmt 1
 369 00a4 17030000 		tail	OPSRV_IRQHandler
 369      67000300 
 370              	.LVL25:
 371              	.L37:
 301:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 302:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MGEUI))
 372              		.loc 1 302 10 discriminator 1
 373              		.loc 1 302 36 is_stmt 0 discriminator 1
 374 00ac 13070001 		li	a4,16
 375 00b0 6396E700 		bne	a5,a4,.L38
 303:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 304:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MGEUI_IRQHandler();
 376              		.loc 1 304 9 is_stmt 1
 377 00b4 17030000 		tail	MGEUI_IRQHandler
 377      67000300 
 378              	.LVL26:
 379              	.L38:
 305:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 306:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == MGECI))
 380              		.loc 1 306 10 discriminator 1
 381              		.loc 1 306 36 is_stmt 0 discriminator 1
 382 00bc 13071001 		li	a4,17
 383 00c0 6396E700 		bne	a5,a4,.L27
 307:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 308:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         MGECI_IRQHandler();
 384              		.loc 1 308 9 is_stmt 1
 385 00c4 17030000 		tail	MGECI_IRQHandler
 385      67000300 
 386              	.LVL27:
 387              	.L27:
 309:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     }
 310:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #endif /* MIV_LEGACY_RV32 */
 311:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 312:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     else
 313:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     {
 314:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #ifndef NDEBUG
 315:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /*
 316:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Arguments supplied to this function are mcause, mepc (exception PC) and
 317:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          stack pointer.
 318:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          Based on privileged-isa specification mcause values and meanings are:
 319:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 320:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          0 Instruction address misaligned (mtval/mtval is the address)
 321:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          1 Instruction access fault       (mtval/mtval is the address)
 322:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          2 Illegal instruction            (mtval/mtval contains the
 323:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****                                            offending instruction opcode)
 324:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          3 Breakpoint
 325:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          4 Load address misaligned        (mtval/mtval is the address)
 326:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          5 Load address fault             (mtval/mtval is the address)
 327:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          6 Store/AMO address fault        (mtval/mtval is the address)
 328:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          7 Store/AMO access fault         (mtval/mtval is the address)
 329:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          8 Environment call from U-mode
 330:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          9 Environment call from S-mode
 331:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          A Environment call from M-mode
 332:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          B Instruction page fault
 333:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          C Load page fault                (mtval/mtval is the address)
 334:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          E Store page fault               (mtval/mtval is the address)
 335:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 336:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # Please note: mtval is the newer name for register mbadaddr
 337:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # If you get a compile failure here, use the older name.
 338:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # At this point, both are supported in latest compiler, older compiler
 339:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # versions only support mbadaddr.
 340:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          # See: https://github.com/riscv/riscv-gcc/issues/133
 341:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         */
 342:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 343:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /* interrupt pending */
 344:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mip      = read_csr(mip);
 345:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 346:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* additional info and meaning depends on mcause */
 347:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtval = read_csr(mtval);
 348:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 349:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* trap vector */
 350:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mtvec    = read_csr(mtvec);
 351:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 352:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* temporary, sometimes might hold temporary value of a0 */
 353:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mscratch = read_csr(mscratch);
 354:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 355:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* status contains many smaller fields: */
 356:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mstatus  = read_csr(mstatus);
 357:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 358:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          /* PC value when the exception was taken*/
 359:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****          uintptr_t mmepc  = read_csr(mepc);
 360:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** 
 361:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         /* breakpoint */
 362:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         __asm__("ebreak");
 363:../src/platform/miv_rv32_hal/miv_rv32_hal.c **** #else
 364:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****         _exit(1 + mcause);
 388              		.loc 1 364 9
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
 389              		.loc 1 256 1 is_stmt 0
 390 00cc 130101FF 		addi	sp,sp,-16
 391              		.cfi_def_cfa_offset 16
 392              		.loc 1 364 9
 393 00d0 13051500 		addi	a0,a0,1
 394              	.LVL28:
 256:../src/platform/miv_rv32_hal/miv_rv32_hal.c ****     if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT))
 395              		.loc 1 256 1
 396 00d4 23261100 		sw	ra,12(sp)
 397              		.cfi_offset 1, -4
 398              		.loc 1 364 9
 399 00d8 97000000 		call	_exit
 399      E7800000 
 400              	.LVL29:
 401              		.cfi_endproc
 402              	.LFE21:
 404              		.comm	MRV_LOCAL_IRQn_Type,4,4
 405              		.section	.sbss.g_systick_cmp_value,"aw",@nobits
 406              		.align	3
 407              		.set	.LANCHOR1,. + 0
 410              	g_systick_cmp_value:
 411 0000 00000000 		.zero	8
 411      00000000 
 412              		.section	.sbss.g_systick_increment,"aw",@nobits
 413              		.align	3
 414              		.set	.LANCHOR0,. + 0
 417              	g_systick_increment:
 418 0000 00000000 		.zero	8
 418      00000000 
 419              		.text
 420              	.Letext0:
 421              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 422              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
 423              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
DEFINED SYMBOLS
                            *ABS*:0000000000000000 miv_rv32_hal.c
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:13     .text.MRV_systick_config:0000000000000000 MRV_systick_config
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:17     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:19     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:20     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:21     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:22     .text.MRV_systick_config:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:26     .text.MRV_systick_config:0000000000000010 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:29     .text.MRV_systick_config:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:37     .text.MRV_systick_config:000000000000002c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:44     .text.MRV_systick_config:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:45     .text.MRV_systick_config:0000000000000048 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:48     .text.MRV_systick_config:0000000000000050 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:51     .text.MRV_systick_config:0000000000000058 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:54     .text.MRV_systick_config:000000000000005c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:58     .text.MRV_systick_config:0000000000000068 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:61     .text.MRV_systick_config:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:62     .text.MRV_systick_config:0000000000000078 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:65     .text.MRV_systick_config:0000000000000080 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:69     .text.MRV_systick_config:000000000000008c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:71     .text.MRV_systick_config:0000000000000090 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:73     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:75     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:76     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:77     .text.MRV_systick_config:0000000000000094 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:86     .text.MRV_systick_config:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:88     .text.MRV_systick_config:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:91     .text.MRV_systick_config:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:92     .text.MRV_systick_config:000000000000009c .L0 
../src/platform/miv_rv32_hal/miv_rv32_hal.h:494    .text.MRV_systick_config:000000000000009c .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:102    .text.MRV_systick_config:00000000000000a0 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:103    .text.MRV_systick_config:00000000000000a0 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:104    .text.MRV_systick_config:00000000000000a0 .L0 
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:108    .text.MRV_systick_config:00000000000000a4 .L0 
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C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2189   .debug_str:00000000000005be .LASF45
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2025   .debug_str:0000000000000057 .LASF46
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2103   .debug_str:0000000000000260 .LASF47
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2127   .debug_str:000000000000039c .LASF48
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2035   .debug_str:00000000000000b6 .LASF49
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2113   .debug_str:000000000000028c .LASF50
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2139   .debug_str:00000000000003e6 .LASF51
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2161   .debug_str:0000000000000484 .LASF52
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2181   .debug_str:000000000000058a .LASF53
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2079   .debug_str:00000000000001d7 .LASF54
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2097   .debug_str:0000000000000240 .LASF55
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2117   .debug_str:00000000000002a3 .LASF56
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2013   .debug_str:000000000000000c .LASF57
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2037   .debug_str:00000000000000c2 .LASF58
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2131   .debug_str:00000000000003ae .LASF59
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2159   .debug_str:0000000000000470 .LASF60
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2055   .debug_str:000000000000012c .LASF61
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2077   .debug_str:00000000000001c3 .LASF62
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2011   .debug_str:0000000000000000 .LASF65
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:283    .text.handle_trap:0000000000000000 .LFB21
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:402    .text.handle_trap:00000000000000e0 .LFE21
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2085   .debug_str:0000000000000200 .LASF63
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:1599   .debug_loc:0000000000000000 .LLST3
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2047   .debug_str:0000000000000109 .LASF64
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:1751   .debug_loc:000000000000015a .LLST4
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:298    .text.handle_trap:000000000000001c .LVL16
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:306    .text.handle_trap:000000000000002c .LVL17
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:314    .text.handle_trap:000000000000003c .LVL18
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:322    .text.handle_trap:000000000000004c .LVL19
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:330    .text.handle_trap:000000000000005c .LVL20
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:338    .text.handle_trap:000000000000006c .LVL21
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:346    .text.handle_trap:000000000000007c .LVL22
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:354    .text.handle_trap:000000000000008c .LVL23
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:362    .text.handle_trap:000000000000009c .LVL24
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:370    .text.handle_trap:00000000000000ac .LVL25
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:378    .text.handle_trap:00000000000000bc .LVL26
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:386    .text.handle_trap:00000000000000cc .LVL27
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:400    .text.handle_trap:00000000000000e0 .LVL29
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2171   .debug_str:0000000000000537 .LASF66
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:240    .text.handle_m_soft_interrupt:0000000000000000 .LFB20
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:276    .text.handle_m_soft_interrupt:000000000000002c .LFE20
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:253    .text.handle_m_soft_interrupt:0000000000000010 .LBB14
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:251    .text.handle_m_soft_interrupt:0000000000000010 .LVL14
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2017   .debug_str:0000000000000023 .LASF67
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:134    .text.handle_m_timer_interrupt:0000000000000000 .LFB19
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:233    .text.handle_m_timer_interrupt:00000000000000b0 .LFE19
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2069   .debug_str:0000000000000184 .LASF68
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2067   .debug_str:000000000000017e .LASF69
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:201    .text.handle_m_timer_interrupt:0000000000000080 .LBB11
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:212    .text.handle_m_timer_interrupt:0000000000000088 .LBE11
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:199    .text.handle_m_timer_interrupt:0000000000000080 .LVL11
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2175   .debug_str:0000000000000563 .LASF89
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:14     .text.MRV_systick_config:0000000000000000 .LFB18
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:127    .text.MRV_systick_config:00000000000000cc .LFE18
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2107   .debug_str:0000000000000273 .LASF70
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:1897   .debug_loc:00000000000002a7 .LLST0
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2023   .debug_str:000000000000004f .LASF71
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:1918   .debug_loc:00000000000002cf .LLST1
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2147   .debug_str:0000000000000435 .LASF72
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:1936   .debug_loc:00000000000002fb .LLST2
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:74     .text.MRV_systick_config:0000000000000094 .LBB6
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:85     .text.MRV_systick_config:000000000000009c .LBE6
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:89     .text.MRV_systick_config:000000000000009c .LBB7
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:101    .text.MRV_systick_config:00000000000000a0 .LBE7
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:90     .text.MRV_systick_config:000000000000009c .LBB8
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:100    .text.MRV_systick_config:00000000000000a0 .LBE8
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2041   .debug_str:00000000000000d9 .LASF90
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2191   .debug_str:00000000000005ca .LASF91
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2193   .debug_str:00000000000005dd .LASF73
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2183   .debug_str:0000000000000596 .LASF74
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2027   .debug_str:0000000000000063 .LASF75
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2173   .debug_str:000000000000054f .LASF76
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2031   .debug_str:000000000000008e .LASF77
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2071   .debug_str:0000000000000191 .LASF78
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2137   .debug_str:00000000000003d2 .LASF79
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2061   .debug_str:0000000000000156 .LASF80
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2121   .debug_str:00000000000002ba .LASF81
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2073   .debug_str:00000000000001a5 .LASF82
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2129   .debug_str:00000000000003a8 .LASF83
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2033   .debug_str:00000000000000a2 .LASF84
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:2153   .debug_str:000000000000044f .LASF85
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:286    .text.handle_trap:0000000000000000 .LVL15
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:394    .text.handle_trap:00000000000000d4 .LVL28
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:18     .text.MRV_systick_config:0000000000000000 .LVL0
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:30     .text.MRV_systick_config:000000000000001c .LVL1
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:97     .text.MRV_systick_config:00000000000000a0 .LVL4
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:105    .text.MRV_systick_config:00000000000000a4 .LVL5
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:109    .text.MRV_systick_config:00000000000000a8 .LVL6
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:52     .text.MRV_systick_config:000000000000005c .LVL2
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:120    .text.MRV_systick_config:00000000000000c0 .LVL7
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:425    .debug_info:0000000000000000 .Ldebug_info0
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:138    .text.handle_m_timer_interrupt:0000000000000000 .LBB9
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:141    .text.handle_m_timer_interrupt:0000000000000000 .LBE9
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:147    .text.handle_m_timer_interrupt:0000000000000008 .LBB10
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:157    .text.handle_m_timer_interrupt:0000000000000010 .LBE10
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:260    .text.handle_m_soft_interrupt:0000000000000018 .LBE14
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:264    .text.handle_m_soft_interrupt:000000000000001c .LBB17
C:\Users\I71825\AppData\Local\Temp\cciCVCXh.s:270    .text.handle_m_soft_interrupt:0000000000000024 .LBE17

UNDEFINED SYMBOLS
SysTick_Handler
Software_IRQHandler
External_IRQHandler
MSYS_EI0_IRQHandler
MSYS_EI1_IRQHandler
MSYS_EI2_IRQHandler
MSYS_EI3_IRQHandler
MSYS_EI4_IRQHandler
MSYS_EI5_IRQHandler
OPSRV_IRQHandler
MGEUI_IRQHandler
MGECI_IRQHandler
_exit
