   1              		.file	"hal_irq.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.HAL_enable_interrupts,"ax",@progbits
  10              		.align	2
  11              		.globl	HAL_enable_interrupts
  13              	HAL_enable_interrupts:
  14              	.LFB18:
  15              		.file 1 "../src/platform/hal/hal_irq.c"
   1:../src/platform/hal/hal_irq.c **** /***************************************************************************//**
   2:../src/platform/hal/hal_irq.c ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/hal/hal_irq.c ****  *
   4:../src/platform/hal/hal_irq.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/hal/hal_irq.c ****  * 
   6:../src/platform/hal/hal_irq.c ****  * @file hal_irq.c
   7:../src/platform/hal/hal_irq.c ****  * @author Microchip FPGA Embedded Systems Solutions
   8:../src/platform/hal/hal_irq.c ****  * @brief Legacy interrupt control functions for the Microchip driver library 
   9:../src/platform/hal/hal_irq.c ****  * hardware abstraction layer.
  10:../src/platform/hal/hal_irq.c ****  *
  11:../src/platform/hal/hal_irq.c ****  */
  12:../src/platform/hal/hal_irq.c **** #include "hal.h"
  13:../src/platform/hal/hal_irq.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
  14:../src/platform/hal/hal_irq.c **** 
  15:../src/platform/hal/hal_irq.c **** #ifdef __cplusplus
  16:../src/platform/hal/hal_irq.c **** extern "C" {
  17:../src/platform/hal/hal_irq.c **** #endif
  18:../src/platform/hal/hal_irq.c **** 
  19:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  20:../src/platform/hal/hal_irq.c ****  * 
  21:../src/platform/hal/hal_irq.c ****  */
  22:../src/platform/hal/hal_irq.c **** void HAL_enable_interrupts(void) {
  16              		.loc 1 22 34
  17              		.cfi_startproc
  23:../src/platform/hal/hal_irq.c ****     MRV_enable_interrupts();
  18              		.loc 1 23 5
  19              		.file 2 "C:\\Work_Folder_Akhil\\Q1_2026_2027\\Koushik\\Final\\Release\\mpf_an3694_v2025p1_df\\src\
   1:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   6:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * of this software and associated documentation files (the "Software"), to
   8:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * deal in the Software without restriction, including without limitation the
   9:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
  10:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * sell copies of the Software, and to permit persons to whom the Software is
  11:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * furnished to do so, subject to the following conditions:
  12:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  13:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The above copyright notice and this permission notice shall be included in
  14:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * all copies or substantial portions of the Software.
  15:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  16:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * IN THE SOFTWARE.
  23:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
  24:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
  25:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
  26:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
  27:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  28:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  29:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  30:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
  31:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
  32:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  33:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
  34:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
  35:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
  36:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  37:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
  38:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "fpga_design_config/fpga_design_config.h"
  39:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
  40:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
  41:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
  42:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  43:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
  44:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
  45:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
  46:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  48:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Return value from External IRQ handler. This will be used to disable the
  49:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * External interrupt.
  50:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  51:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
  52:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
  53:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  54:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  55:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * System tick handler. This handler function gets called when the Machine
  56:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * timer interrupt asserts. An implementation of this function should be
  57:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * provided by the application to implement the application specific machine
  58:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * timer interrupt handling. If application does not provide such implementation
  59:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the weakly linked handler stub function implemented in riscv_hal_stubs.c gets
  60:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * linked.
  61:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  62:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** void SysTick_Handler(void);
  63:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  64:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  65:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * System timer tick configuration.
  66:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Configures the machine timer to generate a system tick interrupt at regular
  67:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * intervals.
  68:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Takes the number of system clock ticks between interrupts.
  69:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  70:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Though this function can take any valid ticks value as parameter, we expect
  71:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * that, for all practical purposes, a small tick value (to generate periodic 
  72:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * interrupts every few miliseconds) will be passed. If you need to generate
  73:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * periodic events in the range of seconds or more, you may use the SysTick_Handler()
  74:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * to further count the number of interrupts and hence the larger time intervals.
  75:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  76:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Returns 0 if successful.
  77:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Returns 1 if the interrupt interval cannot be achieved.
  78:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  79:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** uint32_t MRV_systick_config(uint64_t ticks);
  80:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  81:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
  82:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  83:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
  84:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
  85:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
  86:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
  87:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
  88:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
  89:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  90:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  91:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
  92:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  93:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
  94:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  95:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  96:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
  97:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  98:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* OPSRV stands for "Offload Processor Subsystem for RISC-V" (OPSRV) on the
  99:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * MIV_RV32 IP core. Please see the handbook for more details. */
 100:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 101:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* TCM ECC correctable error irq enable mask value */
 102:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ            0x01u
 103:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 104:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* TCMECC uncorrectable error irq enable */
 105:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ           0x02u
 106:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 107:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* AXI write response error irq enable */
 108:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ           0x10u
 109:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 110:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_BASE_ADDR                 0x00006000UL
 111:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 112:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** typedef struct
 113:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 114:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t cfg;          	/*Parity is not being supported by MIV_RV32 v3.0*/
 115:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t reserved0[3];
 116:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t irq_en;           /*offset 0x10*/
 117:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t irq_pend;
 118:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t reserved1[2];
 119:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t soft_reg;         /*offset 0x20*/
 120:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } OPSRV_Type;
 121:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 122:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV                           ((OPSRV_Type *)OPSRV_BASE_ADDR)
 123:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 124:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 125:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 126:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 127:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 128:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 129:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 130:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 131:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 132:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* On MIV_RV32IMC v2.0 and v2.1 MTIME_PRESCALER is not defined and using this
 133:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * definition will result in crash. For those core use the definition as below
 134:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * #define MTIME_PRESCALER              100u
 135:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 136:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 137:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 138:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 139:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 140:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 141:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 142:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 143:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 144:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 145:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 146:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* These definitions are provided for convenient identification of the interrupts
 147:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * in the MIE/MIP registers.
 148:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Apart from the standard software, timer and external interrupts, the names
 149:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * of the additional interrupts correspond to the names as used in the MIV_RV32
 150:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * handbook. Please refer the MIV_RV32 handbook for more details.
 151:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * */
 152:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 153:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 154:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 155:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 156:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*==============================================================================
 157:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Interrupt numbers:
 158:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * This enum represents the interrupt enable bits in the MIE register.
 159:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 160:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 161:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 162:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 163:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 164:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 165:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE*/
 166:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 167:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 168:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 169:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE*/
 170:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 171:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 172:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 173:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE*/
 174:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 175:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 176:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 177:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 178:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE*/
 179:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE*/
 180:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 181:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 182:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 183:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 184:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),
 185:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),
 186:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_EIE0*/
 187:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_EIE1*/
 188:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_EIE2*/
 189:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_EIE3*/
 190:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_EIE4*/
 191:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_EIE5*/
 192:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u)         /*OPSRV_IRQ_IE*/
 193:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 194:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 195:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 196:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 197:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 198:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 199:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 200:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 201:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 202:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 203:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 204:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 205:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn           MIE_30_IRQn
 206:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 207:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 208:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Enable OPSRV interrupt. Parameter takes logical OR of following values
 209:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 210:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 211:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 212:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 213:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_enable_irq(uint32_t irq_mask)
 214:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 215:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_en = irq_mask;
 216:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 217:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 218:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 219:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Disable OPSRV interrupt. Parameter takes logical OR of following values
 220:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 221:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 222:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 223:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 224:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_disable_irq(uint32_t irq_mask)
 225:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 226:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_en &= ~irq_mask;
 227:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 228:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 229:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 230:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear OPSRV interrupt. Parameter takes logical OR of following values
 231:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 232:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 233:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 234:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 235:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_clear_irq(uint32_t irq_mask)
 236:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 237:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_pend |= irq_mask;
 238:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 239:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 240:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 241:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_is_gpr_ded() returns the core_gpr_ded_reset_reg bit value.
 242:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * When ECC is enabled, the core_gpr_ded_reset_reg is set when the core was
 243:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * reset due to GPR DED error.
 244:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 245:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline uint32_t MRV32_is_gpr_ded(void)
 246:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 247:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     return((OPSRV->soft_reg & 0x04u) >> 0x02u);
 248:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 249:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 250:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 251:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_clear_gpr_ded() can be used to clear the
 252:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * core_gpr_ded_reset_reg bit. When ECC is enabled, the core_gpr_ded_reset_reg
 253:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * is set when the core was previously reset due to GPR DED error.
 254:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 255:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ded(void)
 256:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 257:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x04u;
 258:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 259:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 260:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 261:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When ECC is enabled for the GPRs and if that data has a single bit error then
 262:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data coming out of the ECC block will be corrected and will not have the
 263:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error but the data source will still have the error.
 264:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The ECC block does not write back corrected data to memory.
 265:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Therefore, if data has a single bit error, then the corrected data should be 
 266:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   written back to prevent the single bit error from becoming a double bit error.
 267:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() can be used for that.
 268:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 269:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Clear the pending interrupt bit after this using MRV32_mgeci_clear_irq()
 270:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   function to complete the ECC error handling.
 271:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 272:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 273:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 274:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 275:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 276:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 277:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 278:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 279:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 280:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 281:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 282:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 283:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 284:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 285:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 286:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 287:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 288:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 289:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 290:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 291:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 292:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 293:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 294:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 295:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 296:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 297:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 298:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 299:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 300:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 301:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 302:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 303:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 304:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 305:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 306:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 307:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 308:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 309:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 310:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 311:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 312:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 313:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 314:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 315:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 316:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 317:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 318:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 319:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 320:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 321:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 322:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 323:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 324:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 325:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 326:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 327:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 328:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 329:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 330:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 331:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 332:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 333:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 334:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 335:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 336:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 337:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 338:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 339:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 340:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 341:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 342:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 343:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 344:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 345:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 346:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 347:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 348:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 349:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 350:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 351:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 352:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 353:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 354:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 355:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 356:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 357:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 358:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 359:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 360:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 361:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 362:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 363:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 364:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 365:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 366:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 367:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 368:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 369:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 370:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 371:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 372:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 373:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 374:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 375:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 376:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 377:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 378:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_enable_parity_check() is used to enable parity check on
 379:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the TCM and it's interface transactions. This feature is not available on
 380:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * MIV_RV32 v3.0.100 soft processor core.
 381:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 382:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_enable_parity_check(void)
 383:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 384:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->cfg |= 0x01u;
 385:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 386:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 387:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 388:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_disable_parity_check() is used to disable parity check on
 389:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the TCM and it's interface transactions.
 390:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 391:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_disable_parity_check(void)
 392:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 393:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->cfg &= ~0x01u;
 394:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 395:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 396:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 397:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_cpu_soft_reset() is used to cause a soft cpu reset on
 398:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the MIV_RV32 soft processor core.
 399:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 400:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_cpu_soft_reset(void)
 401:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 402:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x01u;
 403:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 404:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 405:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 406:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear GPR ECC Uncorrectable interrupt. MGEUI interrupt is available only when
 407:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 408:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 409:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(uint32_t irq_mask)
 410:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 411:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 412:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 413:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 414:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 415:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear GPR ECC correctable interrupt. MGECI interrupt is available only when
 416:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 417:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 418:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(uint32_t irq_mask)
 419:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 420:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 421:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 422:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 423:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 424:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Enable interrupts.
 425:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 426:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is enabled.
 427:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 428:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  MRV_enable_local_irq(MRV32_SOFT_IRQn  |
 429:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_TIMER_IRQn |
 430:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_EXT_IRQn   |
 431:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_MSYS_EIE0_IRQn |
 432:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_MSYS_OPSRV_IRQn);
 433:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 434:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 435:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 436:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
 437:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 438:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 439:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 440:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Disable interrupts.
 441:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 442:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is disabled.
 443:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 444:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_disable_local_irq(MRV32_SOFT_IRQn  |
 445:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_TIMER_IRQn |
 446:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_EXT_IRQn   |
 447:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 448:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_OPSRV_IRQn);
 449:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 450:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 451:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 452:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mie, mask);
 453:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 454:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 455:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif /* MIV_LEGACY_RV32 */
 456:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 457:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 458:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV_raise_soft_irq() raises a synchronous software interrupt
 459:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * by writing into the MSIP register.
 460:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 461:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_raise_soft_irq(void)
 462:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 463:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, MIP_MSIP);       /* Enable software interrupt bit */
 464:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 465:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 466:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     /* You need to make sure that the global interrupt is enabled */
 467:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MSIP = 0x01;   /* raise soft interrupt */
 468:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 469:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     /* Raise soft IRQ on MIV_RV32 processor */
 470:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg |= (1u << 1u);
 471:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 472:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 473:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 474:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 475:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV_clear_soft_irq() clears a synchronous software interrupt
 476:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * by clearing the MSIP register.
 477:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 478:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_clear_soft_irq(void)
 479:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 480:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
 481:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MSIP = 0x00u;   /* clear soft interrupt */
 482:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 483:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     /* Clear soft IRQ on MIV_RV32 processor */
 484:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg &= ~(1u << 1u);
 485:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 486:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 487:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 488:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 489:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV_enable_interrupts() enables all interrupts setting the
 490:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * machine mode interrupt enable bit in MSTATUS register.
 491:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 492:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_interrupts(void)
 493:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 494:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mstatus, MSTATUS_MIE);
  20              		.loc 2 494 5
  21              	.LBB5:
  22              	.LBB6:
  23              		.loc 2 494 5
  24              		.loc 2 494 5
  25              	 #APP
  26              	# 494 "C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsol
   0              	
  27              		csrrs a5, mstatus, 8
  28              	# 0 "" 2
  29              	.LVL0:
  30              		.loc 2 494 5
  31              	 #NO_APP
  32              	.LBE6:
  33              	.LBE5:
  24:../src/platform/hal/hal_irq.c **** }
  34              		.loc 1 24 1 is_stmt 0
  35 0004 67800000 		ret
  36              		.cfi_endproc
  37              	.LFE18:
  39              		.section	.text.HAL_disable_interrupts,"ax",@progbits
  40              		.align	2
  41              		.globl	HAL_disable_interrupts
  43              	HAL_disable_interrupts:
  44              	.LFB19:
  25:../src/platform/hal/hal_irq.c **** 
  26:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  27:../src/platform/hal/hal_irq.c ****  * 
  28:../src/platform/hal/hal_irq.c ****  */
  29:../src/platform/hal/hal_irq.c **** psr_t HAL_disable_interrupts(void) {
  45              		.loc 1 29 36 is_stmt 1
  46              		.cfi_startproc
  30:../src/platform/hal/hal_irq.c ****     psr_t psr;
  47              		.loc 1 30 5
  31:../src/platform/hal/hal_irq.c ****     psr = read_csr(mstatus);
  48              		.loc 1 31 5
  49              	.LBB12:
  50              		.loc 1 31 11
  51              		.loc 1 31 11
  52              	 #APP
  53              	# 31 "../src/platform/hal/hal_irq.c" 1
  32              	    MRV_disable_interrupts();
  54              		csrr a0, mstatus
  55              	# 0 "" 2
  56              	.LVL1:
  31:../src/platform/hal/hal_irq.c ****     psr = read_csr(mstatus);
  57              		.loc 1 31 11
  58              	 #NO_APP
  59              	.LBE12:
  60              		.loc 1 32 5
 495:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 496:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 497:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 498:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV_disable_interrupts() disables all interrupts clearing the
 499:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * machine mode interrupt enable bit in MSTATUS register.
 500:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 501:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_disable_interrupts(void)
 502:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 503:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MPIE);
  61              		.loc 2 503 5
  62              	.LBB13:
  63              	.LBB14:
  64              		.loc 2 503 5
  65              		.loc 2 503 5
  66 0004 93070008 		li	a5,128
  67              	 #APP
  68              	# 503 "C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsol
  69              		csrrc a5, mstatus, a5
  70              	# 0 "" 2
  71              	.LVL2:
  72              		.loc 2 503 5
  73              	 #NO_APP
  74              	.LBE14:
  75              	.LBE13:
 504:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mstatus, MSTATUS_MIE);
  76              		.loc 2 504 5
  77              	.LBB16:
  78              	.LBB15:
  79              		.loc 2 504 5
  80              		.loc 2 504 5
  81              	 #APP
  82              	# 504 "C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsol
  83              		csrrc a5, mstatus, 8
  84              	# 0 "" 2
  85              	.LVL3:
  86              		.loc 2 504 5
  87              	 #NO_APP
  88              	.LBE15:
  89              	.LBE16:
  33:../src/platform/hal/hal_irq.c ****     return(psr);
  90              		.loc 1 33 5
  34:../src/platform/hal/hal_irq.c **** }
  91              		.loc 1 34 1 is_stmt 0
  92 0010 67800000 		ret
  93              		.cfi_endproc
  94              	.LFE19:
  96              		.section	.text.HAL_restore_interrupts,"ax",@progbits
  97              		.align	2
  98              		.globl	HAL_restore_interrupts
 100              	HAL_restore_interrupts:
 101              	.LFB20:
  35:../src/platform/hal/hal_irq.c **** 
  36:../src/platform/hal/hal_irq.c **** /*------------------------------------------------------------------------------
  37:../src/platform/hal/hal_irq.c ****  * 
  38:../src/platform/hal/hal_irq.c ****  */
  39:../src/platform/hal/hal_irq.c **** void HAL_restore_interrupts(psr_t saved_psr) {
 102              		.loc 1 39 46 is_stmt 1
 103              		.cfi_startproc
 104              	.LVL4:
  40:../src/platform/hal/hal_irq.c ****     write_csr(mstatus, saved_psr);
 105              		.loc 1 40 5
 106              	 #APP
 107              	# 40 "../src/platform/hal/hal_irq.c" 1
  41              	}
 108              		csrw mstatus, a0
 109              	# 0 "" 2
 110              		.loc 1 41 1 is_stmt 0
 111              	 #NO_APP
 112 0004 67800000 		ret
 113              		.cfi_endproc
 114              	.LFE20:
 116              		.comm	MRV_LOCAL_IRQn_Type,4,4
 117              		.text
 118              	.Letext0:
 119              		.file 3 "../src/platform/hal/cpu_types.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 hal_irq.c
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:13     .text.HAL_enable_interrupts:0000000000000000 HAL_enable_interrupts
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:17     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:18     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:20     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:23     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:24     .text.HAL_enable_interrupts:0000000000000000 .L0 
C:Work_Folder_AkhilQ1_2026_2027KoushikFinalReleasempf_an3694_v2025p1_dfsrcsoftconsole2022p2mpf_an3694_v2025p1_dfsrcplatform/miv_rv32_hal/miv_rv32_hal.h:494    .text.HAL_enable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:34     .text.HAL_enable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:35     .text.HAL_enable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:36     .text.HAL_enable_interrupts:0000000000000008 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:43     .text.HAL_disable_interrupts:0000000000000000 HAL_disable_interrupts
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:46     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:47     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:48     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:50     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:51     .text.HAL_disable_interrupts:0000000000000000 .L0 
../src/platform/hal/hal_irq.c:31     .text.HAL_disable_interrupts:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:60     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:61     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:64     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:65     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:66     .text.HAL_disable_interrupts:0000000000000004 .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:76     .text.HAL_disable_interrupts:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:79     .text.HAL_disable_interrupts:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccTcyAmB.s:80     .text.HAL_disable_interrupts:000000000000000c .L0 
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NO UNDEFINED SYMBOLS
