   1              		.file	"i2c_interrupt.c"
   2              		.option nopic
   3              		.attribute arch, "rv32i2p0"
   4              		.attribute unaligned_access, 0
   5              		.attribute stack_align, 16
   6              		.text
   7              	.Ltext0:
   8              		.cfi_sections	.debug_frame
   9              		.section	.text.I2C_enable_irq,"ax",@progbits
  10              		.align	2
  11              		.globl	I2C_enable_irq
  13              	I2C_enable_irq:
  14              	.LFB18:
  15              		.file 1 "../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c"
   1:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** /*******************************************************************************
   2:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * Copyright 2009-2023 Microchip FPGA Embedded Systems Solutions.
   3:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  *
   4:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * SPDX-License-Identifier: MIT
   5:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  *
   6:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * CoreI2C driver interrupt control.
   7:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  *
   8:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  */
   9:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** #include "core_i2c.h"
  10:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** #include "miv_rv32_hal/miv_rv32_hal.h"
  11:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  12:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** //extern i2c_instance_t g_i2c_instance_hdmi;
  13:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** extern i2c_instance_t g_i2c_instance_cam1;
  14:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  15:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** /*------------------------------------------------------------------------------
  16:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * This function must be modified to enable interrupts generated from the
  17:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * CoreI2C instance identified as parameter.
  18:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  */
  19:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** void I2C_enable_irq( i2c_instance_t * this_i2c )
  20:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** {
  16              		.loc 1 20 1
  17              		.cfi_startproc
  18              	.LVL0:
  21:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     /*if(this_i2c == &g_i2c_instance_hdmi)
  22:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     {
  23:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****         MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
  24:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     }*/
  25:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  26:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     if(this_i2c == &g_i2c_instance_cam1)
  19              		.loc 1 26 5
  20              		.loc 1 26 7 is_stmt 0
  21 0000 97070000 		lla	a5,g_i2c_instance_cam1
  21      93870700 
  22 0008 6396A700 		bne	a5,a0,.L1
  27:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     {
  28:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****         MRV_enable_local_irq(MRV32_MSYS_EIE1_IRQn);
  23              		.loc 1 28 9 is_stmt 1
  24              	.LVL1:
  25              		.file 2 "C:\\Work_Folder_Akhil\\Q1_2026_2027\\Koushik\\Final\\Release\\mpf_an3694_v2025p1_df\\src\
   1:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*******************************************************************************
   2:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Copyright 2019-2022 Microchip FPGA Embedded Systems Solutions.
   3:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   4:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * SPDX-License-Identifier: MIT
   5:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
   6:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * of this software and associated documentation files (the "Software"), to
   8:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * deal in the Software without restriction, including without limitation the
   9:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
  10:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * sell copies of the Software, and to permit persons to whom the Software is
  11:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * furnished to do so, subject to the following conditions:
  12:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  13:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The above copyright notice and this permission notice shall be included in
  14:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * all copies or substantial portions of the Software.
  15:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  16:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  19:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * IN THE SOFTWARE.
  23:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * 
  24:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @file miv_rv32_hal.h
  25:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @author Microchip FPGA Embedded Systems Solutions
  26:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * @brief Hardware Abstraction Layer functions for Mi-V soft processors
  27:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  28:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  29:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  30:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef RISCV_HAL_H
  31:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define RISCV_HAL_H
  32:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  33:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_regs.h"
  34:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_plic.h"
  35:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "miv_rv32_assert.h"
  36:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  37:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef LEGACY_DIR_STRUCTURE
  38:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "fpga_design_config/fpga_design_config.h"
  39:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
  40:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #include "hw_platform.h"
  41:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*LEGACY_DIR_STRUCTURE*/
  42:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  43:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef __cplusplus
  44:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** extern "C" {
  45:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
  46:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  47:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  48:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Return value from External IRQ handler. This will be used to disable the
  49:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * External interrupt.
  50:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  51:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_KEEP_ENABLED                0U
  52:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define EXT_IRQ_DISABLE                     1U
  53:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  54:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  55:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * System tick handler. This handler function gets called when the Machine
  56:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * timer interrupt asserts. An implementation of this function should be
  57:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * provided by the application to implement the application specific machine
  58:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * timer interrupt handling. If application does not provide such implementation
  59:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the weakly linked handler stub function implemented in riscv_hal_stubs.c gets
  60:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * linked.
  61:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  62:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** void SysTick_Handler(void);
  63:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  64:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
  65:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * System timer tick configuration.
  66:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Configures the machine timer to generate a system tick interrupt at regular
  67:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * intervals.
  68:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Takes the number of system clock ticks between interrupts.
  69:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  70:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Though this function can take any valid ticks value as parameter, we expect
  71:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * that, for all practical purposes, a small tick value (to generate periodic 
  72:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * interrupts every few miliseconds) will be passed. If you need to generate
  73:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * periodic events in the range of seconds or more, you may use the SysTick_Handler()
  74:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * to further count the number of interrupts and hence the larger time intervals.
  75:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  *
  76:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Returns 0 if successful.
  77:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Returns 1 if the interrupt interval cannot be achieved.
  78:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
  79:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** uint32_t MRV_systick_config(uint64_t ticks);
  80:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  81:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_DELTA                     5
  82:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  83:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifdef MIV_LEGACY_RV32
  84:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MSIP                            (*(uint32_t*)0x44000000UL)
  85:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(uint32_t*)0x44004000UL)
  86:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(uint32_t*)0x44004004UL)
  87:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(uint32_t*)0x4400BFF8UL)
  88:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(uint32_t*)0x4400BFFCUL)
  89:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  90:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  91:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x44000000UL
  92:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  93:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
  94:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  95:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* To maintain backward compatibility with FreeRTOS config code */
  96:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define PRCI_BASE                       0x02000000UL
  97:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
  98:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* OPSRV stands for "Offload Processor Subsystem for RISC-V" (OPSRV) on the
  99:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * MIV_RV32 IP core. Please see the handbook for more details. */
 100:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 101:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* TCM ECC correctable error irq enable mask value */
 102:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_CE_IRQ            0x01u
 103:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 104:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* TCMECC uncorrectable error irq enable */
 105:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_TCM_ECC_UCE_IRQ           0x02u
 106:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 107:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* AXI write response error irq enable */
 108:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_AXI_WR_RESP_IRQ           0x10u
 109:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 110:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV_BASE_ADDR                 0x00006000UL
 111:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 112:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** typedef struct
 113:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 114:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t cfg;          	/*Parity is not being supported by MIV_RV32 v3.0*/
 115:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t reserved0[3];
 116:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t irq_en;           /*offset 0x10*/
 117:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t irq_pend;
 118:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t reserved1[2];
 119:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     volatile uint32_t soft_reg;         /*offset 0x20*/
 120:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } OPSRV_Type;
 121:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 122:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define OPSRV                           ((OPSRV_Type *)OPSRV_BASE_ADDR)
 123:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 124:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMECMP
 125:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (*(volatile uint32_t*)0x02004000UL)
 126:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (*(volatile uint32_t*)0x02004004UL)
 127:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 128:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMP                        (0u)
 129:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMECMPH                       (0u)
 130:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif
 131:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 132:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* On MIV_RV32IMC v2.0 and v2.1 MTIME_PRESCALER is not defined and using this
 133:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * definition will result in crash. For those core use the definition as below
 134:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * #define MTIME_PRESCALER              100u
 135:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 136:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME_PRESCALER                 (*(volatile uint32_t*)0x02005000UL)
 137:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 138:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #ifndef MIV_RV32_EXT_TIMER
 139:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (*(volatile uint32_t*)0x0200BFF8UL)
 140:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (*(volatile uint32_t*)0x0200BFFCUL)
 141:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #else
 142:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIME                           (0u)
 143:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MTIMEH                          (0u)
 144:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #endif  /*MIV_RV32_EXT_TIMER*/
 145:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 146:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /* These definitions are provided for convenient identification of the interrupts
 147:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * in the MIE/MIP registers.
 148:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Apart from the standard software, timer and external interrupts, the names
 149:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * of the additional interrupts correspond to the names as used in the MIV_RV32
 150:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * handbook. Please refer the MIV_RV32 handbook for more details.
 151:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * */
 152:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_SOFT_IRQn                 MIE_3_IRQn
 153:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_TIMER_IRQn                MIE_7_IRQn
 154:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_EXT_IRQn                  MIE_11_IRQn
 155:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 156:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /*==============================================================================
 157:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Interrupt numbers:
 158:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * This enum represents the interrupt enable bits in the MIE register.
 159:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 160:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** enum
 161:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 162:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_0_IRQn  =  (0x01u),
 163:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_1_IRQn  =  (0x01u<<1u),
 164:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_2_IRQn  =  (0x01u<<2u),
 165:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_3_IRQn  =  (0x01u<<3u),         /*MSIE*/
 166:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_4_IRQn  =  (0x01u<<4u),
 167:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_5_IRQn  =  (0x01u<<5u),
 168:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_6_IRQn  =  (0x01u<<6u),
 169:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_7_IRQn  =  (0x01u<<7u),         /*MTIE*/
 170:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_8_IRQn  =  (0x01u<<8u),
 171:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_9_IRQn  =  (0x01u<<9u),
 172:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_10_IRQn =  (0x01u<<10u),
 173:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_11_IRQn =  (0x01u<<11u),        /*MEIE*/
 174:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_12_IRQn =  (0x01u<<12u),
 175:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_13_IRQn =  (0x01u<<13u),
 176:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_14_IRQn =  (0x01u<<14u),
 177:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_15_IRQn =  (0x01u<<15u),
 178:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_16_IRQn =  (0x01u<<16u),        /*MGEUIE*/
 179:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_17_IRQn =  (0x01u<<17u),        /*MGECIE*/
 180:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_18_IRQn =  (0x01u<<18u),
 181:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_19_IRQn =  (0x01u<<19u),
 182:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_20_IRQn =  (0x01u<<20u),
 183:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_21_IRQn =  (0x01u<<21u),
 184:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_22_IRQn =  (0x01u<<22u),
 185:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_23_IRQn =  (0x01u<<23u),
 186:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_24_IRQn =  (0x01u<<24u),        /*MSYS_EIE0*/
 187:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_25_IRQn =  (0x01u<<25u),        /*MSYS_EIE1*/
 188:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_26_IRQn =  (0x01u<<26u),        /*MSYS_EIE2*/
 189:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_27_IRQn =  (0x01u<<27u),        /*MSYS_EIE3*/
 190:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_28_IRQn =  (0x01u<<28u),        /*MSYS_EIE4*/
 191:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_29_IRQn =  (0x01u<<29u),        /*MSYS_EIE5*/
 192:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     MIE_30_IRQn =  (0x01u<<30u)         /*OPSRV_IRQ_IE*/
 193:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 194:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** } MRV_LOCAL_IRQn_Type;
 195:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 196:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 197:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGEUIE_IRQn               MIE_16_IRQn
 198:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MGECIE_IRQn               MIE_17_IRQn
 199:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE0_IRQn            MIE_24_IRQn
 200:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE1_IRQn            MIE_25_IRQn
 201:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE2_IRQn            MIE_26_IRQn
 202:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE3_IRQn            MIE_27_IRQn
 203:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE4_IRQn            MIE_28_IRQn
 204:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_EIE5_IRQn            MIE_29_IRQn
 205:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** #define MRV32_MSYS_OPSRV_IRQn           MIE_30_IRQn
 206:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 207:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 208:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Enable OPSRV interrupt. Parameter takes logical OR of following values
 209:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 210:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 211:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 212:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 213:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_enable_irq(uint32_t irq_mask)
 214:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 215:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_en = irq_mask;
 216:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 217:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 218:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 219:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Disable OPSRV interrupt. Parameter takes logical OR of following values
 220:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 221:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 222:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 223:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 224:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_disable_irq(uint32_t irq_mask)
 225:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 226:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_en &= ~irq_mask;
 227:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 228:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 229:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 230:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear OPSRV interrupt. Parameter takes logical OR of following values
 231:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_CE_IRQ                    0x01u
 232:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_TCM_ECC_UCE_IRQ                   0x02u
 233:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     #define OPSRV_AXI_WR_RESP_IRQ                   0x10u
 234:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 235:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_opsrv_clear_irq(uint32_t irq_mask)
 236:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 237:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->irq_pend |= irq_mask;
 238:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 239:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 240:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 241:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_is_gpr_ded() returns the core_gpr_ded_reset_reg bit value.
 242:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * When ECC is enabled, the core_gpr_ded_reset_reg is set when the core was
 243:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * reset due to GPR DED error.
 244:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 245:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline uint32_t MRV32_is_gpr_ded(void)
 246:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 247:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     return((OPSRV->soft_reg & 0x04u) >> 0x02u);
 248:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 249:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 250:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 251:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_clear_gpr_ded() can be used to clear the
 252:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * core_gpr_ded_reset_reg bit. When ECC is enabled, the core_gpr_ded_reset_reg
 253:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * is set when the core was previously reset due to GPR DED error.
 254:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 255:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ded(void)
 256:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 257:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x04u;
 258:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 259:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 260:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 261:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   When ECC is enabled for the GPRs and if that data has a single bit error then
 262:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   the data coming out of the ECC block will be corrected and will not have the
 263:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   error but the data source will still have the error.
 264:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The ECC block does not write back corrected data to memory.
 265:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Therefore, if data has a single bit error, then the corrected data should be 
 266:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   written back to prevent the single bit error from becoming a double bit error.
 267:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   The MRV32_clear_gpr_ecc_errors() can be used for that.
 268:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 269:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   Clear the pending interrupt bit after this using MRV32_mgeci_clear_irq()
 270:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   function to complete the ECC error handling.
 271:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 272:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_clear_gpr_ecc_errors(void)
 273:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 274:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     uint32_t temp;
 275:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 276:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 277:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "sw x31, %0"
 278:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"=m" (temp));
 279:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 280:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ volatile (
 281:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x1;"
 282:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x1, x31;"
 283:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 284:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x2;"
 285:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x2, x31;"
 286:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 287:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x3;"
 288:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x3, x31;"
 289:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 290:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x4;"
 291:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x4, x31;"
 292:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 293:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x5;"
 294:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x5, x31;"
 295:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 296:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x6;"
 297:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x6, x31;"
 298:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 299:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x7;"
 300:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x7, x31;"
 301:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 302:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x8;"
 303:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x8, x31;"
 304:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 305:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x9;"
 306:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x9, x31;"
 307:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 308:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x10;"
 309:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x10, x31;"
 310:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 311:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x11;"
 312:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x11, x31;"
 313:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 314:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x12;"
 315:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x12, x31;"
 316:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 317:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x13;"
 318:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x13, x31;"
 319:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 320:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x14;"
 321:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x14, x31;"
 322:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 323:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x15;"
 324:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x15, x31;"
 325:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 326:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x16;"
 327:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x16, x31;"
 328:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 329:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x17;"
 330:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x17, x31;"
 331:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 332:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x18;"
 333:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x18, x31;"
 334:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 335:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x19;"
 336:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x19, x31;"
 337:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 338:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x20;"
 339:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x20, x31;"
 340:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 341:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x21;"
 342:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x21, x31;"
 343:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 344:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x22;"
 345:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x22, x31;"
 346:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 347:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x23;"
 348:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x23, x31;"
 349:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 350:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x24;"
 351:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x24, x31;"
 352:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 353:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x25;"
 354:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x25, x31;"
 355:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 356:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x26;"
 357:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x26, x31;"
 358:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 359:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x27;"
 360:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x27, x31;"
 361:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 362:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x28;"
 363:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x28, x31;"
 364:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 365:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x29;"
 366:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x29, x31;"
 367:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 368:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x31, x30;"
 369:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "mv x30, x31;");
 370:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 371:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     __asm__ __volatile__ (
 372:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             "lw x31, %0;"
 373:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :
 374:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****             :"m" (temp));
 375:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 376:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 377:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 378:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_enable_parity_check() is used to enable parity check on
 379:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the TCM and it's interface transactions. This feature is not available on
 380:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * MIV_RV32 v3.0.100 soft processor core.
 381:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 382:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_enable_parity_check(void)
 383:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 384:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->cfg |= 0x01u;
 385:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 386:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 387:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 388:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_disable_parity_check() is used to disable parity check on
 389:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the TCM and it's interface transactions.
 390:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 391:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_disable_parity_check(void)
 392:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 393:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->cfg &= ~0x01u;
 394:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 395:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 396:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 397:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * The function MRV32_cpu_soft_reset() is used to cause a soft cpu reset on
 398:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * the MIV_RV32 soft processor core.
 399:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 400:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_cpu_soft_reset(void)
 401:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 402:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     OPSRV->soft_reg &= ~0x01u;
 403:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 404:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 405:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 406:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear GPR ECC Uncorrectable interrupt. MGEUI interrupt is available only when
 407:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 408:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 409:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeui_clear_irq(uint32_t irq_mask)
 410:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 411:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGEUIE_IRQn);
 412:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 413:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 414:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 415:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     Clear GPR ECC correctable interrupt. MGECI interrupt is available only when
 416:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     ECC is enabled in MIV_RV32 IP configurator.
 417:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 418:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV32_mgeci_clear_irq(uint32_t irq_mask)
 419:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 420:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mip, MRV32_MGECIE_IRQn);
 421:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 422:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 423:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 424:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Enable interrupts.
 425:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 426:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is enabled.
 427:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 428:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  MRV_enable_local_irq(MRV32_SOFT_IRQn  |
 429:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_TIMER_IRQn |
 430:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_EXT_IRQn   |
 431:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_MSYS_EIE0_IRQn |
 432:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                       MRV32_MSYS_OPSRV_IRQn);
 433:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 434:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_enable_local_irq(uint32_t mask)
 435:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 436:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     set_csr(mie, mask);
  26              		.loc 2 436 5
  27              	.LBB8:
  28              	.LBB9:
  29              		.loc 2 436 5
  30              		.loc 2 436 5
  31 000c B7070002 		li	a5,33554432
  32              	 #APP
  33              	# 436 "C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsol
   0              	
  34              		csrrs a5, mie, a5
  35              	# 0 "" 2
  36              	.LVL2:
  37              		.loc 2 436 5
  38              	 #NO_APP
  39              	.L1:
  40              	.LBE9:
  41              	.LBE8:
  29:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     }
  30:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** }
  42              		.loc 1 30 1 is_stmt 0
  43 0014 67800000 		ret
  44              		.cfi_endproc
  45              	.LFE18:
  47              		.section	.text.I2C_disable_irq,"ax",@progbits
  48              		.align	2
  49              		.globl	I2C_disable_irq
  51              	I2C_disable_irq:
  52              	.LFB19:
  31:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  32:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** /*------------------------------------------------------------------------------
  33:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * This function must be modified to disable interrupts generated from the
  34:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  * CoreI2C instance identified as parameter.
  35:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****  */
  36:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** void I2C_disable_irq( i2c_instance_t * this_i2c )
  37:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** {
  53              		.loc 1 37 1 is_stmt 1
  54              		.cfi_startproc
  55              	.LVL3:
  38:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     /*if(this_i2c == &g_i2c_instance_hdmi)
  39:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     {
  40:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****         MRV_disable_local_irq(MRV32_MSYS_EIE0_IRQn);
  41:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     }*/
  42:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  43:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     if(this_i2c == &g_i2c_instance_cam1)
  56              		.loc 1 43 5
  57              		.loc 1 43 7 is_stmt 0
  58 0000 97070000 		lla	a5,g_i2c_instance_cam1
  58      93870700 
  59 0008 6396A700 		bne	a5,a0,.L3
  44:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     {
  45:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****         MRV_disable_local_irq(MRV32_MSYS_EIE1_IRQn);
  60              		.loc 1 45 9 is_stmt 1
  61              	.LVL4:
 437:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** }
 438:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 439:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** /***************************************************************************//**
 440:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  * Disable interrupts.
 441:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  This function takes a mask value as input. For each set bit in the mask value,
 442:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  corresponding interrupt bit in the MIE register is disabled.
 443:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** 
 444:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****   MRV_disable_local_irq(MRV32_SOFT_IRQn  |
 445:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_TIMER_IRQn |
 446:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_EXT_IRQn   |
 447:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_EIE0_IRQn |
 448:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****                         MRV32_MSYS_OPSRV_IRQn);
 449:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****  */
 450:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** static inline void MRV_disable_local_irq(uint32_t mask)
 451:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h **** {
 452:C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsole2022p2\mpf_an3694_v2025p1_df\src\platform/miv_rv32_hal\miv_rv32_hal.h ****     clear_csr(mie, mask);
  62              		.loc 2 452 5
  63              	.LBB10:
  64              	.LBB11:
  65              		.loc 2 452 5
  66              		.loc 2 452 5
  67 000c B7070002 		li	a5,33554432
  68              	 #APP
  69              	# 452 "C:\Work_Folder_Akhil\Q1_2026_2027\Koushik\Final\Release\mpf_an3694_v2025p1_df\src\softconsol
  70              		csrrc a5, mie, a5
  71              	# 0 "" 2
  72              	.LVL5:
  73              		.loc 2 452 5
  74              	 #NO_APP
  75              	.L3:
  76              	.LBE11:
  77              	.LBE10:
  46:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c ****     }
  47:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  48:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** 
  49:../src/platform/drivers/fpga_ip/CoreI2C/i2c_interrupt.c **** }
  78              		.loc 1 49 1 is_stmt 0
  79 0014 67800000 		ret
  80              		.cfi_endproc
  81              	.LFE19:
  83              		.comm	MRV_LOCAL_IRQn_Type,4,4
  84              		.text
  85              	.Letext0:
  86              		.file 3 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
  87              		.file 4 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
  88              		.file 5 "c:\\microchip\\softconsole-v2022.2-risc-v-747\\riscv-unknown-elf-gcc\\riscv64-unknown-elf
  89              		.file 6 "C:\\Work_Folder_Akhil\\Q1_2026_2027\\Koushik\\Final\\Release\\mpf_an3694_v2025p1_df\\src\
  90              		.file 7 "../src/platform/drivers/fpga_ip/CoreI2C/core_i2c.h"
DEFINED SYMBOLS
                            *ABS*:0000000000000000 i2c_interrupt.c
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:13     .text.I2C_enable_irq:0000000000000000 I2C_enable_irq
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:17     .text.I2C_enable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:19     .text.I2C_enable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:20     .text.I2C_enable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:21     .text.I2C_enable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:26     .text.I2C_enable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:29     .text.I2C_enable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:30     .text.I2C_enable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:31     .text.I2C_enable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:42     .text.I2C_enable_irq:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:43     .text.I2C_enable_irq:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:44     .text.I2C_enable_irq:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:51     .text.I2C_disable_irq:0000000000000000 I2C_disable_irq
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:54     .text.I2C_disable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:56     .text.I2C_disable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:57     .text.I2C_disable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:58     .text.I2C_disable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:62     .text.I2C_disable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:65     .text.I2C_disable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:66     .text.I2C_disable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:67     .text.I2C_disable_irq:000000000000000c .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:78     .text.I2C_disable_irq:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:79     .text.I2C_disable_irq:0000000000000014 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:80     .text.I2C_disable_irq:0000000000000018 .L0 
                            *COM*:0000000000000004 MRV_LOCAL_IRQn_Type
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:47     .text.I2C_enable_irq:0000000000000018 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:84     .text.I2C_disable_irq:0000000000000018 .L0 
                     .debug_frame:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:21     .text.I2C_enable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:39     .text.I2C_enable_irq:0000000000000014 .L1
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:58     .text.I2C_disable_irq:0000000000000000 .L0 
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:75     .text.I2C_disable_irq:0000000000000014 .L3
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:736    .debug_abbrev:0000000000000000 .Ldebug_abbrev0
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1411   .debug_str:00000000000005c4 .LASF96
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1233   .debug_str:0000000000000070 .LASF97
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1267   .debug_str:000000000000017e .LASF98
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1209   .debug_ranges:0000000000000000 .Ldebug_ranges0
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1217   .debug_line:0000000000000000 .Ldebug_line0
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1333   .debug_str:00000000000003b1 .LASF0
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1303   .debug_str:00000000000002ee .LASF3
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1321   .debug_str:0000000000000366 .LASF1
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1241   .debug_str:00000000000000d6 .LASF2
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1255   .debug_str:000000000000012b .LASF4
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1355   .debug_str:0000000000000441 .LASF5
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1297   .debug_str:00000000000002cc .LASF6
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1249   .debug_str:0000000000000109 .LASF7
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1387   .debug_str:0000000000000516 .LASF8
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1291   .debug_str:00000000000002aa .LASF9
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1335   .debug_str:00000000000003bd .LASF10
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1343   .debug_str:00000000000003fa .LASF11
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1269   .debug_str:0000000000000207 .LASF12
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1347   .debug_str:0000000000000412 .LASF13
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1339   .debug_str:00000000000003e1 .LASF14
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1337   .debug_str:00000000000003d4 .LASF15
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1369   .debug_str:00000000000004a2 .LASF16
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1279   .debug_str:0000000000000251 .LASF17
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1349   .debug_str:000000000000041b .LASF23
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1231   .debug_str:0000000000000064 .LASF18
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1225   .debug_str:0000000000000036 .LASF19
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1345   .debug_str:0000000000000407 .LASF20
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1285   .debug_str:0000000000000282 .LASF21
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1227   .debug_str:0000000000000046 .LASF22
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1237   .debug_str:00000000000000b4 .LASF24
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1419   .debug_str:00000000000006b4 .LASF25
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1305   .debug_str:00000000000002f8 .LASF26
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1283   .debug_str:000000000000026a .LASF27
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1361   .debug_str:000000000000046e .LASF28
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1357   .debug_str:0000000000000454 .LASF99
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1359   .debug_str:0000000000000461 .LASF29
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1299   .debug_str:00000000000002d5 .LASF30
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1413   .debug_str:0000000000000689 .LASF31
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1307   .debug_str:000000000000030b .LASF32
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1315   .debug_str:000000000000033a .LASF33
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1293   .debug_str:00000000000002b8 .LASF34
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1395   .debug_str:000000000000054b .LASF35
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1371   .debug_str:00000000000004b0 .LASF36
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1289   .debug_str:000000000000029c .LASF37
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1383   .debug_str:00000000000004fa .LASF38
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1353   .debug_str:0000000000000432 .LASF39
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1399   .debug_str:0000000000000561 .LASF40
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1271   .debug_str:000000000000020f .LASF41
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1281   .debug_str:0000000000000258 .LASF42
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1341   .debug_str:00000000000003ea .LASF43
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1407   .debug_str:00000000000005a6 .LASF44
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1365   .debug_str:0000000000000489 .LASF45
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1317   .debug_str:000000000000034b .LASF46
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1391   .debug_str:0000000000000534 .LASF47
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1329   .debug_str:0000000000000399 .LASF48
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1301   .debug_str:00000000000002e1 .LASF49
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1257   .debug_str:0000000000000136 .LASF50
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1415   .debug_str:0000000000000695 .LASF51
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1229   .debug_str:0000000000000053 .LASF52
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1351   .debug_str:0000000000000426 .LASF53
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1251   .debug_str:0000000000000114 .LASF54
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1401   .debug_str:000000000000056f .LASF55
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1277   .debug_str:000000000000023d .LASF56
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1247   .debug_str:00000000000000f2 .LASF57
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1331   .debug_str:00000000000003a6 .LASF58
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1221   .debug_str:0000000000000016 .LASF59
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1323   .debug_str:0000000000000374 .LASF60
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1379   .debug_str:00000000000004e3 .LASF61
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1421   .debug_str:00000000000006ca .LASF62
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1319   .debug_str:000000000000035b .LASF63
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1385   .debug_str:000000000000050b .LASF64
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1417   .debug_str:00000000000006a9 .LASF65
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1313   .debug_str:000000000000032f .LASF66
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1327   .debug_str:000000000000038e .LASF67
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1381   .debug_str:00000000000004ee .LASF68
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1265   .debug_str:0000000000000172 .LASF69
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1311   .debug_str:0000000000000323 .LASF70
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1375   .debug_str:00000000000004cb .LASF71
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1259   .debug_str:000000000000014e .LASF72
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1295   .debug_str:00000000000002c0 .LASF73
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1373   .debug_str:00000000000004bf .LASF74
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1253   .debug_str:000000000000011f .LASF75
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1287   .debug_str:0000000000000290 .LASF76
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1367   .debug_str:0000000000000496 .LASF77
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1235   .debug_str:00000000000000a8 .LASF78
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1261   .debug_str:000000000000015a .LASF79
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1389   .debug_str:0000000000000528 .LASF80
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1275   .debug_str:0000000000000231 .LASF81
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1377   .debug_str:00000000000004d7 .LASF82
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1403   .debug_str:0000000000000586 .LASF83
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1309   .debug_str:0000000000000317 .LASF84
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1245   .debug_str:00000000000000e6 .LASF85
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1363   .debug_str:000000000000047d .LASF86
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1263   .debug_str:0000000000000166 .LASF87
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1239   .debug_str:00000000000000ca .LASF88
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1273   .debug_str:000000000000021d .LASF89
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1405   .debug_str:0000000000000592 .LASF90
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1409   .debug_str:00000000000005b4 .LASF91
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:52     .text.I2C_disable_irq:0000000000000000 .LFB19
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:81     .text.I2C_disable_irq:0000000000000018 .LFE19
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1393   .debug_str:0000000000000542 .LASF93
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:63     .text.I2C_disable_irq:000000000000000c .LBB10
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:77     .text.I2C_disable_irq:0000000000000014 .LBE10
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1174   .debug_loc:0000000000000000 .LLST1
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:64     .text.I2C_disable_irq:000000000000000c .LBB11
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:76     .text.I2C_disable_irq:0000000000000014 .LBE11
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1325   .debug_str:000000000000037f .LASF92
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:14     .text.I2C_enable_irq:0000000000000000 .LFB18
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:45     .text.I2C_enable_irq:0000000000000018 .LFE18
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:27     .text.I2C_enable_irq:000000000000000c .LBB8
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:41     .text.I2C_enable_irq:0000000000000014 .LBE8
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1184   .debug_loc:0000000000000016 .LLST0
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:28     .text.I2C_enable_irq:000000000000000c .LBB9
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:40     .text.I2C_enable_irq:0000000000000014 .LBE9
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1219   .debug_str:0000000000000000 .LASF100
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1397   .debug_str:000000000000055c .LASF94
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1243   .debug_str:00000000000000e0 .LASF95
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:1223   .debug_str:0000000000000021 .LASF101
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:61     .text.I2C_disable_irq:000000000000000c .LVL4
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:72     .text.I2C_disable_irq:0000000000000014 .LVL5
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:24     .text.I2C_enable_irq:000000000000000c .LVL1
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:36     .text.I2C_enable_irq:0000000000000014 .LVL2
C:\Users\I71825\AppData\Local\Temp\ccPKTIeV.s:92     .debug_info:0000000000000000 .Ldebug_info0

UNDEFINED SYMBOLS
g_i2c_instance_cam1
