# Creating SmartDesign "top"
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_50MHZ} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_IN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ACT_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BG} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD2} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD3} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLVS_EC_RSTN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLVS_EC_XCE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLVS_EC_XMASTER} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}

sd_create_scalar_port -sd_name ${sd_name} -port_name {SLVS_EC_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SLVS_EC_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[13:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM_N} -port_direction {OUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT} -port_range {[3:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[31:0]} -port_is_pad {1}

sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SLVS_EC_XCE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SLVS_EC_XMASTER} -value {GND}
# Add CLKINT_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {CLKINT} -instance_name {CLKINT_0}



# Add Clocks_and_Resets_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Clocks_and_Resets} -instance_name {Clocks_and_Resets_0}



# Add HDMI_2P0_FHD_TX_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_2P0_FHD_TX} -instance_name {HDMI_2P0_FHD_TX_0}



# Add PF_DDR4_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DDR4_C0} -instance_name {PF_DDR4_C0_0}



# Add PROC_SS_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PROC_SS} -instance_name {PROC_SS_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PROC_SS_0:CAM2_RST}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PROC_SS_0:CAM_CLK_EN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PROC_SS_0:TRNG_RST_N}



# Add UART_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_interface} -instance_name {UART_interface_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_edge_sel_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:pip_mode_sel_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:pip_select_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:pulse_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {UART_interface_0:status_i} -value {1010}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:alpha_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:h_shift_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:step_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:v_shift_o}



# Add Video_Pipelining_Block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Pipelining_Block} -instance_name {Video_Pipelining_Block_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACT_N" "PF_DDR4_C0_0:ACT_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BG" "PF_DDR4_C0_0:BG" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "PF_DDR4_C0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "PF_DDR4_C0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "PF_DDR4_C0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "PF_DDR4_C0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:A" "CLK_50MHZ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLKINT_0:Y" "Clocks_and_Resets_0:CLK_50MHZ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_IN" "Clocks_and_Resets_0:CLK_IN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "PF_DDR4_C0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:PLL_REF_CLK" "PF_DDR4_C0_0:PLL_REF_CLK" "PROC_SS_0:PCLK" "UART_interface_0:sys_clk_i" "Video_Pipelining_Block_0:pclk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:XCVR_INIT_DONE" "Video_Pipelining_Block_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:ctrl_ready_i" "PF_DDR4_C0_0:CTRLR_READY" "Video_Pipelining_Block_0:ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:ddr_clk_i" "PF_DDR4_C0_0:SYS_CLK" "Video_Pipelining_Block_0:ddr_clock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:ddr_pll" "PF_DDR4_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:ddr_read_reset_i" "Video_Pipelining_Block_0:ddr_read_reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:ddr_sys_reset_i" "PF_DDR4_C0_0:SYS_RESET_N" "PROC_SS_0:RESETN" "UART_interface_0:reset_i" "Video_Pipelining_Block_0:preset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Clocks_and_Resets_0:video_processing_reset_i" "HDMI_2P0_FHD_TX_0:RESET_N_I" "Video_Pipelining_Block_0:VP_RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:HDMI_CLK" "Video_Pipelining_Block_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:H_SYNC_I" "Video_Pipelining_Block_0:H_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE0_TXD_N" "LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE0_TXD_P" "LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE1_TXD_N" "LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE1_TXD_P" "LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE2_TXD_N" "LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE2_TXD_P" "LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE3_TXD_N" "LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:LANE3_TXD_P" "LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:REF_CLK" "Video_Pipelining_Block_0:REF_CLK_For_HDMI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:VIDEO_DATA_VALID_I" "Video_Pipelining_Block_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:V_SYNC_I" "Video_Pipelining_Block_0:V_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "Video_Pipelining_Block_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "Video_Pipelining_Block_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N" "Video_Pipelining_Block_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P" "Video_Pipelining_Block_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_N" "Video_Pipelining_Block_0:LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_P" "Video_Pipelining_Block_0:LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_N" "Video_Pipelining_Block_0:LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_P" "Video_Pipelining_Block_0:LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE4_RXD_N" "Video_Pipelining_Block_0:LANE4_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE4_RXD_P" "Video_Pipelining_Block_0:LANE4_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE5_RXD_N" "Video_Pipelining_Block_0:LANE5_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE5_RXD_P" "Video_Pipelining_Block_0:LANE5_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE6_RXD_N" "Video_Pipelining_Block_0:LANE6_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE6_RXD_P" "Video_Pipelining_Block_0:LANE6_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE7_RXD_N" "Video_Pipelining_Block_0:LANE7_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE7_RXD_P" "Video_Pipelining_Block_0:LANE7_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "PF_DDR4_C0_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD2" "SHIELD2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD3" "SHIELD3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:CAM1_RST" "SLVS_EC_RSTN" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:CAM1_SCL" "SLVS_EC_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:CAM1_SDA" "SLVS_EC_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:PCS_INTERRUPT" "Video_Pipelining_Block_0:PCS_INTERUPT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "Video_Pipelining_Block_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "Video_Pipelining_Block_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_interface_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_interface_0:TX" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "PF_DDR4_C0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "PF_DDR4_C0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM_N" "PF_DDR4_C0_0:DM_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "PF_DDR4_C0_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "PF_DDR4_C0_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "PF_DDR4_C0_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT" "PROC_SS_0:GPIO_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:DATA_B_I" "Video_Pipelining_Block_0:B_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:DATA_G_I" "Video_Pipelining_Block_0:G_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_2P0_FHD_TX_0:DATA_R_I" "Video_Pipelining_Block_0:R_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bayer_format0_o" "Video_Pipelining_Block_0:BAYER_FORMAT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bgain_o" "Video_Pipelining_Block_0:b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:brightness_o" "Video_Pipelining_Block_0:brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:contrast_o" "Video_Pipelining_Block_0:contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:ggain_o" "Video_Pipelining_Block_0:g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:h_pan_c1_o" "Video_Pipelining_Block_0:h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:rgain_o" "Video_Pipelining_Block_0:r_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:v_pan_c1_o" "Video_Pipelining_Block_0:v_offset_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:AXI4slave0" "Video_Pipelining_Block_0:MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SS_0:APBmslave9" "Video_Pipelining_Block_0:APB_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "top"
generate_component -component_name ${sd_name}
