# Creating SmartDesign "Video_Pipelining_Block"
set sd_name {Video_Pipelining_Block}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_penable_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_psel_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pwrite_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rlast} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rvalid} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wready} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SYS_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {VP_RESETN_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clock_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_ctrl_ready_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_read_reset_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {pclk_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {preset_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pready_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_IF_pslverr_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DATA_VALID_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {H_SYNC_O} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rready} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wlast} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wvalid} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCS_INTERUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_For_HDMI} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {V_SYNC_O} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_paddr_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_pwdata_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {BAYER_FORMAT} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_bresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rdata} -port_direction {IN} -port_range {[255:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rid} -port_direction {IN} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_rresp} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {b_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {brightness_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {contrast_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {g_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {h_offset_i} -port_direction {IN} -port_range {[11:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {r_gain_i} -port_direction {IN} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {v_offset_i} -port_direction {IN} -port_range {[11:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {APB_IF_prdata_o} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {B_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {G_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_araddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_arsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awaddr} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awburst} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awcache} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awid} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awlen} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awlock} -port_direction {OUT} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awprot} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_awsize} -port_direction {OUT} -port_range {[2:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wdata} -port_direction {OUT} -port_range {[255:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4_wstrb} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_out_o} -port_direction {OUT} -port_range {[7:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APB_IF} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {slave} -port_bif_mapping {\
"PADDR:APB_IF_paddr_i" \
"PSELx:APB_IF_psel_i" \
"PENABLE:APB_IF_penable_i" \
"PWRITE:APB_IF_pwrite_i" \
"PRDATA:APB_IF_prdata_o" \
"PWDATA:APB_IF_pwdata_i" \
"PREADY:APB_IF_pready_o" \
"PSLVERR:APB_IF_pslverr_o" } 

sd_create_bif_port -sd_name ${sd_name} -port_name {MIRRORED_SLAVE_AXI4} -port_bif_vlnv {AMBA:AMBA4:AXI4:r0p0_0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"AWID:MIRRORED_SLAVE_AXI4_awid" \
"AWADDR:MIRRORED_SLAVE_AXI4_awaddr" \
"AWLEN:MIRRORED_SLAVE_AXI4_awlen" \
"AWSIZE:MIRRORED_SLAVE_AXI4_awsize" \
"AWBURST:MIRRORED_SLAVE_AXI4_awburst" \
"AWLOCK:MIRRORED_SLAVE_AXI4_awlock" \
"AWCACHE:MIRRORED_SLAVE_AXI4_awcache" \
"AWPROT:MIRRORED_SLAVE_AXI4_awprot" \
"AWVALID:MIRRORED_SLAVE_AXI4_awvalid" \
"AWREADY:MIRRORED_SLAVE_AXI4_awready" \
"WDATA:MIRRORED_SLAVE_AXI4_wdata" \
"WSTRB:MIRRORED_SLAVE_AXI4_wstrb" \
"WLAST:MIRRORED_SLAVE_AXI4_wlast" \
"WVALID:MIRRORED_SLAVE_AXI4_wvalid" \
"WREADY:MIRRORED_SLAVE_AXI4_wready" \
"BID:MIRRORED_SLAVE_AXI4_bid" \
"BRESP:MIRRORED_SLAVE_AXI4_bresp" \
"BVALID:MIRRORED_SLAVE_AXI4_bvalid" \
"BREADY:MIRRORED_SLAVE_AXI4_bready" \
"ARID:MIRRORED_SLAVE_AXI4_arid" \
"ARADDR:MIRRORED_SLAVE_AXI4_araddr" \
"ARLEN:MIRRORED_SLAVE_AXI4_arlen" \
"ARSIZE:MIRRORED_SLAVE_AXI4_arsize" \
"ARBURST:MIRRORED_SLAVE_AXI4_arburst" \
"ARLOCK:MIRRORED_SLAVE_AXI4_arlock" \
"ARCACHE:MIRRORED_SLAVE_AXI4_arcache" \
"ARPROT:MIRRORED_SLAVE_AXI4_arprot" \
"ARVALID:MIRRORED_SLAVE_AXI4_arvalid" \
"ARREADY:MIRRORED_SLAVE_AXI4_arready" \
"RID:MIRRORED_SLAVE_AXI4_rid" \
"RDATA:MIRRORED_SLAVE_AXI4_rdata" \
"RRESP:MIRRORED_SLAVE_AXI4_rresp" \
"RLAST:MIRRORED_SLAVE_AXI4_rlast" \
"RVALID:MIRRORED_SLAVE_AXI4_rvalid" \
"RREADY:MIRRORED_SLAVE_AXI4_rready" } 

# Add apb3_if_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {apb3_if} -instance_name {apb3_if_0}
# Exporting Parameters of instance apb3_if_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -params {\
"g_APB3_IF_DATA_WIDTH:32" \
"g_CONST_WIDTH:12" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_update_instance -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:mode_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALAR_RESET_O}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:RGB_SUM_B2} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {apb3_if_0:Alpha_i} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:alpha_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:step_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:frame_tcount_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_IN_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:VERT_RES_IN_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:VERT_RES_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALE_FACTOR_HORZ_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:SCALE_FACTOR_VERT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:RED_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:GREEN_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:BLUE_FRAME_DDR_ADDR_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:HORZ_RES_DDR_RD_OUT_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:DDR_READ_FRAME_START_ADDR_O}



# Add DDR_AXI4_ARBITER_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0}



# Add DDR_Read_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_C0} -instance_name {DDR_Read_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_C0_0:line_gap_i} -value {0001000000000000}



# Add DDR_Write_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_C0} -instance_name {DDR_Write_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_0:line_gap_i} -value {0001000000000000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_C0_0:frame_ddr_addr_i} -value {GND}



# Add Display_Controller_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Display_Controller_C0} -instance_name {Display_Controller_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C0_0:DATA_O} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:V_ACTIVE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C0_0:V_RES_O}



# Add IMX_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX_TOP} -instance_name {IMX_TOP_0}



# Add Video_Processing_Block_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Video_Processing_Block} -instance_name {Video_Processing_Block_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ARST_N" "IMX_TOP_0:ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DATA_VALID_O" "Display_Controller_C0_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "ddr_ctrl_ready_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_ack_o" "DDR_Read_C0_0:read_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_data_valid_o" "DDR_Read_C0_0:ddr_data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_done_o" "DDR_Read_C0_0:read_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_req_i" "DDR_Read_C0_0:read_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:reset_i" "DDR_Read_C0_0:reset_i" "DDR_Write_C0_0:ddr_clk_rstn_i" "ddr_read_reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "DDR_Read_C0_0:ddr_clk_i" "DDR_Write_C0_0:ddr_clk_i" "ddr_clock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_ack_o" "DDR_Write_C0_0:write_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_valid_i" "DDR_Write_C0_0:data_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_done_o" "DDR_Write_C0_0:write_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_req_i" "DDR_Write_C0_0:write_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:data_valid_o" "Video_Processing_Block_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:frame_start_i" "Display_Controller_C0_0:FRAME_END_O" "Video_Processing_Block_0:EOF_I" "apb3_if_0:frame_end_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:pixel_clk_i" "Display_Controller_C0_0:SYS_CLK_I" "SYS_CLK_I" "Video_Processing_Block_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:read_en_i" "Display_Controller_C0_0:DATA_TRIGGER_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_C0_0:data_valid_i" "IMX_TOP_0:line_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_C0_0:frame_start_i" "IMX_TOP_0:frame_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_C0_0:pixel_clk_i" "IMX_TOP_0:OUT0_FABCLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_C0_0:rstn_i" "IMX_TOP_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:EXT_SYNC_SIGNAL_I" "Video_Processing_Block_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:H_SYNC_O" "H_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:RESETN_I" "VP_RESETN_I" "Video_Processing_Block_0:RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:V_SYNC_O" "V_SYNC_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE0_RXD_N" "LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE0_RXD_P" "LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE1_RXD_N" "LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE1_RXD_P" "LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE2_RXD_N" "LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE2_RXD_P" "LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE3_RXD_N" "LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE3_RXD_P" "LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE4_RXD_N" "LANE4_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE4_RXD_P" "LANE4_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE5_RXD_N" "LANE5_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE5_RXD_P" "LANE5_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE6_RXD_N" "LANE6_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE6_RXD_P" "LANE6_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE7_RXD_N" "LANE7_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:LANE7_RXD_P" "LANE7_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:PCS_INTERUPT" "PCS_INTERUPT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:P_CLK_I" "apb3_if_0:pclk_i" "pclk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:REF_CLK_For_HDMI" "REF_CLK_For_HDMI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX_TOP_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:preset_i" "preset_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"BAYER_FORMAT" "Video_Processing_Block_0:BAYER_FORMAT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_out_o" "Display_Controller_C0_0:DATA_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_burst_size_i" "DDR_Read_C0_0:burst_size_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_rstart_addr_i" "DDR_Read_C0_0:read_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:rdata_o" "DDR_Read_C0_0:wdata_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_burst_size_i" "DDR_Write_C0_0:burst_size_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_i" "DDR_Write_C0_0:data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_wstart_addr_i" "DDR_Write_C0_0:write_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:data_o" "Video_Processing_Block_0:DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:frame_start_addr_i" "DDR_Write_C0_0:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:h_offset_i" "h_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:horz_resl_i" "Display_Controller_C0_0:H_RES_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_C0_0:v_offset_i" "v_offset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_C0_0:data_i" "IMX_TOP_0:pixel_data_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[15:8]" "Video_Processing_Block_0:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[23:16]" "Video_Processing_Block_0:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_I[7:0]" "Video_Processing_Block_0:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_O[15:8]" "G_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C0_0:DATA_O[23:16]" "R_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_0:B_CONST_I" "apb3_if_0:bconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_0:COMMON_CONST_I" "apb3_if_0:second_const_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_0:G_CONST_I" "apb3_if_0:gconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_0:R_CONST_I" "apb3_if_0:rconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Video_Processing_Block_0:Y_AVG_O" "apb3_if_0:RGB_SUM_B1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:b_gain_i" "b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:brightness_i" "brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:contrast_i" "contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:g_gain_i" "g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"apb3_if_0:r_gain_i" "r_gain_i" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_IF" "apb3_if_0:APB_IF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" "MIRRORED_SLAVE_AXI4" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "Video_Pipelining_Block"
generate_component -component_name ${sd_name}
