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COMPLETE RESET STRUCTURE ANALYSIS
Design: IMX_TOP with XCVR_DISPARITY_CORRECTION_MULTI
Date: 2026-03-30
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RESET HIERARCHY:
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Level 1: Top-Level Inputs
─────────────────────────
  ARST_N (external reset button/signal)
  REF_CLK_PAD_P/N (external 148.5 MHz oscillator)


Level 2: PLL Lock
─────────────────
  PF_XCVR_REF_CLK_C0
    Input:  REF_CLK_PAD_P/N
    Output: REF_CLK_For_HDMI_net_0

  PF_CCC_C2_0
    Input:  REF_CLK_For_HDMI_net_0
    Output: PF_CCC_C2_0_OUT0_FABCLK_0 (reference clock for XCVR)
            PF_CCC_C2_0_PLL_LOCK_0 (lock indicator)


Level 3: Qualified Reset for Disparity Modules
───────────────────────────────────────────────
  AND2_1 gate:
    Input A: ARST_N (external reset)
    Input B: PF_CCC_C2_0_PLL_LOCK_0 (PLL locked)
    Output:  AND2_1_Y

  Logic: AND2_1_Y = ARST_N & PLL_LOCK_0

  Purpose: Disparity modules only come out of reset AFTER PLL locks
           Ensures stable reference clock before disparity checking


Level 4: Disparity Detection Module (NEW MULTI-LANE)
─────────────────────────────────────────────────────
  XCVR_DISPARITY_CORRECTION (single instance, handles all 8 lanes)
    Input:  RESET_N_I = AND2_1_Y
    Inputs: LANE0-7_RX_READY_I, RX_VALID_I, DISPARITY_ERR_I[3:0]
    Output: RX_RST_CONTROL_O (single output)
            RX_RST_CONTROL_INTERRUPT_O (single interrupt)

  Function:
    - Monitors disparity errors on all active lanes
    - Detects first lock (all lanes ready, one-time only)
    - Generates interrupt on:
      * First lock (if ENABLE_ERM_FIRST_LOCK = 1)
      * Disparity errors (always)
    - Pulses RX_RST_CONTROL_O = 0 for 32 cycles on trigger


Level 5: Combined Disparity Status (OLD DESIGN - FOR REFERENCE)
────────────────────────────────────────────────────────────────
Note: If using multi-lane module, this changes to single output

  OLD DESIGN (8 separate modules):
    XCVR_DISPARITY_CORRECTION_0 → RX_RST_CONTROL_O
    XCVR_DISPARITY_CORRECTION_1 → RX_RST_CONTROL_O
    ...
    XCVR_DISPARITY_CORRECTION_7 → RX_RST_CONTROL_O

  AND4_0 gate:
    Inputs: XCVR_DISPARITY_0-3 RX_RST_CONTROL_O
    Output: AND4_0_Y

  AND4_1 gate:
    Inputs: XCVR_DISPARITY_4-7 RX_RST_CONTROL_O
    Output: AND4_1_Y

  AND2_0 gate:
    Input A: AND4_0_Y
    Input B: AND4_1_Y
    Output:  AND2_0_Y

  Logic: AND2_0_Y = All 8 lanes disparity OK

  NEW DESIGN (single multi-lane module):
    XCVR_DISPARITY_CORRECTION (single) → RX_RST_CONTROL_O

    Connect directly: AND2_0_Y = RX_RST_CONTROL_O
    (No need for AND4 gates)


Level 6: XCVR PCS Reset
───────────────────────
  PF_XCVR_ERM_C1_0 & PF_XCVR_ERM_C2_0:
    LANE0-3_PCS_ARST_N = AND2_0_Y
    LANE0-3_PMA_ARST_N = ARST_N
    CTRL_ARST_N = ARST_N

  Purpose: PCS only comes out of reset when disparity checking passes


Level 7: Fabric Reset Generator
────────────────────────────────
  CORERESET_PF_C3_0:
    Input CLK:        PF_XCVR_ERM_C2_0_LANE0_RX_CLK_R (RX clock must be running)
    Input EXT_RST_N:  AND2_0_Y (disparity OK)
    Input PLL_LOCK:   PF_CCC_C3_0_PLL_LOCK_0 (pixel clock PLL)
    Input INIT_DONE:  ARST_N (FPGA initialized)
    Output:           CORERESET_PF_C3_0_FABRIC_RESET_N

  Logic: Generates clean fabric reset after:
    - RX_CLK is running (XCVR locked)
    - Disparity OK
    - Pixel PLL locked
    - FPGA init done


Level 8: SLVS_EC_RX Reset
──────────────────────────
  SLVS_EC_RX_C0_0:
    Input ARST_N: CORERESET_PF_C3_0_FABRIC_RESET_N

  Purpose: SLVS receiver only operates after complete system ready


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RESET SEQUENCE - NORMAL BOOT:
================================================================================

t=0ms:    Power up
          ARST_N = LOW → Everything in reset

t=1ms:    ARST_N = HIGH (external reset released)
          PF_CCC_C2 starts locking
          AND2_1_Y = 0 (PLL not locked yet)
          XCVR_DISPARITY in reset

t=5ms:    PF_CCC_C2 locks → PLL_LOCK_0 = HIGH
          AND2_1_Y = HIGH ✓
          XCVR_DISPARITY comes out of reset

t=10ms:   Disparity modules start checking
          RX_RST_CONTROL_O = 1 (initially OK)
          AND2_0_Y = HIGH
          PCS_ARST_N = HIGH → XCVR PCS comes out of reset

t=50ms:   XCVR CDR locks to data
          RX_READY signals go HIGH
          RX_CLK_R is running

t=60ms:   PF_CCC_C3 locks (uses RX_CLK as input)
          PLL_LOCK_0 = HIGH

t=70ms:   CORERESET_PF_C3 releases
          FABRIC_RESET_N = HIGH ✓
          SLVS_EC_RX comes out of reset

t=80ms:   All lanes lock (first lock!)
          XCVR_DISPARITY detects all_lanes_ready posedge
          first_lock_trigger = HIGH
          FSM → s_RST_CNT

t=81ms:   RX_RST_CONTROL_O = 0 (pulsed LOW)
          AND2_0_Y = 0
          PCS resets briefly
          FABRIC_RESET_N = 0
          SLVS_EC_RX resets (clears any transients)

t=82-113ms: Reset counter 0→31 (32 cycles)

t=114ms:  s_REG_RST
          RX_RST_CONTROL_O = 1
          RX_RST_CONTROL_INTERRUPT_O = 1 ← INTERRUPT FIRES!
          first_lock_latch = 1 (set forever)

t=115ms:  Software interrupt handler executes:
          GPIO: CAM_RST = HIGH (release camera from reset)

t=120ms:  Camera boots
          Sends SYNC codes

t=125ms:  SLVS_EC_RX catches SYNC ✓
          Normal operation begins!


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RESET SEQUENCE - CAMERA I2C RESET (LATER):
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t=10s:    Normal operation
          Camera streaming, video working

t=10.1s:  Software: slvs_ec_cam_standby_en_dis(1u)
          I2C writes to camera registers 0x3000, 0x3010
          Camera enters standby

t=10.2s:  Camera stops data
          XCVR loses lock → RX_READY = 0

          BUT:
          ARST_N = HIGH ✓ (no external reset)
          PLL_LOCK_0 = HIGH ✓ (PLL still locked to external ref)
          AND2_1_Y = HIGH ✓ (both inputs HIGH)
          RESET_N_I = HIGH ✓ (disparity module NOT reset)
          first_lock_latch = 1 ✓ (preserved!)

t=10.3s:  Camera resumes (I2C writes 0x3000=0, 0x3010=0)
          Camera restarts

t=10.5s:  XCVR re-locks
          RX_READY signals go HIGH again
          all_lanes_ready_posedge = 1
          first_lock_latch = 1 (still set)
          first_lock_trigger = (1 && !1) = 0 ✓ BLOCKED

          No false interrupt!
          FSM stays in s_ERR_DETECT_CNT
          Disparity checking continues normally


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CAMERA RESET IMPACT ANALYSIS:
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Camera I2C Reset (slvs_ec_cam_standby_en_dis) DOES NOT AFFECT:
──────────────────────────────────────────────────────────────
  ✓ ARST_N (external signal, unaffected)
  ✓ PF_CCC_C2 PLL (locked to external ref, unaffected)
  ✓ AND2_1_Y (stays HIGH)
  ✓ RESET_N_I to disparity module (stays HIGH)
  ✓ first_lock_latch register (preserved, stays = 1)
  ✓ Disparity error detection (continues working)

Camera I2C Reset DOES AFFECT:
──────────────────────────────
  ✗ SLVS-EC data transmission (stops during standby)
  ✗ XCVR data lock (loses lock temporarily)
  ✗ RX_READY signals (go LOW then HIGH)
  ✗ RX_VALID signals (go LOW then HIGH)


================================================================================
VERIFICATION CHECKLIST:
================================================================================

✓ First lock interrupt fires ONCE only (gated by latch)
✓ Camera I2C reset does NOT clear latch (RESET_N_I stays HIGH)
✓ Camera I2C reset does NOT trigger false first-lock (latch blocks)
✓ Disparity error detection continues after first lock
✓ FSM returns to s_ERR_DETECT_CNT after first lock
✓ ERM first-lock can be disabled via parameter (non-ERM mode)
✓ Single module handles all lanes (reduces from 8 to 1 instance)
✓ Parameterized for 2/4/8 lanes


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SOFTWARE INTEGRATION:
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Interrupt Handler:
──────────────────

uint8_t MSYS_EI0_IRQHandler(void)
{
    static uint8_t first_time = 1;

    if (first_time) {
        // First interrupt = XCVR first lock
        printf("FPGA XCVR ready! Releasing camera...\n");
        GPIO_set_output(&g_gpio_out, CAM1_RST, 1u);
        GPIO_set_output(&g_gpio_out, CAM2_RST, 1u);
        first_time = 0;
    }
    else {
        // Subsequent interrupts = disparity errors
        printf("Disparity error detected!\n");
        sem = 1;  // Trigger camera I2C reset
    }

    return (EXT_IRQ_KEEP_ENABLED);
}

Main Loop:
──────────

if(sem==1) {
    sem=0;
    printf("Resetting camera via I2C...\n");
    slvs_ec_cam_standby_en_dis(1u);
}


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CONFIGURATION:
================================================================================

For ERM-enabled XCVR:
─────────────────────
  Set parameter: ENABLE_ERM_FIRST_LOCK = 1
  → First lock detection enabled
  → Interrupt fires on first lock
  → Camera released from GPIO reset at right time

For Non-ERM XCVR:
─────────────────
  Set parameter: ENABLE_ERM_FIRST_LOCK = 0
  → First lock detection disabled
  → Only disparity errors generate interrupts
  → Use timer-based camera release


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CONCLUSION:
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The reset structure is SAFE for camera I2C resets because:

1. Camera reset is SOFTWARE ONLY (I2C register writes)
2. No FPGA hardware signals are affected
3. RESET_N_I to disparity module stays HIGH
4. first_lock_latch persists through camera reset
5. First lock will NOT re-trigger on subsequent resets
6. Disparity error detection continues normally

The design correctly handles:
  ✓ Power-up sequencing
  ✓ First lock detection (one-time)
  ✓ Camera GPIO release timing
  ✓ Disparity error recovery (ongoing)
  ✓ Camera I2C resets (no false triggers)

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