# Creating SmartDesign "IMX_TOP"
set sd_name {IMX_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {ARST_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE4_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE5_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE6_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE7_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {P_CLK_I} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}

sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RX_READY} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {OUT0_FABCLK_0} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCS_INTERUPT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_For_HDMI} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_valid_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {line_valid_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {pixel_data_o} -port_direction {OUT} -port_range {[255:0]}


# Add AND2_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_1}



# Add CORERESET_PF_C3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C3} -instance_name {CORERESET_PF_C3_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C3_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C3_0:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C3_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C3_0:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C3_0:FPGA_POR_N} -value {VCC}



# Add PF_CCC_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C2} -instance_name {PF_CCC_C2_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_CCC_C2_0:PLL_POWERDOWN_N_0} -value {VCC}



# Add PF_CCC_C3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C3} -instance_name {PF_CCC_C3_0}



# Add PF_CLK_DIV_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}



# Add PF_OSC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_C0} -instance_name {PF_OSC_C0_0}



# Add PF_XCVR_ERM_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C1} -instance_name {PF_XCVR_ERM_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE2_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE3_RX_IDLE}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE1_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE2_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE2_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE3_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE3_CALIB_REQ} -value {GND}



# Add PF_XCVR_ERM_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C2} -instance_name {PF_XCVR_ERM_C2_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE1_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE2_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE3_RX_IDLE}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE0_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE1_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE1_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE2_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE2_CALIB_REQ} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE3_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C2_0:LANE3_CALIB_REQ} -value {GND}



# Add PF_XCVR_REF_CLK_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}



# Add SLVS_EC_RX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {SLVS_EC_RX_C0} -instance_name {SLVS_EC_RX_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:EBD_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:HEADER_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE0_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE1_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE2_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE3_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE4_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE5_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE6_FSM_STATE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SLVS_EC_RX_C0_0:LANE7_FSM_STATE_O}



# Add slvs_frame_end_gen_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {slvs_frame_end_gen} -hdl_file {hdl\gen.v} -instance_name {slvs_frame_end_gen_0}



# Add XCVR_DISPARITY_CORRECTION_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {XCVR_DISPARITY_CORRECTION} -hdl_file {hdl\XCVR_DISPARITY_CORRECTION.v} -instance_name {XCVR_DISPARITY_CORRECTION_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:A" "ARST_N" "CORERESET_PF_C3_0:INIT_DONE" "PF_XCVR_ERM_C1_0:CTRL_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PMA_ARST_N" "PF_XCVR_ERM_C1_0:LANE1_PMA_ARST_N" "PF_XCVR_ERM_C1_0:LANE2_PMA_ARST_N" "PF_XCVR_ERM_C1_0:LANE3_PMA_ARST_N" "PF_XCVR_ERM_C2_0:CTRL_ARST_N" "PF_XCVR_ERM_C2_0:LANE0_PMA_ARST_N" "PF_XCVR_ERM_C2_0:LANE1_PMA_ARST_N" "PF_XCVR_ERM_C2_0:LANE2_PMA_ARST_N" "PF_XCVR_ERM_C2_0:LANE3_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:B" "PF_CCC_C2_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_1:Y" "XCVR_DISPARITY_CORRECTION_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C3_0:CLK" "PF_CCC_C3_0:REF_CLK_0" "PF_XCVR_ERM_C2_0:LANE0_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE0_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE0_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C3_0:EXT_RST_N" "PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE1_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE2_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE3_PCS_ARST_N" "PF_XCVR_ERM_C2_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C2_0:LANE1_PCS_ARST_N" "PF_XCVR_ERM_C2_0:LANE2_PCS_ARST_N" "PF_XCVR_ERM_C2_0:LANE3_PCS_ARST_N" "XCVR_DISPARITY_CORRECTION_0:RX_RST_CONTROL_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C3_0:FABRIC_RESET_N" "SLVS_EC_RX_C0_0:ARST_N" "slvs_frame_end_gen_0:resetn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C3_0:PLL_LOCK" "PF_CCC_C3_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C2_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C2_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RX_READY" "PF_XCVR_ERM_C2_0:LANE0_RX_READY" "SLVS_EC_RX_C0_0:LANE0_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N" "PF_XCVR_ERM_C2_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P" "PF_XCVR_ERM_C2_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_N" "PF_XCVR_ERM_C2_0:LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_P" "PF_XCVR_ERM_C2_0:LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_N" "PF_XCVR_ERM_C2_0:LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_P" "PF_XCVR_ERM_C2_0:LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE4_RXD_N" "PF_XCVR_ERM_C1_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE4_RXD_P" "PF_XCVR_ERM_C1_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE5_RXD_N" "PF_XCVR_ERM_C1_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE5_RXD_P" "PF_XCVR_ERM_C1_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE6_RXD_N" "PF_XCVR_ERM_C1_0:LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE6_RXD_P" "PF_XCVR_ERM_C1_0:LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE7_RXD_N" "PF_XCVR_ERM_C1_0:LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE7_RXD_P" "PF_XCVR_ERM_C1_0:LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"OUT0_FABCLK_0" "PF_CCC_C3_0:OUT0_FABCLK_0" "SLVS_EC_RX_C0_0:PIXEL_CLOCK_I" "slvs_frame_end_gen_0:clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PCS_INTERUPT" "XCVR_DISPARITY_CORRECTION_0:RX_RST_CONTROL_INTERRUPT_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C2_0:OUT0_FABCLK_0" "PF_XCVR_ERM_C1_0:LANE0_CLK_REF" "PF_XCVR_ERM_C1_0:LANE1_CLK_REF" "PF_XCVR_ERM_C1_0:LANE2_CLK_REF" "PF_XCVR_ERM_C1_0:LANE3_CLK_REF" "PF_XCVR_ERM_C2_0:LANE0_CLK_REF" "PF_XCVR_ERM_C2_0:LANE1_CLK_REF" "PF_XCVR_ERM_C2_0:LANE2_CLK_REF" "PF_XCVR_ERM_C2_0:LANE3_CLK_REF" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C2_0:REF_CLK_0" "PF_XCVR_ERM_C1_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_ERM_C1_0:LANE1_CDR_REF_CLK_0" "PF_XCVR_ERM_C1_0:LANE2_CDR_REF_CLK_0" "PF_XCVR_ERM_C1_0:LANE3_CDR_REF_CLK_0" "PF_XCVR_ERM_C2_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_ERM_C2_0:LANE1_CDR_REF_CLK_0" "PF_XCVR_ERM_C2_0:LANE2_CDR_REF_CLK_0" "PF_XCVR_ERM_C2_0:LANE3_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:REF_CLK" "REF_CLK_For_HDMI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_IN" "PF_OSC_C0_0:RCOSC_160MHZ_CLK_DIV" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "PF_XCVR_ERM_C1_0:CTRL_CLK" "PF_XCVR_ERM_C2_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE4_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE4_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE4_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_READY" "SLVS_EC_RX_C0_0:LANE4_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_VAL" "SLVS_EC_RX_C0_0:LANE4_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE4_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE5_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE5_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE5_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_RX_READY" "SLVS_EC_RX_C0_0:LANE5_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_RX_VAL" "SLVS_EC_RX_C0_0:LANE5_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE5_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE6_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE6_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE6_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_RX_READY" "SLVS_EC_RX_C0_0:LANE6_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_RX_VAL" "SLVS_EC_RX_C0_0:LANE6_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE6_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE7_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE7_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE7_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_RX_READY" "SLVS_EC_RX_C0_0:LANE7_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_RX_VAL" "SLVS_EC_RX_C0_0:LANE7_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE7_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE0_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE0_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE0_RX_VAL" "SLVS_EC_RX_C0_0:LANE0_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE0_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE1_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE1_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE1_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_RX_READY" "SLVS_EC_RX_C0_0:LANE1_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_RX_VAL" "SLVS_EC_RX_C0_0:LANE1_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE1_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE2_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE2_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE2_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_RX_READY" "SLVS_EC_RX_C0_0:LANE2_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_RX_VAL" "SLVS_EC_RX_C0_0:LANE2_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE2_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_CALIBRATING" "XCVR_DISPARITY_CORRECTION_0:LANE3_CALIBRATING_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_RX_CLK_R" "SLVS_EC_RX_C0_0:LANE3_RX_CLK_I" "XCVR_DISPARITY_CORRECTION_0:LANE3_RX_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_RX_READY" "SLVS_EC_RX_C0_0:LANE3_RX_READY_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_RX_VAL" "SLVS_EC_RX_C0_0:LANE3_RX_VALID_I" "XCVR_DISPARITY_CORRECTION_0:LANE3_RX_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"P_CLK_I" "XCVR_DISPARITY_CORRECTION_0:P_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SLVS_EC_RX_C0_0:FRAME_VALID_O" "slvs_frame_end_gen_0:frame_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SLVS_EC_RX_C0_0:LINE_VALID_O" "slvs_frame_end_gen_0:line_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"frame_valid_o" "slvs_frame_end_gen_0:frame_end_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"line_valid_o" "slvs_frame_end_gen_0:line_valid_o" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE4_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_DATA" "SLVS_EC_RX_C0_0:LANE4_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE0_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE4_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE5_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_RX_DATA" "SLVS_EC_RX_C0_0:LANE5_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE1_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE5_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE6_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_RX_DATA" "SLVS_EC_RX_C0_0:LANE6_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE2_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE6_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE7_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_RX_DATA" "SLVS_EC_RX_C0_0:LANE7_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C1_0:LANE3_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE7_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE0_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE0_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE0_RX_DATA" "SLVS_EC_RX_C0_0:LANE0_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE0_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE0_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE1_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_RX_DATA" "SLVS_EC_RX_C0_0:LANE1_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE1_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE1_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE2_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_RX_DATA" "SLVS_EC_RX_C0_0:LANE2_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE2_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE2_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_8B10B_RX_K" "SLVS_EC_RX_C0_0:LANE3_8b10b_RX_K_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_RX_DATA" "SLVS_EC_RX_C0_0:LANE3_RX_DATA_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_ERM_C2_0:LANE3_RX_DISPARITY_ERROR" "XCVR_DISPARITY_CORRECTION_0:LANE3_DISPARITY_ERR_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"SLVS_EC_RX_C0_0:DATA_OUT_O" "pixel_data_o" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the SmartDesign 
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign "IMX_TOP"
generate_component -component_name ${sd_name}
