#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I52881 # Thu Jan 7 09:25:12 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\polarfire_syn_comps.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\acmtable.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructnvm_bb.v" (library work) @I:"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructnvm_bb.v":"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\support.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\iram512x9_rtl.v" (library work) @N:CG334 : iram512x9_rtl.v(57) | Read directive translate_off. @N:CG333 : iram512x9_rtl.v(65) | Read directive translate_on. @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructram.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\debugblk.v" (library work) @N:CG334 : debugblk.v(68) | Read directive translate_off. @N:CG333 : debugblk.v(745) | Read directive translate_on. @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructions.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram128x8_polarfire.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256x16_rtl.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256x8_rtl.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256xdwidth_ecc_g5.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ramblocks.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\coreabc.v" (library work) @N:CG334 : coreabc.v(992) | Read directive translate_off. @N:CG333 : coreabc.v(994) | Read directive translate_on. @N:CG334 : coreabc.v(1389) | Read directive translate_off. @N:CG333 : coreabc.v(1433) | Read directive translate_on. @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\Flag_for_RXPLL_lock.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\INIT_MONITOR\INIT_MONITOR.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CCC_50\PF_CCC_50_0\PF_CCC_50_PF_CCC_50_0_PF_CCC.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CCC_50\PF_CCC_50.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0_0\PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_OSC_160\PF_OSC_160_0\PF_OSC_160_PF_OSC_160_0_PF_OSC.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_OSC_160\PF_OSC_160.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_TX_PLL_0\PF_TX_PLL_0_0\PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_TX_PLL_0\PF_TX_PLL_0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELCKMGT\2.0.100\rtl\vlog\core\CORELCKMGT.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDbincnt.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsmplcnt.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDfrqerrarb.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDgrycnt.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDplsgen.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDshcnt.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsyncen.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsync.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsicr.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFD.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_0\I_XCVR\PF_XCVR_0_I_XCVR_PF_XCVR.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\SgCore\PF_XCVR_APBLINK_V\1.0.102\hdl\PF_XCVR_APBLINK_V.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode0.v" (library work) @I:"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode0.v":"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\request_code.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode1.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode2.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTR.v" (library work) @N:CG334 : CORELANEMSTR.v(124) | Read directive translate_off. @N:CG333 : CORELANEMSTR.v(126) | Read directive translate_on. @N:CG334 : CORELANEMSTR.v(203) | Read directive translate_off. @N:CG333 : CORELANEMSTR.v(216) | Read directive translate_on. @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_0\PF_XCVR_0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_DRI\PF_XCVR_DRI_0\PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_DRI\PF_XCVR_DRI.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_REF_CLK_0\PF_XCVR_REF_CLK_0_0\PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_REF_CLK_0\PF_XCVR_REF_CLK_0.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\prbs_asic_chk.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\PRBS_chk.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\prbs_asic_gen.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\PRBS_gen.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_rx\reset_syn_rx_0\core\corereset_pf.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_rx\reset_syn_rx.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_tx\reset_syn_tx_0\core\corereset_pf.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_tx\reset_syn_tx.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_logic\reset_logic.v" (library work) @I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Selecting top level module top @N:CG364 : acg5.v(121) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... @N:CG364 : coreabc.v(46) | Synthesizing module CoreABC_Inst_CoreABC_Inst_0_COREABC in library work. FAMILY=32'b00000000000000000000000000011010 APB_AWIDTH=32'b00000000000000000000000000001101 APB_DWIDTH=32'b00000000000000000000000000100000 APB_SDEPTH=32'b00000000000000000000000000000010 ICWIDTH=32'b00000000000000000000000000000101 ZRWIDTH=32'b00000000000000000000000000000000 IFWIDTH=32'b00000000000000000000000000000000 IIWIDTH=32'b00000000000000000000000000000001 IOWIDTH=32'b00000000000000000000000000001010 STWIDTH=32'b00000000000000000000000000000100 EN_RAM=32'b00000000000000000000000000000001 EN_RAM_ECC=32'b00000000000000000000000000000000 EN_AND=32'b00000000000000000000000000000001 EN_XOR=32'b00000000000000000000000000000001 EN_OR=32'b00000000000000000000000000000001 EN_ADD=32'b00000000000000000000000000000001 EN_INC=32'b00000000000000000000000000000001 EN_SHL=32'b00000000000000000000000000000001 EN_SHR=32'b00000000000000000000000000000001 EN_CALL=32'b00000000000000000000000000000001 EN_PUSH=32'b00000000000000000000000000000001 EN_MULT=32'b00000000000000000000000000000000 EN_ACM=32'b00000000000000000000000000000000 EN_DATAM=32'b00000000000000000000000000000010 EN_INT=32'b00000000000000000000000000000000 EN_IOREAD=32'b00000000000000000000000000000001 EN_IOWRT=32'b00000000000000000000000000000001 EN_ALURAM=32'b00000000000000000000000000000000 EN_INDIRECT=32'b00000000000000000000000000000000 ISRADDR=32'b00000000000000000000000000000001 DEBUG=32'b00000000000000000000000000000001 INSMODE=32'b00000000000000000000000000000000 INITWIDTH=32'b00000000000000000000000000001011 TESTMODE=32'b00000000000000000000000000000000 ACT_CALIBRATIONDATA=32'b00000000000000000000000000000001 IMEM_APB_ACCESS=32'b00000000000000000000000000000000 UNIQ_STRING_LENGTH=32'b00000000000000000000000000011011 MAX_NVMDWIDTH=32'b00000000000000000000000000100000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 IRWIDTH=32'b00000000000000000000000000100000 ICDEPTH=32'b00000000000000000000000000100000 APB_SWIDTH=32'b00000000000000000000000000000001 RAMWIDTH=32'b00000000000000000000000000110100 SYNC_RESET=32'b00000000000000000000000000000000 ZRWIDTH_ZR=32'b00000000000000000000000000000001 CYCLE0=2'b00 CYCLE1=2'b01 CYCLE2=2'b10 CYCLE3=2'b11 Generated name = CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1 @N:CG364 : ramblocks.v(25) | Synthesizing module CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS in library work. EN_RAM_ECC=32'b00000000000000000000000000000000 DWIDTH=32'b00000000000000000000000000100000 FAMILY=32'b00000000000000000000000000011010 Generated name = CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s @N:CG364 : acg5.v(578) | Synthesizing module RAM1K20 in library work. Running optimization stage 1 on RAM1K20 ....... @N:CG364 : ram128x8_polarfire.v(23) | Synthesizing module CoreABC_Inst_CoreABC_Inst_0_RAM128X8 in library work. Running optimization stage 1 on CoreABC_Inst_CoreABC_Inst_0_RAM128X8 ....... @W:CG360 : ramblocks.v(43) | Removing wire RDW, as there is no assignment to it. @W:CG360 : ramblocks.v(45) | Removing wire WDX, as there is no assignment to it. @W:CG360 : ramblocks.v(46) | Removing wire RDX, as there is no assignment to it. @W:CG360 : ramblocks.v(47) | Removing wire WDY, as there is no assignment to it. @W:CG360 : ramblocks.v(48) | Removing wire RDY, as there is no assignment to it. @W:CG360 : ramblocks.v(49) | Removing wire RDYY, as there is no assignment to it. Running optimization stage 1 on CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s ....... @W:CL318 : ramblocks.v(40) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : ramblocks.v(41) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : instructions.v(26) | Synthesizing module CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS in library work. AWIDTH=32'b00000000000000000000000000001101 DWIDTH=32'b00000000000000000000000000100000 SWIDTH=32'b00000000000000000000000000000001 ICWIDTH=32'b00000000000000000000000000000101 IIWIDTH=32'b00000000000000000000000000000001 IFWIDTH=32'b00000000000000000000000000000000 IWWIDTH=32'b00000000000000000000000000111010 EN_MULT=32'b00000000000000000000000000000000 EN_INC=32'b00000000000000000000000000000001 TESTMODE=32'b00000000000000000000000000000000 BLANK=32'b11111111111111111111111111111111 iNOP=32'b00000000000000000000000100000000 iLOAD=32'b00000000000000000000001000000000 iINCB=32'b00000000000000000000001100000000 iAND=32'b00000000000000000000010000000000 iOR=32'b00000000000000000000010100000000 iXOR=32'b00000000000000000000011000000000 iADD=32'b00000000000000000000011100000000 iSUB=32'b00000000000000000000100000000000 iSHL0=32'b00000000000000000000100100000000 iSHL1=32'b00000000000000000000101000000000 iSHLE=32'b00000000000000000000101100000000 iROL=32'b00000000000000000000110000000000 iSHR0=32'b00000000000000000000110100000000 iSHR1=32'b00000000000000000000111000000000 iSHRE=32'b00000000000000000000111100000000 iROR=32'b00000000000000000001000000000000 iCMP=32'b00000000000000000001000100000000 iCMPLEQ=32'b00000000000000000001001000000000 iBITCLR=32'b00000000000000000001001100000000 iBITSET=32'b00000000000000000001010000000000 iBITTST=32'b00000000000000000001010100000000 iAPBREAD=32'b00000000000000000001011000000000 iAPBWRT=32'b00000000000000000001011100000000 iLOADZ=32'b00000000000000000001100000000000 iDECZ=32'b00000000000000000001100100000000 iINCZ=32'b00000000000000000001101000000000 iIOWRT=32'b00000000000000000001101100000000 iRAMREAD=32'b00000000000000000001110000000000 iRAMWRT=32'b00000000000000000001110100000000 iPUSH=32'b00000000000000000001111000000000 iPOP=32'b00000000000000000001111100000000 iIOREAD=32'b00000000000000000010000000000000 iUSER=32'b00000000000000000010000100000000 iJUMPB=32'b00000000000000000010001000000000 iCALLB=32'b00000000000000000010001100000000 iRETURNB=32'b00000000000000000010010000000000 iRETISRB=32'b00000000000000000010010100000000 iWAITB=32'b00000000000000000010011000000000 iHALTB=32'b00000000000000000010011000000000 iMULT=32'b00000000000000000010011100000000 iDEC=32'b00000000000000000010100000000000 iAPBREADZ=32'b00000000000000000010100100000000 iAPBWRTZ=32'b00000000000000000010101000000000 iADDZ=32'b00000000000000000010101100000000 iSUBZ=32'b00000000000000000010110000000000 iDAT=32'b00000000000000000000000000001010 iDAT8=32'b00000000000000000000000000001011 iDAT16=32'b00000000000000000000000000001100 iDAT32=32'b00000000000000000000000000001101 iACM=32'b00000000000000000000000000001110 iACC=32'b00000000000000000000000000001111 iRAM=32'b00000000000000000000000000010000 DAT=32'b00000000000000000000000000001010 DAT8=32'b00000000000000000000000000001011 DAT16=32'b00000000000000000000000000001100 DAT32=32'b00000000000000000000000000001101 ACM=32'b00000000000000000000000000001110 ACC=32'b00000000000000000000000000001111 RAM=32'b00000000000000000000000000010000 iIFNOT=32'b00000000000000000000000000000000 iNOTIF=32'b00000000000000000000000000000000 iIF=32'b00000000000000000000000000000001 iUNTIL=32'b00000000000000000000000000000000 iNOTUNTIL=32'b00000000000000000000000000000001 iUNTILNOT=32'b00000000000000000000000000000001 iWHILE=32'b00000000000000000000000000000001 iZZERO=8'b00001000 iNEGATIVE=8'b00000100 iZERO=8'b00000010 iLTE_ZERO=8'b00000110 iALWAYS=8'b00000001 iINPUT0=12'b000000010000 iINPUT1=12'b000000100000 iINPUT2=12'b000001000000 iINPUT3=12'b000010000000 iINPUT4=12'b000100000000 iINPUT5=12'b001000000000 iINPUT6=12'b010000000000 iINPUT7=12'b100000000000 iINPUT8=16'b0001000000000000 iINPUT9=16'b0010000000000000 iINPUT10=16'b0100000000000000 iINPUT11=16'b1000000000000000 iINPUT12=20'b00010000000000000000 iINPUT13=20'b00100000000000000000 iINPUT14=20'b01000000000000000000 iINPUT15=20'b10000000000000000000 iINPUT16=24'b000100000000000000000000 iINPUT17=24'b001000000000000000000000 iINPUT18=24'b010000000000000000000000 iINPUT19=24'b100000000000000000000000 iINPUT20=28'b0001000000000000000000000000 iINPUT21=28'b0010000000000000000000000000 iINPUT22=28'b0100000000000000000000000000 iINPUT23=28'b1000000000000000000000000000 iINPUT24=32'b00010000000000000000000000000000 iINPUT25=32'b00100000000000000000000000000000 iINPUT26=32'b01000000000000000000000000000000 iINPUT27=32'b10000000000000000000000000000000 iANYINPUT=32'b01111111111111111111111111110000 ALWAYS=8'b00000001 ZZERO=8'b00001000 NEGATIVE=8'b00000100 ZERO=8'b00000010 LTE_ZERO=8'b00000110 INPUT0=12'b000000010000 INPUT1=12'b000000100000 INPUT2=12'b000001000000 INPUT3=12'b000010000000 INPUT4=12'b000100000000 INPUT5=12'b001000000000 INPUT6=12'b010000000000 INPUT7=12'b100000000000 INPUT8=16'b0001000000000000 INPUT9=16'b0010000000000000 INPUT10=16'b0011000000000000 INPUT11=16'b1000000000000000 INPUT12=20'b00010000000000000000 INPUT13=20'b00100000000000000000 INPUT14=20'b01000000000000000000 INPUT15=20'b10000000000000000000 INPUT16=24'b000100000000000000000000 INPUT17=24'b001000000000000000000000 INPUT18=24'b001100000000000000000000 INPUT19=24'b100000000000000000000000 INPUT20=28'b0001000000000000000000000000 INPUT21=28'b0010000000000000000000000000 INPUT22=28'b0100000000000000000000000000 INPUT23=28'b1000000000000000000000000000 INPUT24=32'b00010000000000000000000000000000 INPUT25=32'b00100000000000000000000000000000 INPUT26=32'b01000000000000000000000000000000 INPUT27=32'b01000000000000000000000000000000 ANYINPUT=32'b01111111111111111111111111110000 iLOADLOOP=32'b00000000000000000001100000000000 iDECLOOP=32'b00000000000000000001100100000000 iINCLOOP=32'b00000000000000000001101000000000 iLOOPZ=32'b00000000000000000000000000001000 LOOPZ=32'b00000000000000000000000000001000 EN_USER=32'b00000000000000000000000000000000 AW=32'b00000000000000000000000000001101 DW=32'b00000000000000000000000000100000 SW=32'b00000000000000000000000000000001 IW=32'b00000000000000000000000000000101 FW=32'b00000000000000000000000000000101 iJUMP=32'b00000000000000000010001000000000 iCALL=32'b00000000000000000010001100000000 iRETURN=32'b00000000000000000010010000000000 iRETISR=32'b00000000000000000010010100000000 iWAIT=32'b00000000000000000010011000000000 iHALT=32'b00000000000000000010011000000000 iINC=32'b00000000000000000000001100000000 iACM_CTRLSTAT=8'b00000000 iACM_ADDR_ADDR=8'b00000100 iACM_DATA_ADDR=8'b00001000 iADC_CTRL2_HI_ADDR=8'b00010000 iADC_STAT_HI_ADDR=8'b00100000 Label_Wait_For_DFE_Trigger=32'b00000000000000000000000000000000 Label_DFE_Enable=32'b00000000000000000000000000000011 Label_WaitCalibrate=32'b00000000000000000000000000001100 Label_Calibrate_Done=32'b00000000000000000000000000001111 Label_Wait_In_Loop=32'b00000000000000000000000000010010 Generated name = CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2 Running optimization stage 1 on CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2 ....... @W:CG133 : coreabc.v(696) | Object MULT is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(697) | Object A is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(698) | Object B is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(1358) | Object b is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : coreabc.v(234) | Removing wire DEBUG1, as there is no assignment to it. @W:CG360 : coreabc.v(235) | Removing wire DEBUG2, as there is no assignment to it. @W:CG360 : coreabc.v(236) | Removing wire DEBUGBLK_RESETN, as there is no assignment to it. @W:CG133 : coreabc.v(262) | Object iii is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : coreabc.v(263) | Object RAMDOUTXX is declared but not assigned. Either assign a value or remove the declaration. @W:CG134 : coreabc.v(267) | No assignment to bit 5 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 6 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 7 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 8 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 9 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 10 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 11 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 12 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 13 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 14 of ins_addr @W:CG134 : coreabc.v(267) | No assignment to bit 15 of ins_addr Running optimization stage 1 on CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1 ....... @W:CL169 : coreabc.v(1041) | Pruning unused register ZREGISTER[0]. Make sure that there are no unused intermediate registers. @W:CL169 : coreabc.v(1041) | Pruning unused register GETINST. Make sure that there are no unused intermediate registers. @W:CL169 : coreabc.v(511) | Pruning unused register UROM.upper_addr[7:0]. Make sure that there are no unused intermediate registers. @W:CL208 : coreabc.v(1041) | All reachable assignments to bit 4 of STKPTR[7:0] assign 1, register removed by optimization. @W:CL208 : coreabc.v(1041) | All reachable assignments to bit 5 of STKPTR[7:0] assign 1, register removed by optimization. @W:CL208 : coreabc.v(1041) | All reachable assignments to bit 6 of STKPTR[7:0] assign 1, register removed by optimization. @W:CL208 : coreabc.v(1041) | All reachable assignments to bit 7 of STKPTR[7:0] assign 1, register removed by optimization. @W:CL207 : coreabc.v(1041) | All reachable assignments to ISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(1041) | All reachable assignments to DOISR assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_ZERO assign 0, register removed by optimization. @W:CL207 : coreabc.v(818) | All reachable assignments to ISR_ACCUM_NEG assign 0, register removed by optimization. @W:CL260 : coreabc.v(494) | Pruning register bit 1 of UROM.INSTR_SLOT[1:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CG364 : CoreABC_Inst.v(109) | Synthesizing module CoreABC_Inst in library work. Running optimization stage 1 on CoreABC_Inst ....... @N:CG364 : Flag_for_RXPLL_lock.v(26) | Synthesizing module Flag_for_RXPLL_lock in library work. @N:CG179 : Flag_for_RXPLL_lock.v(52) | Removing redundant assignment. Running optimization stage 1 on Flag_for_RXPLL_lock ....... @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(40) | Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(40) | Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(40) | Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(40) | Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(40) | Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(1714) | Synthesizing module INIT in library work. Running optimization stage 1 on INIT ....... @W:CG1283 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(50) | Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(216) | Synthesizing module BANKEN in library work. Running optimization stage 1 on BANKEN ....... @N:CG364 : acg5.v(504) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : acg5.v(500) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(5) | Synthesizing module INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR in library work. Running optimization stage 1 on INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR ....... @W:CL168 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(52) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v(51) | Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : INIT_MONITOR.v(82) | Synthesizing module INIT_MONITOR in library work. Running optimization stage 1 on INIT_MONITOR ....... @N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @W:CG1283 : PF_CCC_50_PF_CCC_50_0_PF_CCC.v(39) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(8364) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : PF_CCC_50_PF_CCC_50_0_PF_CCC.v(5) | Synthesizing module PF_CCC_50_PF_CCC_50_0_PF_CCC in library work. Running optimization stage 1 on PF_CCC_50_PF_CCC_50_0_PF_CCC ....... @N:CG364 : PF_CCC_50.v(263) | Synthesizing module PF_CCC_50 in library work. Running optimization stage 1 on PF_CCC_50 ....... @N:CG364 : polarfire_syn_comps.v(1565) | Synthesizing module ICB_CLKDIV in library work. Running optimization stage 1 on ICB_CLKDIV ....... @N:CG364 : PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v(5) | Synthesizing module PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV in library work. Running optimization stage 1 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV ....... @N:CG364 : PF_CLK_DIV_C0.v(24) | Synthesizing module PF_CLK_DIV_C0 in library work. Running optimization stage 1 on PF_CLK_DIV_C0 ....... @N:CG364 : polarfire_syn_comps.v(6869) | Synthesizing module OSC_RC160MHZ in library work. Running optimization stage 1 on OSC_RC160MHZ ....... @N:CG364 : PF_OSC_160_PF_OSC_160_0_PF_OSC.v(5) | Synthesizing module PF_OSC_160_PF_OSC_160_0_PF_OSC in library work. Running optimization stage 1 on PF_OSC_160_PF_OSC_160_0_PF_OSC ....... @W:CL168 : PF_OSC_160_PF_OSC_160_0_PF_OSC.v(15) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : PF_OSC_160.v(27) | Synthesizing module PF_OSC_160 in library work. Running optimization stage 1 on PF_OSC_160 ....... @N:CG364 : polarfire_syn_comps.v(8786) | Synthesizing module TX_PLL in library work. Running optimization stage 1 on TX_PLL ....... @N:CG364 : PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL.v(5) | Synthesizing module PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL in library work. Running optimization stage 1 on PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL ....... @N:CG364 : PF_TX_PLL_0.v(50) | Synthesizing module PF_TX_PLL_0 in library work. Running optimization stage 1 on PF_TX_PLL_0 ....... @N:CG364 : acg5.v(133) | Synthesizing module OR2 in library work. Running optimization stage 1 on OR2 ....... @N:CG364 : acg5.v(484) | Synthesizing module RCLKINT in library work. Running optimization stage 1 on RCLKINT ....... @W:CG1283 : PF_XCVR_0_I_XCVR_PF_XCVR.v(317) | Type of parameter INTERFACE_LEVEL on the instance LANE0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(14615) | Synthesizing module XCVR_PMA in library work. Running optimization stage 1 on XCVR_PMA ....... @N:CG364 : PF_XCVR_0_I_XCVR_PF_XCVR.v(5) | Synthesizing module PF_XCVR_0_I_XCVR_PF_XCVR in library work. Running optimization stage 1 on PF_XCVR_0_I_XCVR_PF_XCVR ....... @N:CG364 : polarfire_syn_comps.v(10938) | Synthesizing module XCVR_APB_LINK_V in library work. Running optimization stage 1 on XCVR_APB_LINK_V ....... @N:CG364 : PF_XCVR_APBLINK_V.v(21) | Synthesizing module PF_XCVR_APBLINK_V in library work. Running optimization stage 1 on PF_XCVR_APBLINK_V ....... @N:CG364 : CORELANEMSTR.v(58) | Synthesizing module CORELANEMSTR in library work. MODE=32'b00000000000000000000000000000011 SIMULATION_MODE=32'b00000000000000000000000000000001 Generated name = CORELANEMSTR_3s_1s @N:CG364 : CORELANEMSTRmode1.v(64) | Synthesizing module CORELANEMSTRmode1 in library work. AUTO=32'b00000000000000000000000000000000 SZ_RQCODE=32'b00000000000000000000000000000011 RQC_L2D=3'b000 RQC_L2R=3'b001 RQC_PCSRST0=3'b010 RQC_PCSRST1=3'b011 RQC_TGLCALRST=3'b100 RQC_TGLRUNCAL=3'b101 RQC_READDFC=3'b110 MIDLE=4'b0000 MSLO=4'b0001 MALF=4'b0010 MWRDY=4'b0011 MPPOL=4'b0100 MSTMR=4'b0101 MRDFC=4'b0110 MCHKDONE=4'b0111 MRXOK=4'b1000 MPRECAL=4'b1001 MCAL1=4'b1010 MCAL2=4'b1011 MCAL3=4'b1100 Generated name = CORELANEMSTRmode1_Z3 Running optimization stage 1 on CORELANEMSTRmode1_Z3 ....... @W:CL169 : CORELANEMSTRmode1.v(190) | Pruning unused register firstcal. Make sure that there are no unused intermediate registers. Running optimization stage 1 on CORELANEMSTR_3s_1s ....... @N:CG364 : CORELCKMGT.v(33) | Synthesizing module CORELCKMGT in library work. DEBOUNCEUS=32'b00000000000000000000000000001010 IQUIETUS=32'b00000000000000000000000000001010 ILOCKDLYUS=32'b00000000000000000000000000000000 SDWIN=32'b00000000000000000000000000000000 SDTHR=32'b00000000000000000000000000000000 DEBOUNCETAP=32'b00000000000000000000000000000000 IQWAIT=32'b00000000000000000000000000000001 IQTAP=32'b00000000000000000000000000000000 ILWAIT=32'b00000000000000000000000000000000 ILTAP=32'b00000000000000000000000000000000 WINTAP=32'b00000000000000000000000000000000 WINMAX=32'b00000000000000000000000011111111 SIGMIN=32'b00000000000000000000000001000000 SZ_INTG=32'b00000000000000000000000000000111 REQL2R=4'b0000 QPKDET=4'b0001 WINRST=4'b0010 WINCNT=4'b0011 IPLCK1=4'b0100 IPLCK2=4'b0101 REQNRM=4'b0110 CDRNRM=4'b0111 Generated name = CORELCKMGT_Z4 Running optimization stage 1 on CORELCKMGT_Z4 ....... @W:CL169 : CORELCKMGT.v(211) | Pruning unused register neverlocked. Make sure that there are no unused intermediate registers. @N:CG364 : polarfire_syn_comps.v(17436) | Synthesizing module CORELNKTMR_V in library work. Running optimization stage 1 on CORELNKTMR_V ....... @W:CG813 : CORERFD.v(79) | Rounding real from 4398.826979 to 4399 (simulation mismatch possible) @W:CG813 : CORERFD.v(80) | Rounding real from 4154.447703 to 4154 (simulation mismatch possible) @N:CG364 : CORERFDsync.v(8) | Synthesizing module CORERFDsync in library work. SIGNAL_WIDTH=32'b00000000000000000000000000000001 INIT_VAL=1'b0 Generated name = CORERFDsync_1s_0 Running optimization stage 1 on CORERFDsync_1s_0 ....... @N:CG364 : CORERFDplsgen.v(26) | Synthesizing module CORERFDplsgen in library work. NBITS=32'b00000000000000000000000000000010 Generated name = CORERFDplsgen_2s Running optimization stage 1 on CORERFDplsgen_2s ....... @N:CG364 : CORERFDgrycnt.v(26) | Synthesizing module CORERFDgrycnt in library work. NBITS=32'b00000000000000000000000000000010 Generated name = CORERFDgrycnt_2s Running optimization stage 1 on CORERFDgrycnt_2s ....... @N:CG364 : CORERFDsyncen.v(20) | Synthesizing module CORERFDsyncen in library work. SIGNAL_WIDTH=32'b00000000000000000000000000000010 INIT_VAL=2'b00 Generated name = CORERFDsyncen_2s_0 Running optimization stage 1 on CORERFDsyncen_2s_0 ....... @N:CG364 : CORERFDbincnt.v(26) | Synthesizing module CORERFDbincnt in library work. NBITS=32'b00000000000000000000000000001010 Generated name = CORERFDbincnt_10s Running optimization stage 1 on CORERFDbincnt_10s ....... @N:CG364 : CORERFDsmplcnt.v(26) | Synthesizing module CORERFDsmplcnt in library work. CTR_SIZE=32'b00000000000000000000000000001010 Generated name = CORERFDsmplcnt_10s Running optimization stage 1 on CORERFDsmplcnt_10s ....... @N:CG364 : CORERFDshcnt.v(26) | Synthesizing module CORERFDshcnt in library work. CTR_SIZE=32'b00000000000000000000000000000110 ROT_SIZE=32'b00000000000000000000000000000010 Generated name = CORERFDshcnt_6s_2s Running optimization stage 1 on CORERFDshcnt_6s_2s ....... @N:CG364 : CORERFDfrqerrarb.v(26) | Synthesizing module CORERFDfrqerrarb in library work. ROT_SH_CTR_SIZE=32'b00000000000000000000000000000110 Generated name = CORERFDfrqerrarb_6s Running optimization stage 1 on CORERFDfrqerrarb_6s ....... @N:CG364 : CORERFDsicr.v(23) | Synthesizing module CORERFDsicr in library work. ROT_SH_CTR_SIZE=32'b00000000000000000000000000000110 SAMPLE_CTR_SIZE=32'b00000000000000000000000000001010 PH_ROT_SIZE=32'b00000000000000000000000000000010 Generated name = CORERFDsicr_6s_10s_2s Running optimization stage 1 on CORERFDsicr_6s_10s_2s ....... @N:CG364 : CORERFD.v(30) | Synthesizing module CORERFD in library work. PPM=32'b00000000000000000000111110100000 SAMPLE_CTR_SIZE=32'b00000000000000000000000000001010 ROT_SH_CTR_SIZE=32'b00000000000000000000000000000110 SAMPLECNT=32'b00000000000000000000001111111111 ROTSH=32'b00000000000000000000000000010010 PPMHIGH=32'b00000000000000000001000100101111 PPMLOW=32'b00000000000000000001000000111010 HIST=32'b00000000000000000000000000000010 UNLOCK_HIST=32'b00000000000000000000000000000010 LOCK_HIST=32'b00000000000000000000000000000000 Generated name = CORERFD_4000s_10s_6s_1023s_18s_4399s_4154s_2s_2s_0s_Z5 Running optimization stage 1 on CORERFD_4000s_10s_6s_1023s_18s_4399s_4154s_2s_2s_0s_Z5 ....... @N:CG364 : acg5.v(17) | Synthesizing module DFN1 in library work. Running optimization stage 1 on DFN1 ....... @N:CG364 : acg5.v(1647) | Synthesizing module SLE_DEBUG in library work. @W:CG146 : acg5.v(1647) | Creating black box for empty module SLE_DEBUG @N:CG364 : PF_XCVR_0.v(68) | Synthesizing module PF_XCVR_0 in library work. Running optimization stage 1 on PF_XCVR_0 ....... @N:CG364 : polarfire_syn_comps.v(874) | Synthesizing module DRI in library work. Running optimization stage 1 on DRI ....... @N:CG364 : PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v(5) | Synthesizing module PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI in library work. Running optimization stage 1 on PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI ....... @W:CL168 : PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v(393) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v(392) | Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : PF_XCVR_DRI.v(81) | Synthesizing module PF_XCVR_DRI in library work. Running optimization stage 1 on PF_XCVR_DRI ....... @N:CG364 : polarfire_syn_comps.v(15445) | Synthesizing module XCVR_REF_CLK in library work. Running optimization stage 1 on XCVR_REF_CLK ....... @N:CG364 : PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v(5) | Synthesizing module PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK in library work. Running optimization stage 1 on PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK ....... @W:CL168 : PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v(25) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v(24) | Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : PF_XCVR_REF_CLK_0.v(27) | Synthesizing module PF_XCVR_REF_CLK_0 in library work. Running optimization stage 1 on PF_XCVR_REF_CLK_0 ....... @N:CG364 : prbs_asic_chk.v(1) | Synthesizing module prbs_asic_chk in library work. @W:CG133 : prbs_asic_chk.v(160) | Object O1 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on prbs_asic_chk ....... @W:CL169 : prbs_asic_chk.v(251) | Pruning unused register IIl. Make sure that there are no unused intermediate registers. @N:CG364 : PRBS_chk.v(26) | Synthesizing module PRBS_chk in library work. Running optimization stage 1 on PRBS_chk ....... @W:CL208 : PRBS_chk.v(116) | All reachable assignments to bit 0 of prbs_rxn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_chk.v(116) | All reachable assignments to bit 2 of prbs_rxn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_chk.v(116) | All reachable assignments to bit 3 of prbs_rxn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_chk.v(116) | All reachable assignments to bit 4 of prbs_rxn[4:0] assign 0, register removed by optimization. @N:CG364 : prbs_asic_gen.v(1) | Synthesizing module prbs_asic_gen in library work. Running optimization stage 1 on prbs_asic_gen ....... @N:CG364 : PRBS_gen.v(27) | Synthesizing module PRBS_gen in library work. Running optimization stage 1 on PRBS_gen ....... @W:CL208 : PRBS_gen.v(71) | All reachable assignments to bit 0 of prbs_txn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_gen.v(71) | All reachable assignments to bit 2 of prbs_txn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_gen.v(71) | All reachable assignments to bit 3 of prbs_txn[4:0] assign 0, register removed by optimization. @W:CL208 : PRBS_gen.v(71) | All reachable assignments to bit 4 of prbs_txn[4:0] assign 0, register removed by optimization. @N:CG364 : corereset_pf.v(21) | Synthesizing module reset_syn_rx_reset_syn_rx_0_CORERESET_PF in library work. Running optimization stage 1 on reset_syn_rx_reset_syn_rx_0_CORERESET_PF ....... @N:CG364 : reset_syn_rx.v(21) | Synthesizing module reset_syn_rx in library work. Running optimization stage 1 on reset_syn_rx ....... @N:CG364 : corereset_pf.v(21) | Synthesizing module reset_syn_tx_reset_syn_tx_0_CORERESET_PF in library work. Running optimization stage 1 on reset_syn_tx_reset_syn_tx_0_CORERESET_PF ....... @N:CG364 : reset_syn_tx.v(21) | Synthesizing module reset_syn_tx in library work. Running optimization stage 1 on reset_syn_tx ....... @N:CG364 : reset_logic.v(9) | Synthesizing module reset_logic in library work. Running optimization stage 1 on reset_logic ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on reset_logic ....... Running optimization stage 2 on reset_syn_tx ....... Running optimization stage 2 on reset_syn_tx_reset_syn_tx_0_CORERESET_PF ....... @N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1. Running optimization stage 2 on reset_syn_rx ....... Running optimization stage 2 on reset_syn_rx_reset_syn_rx_0_CORERESET_PF ....... @N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1. Running optimization stage 2 on PRBS_gen ....... Running optimization stage 2 on prbs_asic_gen ....... @N:CL159 : prbs_asic_gen.v(5) | Input custom_pattern is unused. Running optimization stage 2 on PRBS_chk ....... Running optimization stage 2 on prbs_asic_chk ....... @N:CL201 : prbs_asic_chk.v(780) | Trying to extract state machine for register i10. Extracted state machine for register i10 State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 @N:CL159 : prbs_asic_chk.v(8) | Input custom_sel is unused. @N:CL159 : prbs_asic_chk.v(9) | Input custom_auto is unused. @N:CL159 : prbs_asic_chk.v(11) | Input custom_pattern is unused. @N:CL159 : prbs_asic_chk.v(13) | Input custom_chk is unused. Running optimization stage 2 on PF_XCVR_REF_CLK_0 ....... Running optimization stage 2 on PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK ....... Running optimization stage 2 on XCVR_REF_CLK ....... Running optimization stage 2 on PF_XCVR_DRI ....... Running optimization stage 2 on PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI ....... Running optimization stage 2 on DRI ....... Running optimization stage 2 on PF_XCVR_0 ....... Running optimization stage 2 on DFN1 ....... Running optimization stage 2 on CORERFD_4000s_10s_6s_1023s_18s_4399s_4154s_2s_2s_0s_Z5 ....... Running optimization stage 2 on CORERFDsicr_6s_10s_2s ....... Running optimization stage 2 on CORERFDfrqerrarb_6s ....... Running optimization stage 2 on CORERFDshcnt_6s_2s ....... Running optimization stage 2 on CORERFDsmplcnt_10s ....... Running optimization stage 2 on CORERFDbincnt_10s ....... Running optimization stage 2 on CORERFDsyncen_2s_0 ....... Running optimization stage 2 on CORERFDgrycnt_2s ....... Running optimization stage 2 on CORERFDplsgen_2s ....... Running optimization stage 2 on CORERFDsync_1s_0 ....... Running optimization stage 2 on CORELNKTMR_V ....... Running optimization stage 2 on CORELCKMGT_Z4 ....... @N:CL201 : CORELCKMGT.v(211) | Trying to extract state machine for register fsm_st. Extracted state machine for register fsm_st State machine has 6 reachable states with original encodings of: 000 001 010 011 110 111 @W:CL246 : CORELCKMGT.v(83) | Input port bits 20 to 1 of LTPULSE[20:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORELANEMSTRmode1_Z3 ....... @N:CL201 : CORELANEMSTRmode1.v(190) | Trying to extract state machine for register rmfsm. Extracted state machine for register rmfsm State machine has 13 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 @W:CL246 : CORELANEMSTRmode1.v(73) | Input port bits 20 to 1 of LTPULSE[20:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORELANEMSTR_3s_1s ....... Running optimization stage 2 on PF_XCVR_APBLINK_V ....... Running optimization stage 2 on XCVR_APB_LINK_V ....... Running optimization stage 2 on PF_XCVR_0_I_XCVR_PF_XCVR ....... Running optimization stage 2 on XCVR_PMA ....... Running optimization stage 2 on RCLKINT ....... Running optimization stage 2 on OR2 ....... Running optimization stage 2 on PF_TX_PLL_0 ....... Running optimization stage 2 on PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL ....... Running optimization stage 2 on TX_PLL ....... Running optimization stage 2 on PF_OSC_160 ....... Running optimization stage 2 on PF_OSC_160_PF_OSC_160_0_PF_OSC ....... Running optimization stage 2 on OSC_RC160MHZ ....... Running optimization stage 2 on PF_CLK_DIV_C0 ....... Running optimization stage 2 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV ....... Running optimization stage 2 on ICB_CLKDIV ....... Running optimization stage 2 on PF_CCC_50 ....... Running optimization stage 2 on PF_CCC_50_PF_CCC_50_0_PF_CCC ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on INIT_MONITOR ....... Running optimization stage 2 on INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on BANKEN ....... Running optimization stage 2 on INIT ....... Running optimization stage 2 on Flag_for_RXPLL_lock ....... Running optimization stage 2 on CoreABC_Inst ....... Running optimization stage 2 on CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2 ....... Running optimization stage 2 on CoreABC_Inst_CoreABC_Inst_0_RAM128X8 ....... @N:CL159 : ram128x8_polarfire.v(34) | Input RESETN is unused. Running optimization stage 2 on RAM1K20 ....... Running optimization stage 2 on CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s ....... Running optimization stage 2 on CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1 ....... @N:CL201 : coreabc.v(1041) | Trying to extract state machine for register ICYCLE. Extracted state machine for register ICYCLE State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL159 : coreabc.v(135) | Input PSLVERR_M is unused. @N:CL159 : coreabc.v(139) | Input INTREQ is unused. @N:CL159 : coreabc.v(142) | Input INITDATVAL is unused. @N:CL159 : coreabc.v(143) | Input INITDONE is unused. @N:CL159 : coreabc.v(144) | Input INITADDR is unused. @N:CL159 : coreabc.v(145) | Input INITDATA is unused. @N:CL159 : coreabc.v(153) | Input PSEL_S is unused. @N:CL159 : coreabc.v(154) | Input PENABLE_S is unused. @N:CL159 : coreabc.v(155) | Input PWRITE_S is unused. @N:CL159 : coreabc.v(156) | Input PADDR_S is unused. @N:CL159 : coreabc.v(157) | Input PWDATA_S is unused. Running optimization stage 2 on AND2 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:22s; Memory used current: 123MB peak: 124MB) Process took 0h:00m:22s realtime, 0h:00m:22s cputime Process completed successfully. # Thu Jan 7 09:25:35 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Jan 7 09:25:36 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:23s; CPU Time elapsed 0h:00m:23s; Memory used current: 23MB peak: 32MB) Process took 0h:00m:23s realtime, 0h:00m:23s cputime Process completed successfully. # Thu Jan 7 09:25:36 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 101MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Jan 7 09:25:38 2021 ###########################################################] Premap Report # Thu Jan 7 09:25:40 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Reading constraint file: C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(11) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 137MB peak: 137MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 137MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 137MB) Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 137MB peak: 139MB) @W:BN132 : coreabc.v(494) | Removing sequential instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_SLOT[0] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_MUXC. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance reset_logic_0.reset_syn_rx_0.reset_syn_rx_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance reset_logic_0.reset_syn_tx_0.reset_syn_tx_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND. @N:BN362 : prbs_chk.v(116) | Removing sequential instance prbs_rxn[1] (in view: work.PRBS_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(780) | Removing sequential instance lO0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(414) | Removing sequential instance prbs_err[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : prbs_gen.v(71) | Removing sequential instance prbs_txn[1] (in view: work.PRBS_gen(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_chk.v(96) | Removing sequential instance rx_val_o (in view: work.PRBS_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(848) | Removing sequential instance lo0[2:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(848) | Removing sequential instance Io0[2:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=952 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:02s; Memory used current: 174MB peak: 174MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ 0 - PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK 160.0 MHz 6.250 declared default_clkgroup 2 1 . PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 50.0 MHz 20.000 generated (from PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK) default_clkgroup 135 1 . PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV 40.0 MHz 25.000 generated (from PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK) default_clkgroup 48 0 - PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R 257.8 MHz 3.879 declared default_clkgroup 170 0 - PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R 257.8 MHz 3.879 declared default_clkgroup 154 0 - REF_CLK_PAD_P 125.0 MHz 8.000 declared default_clkgroup 1 0 - System 100.0 MHz 10.000 system system_clkgroup 0 ============================================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK 2 PF_OSC_160_0.PF_OSC_160_0.I_OSC_160.CLK(OSC_RC160MHZ) PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD.A - PF_OSC_160_0.PF_OSC_160_0.I_OSC_160_INT.I(BUFG) PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 135 PF_CCC_50_0.PF_CCC_50_0.pll_inst_0.OUT0(PLL) PF_XCVR_DRI_0.PF_XCVR_DRI_0.I_DRI.PCLK - PF_CCC_50_0.PF_CCC_50_0.clkint_0.I(BUFG) PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV 48 PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD.Y_DIV(ICB_CLKDIV) PF_XCVR_0_0.I_XCVR_LANE0_SD_DFN1.CLK - - PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R 170 PF_XCVR_0_0.I_XCVR.LANE0.TX_CLK_R(XCVR_PMA) reset_logic_0.reset_syn_tx_0.reset_syn_tx_0.dff_0.C - PF_XCVR_0_0.I_XCVR.LANE0_TX_rclkint.A(RCLKINT) PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R 154 PF_XCVR_0_0.I_XCVR.LANE0.RX_CLK_R(XCVR_PMA) reset_logic_0.reset_syn_rx_0.reset_syn_rx_0.dff_0.C PRBS_chk_0.prbs_asic_chk_inst.ol0.D[0] PF_XCVR_0_0.I_XCVR.LANE0_RX_rclkint.A(RCLKINT) REF_CLK_PAD_P 1 REF_CLK_PAD_P(port) - PF_XCVR_0_0.I_XCVR.LANE0.REF_CLK_P PF_XCVR_REF_CLK_0_0.PF_XCVR_REF_CLK_0_0.I_IO.PAD_P(XCVR_REF_CLK) System 0 - - - - ======================================================================================================================================================================================================================================================================================= @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 173MB peak: 175MB) Encoding state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)); safe FSM implementation is not required. Encoding state machine rmfsm[12:0] (in view: work.CORELANEMSTRmode1_Z3(verilog)) original code -> new code 0000 -> 0000000000001 0001 -> 0000000000010 0010 -> 0000000000100 0011 -> 0000000001000 0100 -> 0000000010000 0101 -> 0000000100000 0110 -> 0000001000000 0111 -> 0000010000000 1000 -> 0000100000000 1001 -> 0001000000000 1010 -> 0010000000000 1011 -> 0100000000000 1100 -> 1000000000000 Encoding state machine fsm_st[5:0] (in view: work.CORELCKMGT_Z4(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 110 -> 010000 111 -> 100000 Encoding state machine i10[5:0] (in view: work.prbs_asic_chk(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 @N:BN362 : prbs_asic_chk.v(780) | Removing sequential instance i10[5] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(780) | Removing sequential instance i10[0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 178MB peak: 178MB) Finished constraint checker (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:03s; Memory used current: 179MB peak: 179MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:04s; Memory used current: 92MB peak: 179MB) Process took 0h:00m:05s realtime, 0h:00m:04s cputime # Thu Jan 7 09:25:45 2021 ###########################################################] Map & Optimize Report # Thu Jan 7 09:25:46 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I52881 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 123MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 166MB peak: 166MB) @N:MO111 : ramblocks.v(41) | Tristate driver DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND. @N:MO111 : ramblocks.v(40) | Tristate driver SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND. @W:BN132 : prbs_asic_chk.v(36) | Removing sequential instance PRBS_chk_0.prbs_asic_chk_inst.OI because it is equivalent to instance PRBS_chk_0.prbs_asic_chk_inst.I. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : prbs_asic_chk.v(36) | Removing sequential instance PRBS_chk_0.prbs_asic_chk_inst.l because it is equivalent to instance PRBS_chk_0.prbs_asic_chk_inst.II. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @W:FA239 : instructions.v(82) | ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : instructions.v(82) | ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : instructions.v(82) | ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : instructions.v(82) | ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : instructions.v(82) | ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : instructions.v(82) | ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : instructions.v(82) | Found ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 12 words by 2 bits. @W:FA239 : instructions.v(82) | ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : instructions.v(82) | Found ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 12 words by 2 bits. @W:FA239 : instructions.v(82) | ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : instructions.v(82) | Found ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 17 words by 3 bits. @W:FA239 : instructions.v(82) | ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : instructions.v(82) | Found ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 13 words by 7 bits. @W:FA239 : instructions.v(82) | ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : instructions.v(82) | Found ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 20 words by 6 bits. @N:BN362 : prbs_asic_chk.v(251) | Removing sequential instance IOl[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(780) | Removing sequential instance Oo0[3:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(414) | Removing sequential instance oIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(390) | Removing sequential instance lOl[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(390) | Removing sequential instance oOl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(780) | Removing sequential instance i10[5:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(740) | Removing sequential instance ol0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(414) | Removing sequential instance lIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(390) | Removing sequential instance OIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(740) | Removing sequential instance il0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(414) | Removing sequential instance iIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : prbs_asic_chk.v(390) | Removing sequential instance iOl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 175MB peak: 175MB) Encoding state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coreabc.v(1041) | There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)); safe FSM implementation is not required. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[19] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[16] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[15] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[14] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[13] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[12] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[8] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[7] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[6] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[25] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[24] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[22] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[21] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[20] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[23] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[17] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(494) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[9] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(1041) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[8] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(1041) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[7] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : coreabc.v(1041) | Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[6] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine rmfsm[12:0] (in view: work.CORELANEMSTRmode1_Z3(verilog)) original code -> new code 0000 -> 0000000000001 0001 -> 0000000000010 0010 -> 0000000000100 0011 -> 0000000001000 0100 -> 0000000010000 0101 -> 0000000100000 0110 -> 0000001000000 0111 -> 0000010000000 1000 -> 0000100000000 1001 -> 0001000000000 1010 -> 0010000000000 1011 -> 0100000000000 1100 -> 1000000000000 Encoding state machine fsm_st[5:0] (in view: work.CORELCKMGT_Z4(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 110 -> 010000 111 -> 100000 @N:MO231 : corelckmgt.v(211) | Found counter in view:work.CORELCKMGT_Z4(verilog) instance intg_st[6:0] @N:MO231 : prbs_asic_chk.v(251) | Found counter in view:work.prbs_asic_chk(verilog) instance OoI[7:0] @N:MF179 : prbs_asic_chk.v(385) | Found 40 by 40 bit equality operator ('==') OOl (in view: work.prbs_asic_chk(verilog)) Starting factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 177MB peak: 182MB) Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 181MB peak: 182MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 183MB peak: 183MB) Starting Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 183MB peak: 183MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 183MB peak: 183MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 183MB peak: 183MB) Finished preparing to map (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 183MB peak: 183MB) Finished technology mapping (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 187MB peak: 187MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:09s -1.49ns 1064 / 424 @N:FX271 : corelanemstrmode1.v(190) | Replicating instance PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ok_st (in view: work.top(verilog)) with 4 loads 1 time to improve timing. @N:FX271 : corerfd.v(120) | Replicating instance PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock (in view: work.top(verilog)) with 5 loads 1 time to improve timing. Timing driven replication report Added 2 Registers via timing driven replication Added 1 LUTs via timing driven replication @N:MF322 : | Retiming summary: 9 registers retimed to 15 ##### BEGIN RETIMING REPORT ##### Retiming summary : 9 registers retimed to 15 Original and Pipelined registers replaced by retiming : PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[0] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[1] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[2] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[3] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[4] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh[5] PRBS_chk_0.reg_error_out PRBS_chk_0.reg_lock New registers created by retiming : PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_2 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_5 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_6 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_7 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xfreq_err_arb.error_ret_8 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[0] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[1] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[2] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[3] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[4] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 PRBS_chk_0.reg_lock_ret PRBS_chk_0.reg_lock_ret_0 ##### END RETIMING REPORT ##### @N:FP130 : | Promoting Net PF_CLK_DIV_C0_0_CLK_OUT on CLKINT I_206 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 188MB peak: 188MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 188MB peak: 189MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 3 non-gated/non-generated clock tree(s) driving 296 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 153 clock pin(s) of sequential element(s) 0 instances converted, 153 sequential instances remain driven by gated/generated clocks ======================================================= Non-Gated/Non-Generated Clocks ======================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ---------------------------------------------------------------------------------------------------------------------------------------------- ClockId0003 PF_XCVR_0_0.I_XCVR.LANE0 clock definition on XCVR_PMA 177 PF_XCVR_0_0.I_XCVR.LANE0 ClockId0004 PF_XCVR_0_0.I_XCVR.LANE0 clock definition on XCVR_PMA 117 PF_XCVR_0_0.I_XCVR.LANE0 ClockId0005 PF_OSC_160_0.PF_OSC_160_0.I_OSC_160 clock definition on OSC_RC160MHZ 2 PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD ============================================================================================================================================== ======================================================================================= Gated/Generated Clocks ======================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 PF_CCC_50_0.PF_CCC_50_0.pll_inst_0 PLL 104 Flag_for_RXPLL_lock_0.flag_s No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD clock definition on ICB_CLKDIV 49 PF_XCVR_0_0.I_XCVR_LANE0_SD_DFN1 No gated clock conversion method for cell cell:ACG4.DFN1 ====================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 157MB peak: 189MB) Writing Analyst data base C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:11s; Memory used current: 188MB peak: 189MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 189MB peak: 189MB) Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:13s; Memory used current: 186MB peak: 189MB) @W:MT246 : pf_xcvr_0.v(488) | Blackbox CORELNKTMR_V is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : pf_xcvr_apblink_v.v(57) | Blackbox XCVR_APB_LINK_V is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : pf_osc_160_pf_osc_160_0_pf_osc.v(13) | Blackbox OSC_RC160MHZ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : init_monitor_init_monitor_0_pf_init_monitor.v(40) | Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK with period 6.25ns @N:MT615 : | Found clock REF_CLK_PAD_P with period 8.00ns @N:MT615 : | Found clock PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R with period 3.88ns @N:MT615 : | Found clock PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R with period 3.88ns @N:MT615 : | Found clock PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 with period 20.00ns @N:MT615 : | Found clock PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV with period 25.00ns ##### START OF TIMING REPORT #####[ # Timing report written on Thu Jan 7 09:26:00 2021 # Top view: top Requested Frequency: 40.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: -1.413 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 50.0 MHz 6.8 MHz 20.000 147.195 11.914 generated (from PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK) default_clkgroup PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV 40.0 MHz 1.3 MHz 25.000 781.370 -1.413 generated (from PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK) default_clkgroup PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK 160.0 MHz NA 6.250 NA NA declared default_clkgroup PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R 257.8 MHz 8.2 MHz 3.879 121.228 0.409 declared default_clkgroup PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R 257.8 MHz 8.7 MHz 3.879 115.190 -1.340 declared default_clkgroup REF_CLK_PAD_P 125.0 MHz NA 8.000 NA NA declared default_clkgroup System 100.0 MHz 999.0 MHz 10.000 1.001 8.999 system system_clkgroup =============================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform @W:MT116 : | Paths from clock (PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R:r) to clock (PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV:r) are overconstrained because the required time of 0.05 ns is too small. @W:MT116 : | Paths from clock (PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV:r) to clock (PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R:r) are overconstrained because the required time of 0.05 ns is too small. @W:MT116 : | Paths from clock (PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R:r) to clock (PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.12 ns is too small. Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 8.999 | No paths - | No paths - | No paths - System PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 3.879 2.703 | No paths - | No paths - | No paths - System PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 3.879 2.703 | No paths - | No paths - | No paths - System PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 25.000 22.851 | No paths - | No paths - | No paths - PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 3.879 0.271 | No paths - | No paths - | No paths - PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 0.121 -0.771 | No paths - | No paths - | No paths - PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 0.047 -1.340 | No paths - | No paths - | No paths - PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 3.879 3.325 | No paths - | No paths - | No paths - PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 3.879 0.409 | No paths - | No paths - | No paths - PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 20.000 11.914 | No paths - | No paths - | No paths - PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV System | 25.000 23.808 | No paths - | No paths - | No paths - PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 0.047 -1.413 | No paths - | No paths - | No paths - PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 25.000 22.007 | No paths - | No paths - | No paths - =============================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD[2] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE Q UROM\.INSTR_SCMD[2] 0.218 11.914 CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD[1] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE Q UROM\.INSTR_SCMD[1] 0.218 12.005 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r0c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[0] RD_r0c0[0] 3.023 12.522 CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_CMD[1] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE Q UROM\.INSTR_CMD[1] 0.218 12.579 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r1c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[0] RD_r1c0[0] 3.023 12.587 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r0c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[2] RD_r0c0[2] 3.023 12.640 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r0c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[3] RD_r0c0[3] 3.023 12.648 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r0c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[4] RD_r0c0[4] 3.023 12.656 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r1c0.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[2] RD_r1c0[2] 3.023 12.705 CoreABC_Inst_0.CoreABC_Inst_0.URAM\.UR.UG4\.UR32\.ram_r0c1.RAM1K20_R0C0 PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[0] RD_r0c1[0] 3.023 12.709 ============================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- CoreABC_Inst_0.CoreABC_Inst_0.STD_ACCUM_ZERO PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D to_logic_2\.tmp_4[0] 20.000 11.914 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[31] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[31] 20.000 12.863 CoreABC_Inst_0.CoreABC_Inst_0.STD_ACCUM_NEG PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[31] 20.000 12.863 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[30] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[30] 20.000 13.294 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[29] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[29] 20.000 13.302 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[28] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[28] 20.000 13.310 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[27] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[27] 20.000 13.318 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[26] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[26] 20.000 13.326 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[25] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[25] 20.000 13.334 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR[24] PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 SLE D ACCUM_NEXT[24] 20.000 13.342 =========================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 20.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 20.000 - Propagation time: 8.086 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 11.914 Number of logic level(s): 43 Starting point: CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD[2] / Q Ending point: CoreABC_Inst_0.CoreABC_Inst_0.STD_ACCUM_ZERO / D The start point is clocked by PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK The end point is clocked by PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD[2] SLE Q Out 0.218 0.218 r - UROM\.INSTR_SCMD[2] Net - - 0.747 - 19 CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD_RNI16U[1] CFG2 A In - 0.965 r - CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD_RNI16U[1] CFG2 Y Out 0.051 1.016 r - m10_0 Net - - 0.547 - 3 CoreABC_Inst_0.CoreABC_Inst_0.un1_STKPTR_1.to_logic_9[0] CFG4 D In - 1.563 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_STKPTR_1.to_logic_9[0] CFG4 Y Out 0.212 1.775 f - to_logic_9[0] Net - - 0.939 - 55 CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD_RNIQ3L1[2] CFG2 A In - 2.714 f - CoreABC_Inst_0.CoreABC_Inst_0.UROM\.INSTR_SCMD_RNIQ3L1[2] CFG2 Y Out 0.047 2.761 r - xhdl_31\.MSEL_i_0[2] Net - - 0.708 - 15 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2s2 CFG3 C In - 3.469 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2s2 CFG3 Y Out 0.148 3.617 r - ACCUM_NEXT_sm0 Net - - 0.951 - 59 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2_1[0] CFG4 D In - 4.568 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2_1[0] CFG4 Y Out 0.232 4.800 r - ACCUM_NEXT_m2_1[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2[0] CFG4 B In - 4.918 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2[0] CFG4 Y Out 0.088 5.005 r - ACCUM_NEXT_m2[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2_RNIE76E1[0] CFG4 C In - 5.123 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m2_RNIE76E1[0] CFG4 Y Out 0.148 5.271 r - ACCUM_NEXT_m2_RNIE76E1[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIJ1992[0] ARI1 D In - 5.389 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIJ1992[0] ARI1 FCO Out 0.492 5.881 r - ACCUM_NEXT_m6_cry_0 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNIK9LG4[1] ARI1 FCI In - 5.881 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNIK9LG4[1] ARI1 FCO Out 0.008 5.889 r - ACCUM_NEXT_m6_cry_1 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.un1_STKPTR_1.ACCUM_IN_RNI1V786[2] ARI1 FCI In - 5.889 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_STKPTR_1.ACCUM_IN_RNI1V786[2] ARI1 FCO Out 0.008 5.897 r - ACCUM_NEXT_m6_cry_2 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI0DHH8[3] ARI1 FCI In - 5.897 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI0DHH8[3] ARI1 FCO Out 0.008 5.905 r - ACCUM_NEXT_m6_cry_3 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI3VQQA[4] ARI1 FCI In - 5.905 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI3VQQA[4] ARI1 FCO Out 0.008 5.913 r - ACCUM_NEXT_m6_cry_4 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI80RDC[5] ARI1 FCI In - 5.913 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI80RDC[5] ARI1 FCO Out 0.008 5.921 r - ACCUM_NEXT_m6_cry_5 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIBTNAD[6] ARI1 FCI In - 5.921 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIBTNAD[6] ARI1 FCO Out 0.008 5.929 r - ACCUM_NEXT_m6_cry_6 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNI4U4IF[7] ARI1 FCI In - 5.929 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNI4U4IF[7] ARI1 FCO Out 0.008 5.937 r - ACCUM_NEXT_m6_cry_7 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIN0FRH[8] ARI1 FCI In - 5.937 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIN0FRH[8] ARI1 FCO Out 0.008 5.945 r - ACCUM_NEXT_m6_cry_8 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIITR0J[9] ARI1 FCI In - 5.945 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIITR0J[9] ARI1 FCO Out 0.008 5.953 r - ACCUM_NEXT_m6_cry_9 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI9S36L[10] ARI1 FCI In - 5.953 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNI9S36L[10] ARI1 FCO Out 0.008 5.961 r - ACCUM_NEXT_m6_cry_10 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIVHJ6N[11] ARI1 FCI In - 5.961 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIVHJ6N[11] ARI1 FCO Out 0.008 5.969 r - ACCUM_NEXT_m6_cry_11 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIUORBP[12] ARI1 FCI In - 5.969 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIUORBP[12] ARI1 FCO Out 0.008 5.977 r - ACCUM_NEXT_m6_cry_12 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI1NPLR[13] ARI1 FCI In - 5.977 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI1NPLR[13] ARI1 FCO Out 0.008 5.985 r - ACCUM_NEXT_m6_cry_13 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIHVPDT[14] ARI1 FCI In - 5.985 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIHVPDT[14] ARI1 FCO Out 0.008 5.993 r - ACCUM_NEXT_m6_cry_14 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIS5ONV[15] ARI1 FCI In - 5.993 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIS5ONV[15] ARI1 FCO Out 0.008 6.001 r - ACCUM_NEXT_m6_cry_15 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNIL3AJ11[16] ARI1 FCI In - 6.001 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_PSLVERR_S_2_0_RNIL3AJ11[16] ARI1 FCO Out 0.008 6.009 r - ACCUM_NEXT_m6_cry_16 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNITBQJ31[17] ARI1 FCI In - 6.009 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNITBQJ31[17] ARI1 FCO Out 0.008 6.017 r - ACCUM_NEXT_m6_cry_17 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIIK4P51[18] ARI1 FCI In - 6.017 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIIK4P51[18] ARI1 FCO Out 0.008 6.025 r - ACCUM_NEXT_m6_cry_18 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIHC5H71[19] ARI1 FCI In - 6.025 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIHC5H71[19] ARI1 FCO Out 0.008 6.033 r - ACCUM_NEXT_m6_cry_19 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNICJHM91[20] ARI1 FCI In - 6.033 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNICJHM91[20] ARI1 FCO Out 0.008 6.041 r - ACCUM_NEXT_m6_cry_20 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIBUTRB1[21] ARI1 FCI In - 6.041 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIBUTRB1[21] ARI1 FCO Out 0.008 6.049 r - ACCUM_NEXT_m6_cry_21 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIO61KD1[22] ARI1 FCI In - 6.049 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNIO61KD1[22] ARI1 FCO Out 0.008 6.057 r - ACCUM_NEXT_m6_cry_22 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIVPDPF1[23] ARI1 FCI In - 6.057 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_IN_RNIVPDPF1[23] ARI1 FCO Out 0.008 6.065 r - ACCUM_NEXT_m6_cry_23 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNII8HHH1[24] ARI1 FCI In - 6.065 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNII8HHH1[24] ARI1 FCO Out 0.008 6.073 r - ACCUM_NEXT_m6_cry_24 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNI8QK9J1[25] ARI1 FCI In - 6.073 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_m5_RNI8QK9J1[25] ARI1 FCO Out 0.008 6.081 r - ACCUM_NEXT_m6_cry_25 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIDMSHK1[26] ARI1 FCI In - 6.081 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIDMSHK1[26] ARI1 FCO Out 0.008 6.089 r - ACCUM_NEXT_m6_cry_26 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNILL4QL1[27] ARI1 FCI In - 6.089 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNILL4QL1[27] ARI1 FCO Out 0.008 6.097 r - ACCUM_NEXT_m6_cry_27 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI0OC2N1[28] ARI1 FCI In - 6.097 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNI0OC2N1[28] ARI1 FCO Out 0.008 6.105 r - ACCUM_NEXT_m6_cry_28 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIETKAO1[29] ARI1 FCI In - 6.105 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUMULATOR_RNIETKAO1[29] ARI1 FCO Out 0.008 6.113 r - ACCUM_NEXT_m6_cry_29 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.un1_ACCUM_NEXT8_1_0_a3_RNIJR1CR1 ARI1 FCI In - 6.113 r - CoreABC_Inst_0.CoreABC_Inst_0.un1_ACCUM_NEXT8_1_0_a3_RNIJR1CR1 ARI1 FCO Out 0.008 6.121 r - ACCUM_NEXT_m6_cry_30 Net - - 0.000 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_RNO[31] ARI1 FCI In - 6.121 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT_RNO[31] ARI1 S Out 0.300 6.421 r - ACCUM_NEXT_m6[31] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT[31] CFG3 A In - 6.539 r - CoreABC_Inst_0.CoreABC_Inst_0.ACCUM_NEXT[31] CFG3 Y Out 0.051 6.590 r - ACCUM_NEXT[31] Net - - 0.547 - 3 CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4_23[0] CFG4 D In - 7.137 r - CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4_23[0] CFG4 Y Out 0.212 7.349 f - to_logic_2\.tmp_4_23[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4_29[0] CFG4 D In - 7.467 f - CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4_29[0] CFG4 Y Out 0.192 7.659 f - to_logic_2\.tmp_4_29[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4[0] CFG4 D In - 7.777 f - CoreABC_Inst_0.CoreABC_Inst_0.to_logic_2\.tmp_4[0] CFG4 Y Out 0.192 7.968 f - to_logic_2\.tmp_4[0] Net - - 0.118 - 1 CoreABC_Inst_0.CoreABC_Inst_0.STD_ACCUM_ZERO SLE D In - 8.086 f - ============================================================================================================================== Total path delay (propagation time + setup) of 8.086 is 2.821(34.9%) logic and 5.265(65.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ok_st_fast PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rx_ok_st_fast 0.218 -1.413 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q I_XCVR_CORELANEMSTR_0_RQI[0] 0.201 22.007 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[7] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[7] 0.218 22.315 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.sync_hold_st PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q I_XCVR_CORELANEMSTR_0_CALIB_SYNC_HOLD 0.201 22.349 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[3] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[3] 0.218 22.389 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[11] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[11] 0.201 22.440 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[2] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[2] 0.218 22.446 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[4] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[4] 0.218 22.459 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[5] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[5] 0.218 22.462 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rmfsm[9] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE Q rmfsm[9] 0.201 22.500 ================================================================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PRBS_chk_0.reg_lock_ret PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE D PF_XCVR_0_0_LANE0_RX_VAL 0.047 -1.413 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE D un1_rqEn_nx12_i 25.000 22.007 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[0] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN rqEn_nx11 24.873 22.098 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[1] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN rqEn_nx11 24.873 22.098 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[2] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN rqEn_nx11 24.873 22.098 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.lckfrc_st PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN un1_lckfrc_nx5 24.873 22.349 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.fsm_st[0] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE D fsm_st_ns[0] 25.000 22.512 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.lckfrc_st PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE D fsm_st_ns[0] 25.000 22.512 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[0] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN intg_ste 24.873 22.550 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[1] PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV SLE EN intg_ste 24.873 22.550 ================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.047 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.047 - Propagation time: 1.460 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.413 Number of logic level(s): 1 Starting point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ok_st_fast / Q Ending point: PRBS_chk_0.reg_lock_ret / D The start point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK The end point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ok_st_fast SLE Q Out 0.218 0.218 r - rx_ok_st_fast Net - - 0.948 - 1 PF_XCVR_0_0.I_AND2_RX_VAL_0 AND2 B In - 1.166 r - PF_XCVR_0_0.I_AND2_RX_VAL_0 AND2 Y Out 0.169 1.336 r - PF_XCVR_0_0_LANE0_RX_VAL Net - - 0.124 - 2 PRBS_chk_0.reg_lock_ret SLE D In - 1.460 r - ============================================================================================================================== Total path delay (propagation time + setup) of 1.460 is 0.388(26.6%) logic and 1.072(73.4%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 25.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 25.000 - Propagation time: 2.993 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 22.007 Number of logic level(s): 5 Starting point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn / D The start point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn SLE Q Out 0.201 0.201 f - I_XCVR_CORELANEMSTR_0_RQI[0] Net - - 0.974 - 18 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 C In - 1.175 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 Y Out 0.145 1.320 f - N_179 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 D In - 1.867 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 Y Out 0.192 2.059 f - N_184 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 D In - 2.177 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 Y Out 0.192 2.369 f - N_189 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 D In - 2.486 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 Y Out 0.192 2.678 f - rqEn_nx11 Net - - 0.149 - 4 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_RNO CFG3 A In - 2.828 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_RNO CFG3 Y Out 0.048 2.875 f - un1_rqEn_nx12_i Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn SLE D In - 2.993 f - ================================================================================================================================================== Total path delay (propagation time + setup) of 2.993 is 0.969(32.4%) logic and 2.024(67.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 25.000 - Setup time: 0.035 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.965 - Propagation time: 2.828 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 22.138 Number of logic level(s): 4 Starting point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[2] / EN The start point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn SLE Q Out 0.201 0.201 f - I_XCVR_CORELANEMSTR_0_RQI[0] Net - - 0.974 - 18 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 C In - 1.175 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 Y Out 0.145 1.320 f - N_179 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 D In - 1.867 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 Y Out 0.192 2.059 f - N_184 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 D In - 2.177 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 Y Out 0.192 2.369 f - N_189 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 D In - 2.486 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 Y Out 0.192 2.678 f - rqEn_nx11 Net - - 0.149 - 4 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[2] SLE EN In - 2.828 f - ================================================================================================================================================== Total path delay (propagation time + setup) of 2.862 is 0.956(33.4%) logic and 1.906(66.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 25.000 - Setup time: 0.035 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.965 - Propagation time: 2.828 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 22.138 Number of logic level(s): 4 Starting point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[1] / EN The start point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn SLE Q Out 0.201 0.201 f - I_XCVR_CORELANEMSTR_0_RQI[0] Net - - 0.974 - 18 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 C In - 1.175 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 Y Out 0.145 1.320 f - N_179 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 D In - 1.867 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 Y Out 0.192 2.059 f - N_184 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 D In - 2.177 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 Y Out 0.192 2.369 f - N_189 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 D In - 2.486 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 Y Out 0.192 2.678 f - rqEn_nx11 Net - - 0.149 - 4 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[1] SLE EN In - 2.828 f - ================================================================================================================================================== Total path delay (propagation time + setup) of 2.862 is 0.956(33.4%) logic and 1.906(66.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 25.000 - Setup time: 0.035 + Clock delay at ending point: 0.000 (ideal) = Required time: 24.965 - Propagation time: 2.828 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 22.138 Number of logic level(s): 4 Starting point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[0] / EN The start point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn SLE Q Out 0.201 0.201 f - I_XCVR_CORELANEMSTR_0_RQI[0] Net - - 0.974 - 18 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 C In - 1.175 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.o_lckfrc_combo\.rmfsm_nx_15_o2[0] CFG3 Y Out 0.145 1.320 f - N_179 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 D In - 1.867 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2_0 CFG4 Y Out 0.192 2.059 f - N_184 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 D In - 2.177 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o2 CFG4 Y Out 0.192 2.369 f - N_189 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 D In - 2.486 f - PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqEn_combo\.rqEn_nx11_0_o4 CFG4 Y Out 0.192 2.678 f - rqEn_nx11 Net - - 0.149 - 4 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rqCode[0] SLE EN In - 2.828 f - ================================================================================================================================================== Total path delay (propagation time + setup) of 2.862 is 0.956(33.4%) logic and 1.906(66.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_VAL I_XCVR_LANE0_RX_VAL 2.295 0.409 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[33] PF_XCVR_0_0_LANE0_RX_DATA[33] 2.886 0.619 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[36] PF_XCVR_0_0_LANE0_RX_DATA[36] 2.883 0.622 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[39] PF_XCVR_0_0_LANE0_RX_DATA[39] 2.883 0.622 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[35] PF_XCVR_0_0_LANE0_RX_DATA[35] 2.879 0.626 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[34] PF_XCVR_0_0_LANE0_RX_DATA[34] 2.877 0.628 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[27] PF_XCVR_0_0_LANE0_RX_DATA[27] 2.875 0.630 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[29] PF_XCVR_0_0_LANE0_RX_DATA[29] 2.875 0.630 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[3] PF_XCVR_0_0_LANE0_RX_DATA[3] 2.964 0.632 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R XCVR_PMA RX_DATA[32] PF_XCVR_0_0_LANE0_RX_DATA[32] 2.866 0.639 =================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------ PRBS_chk_0.reg_lock_ret PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D PF_XCVR_0_0_LANE0_RX_VAL 3.879 0.409 PRBS_chk_0.prbs_asic_chk_inst.lI[6] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[6] 3.879 0.619 PRBS_chk_0.prbs_asic_chk_inst.lI[0] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[0] 3.879 0.622 PRBS_chk_0.prbs_asic_chk_inst.lI[3] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[3] 3.879 0.622 PRBS_chk_0.prbs_asic_chk_inst.lI[4] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[4] 3.879 0.626 PRBS_chk_0.prbs_asic_chk_inst.lI[5] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[5] 3.879 0.628 PRBS_chk_0.prbs_asic_chk_inst.lI[10] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[10] 3.879 0.630 PRBS_chk_0.prbs_asic_chk_inst.lI[12] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[12] 3.879 0.630 PRBS_chk_0.prbs_asic_chk_inst.ioI[36] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D PF_XCVR_0_0_LANE0_RX_DATA_i[3] 3.879 0.632 PRBS_chk_0.prbs_asic_chk_inst.lI[7] PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R SLE D lI_39[7] 3.879 0.639 ====================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.879 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.879 - Propagation time: 3.470 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.409 Number of logic level(s): 1 Starting point: PF_XCVR_0_0.I_XCVR.LANE0 / RX_VAL Ending point: PRBS_chk_0.reg_lock_ret / D The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin RX_FWF_CLK The end point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------ PF_XCVR_0_0.I_XCVR.LANE0 XCVR_PMA RX_VAL Out 2.295 2.295 r - I_XCVR_LANE0_RX_VAL Net - - 0.948 - 1 PF_XCVR_0_0.I_AND2_RX_VAL_0 AND2 A In - 3.243 r - PF_XCVR_0_0.I_AND2_RX_VAL_0 AND2 Y Out 0.103 3.346 r - PF_XCVR_0_0_LANE0_RX_VAL Net - - 0.124 - 2 PRBS_chk_0.reg_lock_ret SLE D In - 3.470 r - ================================================================================================ Total path delay (propagation time + setup) of 3.470 is 2.398(69.1%) logic and 1.072(30.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock_fast PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q fine_lock_fast 0.218 -1.340 PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q PF_XCVR_0_0_LANE0_RX_READY 0.218 -0.771 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q timeout_o 0.201 0.271 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q un1_rot_sh_3_o[5] 0.218 0.316 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[2] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q un1_rot_sh_3_o[2] 0.218 0.629 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[3] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q un1_rot_sh_3_o[3] 0.218 0.689 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[4] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q un1_rot_sh_3_o[4] 0.218 0.746 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xclk_in_rot_Sync.syncOutput[1] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q clk_ref_rot[1] 0.218 0.829 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_last[0] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q rot_last[0] 0.218 0.913 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xclk_in_rot_Sync.syncOutput[0] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE Q clk_ref_rot[0] 0.218 0.930 =============================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.sync_st[0] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D I_AND2_FINE_LOCK_0_Y 0.047 -1.340 Flag_for_RXPLL_lock_0.flag_s PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE EN PF_XCVR_0_0_LANE0_RX_READY -0.006 -0.771 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ready_sync[0] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D PF_XCVR_0_0_LANE0_RX_READY 0.047 -0.718 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D un1_rot_sh_3_s_5_S 3.879 0.271 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[4] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D un1_rot_sh_3_cry_4_S 3.879 0.279 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[3] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D un1_rot_sh_3_cry_3_S 3.879 0.287 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[2] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D un1_rot_sh_3_cry_2_S 3.879 0.394 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[1] PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R SLE D un1_rot_sh_3_cry_1_S 3.879 0.829 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R XCVR_PMA TX_DATA[25] PRBS_gen_0_data_out[25] 2.603 1.437 PF_XCVR_0_0.I_XCVR.LANE0 PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R XCVR_PMA TX_DATA[21] PRBS_gen_0_data_out[21] 2.606 1.440 ============================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 0.047 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.047 - Propagation time: 1.387 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.340 Number of logic level(s): 1 Starting point: PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock_fast / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.sync_st[0] / D The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock_fast SLE Q Out 0.218 0.218 r - fine_lock_fast Net - - 0.948 - 2 PF_XCVR_0_0.I_AND2_FINE_LOCK_0 AND2 A In - 1.166 r - PF_XCVR_0_0.I_AND2_FINE_LOCK_0 AND2 Y Out 0.103 1.269 r - I_AND2_FINE_LOCK_0_Y Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.sync_st[0] SLE D In - 1.387 r - ========================================================================================================== Total path delay (propagation time + setup) of 1.387 is 0.321(23.1%) logic and 1.066(76.9%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 0.121 - Setup time: 0.127 + Clock delay at ending point: 0.000 (ideal) = Required time: -0.006 - Propagation time: 0.765 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.771 Number of logic level(s): 0 Starting point: PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock / Q Ending point: Flag_for_RXPLL_lock_0.flag_s / EN The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK The end point is clocked by PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock SLE Q Out 0.218 0.218 r - PF_XCVR_0_0_LANE0_RX_READY Net - - 0.547 - 4 Flag_for_RXPLL_lock_0.flag_s SLE EN In - 0.765 r - ===================================================================================================== Total path delay (propagation time + setup) of 0.892 is 0.345(38.7%) logic and 0.547(61.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 0.047 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 0.047 - Propagation time: 0.765 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.718 Number of logic level(s): 0 Starting point: PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock / Q Ending point: PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ready_sync[0] / D The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK The end point is clocked by PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV [rising] (rise=0.000 fall=12.500 period=25.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock SLE Q Out 0.218 0.218 r - PF_XCVR_0_0_LANE0_RX_READY Net - - 0.547 - 4 PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ready_sync[0] SLE D In - 0.765 r - ================================================================================================================================= Total path delay (propagation time + setup) of 0.765 is 0.218(28.5%) logic and 0.547(71.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 3.879 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.879 - Propagation time: 3.608 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.271 Number of logic level(s): 8 Starting point: PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 / Q Ending point: PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] / D The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK The end point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 SLE Q Out 0.201 0.201 f - timeout_o Net - - 0.697 - 14 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2[5] CFG2 A In - 0.898 f - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2[5] CFG2 Y Out 0.048 0.945 f - N_82 Net - - 0.124 - 2 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2_RNI95761[5] CFG4 D In - 1.069 f - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2_RNI95761[5] CFG4 Y Out 0.232 1.301 r - un1_m2_e_2 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_RNICSJO1[0] CFG3 C In - 1.848 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_RNICSJO1[0] CFG3 Y Out 0.148 1.996 r - N_104 Net - - 0.579 - 5 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_axb_2 CFG4 B In - 2.575 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_axb_2 CFG4 Y Out 0.088 2.663 r - un1_rot_sh_3_axb_2 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_2 ARI1 C In - 2.780 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_2 ARI1 FCO Out 0.393 3.174 r - un1_rot_sh_3_cry_2 Net - - 0.000 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_3 ARI1 FCI In - 3.174 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_3 ARI1 FCO Out 0.008 3.182 r - un1_rot_sh_3_cry_3 Net - - 0.000 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_4 ARI1 FCI In - 3.182 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_4 ARI1 FCO Out 0.008 3.190 r - un1_rot_sh_3_cry_4 Net - - 0.000 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_s_5 ARI1 FCI In - 3.190 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_s_5 ARI1 S Out 0.300 3.490 r - un1_rot_sh_3_s_5_S Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] SLE D In - 3.608 r - ========================================================================================================================================== Total path delay (propagation time + setup) of 3.608 is 1.425(39.5%) logic and 2.183(60.5%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 3.879 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.879 - Propagation time: 3.600 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 0.279 Number of logic level(s): 7 Starting point: PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 / Q Ending point: PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] / D The start point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK The end point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------------------ PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_5 SLE Q Out 0.201 0.201 f - timeout_o Net - - 0.697 - 14 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2[5] CFG2 A In - 0.898 f - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2[5] CFG2 Y Out 0.048 0.945 f - N_82 Net - - 0.124 - 2 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2_RNI95761[5] CFG4 D In - 1.069 f - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_nxt_i_o2_RNI95761[5] CFG4 Y Out 0.232 1.301 r - un1_m2_e_2 Net - - 0.547 - 3 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_RNICSJO1[0] CFG3 C In - 1.848 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret_RNICSJO1[0] CFG3 Y Out 0.148 1.996 r - N_104 Net - - 0.579 - 5 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_axb_3 CFG4 B In - 2.575 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_axb_3 CFG4 Y Out 0.088 2.663 r - un1_rot_sh_3_axb_3 Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_3 ARI1 C In - 2.780 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_3 ARI1 FCO Out 0.393 3.174 r - un1_rot_sh_3_cry_3 Net - - 0.000 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_4 ARI1 FCI In - 3.174 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_cry_4 ARI1 FCO Out 0.008 3.182 r - un1_rot_sh_3_cry_4 Net - - 0.000 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_s_5 ARI1 FCI In - 3.182 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.un1_rot_sh_3_s_5 ARI1 S Out 0.300 3.482 r - un1_rot_sh_3_s_5_S Net - - 0.118 - 1 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrot_sh_ctr.rot_sh_ret[5] SLE D In - 3.600 r - ========================================================================================================================================== Total path delay (propagation time + setup) of 3.600 is 1.417(39.4%) logic and 2.183(60.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------- INIT_MONITOR_0.INIT_MONITOR_0.I_INIT System INIT RFU[0] XCVR_INIT_DONE 0.000 2.703 PF_XCVR_0_0.I_XCVR_CORELNKTMR System CORELNKTMR_V CTRL_SRST_N I_XCVR_CORELNKTMR_CTRL_SRST_N 0.000 9.052 PF_XCVR_0_0.I_XCVR_CORELNKTMR System CORELNKTMR_V LTPULSE[0] I_XCVR_CORELNKTMR_LTPULSE[0] 0.000 22.851 INIT_MONITOR_0.INIT_MONITOR_0.I_INIT System INIT UIC_INIT_DONE INIT_MONITOR_0_DEVICE_INIT_DONE 0.000 22.935 PF_XCVR_0_0.I_XCVR_APBLINK_V_0.u0 System XCVR_APB_LINK_V GRANT I_XCVR_APBLINK_V_0_GRANT 0.000 24.262 PF_XCVR_0_0.I_XCVR_APBLINK_V_0.u0 System XCVR_APB_LINK_V RQR[0] I_XCVR_APBLINK_V_0_RQR[0] 0.000 24.294 PF_XCVR_0_0.I_XCVR_APBLINK_V_0.u0 System XCVR_APB_LINK_V RQR[1] I_XCVR_APBLINK_V_0_RQR[1] 0.000 24.717 =================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrst_Sync_clk_ref.syncTemp[0] System SLE D rstn 3.879 2.703 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrst_Sync_clk_in.syncTemp[0] System SLE D rstn 3.879 2.703 PF_XCVR_0_0.I_XCVR_CORELNKTMR System CORELNKTMR_V CTRL_ARST_N XCVR_INIT_DONE 10.000 8.999 PF_XCVR_0_0.I_XCVR_APBLINK_V_0.u0 System XCVR_APB_LINK_V ARST_N XCVR_INIT_DONE 10.000 8.999 PF_XCVR_0_0.I_XCVR_APBLINK_V_0.u0 System XCVR_APB_LINK_V CTRL_SRST_N I_XCVR_CORELNKTMR_CTRL_SRST_N 10.000 9.052 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[6] System SLE D intg_st_s[6] 25.000 22.851 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[5] System SLE D intg_st_s[5] 25.000 22.859 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[4] System SLE D intg_st_s[4] 25.000 22.867 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[3] System SLE D intg_st_s[3] 25.000 22.875 PF_XCVR_0_0.I_XCVR_CORELCKMGT_0.intg_st[2] System SLE D intg_st_s[2] 25.000 22.883 ============================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 3.879 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 3.879 - Propagation time: 1.176 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 2.703 Number of logic level(s): 1 Starting point: INIT_MONITOR_0.INIT_MONITOR_0.I_INIT / RFU[0] Ending point: PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrst_Sync_clk_in.syncTemp[0] / D The start point is clocked by System [rising] The end point is clocked by PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R [rising] (rise=0.000 fall=1.939 period=3.879) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------- INIT_MONITOR_0.INIT_MONITOR_0.I_INIT INIT RFU[0] Out 0.000 0.000 r - XCVR_INIT_DONE Net - - 1.001 - 6 PF_XCVR_0_0.I_XCVR_CORERFD_0.rstn CFG2 A In - 1.001 r - PF_XCVR_0_0.I_XCVR_CORERFD_0.rstn CFG2 Y Out 0.051 1.052 r - rstn Net - - 0.124 - 10 PF_XCVR_0_0.I_XCVR_CORERFD_0.u_sicr.Xrst_Sync_clk_in.syncTemp[0] SLE D In - 1.176 r - ================================================================================================================================= Total path delay (propagation time + setup) of 1.176 is 0.051(4.3%) logic and 1.125(95.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(13) | Timing constraint (through [get_pins { CoreABC_Inst_0.CoreABC_Inst_0.NSYSRESET* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 186MB peak: 189MB) Finished timing report (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 186MB peak: 189MB) --------------------------------------- Resource Usage Report for top Mapping to part: mpf300tfcg1152-1 Cell usage: AND2 3 uses BANKEN 1 use CLKINT 3 uses CORELNKTMR_V 1 use DFN1 2 uses DRI 1 use ICB_CLKDIV 1 use INIT 1 use OR2 2 uses OSC_RC160MHZ 1 use PLL 1 use RCLKINT 2 uses TX_PLL 1 use XCVR_APB_LINK_V 1 use XCVR_PMA 1 use XCVR_REF_CLK 1 use CFG1 87 uses CFG2 74 uses CFG3 229 uses CFG4 365 uses Carry cells: ARI1 85 uses - used for arithmetic functions Sequential Cells: SLE 426 uses SLE_DEBUG 1 uses Total SLE 427 uses DSP Blocks: 0 of 924 (0%) I/O ports: 11 I/O primitives: 5 INBUF 1 use OUTBUF 4 uses Global Clock Buffers: 5 RAM/ROM usage summary Total Block RAMs (RAM1K20) : 8 of 952 (0%) Total LUTs: 840 Extra resources required for RAM and MACC_PA interface logic during P&R: RAM64X12 Interface Logic : SLEs = 0; LUTs = 0; RAM1K20 Interface Logic : SLEs = 288; LUTs = 288; MACC_PA Interface Logic : SLEs = 0; LUTs = 0; MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 427 + 0 + 288 + 0 = 715; Total number of LUTs after P&R: 840 + 0 + 288 + 0 = 1128; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 68MB peak: 189MB) Process took 0h:00m:15s realtime, 0h:00m:14s cputime # Thu Jan 7 09:26:01 2021 ###########################################################]