Project Settings Project Name top_syn Device Name synthesis: Microchip PolarFire : MPF300T Implementation Name synthesis Top Module top Retiming 1 Resource Sharing 1 Fanout Guide 10000 Disable I/O Insertion 0 Disable Sequential Optimizations 0 FSM Compiler 1 Run Status Job Name Status CPU Time Real Time Memory Date/Time (compiler) Complete 106 72 0 - 00m:24s - 07-01-2021 09:25:36 (premap) Complete 18 4 0 0m:04s 0m:05s 179MB 07-01-2021 09:25:45 (fpga_mapper) Complete 40 40 0 0m:14s 0m:15s 189MB 07-01-2021 09:26:01 Multi-srs Generator Complete 00m:01s 07-01-2021 09:25:38 Area Summary Carry Cells 85 Sequential Cells 427 DSP Blocks (dsp_used) 0 I/O Cells 5 Global Clock Buffers 5 RAM1K20 (v_ram) 8 LUTs (total_luts) 840 Timing Summary Clock Name Req Freq Est Freq Slack PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 50.0 MHz 6.8 MHz 11.914 PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV 40.0 MHz 1.3 MHz -1.413 PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK 160.0 MHz NA NA PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R 257.8 MHz 8.2 MHz 0.409 PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R 257.8 MHz 8.7 MHz -1.340 REF_CLK_PAD_P 125.0 MHz NA NA System 100.0 MHz 999.0 MHz 8.999 Optimizations Summary Retiming 9 / 15 Combined Clock Conversion 3 / 2