@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\ramblocks.v":41:11:41:19|Tristate driver DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND.
@N: MO111 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\ramblocks.v":40:11:40:20|Tristate driver SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_chk.v":116:0:116:5|Removing sequential instance prbs_rxn[1] (in view: work.PRBS_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":780:2:780:7|Removing sequential instance lO0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":414:2:414:7|Removing sequential instance prbs_err[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_gen.v":71:0:71:5|Removing sequential instance prbs_txn[1] (in view: work.PRBS_gen(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_chk.v":96:0:96:5|Removing sequential instance rx_val_o (in view: work.PRBS_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":848:2:848:7|Removing sequential instance lo0[2:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":848:2:848:7|Removing sequential instance Io0[2:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\synthesis\top.sap.
@N: MO225 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)); safe FSM implementation is not required.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":780:2:780:7|Removing sequential instance i10[5] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":780:2:780:7|Removing sequential instance i10[0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
