@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":36:2:36:7|Removing sequential instance PRBS_chk_0.prbs_asic_chk_inst.OI because it is equivalent to instance PRBS_chk_0.prbs_asic_chk_inst.I. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":36:2:36:7|Removing sequential instance PRBS_chk_0.prbs_asic_chk_inst.l because it is equivalent to instance PRBS_chk_0.prbs_asic_chk_inst.II. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[19] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[16] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[15] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[14] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[13] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[12] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[8] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[7] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[6] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[25] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[24] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[22] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[21] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[20] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[23] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[17] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":494:12:494:17|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[9] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.UROM.INSTR_DATA[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[8] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[7] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|Removing instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[6] because it is equivalent to instance CoreABC_Inst_0.CoreABC_Inst_0.IO_OUT[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\pf_xcvr_0\pf_xcvr_0.v":488:13:488:29|Blackbox CORELNKTMR_V is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\actel\sgcore\pf_xcvr_apblink_v\1.0.102\hdl\pf_xcvr_apblink_v.v":57:16:57:17|Blackbox XCVR_APB_LINK_V is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\pf_osc_160\pf_osc_160_0\pf_osc_160_pf_osc_160_0_pf_osc.v":13:17:13:25|Blackbox OSC_RC160MHZ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\init_monitor\init_monitor_0\init_monitor_init_monitor_0_pf_init_monitor.v":40:53:40:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT116 |Paths from clock (PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R:r) to clock (PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV:r) are overconstrained because the required time of 0.05 ns is too small.  
@W: MT116 |Paths from clock (PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV:r) to clock (PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R:r) are overconstrained because the required time of 0.05 ns is too small.  
@W: MT116 |Paths from clock (PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R:r) to clock (PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.12 ns is too small.  
@W: MT447 :"c:/wfh_tasks/rtg4_v12.6_updates/pf_v12.6/ac468_dfe/libero_project/designer/top/synthesis.fdc":13:0:13:0|Timing constraint (through [get_pins { CoreABC_Inst_0.CoreABC_Inst_0.NSYSRESET* }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
