@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MO111 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\ramblocks.v":41:11:41:19|Tristate driver DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net DB_DETECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND.
@N: MO111 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\ramblocks.v":40:11:40:20|Tristate driver SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) on net SB_CORRECT (in view: work.CoreABC_Inst_CoreABC_Inst_0_RAMBLOCKS_0s_32s_26s(verilog)) has its enable tied to GND.
@N: MO106 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|Found ROM doins[36:35] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 12 words by 2 bits.
@N: MO106 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|Found ROM doins[31:30] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 12 words by 2 bits.
@N: MO106 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|Found ROM doins[28:26] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 17 words by 3 bits.
@N: MO106 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|Found ROM doins[17:11] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 13 words by 7 bits.
@N: MO106 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\instructions.v":82:4:82:7|Found ROM doins[5:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_INSTRUCTIONS_Z2(verilog)) with 20 words by 6 bits.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":251:2:251:7|Removing sequential instance IOl[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":780:2:780:7|Removing sequential instance Oo0[3:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":414:2:414:7|Removing sequential instance oIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":390:2:390:7|Removing sequential instance lOl[7:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":390:2:390:7|Removing sequential instance oOl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":780:2:780:7|Removing sequential instance i10[5:0] (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":740:2:740:7|Removing sequential instance ol0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":414:2:414:7|Removing sequential instance lIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":390:2:390:7|Removing sequential instance OIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":740:2:740:7|Removing sequential instance il0 (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":414:2:414:7|Removing sequential instance iIl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":390:2:390:7|Removing sequential instance iOl (in view: work.prbs_asic_chk(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: MO225 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\work\coreabc_inst\coreabc_inst_0\rtl\vlog\core\coreabc.v":1041:4:1041:9|There are no possible illegal states for state machine ICYCLE[3:0] (in view: work.CoreABC_Inst_CoreABC_Inst_0_COREABC_Z1(verilog)); safe FSM implementation is not required.
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\actel\directcore\corelckmgt\2.0.100\rtl\vlog\core\corelckmgt.v":211:0:211:5|Found counter in view:work.CORELCKMGT_Z4(verilog) instance intg_st[6:0] 
@N: MO231 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":251:2:251:7|Found counter in view:work.prbs_asic_chk(verilog) instance OoI[7:0] 
@N: MF179 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\hdl\prbs_asic_chk.v":385:16:385:41|Found 40 by 40 bit equality operator ('==') OOl (in view: work.prbs_asic_chk(verilog))
@N: FX271 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\actel\directcore\corelanemstr\2.0.100\rtl\vlog\core\corelanemstrmode1.v":190:0:190:5|Replicating instance PF_XCVR_0_0.I_XCVR_CORELANEMSTR_0.g_mode3\.u_mstr.rx_ok_st (in view: work.top(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\ac468_dfe\libero_project\component\actel\directcore\corerfd\2.0.100\rtl\vlog\core\corerfd.v":120:0:120:5|Replicating instance PF_XCVR_0_0.I_XCVR_CORERFD_0.fine_lock (in view: work.top(verilog)) with 5 loads 1 time to improve timing.
@N: MF322 |Retiming summary: 9 registers retimed to 15 
@N: FP130 |Promoting Net PF_CLK_DIV_C0_0_CLK_OUT on CLKINT  I_206 
@N: BW103 |The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns.
@N: BW107 |Synopsys Constraint File capacitance units using default value of 1pF 
@N: MT615 |Found clock PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK with period 6.25ns 
@N: MT615 |Found clock REF_CLK_PAD_P with period 8.00ns 
@N: MT615 |Found clock PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R with period 3.88ns 
@N: MT615 |Found clock PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R with period 3.88ns 
@N: MT615 |Found clock PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 with period 20.00ns 
@N: MT615 |Found clock PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV with period 25.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
