#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\synthesis\run_options.txt
#--  Written on Thu Jan  7 09:25:12 2021


#project files
add_file -verilog "../component/polarfire_syn_comps.v"
add_file -include "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/support.v"
add_file -include "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/request_code.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/acmtable.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/instructnvm_bb.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/iram512x9_rtl.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/instructram.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/debugblk.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/instructions.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/ram128x8_polarfire.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/ram256x16_rtl.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/ram256x8_rtl.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/ram256xdwidth_ecc_g5.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/ramblocks.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst_0/rtl/vlog/core/coreabc.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/CoreABC_Inst/CoreABC_Inst.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/hdl/Flag_for_RXPLL_lock.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/INIT_MONITOR/INIT_MONITOR_0/INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/INIT_MONITOR/INIT_MONITOR.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_CCC_50/PF_CCC_50_0/PF_CCC_50_PF_CCC_50_0_PF_CCC.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_CCC_50/PF_CCC_50.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_CLK_DIV_C0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_CLK_DIV_C0/PF_CLK_DIV_C0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_OSC_160/PF_OSC_160_0/PF_OSC_160_PF_OSC_160_0_PF_OSC.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_OSC_160/PF_OSC_160.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_TX_PLL_0/PF_TX_PLL_0_0/PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_TX_PLL_0/PF_TX_PLL_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELCKMGT/2.0.100/rtl/vlog/core/CORELCKMGT.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDbincnt.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsmplcnt.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDfrqerrarb.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDgrycnt.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDplsgen.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDshcnt.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsyncen.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsync.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsicr.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFD.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_0/I_XCVR/PF_XCVR_0_I_XCVR_PF_XCVR.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/SgCore/PF_XCVR_APBLINK_V/1.0.102/hdl/PF_XCVR_APBLINK_V.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode1.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode2.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTR.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_0/PF_XCVR_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_DRI/PF_XCVR_DRI_0/PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_DRI/PF_XCVR_DRI.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_REF_CLK_0/PF_XCVR_REF_CLK_0_0/PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_REF_CLK_0/PF_XCVR_REF_CLK_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/hdl/prbs_asic_chk.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/hdl/PRBS_chk.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/hdl/prbs_asic_gen.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/hdl/PRBS_gen.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/reset_syn_rx/reset_syn_rx_0/core/corereset_pf.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/reset_syn_rx/reset_syn_rx.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/reset_syn_tx/reset_syn_tx_0/core/corereset_pf.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/reset_syn_tx/reset_syn_tx.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/reset_logic/reset_logic.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 1
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
