SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Thu Jan 7 09:31:20 2021
| Design | top |
| Family | PolarFire |
| Die | MPF300TS |
| Package | FCG1152 |
| Temperature Range | -40 - 100 C |
| Voltage Range | 1.0185 - 1.0815 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | slow_lv_ht, slow_lv_lt, fast_hv_lt |
| Scenario for Timing Analysis | timing_analysis |
*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 20.000 | 50.000 | 9.214 | slow_lv_ht |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 25.000 | 40.000 | 20.334 | slow_lv_lt |
| PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK | 6.250 | 160.000 | ||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 3.879 | 257.798 | 0.897 | slow_lv_ht |
| PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 3.879 | 257.798 | 1.294 | slow_lv_ht |
| REF_CLK_PAD_P | 8.000 | 125.000 |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | Flag_for_RXPLL_lock_0/flag_s:CLK | CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | 9.868 | 9.950 | 14.835 | 24.785 | 0.000 | 10.050 | slow_lv_ht |
| Path 2 | Flag_for_RXPLL_lock_0/flag_s:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[0]:D | 9.134 | 10.687 | 14.101 | 24.788 | 0.000 | 9.313 | slow_lv_ht |
| Path 3 | CoreABC_Inst_0/CoreABC_Inst_0/URAM.UR/UG4.UR32.ram_r0c0/RAM1K20_R0C0/INST_RAM1K20_IP:A_CLK | CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | 8.073 | 11.695 | 13.143 | 24.838 | 0.000 | 8.305 | slow_lv_ht |
| Path 4 | CoreABC_Inst_0/CoreABC_Inst_0/URAM.UR/UG4.UR32.ram_r1c0/RAM1K20_R0C0/INST_RAM1K20_IP:A_CLK | CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | 8.078 | 11.697 | 13.141 | 24.838 | 0.000 | 8.303 | slow_lv_ht |
| Path 5 | CoreABC_Inst_0/CoreABC_Inst_0/URAM.UR/UG4.UR32.ram_r1c1/RAM1K20_R0C0/INST_RAM1K20_IP:A_CLK | CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | 7.828 | 11.949 | 12.889 | 24.838 | 0.000 | 8.051 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: Flag_for_RXPLL_lock_0/flag_s:CLK | ||||||||
| To: CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | ||||||||
| data required time | 24.785 | |||||||
| data arrival time | - | 14.835 | ||||||
| slack | 9.950 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.104 | 3.104 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.176 | 3.280 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.151 | 3.431 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_GB0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.379 | 3.810 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.151 | 3.961 | 1 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_gbs_1 | + | 0.383 | 4.344 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.052 | 4.396 | 1 | f | |
| Flag_for_RXPLL_lock_0/flag_s:CLK | net | PF_CCC_50_0_OUT0_FABCLK_0 | + | 0.571 | 4.967 | r | ||
| Flag_for_RXPLL_lock_0/flag_s:Q | cell | ADLIB:SLE | + | 0.175 | 5.142 | 2 | r | |
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4_1_0[0]:C | net | Flag_for_RXPLL_lock_0_flag_o | + | 8.042 | 13.184 | r | ||
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4_1_0[0]:Y | cell | ADLIB:CFG3 | + | 0.132 | 13.316 | 1 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4[0]:B | net | CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4_1_0_Z[0] | + | 0.296 | 13.612 | f | ||
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4[0]:Y | cell | ADLIB:CFG4 | + | 0.106 | 13.718 | 1 | r | |
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT[0]:B | net | CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_m4_Z[0] | + | 0.114 | 13.832 | r | ||
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT[0]:Y | cell | ADLIB:CFG3 | + | 0.066 | 13.898 | 2 | r | |
| CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4_16[0]:A | net | CoreABC_Inst_0/CoreABC_Inst_0/ACCUM_NEXT_Z[0] | + | 0.218 | 14.116 | r | ||
| CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4_16[0]:Y | cell | ADLIB:CFG4 | + | 0.061 | 14.177 | 1 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4[0]:A | net | CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4_16_Z[0] | + | 0.123 | 14.300 | f | ||
| CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4[0]:Y | cell | ADLIB:CFG4 | + | 0.061 | 14.361 | 1 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | net | CoreABC_Inst_0/CoreABC_Inst_0/to_logic_2.tmp_4_Z[0] | + | 0.474 | 14.835 | f | ||
| data arrival time | 14.835 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | Clock Constraint | 20.000 | 20.000 | |||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 20.000 | r | |||
| Clock generation | + | 2.820 | 22.820 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.160 | 22.980 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 23.111 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.345 | 23.456 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:Y | cell | ADLIB:GB | + | 0.132 | 23.588 | 3 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_Y | + | 0.326 | 23.914 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 23.961 | 98 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:CLK | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 | + | 0.470 | 24.431 | r | ||
| clock reconvergence pessimism | + | 0.354 | 24.785 | |||||
| CoreABC_Inst_0/CoreABC_Inst_0/STD_ACCUM_ZERO:D | Library setup time | ADLIB:SLE | - | 0.000 | 24.785 | |||
| data required time | 24.785 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | CoreABC_Inst_0/CoreABC_Inst_0/IO_OUT_Z[0]:CLK | DFE_CAL_DONE | 7.991 | 9.214 | 12.890 | 22.104 | 12.890 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoreABC_Inst_0/CoreABC_Inst_0/IO_OUT_Z[0]:CLK | ||||||||
| To: DFE_CAL_DONE | ||||||||
| data required time | 22.104 | |||||||
| data arrival time | - | 12.890 | ||||||
| slack | 9.214 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.104 | 3.104 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.176 | 3.280 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.151 | 3.431 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.379 | 3.810 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:Y | cell | ADLIB:GB | + | 0.145 | 3.955 | 3 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_Y | + | 0.361 | 4.316 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:Y | cell | ADLIB:RGB | + | 0.052 | 4.368 | 98 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/IO_OUT_Z[0]:CLK | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 | + | 0.531 | 4.899 | r | ||
| CoreABC_Inst_0/CoreABC_Inst_0/IO_OUT_Z[0]:Q | cell | ADLIB:SLE | + | 0.166 | 5.065 | 1 | f | |
| DFE_CAL_DONE_obuf/U_IOTRI:D | net | DFE_CAL_DONE_c | + | 4.874 | 9.939 | f | ||
| DFE_CAL_DONE_obuf/U_IOTRI:DOUT | cell | ADLIB:IOTRI_OB_EB | + | 0.918 | 10.857 | 1 | f | |
| DFE_CAL_DONE_obuf/U_IOPAD:D | net | DFE_CAL_DONE_obuf/DOUT | + | 0.000 | 10.857 | f | ||
| DFE_CAL_DONE_obuf/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.033 | 12.890 | 0 | f | |
| DFE_CAL_DONE | net | DFE_CAL_DONE | + | 0.000 | 12.890 | f | ||
| data arrival time | 12.890 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | Clock Constraint | 20.000 | 20.000 | |||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 20.000 | r | |||
| Clock generation | + | 2.820 | 22.820 | |||||
| clock reconvergence pessimism | + | 0.284 | 23.104 | |||||
| DFE_CAL_DONE | Output Delay Constraint | - | 1.000 | 22.104 | f | |||
| data required time | 22.104 | |||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[9]:ALn | 2.030 | 17.712 | 6.913 | 24.625 | 0.170 | 2.288 | 0.088 | slow_lv_ht |
| Path 2 | CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[8]:ALn | 2.030 | 17.712 | 6.913 | 24.625 | 0.170 | 2.288 | 0.088 | slow_lv_ht |
| Path 3 | CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[15]:ALn | 2.029 | 17.712 | 6.912 | 24.624 | 0.170 | 2.288 | 0.089 | slow_lv_ht |
| Path 4 | CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[13]:ALn | 2.029 | 17.713 | 6.912 | 24.625 | 0.170 | 2.287 | 0.088 | slow_lv_ht |
| Path 5 | CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[12]:ALn | 2.029 | 17.713 | 6.912 | 24.625 | 0.170 | 2.287 | 0.088 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | ||||||||
| To: CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[9]:ALn | ||||||||
| data required time | 24.625 | |||||||
| data arrival time | - | 6.913 | ||||||
| slack | 17.712 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 3.104 | 3.104 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.176 | 3.280 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.151 | 3.431 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.379 | 3.810 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:Y | cell | ADLIB:GB | + | 0.145 | 3.955 | 3 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_Y | + | 0.361 | 4.316 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB0:Y | cell | ADLIB:RGB | + | 0.052 | 4.368 | 2 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:CLK | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB0_rgb_net_1 | + | 0.515 | 4.883 | r | ||
| CoreABC_Inst_0/CoreABC_Inst_0/genblk2.RSTSYNC2:Q | cell | ADLIB:SLE | + | 0.179 | 5.062 | 58 | r | |
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[9]:ALn | net | CoreABC_Inst_0/PRESETN | + | 1.851 | 6.913 | r | ||
| data arrival time | 6.913 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | Clock Constraint | 20.000 | 20.000 | |||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 20.000 | r | |||
| Clock generation | + | 2.820 | 22.820 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.160 | 22.980 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 23.111 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.345 | 23.456 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0:Y | cell | ADLIB:GB | + | 0.132 | 23.588 | 3 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_Y | + | 0.326 | 23.914 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 23.961 | 98 | f | |
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[9]:CLK | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 | + | 0.462 | 24.423 | r | ||
| clock reconvergence pessimism | + | 0.372 | 24.795 | |||||
| CoreABC_Inst_0/CoreABC_Inst_0/ACCUMULATOR[9]:ALn | Library recovery time | ADLIB:SLE | - | 0.170 | 24.625 | |||
| data required time | 24.625 | |||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | External Recovery (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | SWITCH | Flag_for_RXPLL_lock_0/flag_s:ALn | 6.439 | 12.776 | 11.543 | 24.319 | 0.170 | 2.120 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: SWITCH | ||||||||
| To: Flag_for_RXPLL_lock_0/flag_s:ALn | ||||||||
| data required time | 24.319 | |||||||
| data arrival time | - | 11.543 | ||||||
| slack | 12.776 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| Clock generation | + | 3.104 | 3.104 | |||||
| SWITCH | Input Delay Constraint | + | 2.000 | 5.104 | r | |||
| SWITCH_ibuf/U_IOPAD:PAD | net | SWITCH | + | 0.000 | 5.104 | r | ||
| SWITCH_ibuf/U_IOPAD:Y | cell | ADLIB:IOPAD_IN | + | 0.599 | 5.703 | 1 | r | |
| SWITCH_ibuf/U_IOIN:YIN | net | SWITCH_ibuf/YIN | + | 0.000 | 5.703 | r | ||
| SWITCH_ibuf/U_IOIN:Y | cell | ADLIB:IOIN_IB_E | + | 0.336 | 6.039 | 1 | r | |
| AND2_0:A | net | SWITCH_c | + | 0.828 | 6.867 | r | ||
| AND2_0:Y | cell | ADLIB:CFG2 | + | 0.066 | 6.933 | 4 | r | |
| Flag_for_RXPLL_lock_0/flag_s:ALn | net | AND2_0_Y | + | 4.610 | 11.543 | r | ||
| data arrival time | 11.543 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0 | Clock Constraint | 20.000 | 20.000 | |||||
| PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 20.000 | r | |||
| Clock generation | + | 2.820 | 22.820 | |||||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:A | net | PF_CCC_50_0/PF_CCC_50_0/pll_inst_0_clkint_0 | + | 0.160 | 22.980 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 23.111 | 2 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_GB0:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0_NET | + | 0.345 | 23.456 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.137 | 23.593 | 1 | r | |
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1:A | net | PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_gbs_1 | + | 0.343 | 23.936 | r | ||
| PF_CCC_50_0/PF_CCC_50_0/clkint_0/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 23.983 | 1 | f | |
| Flag_for_RXPLL_lock_0/flag_s:CLK | net | PF_CCC_50_0_OUT0_FABCLK_0 | + | 0.506 | 24.489 | r | ||
| Flag_for_RXPLL_lock_0/flag_s:ALn | Library recovery time | ADLIB:SLE | - | 0.170 | 24.319 | |||
| data required time | 24.319 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin ARBITER_INST/APB_LINK_INST_0/U0:S_CLK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ARBITER_INST/CORELNKMSTR_0/cache[4]:D | 4.363 | 20.334 | 8.574 | 28.908 | 0.000 | 4.666 | slow_lv_lt |
| Path 2 | ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ARBITER_INST/CORELNKMSTR_0/cache[5]:D | 4.361 | 20.336 | 8.572 | 28.908 | 0.000 | 4.664 | slow_lv_lt |
| Path 3 | ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ARBITER_INST/CORELNKMSTR_0/cache[6]:D | 4.269 | 20.426 | 8.480 | 28.906 | 0.000 | 4.574 | slow_lv_lt |
| Path 4 | ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ARBITER_INST/CORELNKMSTR_0/cache[3]:D | 4.268 | 20.428 | 8.479 | 28.907 | 0.000 | 4.572 | slow_lv_lt |
| Path 5 | ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ARBITER_INST/CORELNKMSTR_0/cache[7]:D | 4.265 | 20.431 | 8.476 | 28.907 | 0.000 | 4.569 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | ||||||||
| To: ARBITER_INST/CORELNKMSTR_0/cache[4]:D | ||||||||
| data required time | 28.908 | |||||||
| data arrival time | - | 8.574 | ||||||
| slack | 20.334 | |||||||
| Data arrival time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 0.000 | 0.000 | ||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.417 | 2.417 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/Y_DIV | + | 0.000 | 2.417 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.146 | 2.563 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_NET | + | 0.339 | 2.902 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:Y | cell | ADLIB:GB | + | 0.153 | 3.055 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_Y | + | 0.352 | 3.407 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.053 | 3.460 | 127 | f | |
| ARBITER_INST/APB_LINK_INST_0/U0:S_CLK | net | PF_CLK_DIV_C0_0_CLK_OUT | + | 0.751 | 4.211 | r | ||
| ARBITER_INST/APB_LINK_INST_0/U0:S_RDATA[0] | cell | ADLIB:XCVR_APB_LINK | + | 3.128 | 7.339 | 8 | r | |
| ARBITER_INST/CORELNKMSTR_0/cache_RNO[4]:B | net | ARBITER_INST/APB_LINK_INST_0_S_RDATA[0] | + | 1.005 | 8.344 | r | ||
| ARBITER_INST/CORELNKMSTR_0/cache_RNO[4]:Y | cell | ADLIB:CFG4 | + | 0.204 | 8.548 | 1 | r | |
| ARBITER_INST/CORELNKMSTR_0/cache[4]:D | net | ARBITER_INST/CORELNKMSTR_0/N_20_i_0 | + | 0.026 | 8.574 | r | ||
| data arrival time | 8.574 | |||||||
| Data required time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | Clock Constraint | 25.000 | 25.000 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | 25.000 | r | |||
| Clock generation | + | 2.153 | 27.153 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/Y_DIV | + | 0.000 | 27.153 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.126 | 27.279 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_NET | + | 0.309 | 27.588 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:Y | cell | ADLIB:GB | + | 0.139 | 27.727 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_Y | + | 0.317 | 28.044 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 28.091 | 127 | f | |
| ARBITER_INST/CORELNKMSTR_0/cache[4]:CLK | net | PF_CLK_DIV_C0_0_CLK_OUT | + | 0.448 | 28.539 | r | ||
| clock reconvergence pessimism | + | 0.369 | 28.908 | |||||
| ARBITER_INST/CORELNKMSTR_0/cache[4]:D | Library setup time | ADLIB:SLE | - | 0.000 | 28.908 | |||
| data required time | 28.908 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | PF_XCVR_0_0/I_XCVR_CORELANEMSTR_0/g_mode3.u_mstr/calib_st:CLK | LANE0_CALIBRATING | 8.159 | 12.437 | 12.437 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PF_XCVR_0_0/I_XCVR_CORELANEMSTR_0/g_mode3.u_mstr/calib_st:CLK | ||||||||
| To: LANE0_CALIBRATING | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 12.437 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 0.000 | 0.000 | ||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.593 | 2.593 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/Y_DIV | + | 0.000 | 2.593 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.152 | 2.745 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_NET | + | 0.379 | 3.124 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:Y | cell | ADLIB:GB | + | 0.152 | 3.276 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_Y | + | 0.387 | 3.663 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.052 | 3.715 | 127 | f | |
| PF_XCVR_0_0/I_XCVR_CORELANEMSTR_0/g_mode3.u_mstr/calib_st:CLK | net | PF_CLK_DIV_C0_0_CLK_OUT | + | 0.563 | 4.278 | r | ||
| PF_XCVR_0_0/I_XCVR_CORELANEMSTR_0/g_mode3.u_mstr/calib_st:Q | cell | ADLIB:SLE | + | 0.166 | 4.444 | 7 | f | |
| LANE0_CALIBRATING_obuf/U_IOTRI:D | net | LANE0_CALIBRATING_c | + | 5.041 | 9.485 | f | ||
| LANE0_CALIBRATING_obuf/U_IOTRI:DOUT | cell | ADLIB:IOTRI_OB_EB | + | 0.918 | 10.403 | 1 | f | |
| LANE0_CALIBRATING_obuf/U_IOPAD:D | net | LANE0_CALIBRATING_obuf/DOUT | + | 0.000 | 10.403 | f | ||
| LANE0_CALIBRATING_obuf/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.034 | 12.437 | 0 | f | |
| LANE0_CALIBRATING | net | LANE0_CALIBRATING | + | 0.000 | 12.437 | f | ||
| data arrival time | 12.437 | |||||||
| Data required time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | N/C | N/C | ||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 2.316 | N/C | |||||
| LANE0_CALIBRATING | N/C | f | ||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[1]:ALn | 1.587 | 23.203 | 5.890 | 29.093 | 0.170 | 1.797 | 0.040 | slow_lv_ht |
| Path 2 | PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/sync_st[1]:ALn | 1.587 | 23.204 | 5.890 | 29.094 | 0.170 | 1.796 | 0.039 | slow_lv_ht |
| Path 3 | PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[4]:ALn | 1.586 | 23.204 | 5.889 | 29.093 | 0.170 | 1.796 | 0.040 | slow_lv_ht |
| Path 4 | PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[2]:ALn | 1.586 | 23.204 | 5.889 | 29.093 | 0.170 | 1.796 | 0.040 | slow_lv_ht |
| Path 5 | PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[0]:ALn | 1.585 | 23.205 | 5.888 | 29.093 | 0.170 | 1.795 | 0.040 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | ||||||||
| To: PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[1]:ALn | ||||||||
| data required time | 29.093 | |||||||
| data arrival time | - | 5.890 | ||||||
| slack | 23.203 | |||||||
| Data arrival time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | 0.000 | 0.000 | ||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.593 | 2.593 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/Y_DIV | + | 0.000 | 2.593 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.152 | 2.745 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_NET | + | 0.379 | 3.124 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:Y | cell | ADLIB:GB | + | 0.152 | 3.276 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_Y | + | 0.387 | 3.663 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.052 | 3.715 | 127 | f | |
| PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:CLK | net | PF_CLK_DIV_C0_0_CLK_OUT | + | 0.588 | 4.303 | r | ||
| PF_XCVR_0_0/I_XCVR_CORELNKTMR/syncr:Q | cell | ADLIB:SLE | + | 0.175 | 4.478 | 115 | r | |
| PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[1]:ALn | net | PF_XCVR_0_0/I_XCVR_CORELNKTMR_CTRL_SRST_N | + | 1.412 | 5.890 | r | ||
| data arrival time | 5.890 | |||||||
| Data required time calculation | ||||||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV | Clock Constraint | 25.000 | 25.000 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV | Clock source | + | 0.000 | 25.000 | r | |||
| Clock generation | + | 2.316 | 27.316 | |||||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/Y_DIV | + | 0.000 | 27.316 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 27.447 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3_NET | + | 0.345 | 27.792 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3:Y | cell | ADLIB:GB | + | 0.138 | 27.930 | 1 | r | |
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:A | net | PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_Y | + | 0.350 | 28.280 | r | ||
| PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_RNIF7Q3/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 28.327 | 127 | f | |
| PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[1]:CLK | net | PF_CLK_DIV_C0_0_CLK_OUT | + | 0.520 | 28.847 | r | ||
| clock reconvergence pessimism | + | 0.416 | 29.263 | |||||
| PF_XCVR_0_0/I_XCVR_CORELCKMGT_0/fsm_st[1]:ALn | Library recovery time | ADLIB:SLE | - | 0.170 | 29.093 | |||
| data required time | 29.093 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin PF_OSC_160_0/PF_OSC_160_0/I_OSC_160_INT/U0_RGB1:A
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | PRBS_chk_0/prbs_asic_chk_inst/ioI[19]:CLK | PRBS_chk_0/reg_lock_ret_0:D | 2.773 | 0.897 | 4.049 | 4.946 | 0.000 | 2.807 | slow_lv_ht |
| Path 2 | PRBS_chk_0/prbs_asic_chk_inst/lI[6]:CLK | PRBS_chk_0/reg_lock_ret_0:D | 2.750 | 0.915 | 4.031 | 4.946 | 0.000 | 2.789 | slow_lv_ht |
| Path 3 | PRBS_chk_0/prbs_asic_chk_inst/ioI[18]:CLK | PRBS_chk_0/reg_lock_ret_0:D | 2.729 | 0.941 | 4.005 | 4.946 | 0.000 | 2.763 | slow_lv_ht |
| Path 4 | PRBS_chk_0/prbs_asic_chk_inst/lI[2]:CLK | PRBS_chk_0/reg_lock_ret_0:D | 2.690 | 0.974 | 3.972 | 4.946 | 0.000 | 2.730 | slow_lv_ht |
| Path 5 | PRBS_chk_0/prbs_asic_chk_inst/lI[18]:CLK | PRBS_chk_0/reg_lock_ret_0:D | 2.629 | 1.041 | 3.905 | 4.946 | 0.000 | 2.663 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PRBS_chk_0/prbs_asic_chk_inst/ioI[19]:CLK | ||||||||
| To: PRBS_chk_0/reg_lock_ret_0:D | ||||||||
| data required time | 4.946 | |||||||
| data arrival time | - | 4.049 | ||||||
| slack | 0.897 | |||||||
| Data arrival time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 0.000 | 0.000 | ||||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_rx_rclkint_input_net | + | 0.622 | 0.622 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint:Y | cell | ADLIB:RGB | + | 0.052 | 0.674 | 99 | f | |
| PRBS_chk_0/prbs_asic_chk_inst/ioI[19]:CLK | net | PF_XCVR_0_0_LANE0_RX_CLK_R | + | 0.602 | 1.276 | r | ||
| PRBS_chk_0/prbs_asic_chk_inst/ioI[19]:Q | cell | ADLIB:SLE | + | 0.175 | 1.451 | 1 | r | |
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_51:C | net | PRBS_chk_0/prbs_asic_chk_inst/ioI_Z[19] | + | 0.746 | 2.197 | r | ||
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_51:P | cell | ADLIB:ARI1_CC | + | 0.129 | 2.326 | 1 | f | |
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_1_CC_1:P[0] | net | NET_CC_CONFIG112 | + | 0.013 | 2.339 | f | ||
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_1_CC_1:CC[11] | cell | ADLIB:CC_CONFIG | + | 0.394 | 2.733 | 1 | r | |
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_93_FCINST1:CC | net | NET_CC_CONFIG159 | + | 0.000 | 2.733 | r | ||
| PRBS_chk_0/prbs_asic_chk_inst/OOl_0_I_93_FCINST1:CO | cell | ADLIB:FCEND_BUFF_CC | + | 0.055 | 2.788 | 1 | r | |
| PRBS_chk_0/reg_lock_ret_0:D | net | PRBS_chk_0/OOl_0_data_tmp[19] | + | 1.261 | 4.049 | r | ||
| data arrival time | 4.049 | |||||||
| Data required time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | Clock Constraint | 3.879 | 3.879 | |||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 3.879 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB1:A | net | PF_XCVR_0_0/I_XCVR/LANE0_rx_rclkint_input_net | + | 0.636 | 4.515 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | 4.562 | 1 | f | |
| PRBS_chk_0/reg_lock_ret_0:CLK | net | PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB1_rgb_net_1 | + | 0.525 | 5.087 | r | ||
| clock reconvergence pessimism | + | 0.034 | 5.121 | |||||
| clock uncertainty | - | 0.175 | 4.946 | |||||
| PRBS_chk_0/reg_lock_ret_0:D | Library setup time | ADLIB:SLE | - | 0.000 | 4.946 | |||
| data required time | 4.946 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | PRBS_chk_0/error_out:CLK | error_out | 5.676 | 4.463 | 7.037 | 11.500 | 7.037 | slow_lv_ht |
| Path 2 | PRBS_chk_0/lock:CLK | lock | 5.971 | 5.668 | 7.332 | 13.000 | 7.332 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PRBS_chk_0/error_out:CLK | ||||||||
| To: error_out | ||||||||
| data required time | 11.500 | |||||||
| data arrival time | - | 7.037 | ||||||
| slack | 4.463 | |||||||
| Data arrival time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 0.000 | 0.000 | ||||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2:A | net | PF_XCVR_0_0/I_XCVR/LANE0_rx_rclkint_input_net | + | 0.715 | 0.715 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2:Y | cell | ADLIB:RGB | + | 0.052 | 0.767 | 2 | f | |
| PRBS_chk_0/error_out:CLK | net | PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2_rgb_net_1 | + | 0.594 | 1.361 | r | ||
| PRBS_chk_0/error_out:Q | cell | ADLIB:SLE | + | 0.166 | 1.527 | 1 | f | |
| error_out_obuf/U_IOTRI:D | net | error_out_c | + | 2.559 | 4.086 | f | ||
| error_out_obuf/U_IOTRI:DOUT | cell | ADLIB:IOTRI_OB_EB | + | 0.918 | 5.004 | 1 | f | |
| error_out_obuf/U_IOPAD:D | net | error_out_obuf/DOUT | + | 0.000 | 5.004 | f | ||
| error_out_obuf/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.033 | 7.037 | 0 | f | |
| error_out | net | error_out | + | 0.000 | 7.037 | f | ||
| data arrival time | 7.037 | |||||||
| Data required time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | Max Delay Constraint | 12.500 | 12.500 | |||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 12.500 | r | |||
| error_out | Output Delay Constraint | - | 1.000 | 11.500 | f | |||
| data required time | 11.500 | |||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | PRBS_chk_0/lock:ALn | 2.447 | 1.069 | 3.721 | 4.790 | 0.170 | 2.635 | 0.018 | slow_lv_ht |
| Path 2 | reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | PRBS_chk_0/error_out:ALn | 2.447 | 1.069 | 3.721 | 4.790 | 0.170 | 2.635 | 0.018 | slow_lv_ht |
| Path 3 | reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | PRBS_chk_0/reg_lock_ret_0:ALn | 2.007 | 1.482 | 3.281 | 4.763 | 0.183 | 2.222 | 0.032 | slow_lv_ht |
| Path 4 | reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | PRBS_chk_0/prbs_asic_chk_inst/lI[15]:ALn | 0.923 | 2.561 | 2.197 | 4.758 | 0.183 | 1.143 | 0.037 | slow_lv_ht |
| Path 5 | reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | PRBS_chk_0/prbs_asic_chk_inst/ioI[15]:ALn | 0.923 | 2.562 | 2.197 | 4.759 | 0.183 | 1.142 | 0.036 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | ||||||||
| To: PRBS_chk_0/lock:ALn | ||||||||
| data required time | 4.790 | |||||||
| data arrival time | - | 3.721 | ||||||
| slack | 1.069 | |||||||
| Data arrival time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | 0.000 | 0.000 | ||||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_rx_rclkint_input_net | + | 0.622 | 0.622 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint:Y | cell | ADLIB:RGB | + | 0.052 | 0.674 | 99 | f | |
| reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:CLK | net | PF_XCVR_0_0_LANE0_RX_CLK_R | + | 0.600 | 1.274 | r | ||
| reset_logic_0/reset_syn_rx_0/reset_syn_rx_0/dff_15:Q | cell | ADLIB:SLE | + | 0.175 | 1.449 | 96 | r | |
| PRBS_chk_0/lock:ALn | net | reset_logic_0.reset_syn_rx_0.reset_syn_rx_0.dff | + | 2.272 | 3.721 | r | ||
| data arrival time | 3.721 | |||||||
| Data required time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R | Clock Constraint | 3.879 | 3.879 | |||||
| PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R | Clock source | + | 0.000 | 3.879 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2:A | net | PF_XCVR_0_0/I_XCVR/LANE0_rx_rclkint_input_net | + | 0.649 | 4.528 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2:Y | cell | ADLIB:RGB | + | 0.047 | 4.575 | 2 | f | |
| PRBS_chk_0/lock:CLK | net | PF_XCVR_0_0/I_XCVR/LANE0_RX_rclkint/U0_RGB2_rgb_net_1 | + | 0.526 | 5.101 | r | ||
| clock reconvergence pessimism | + | 0.034 | 5.135 | |||||
| clock uncertainty | - | 0.175 | 4.960 | |||||
| PRBS_chk_0/lock:ALn | Library recovery time | ADLIB:SLE | - | 0.170 | 4.790 | |||
| data required time | 4.790 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin PF_XCVR_0_0/I_XCVR/LANE0:TX_FWF_CLK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:D | 2.407 | 1.294 | 3.608 | 4.902 | 0.000 | 2.435 | slow_lv_ht |
| Path 2 | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[4]:D | 2.315 | 1.386 | 3.516 | 4.902 | 0.000 | 2.343 | slow_lv_ht |
| Path 3 | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[3]:D | 2.270 | 1.432 | 3.471 | 4.903 | 0.000 | 2.297 | slow_lv_ht |
| Path 4 | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[1]:D | 2.261 | 1.439 | 3.462 | 4.901 | 0.000 | 2.290 | slow_lv_ht |
| Path 5 | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_last[1]:CLK | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:D | 2.134 | 1.531 | 3.358 | 4.889 | 0.000 | 2.198 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | ||||||||
| To: PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:D | ||||||||
| data required time | 4.902 | |||||||
| data arrival time | - | 3.608 | ||||||
| slack | 1.294 | |||||||
| Data arrival time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 0.000 | 0.000 | ||||||
| PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.599 | 0.599 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.052 | 0.651 | 176 | f | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:CLK | net | PF_XCVR_0_0_LANE0_TX_CLK_R | + | 0.550 | 1.201 | r | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[0]:Q | cell | ADLIB:SLE | + | 0.175 | 1.376 | 7 | r | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xfreq_err_arb/abs_i_o2[1]:A | net | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/un1_rot_sh_3_o[0] | + | 0.416 | 1.792 | r | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xfreq_err_arb/abs_i_o2[1]:Y | cell | ADLIB:CFG2 | + | 0.105 | 1.897 | 3 | r | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_v_i_a0[0]:A | net | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/N_70 | + | 0.645 | 2.542 | r | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_v_i_a0[0]:Y | cell | ADLIB:CFG4 | + | 0.046 | 2.588 | 1 | f | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_cry_0:B | net | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_v_i_a0_Z[0] | + | 0.222 | 2.810 | f | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_cry_0:P | cell | ADLIB:ARI1_CC | + | 0.078 | 2.888 | 1 | f | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_cry_0_CC_0:P[0] | net | NET_CC_CONFIG224 | + | 0.013 | 2.901 | f | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_cry_0_CC_0:CC[5] | cell | ADLIB:CC_CONFIG | + | 0.342 | 3.243 | 1 | r | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_s_5:CC | net | NET_CC_CONFIG247 | + | 0.000 | 3.243 | r | ||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_s_5:S | cell | ADLIB:ARI1_CC | + | 0.055 | 3.298 | 1 | r | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:D | net | PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/un1_rot_sh_3_s_5_S | + | 0.310 | 3.608 | r | ||
| data arrival time | 3.608 | |||||||
| Data required time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | Clock Constraint | 3.879 | 3.879 | |||||
| PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 3.879 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.540 | 4.419 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.047 | 4.466 | 176 | f | |
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:CLK | net | PF_XCVR_0_0_LANE0_TX_CLK_R | + | 0.494 | 4.960 | r | ||
| clock reconvergence pessimism | + | 0.092 | 5.052 | |||||
| clock uncertainty | - | 0.150 | 4.902 | |||||
| PF_XCVR_0_0/I_XCVR_CORERFD_0/u_sicr/Xrot_sh_ctr/rot_sh_ret[5]:D | Library setup time | ADLIB:SLE | - | 0.000 | 4.902 | |||
| data required time | 4.902 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | PRBS_gen_0/prbs_asic_gen_inst/lI[20]:ALn | 1.104 | 2.402 | 2.331 | 4.733 | 0.183 | 1.327 | 0.040 | slow_lv_ht |
| Path 2 | reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | PRBS_gen_0/prbs_asic_gen_inst/lI[14]:ALn | 1.104 | 2.402 | 2.331 | 4.733 | 0.183 | 1.327 | 0.040 | slow_lv_ht |
| Path 3 | reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | PRBS_gen_0/prbs_asic_gen_inst/lI[10]:ALn | 1.104 | 2.402 | 2.331 | 4.733 | 0.183 | 1.327 | 0.040 | slow_lv_ht |
| Path 4 | reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | PRBS_gen_0/prbs_asic_gen_inst/lI[4]:ALn | 1.103 | 2.403 | 2.330 | 4.733 | 0.183 | 1.326 | 0.040 | slow_lv_ht |
| Path 5 | reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | PRBS_gen_0/prbs_asic_gen_inst/lI[1]:ALn | 1.103 | 2.403 | 2.330 | 4.733 | 0.183 | 1.326 | 0.040 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | ||||||||
| To: PRBS_gen_0/prbs_asic_gen_inst/lI[20]:ALn | ||||||||
| data required time | 4.733 | |||||||
| data arrival time | - | 2.331 | ||||||
| slack | 2.402 | |||||||
| Data arrival time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | 0.000 | 0.000 | ||||||
| PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.599 | 0.599 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.052 | 0.651 | 176 | f | |
| reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:CLK | net | PF_XCVR_0_0_LANE0_TX_CLK_R | + | 0.576 | 1.227 | r | ||
| reset_logic_0/reset_syn_tx_0/reset_syn_tx_0/dff_15:Q | cell | ADLIB:SLE | + | 0.179 | 1.406 | 123 | r | |
| PRBS_gen_0/prbs_asic_gen_inst/lI[20]:ALn | net | reset_logic_0.reset_syn_tx_0.reset_syn_tx_0.dff | + | 0.925 | 2.331 | r | ||
| data arrival time | 2.331 | |||||||
| Data required time calculation | ||||||||
| PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R | Clock Constraint | 3.879 | 3.879 | |||||
| PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 3.879 | r | |||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:A | net | PF_XCVR_0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.540 | 4.419 | r | ||
| PF_XCVR_0_0/I_XCVR/LANE0_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.047 | 4.466 | 176 | f | |
| PRBS_gen_0/prbs_asic_gen_inst/lI[20]:CLK | net | PF_XCVR_0_0_LANE0_TX_CLK_R | + | 0.508 | 4.974 | r | ||
| clock reconvergence pessimism | + | 0.092 | 5.066 | |||||
| clock uncertainty | - | 0.150 | 4.916 | |||||
| PRBS_gen_0/prbs_asic_gen_inst/lI[20]:ALn | Library recovery time | ADLIB:SLE | - | 0.183 | 4.733 | |||
| data required time | 4.733 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path