Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date      :  Thu Jan  7 09:24:44 2021
Project   :  C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project
Component :  PF_XCVR_0
Family    :  PolarFire


HDL source files for all Synthesis and Simulation tools:
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/SgCore/PF_XCVR_APBLINK_V/1.0.102/hdl/PF_XCVR_APBLINK_V.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTR.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/request_code.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode0.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode1.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELANEMSTR/2.0.100/rtl/vlog/core/CORELANEMSTRmode2.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORELCKMGT/2.0.100/rtl/vlog/core/CORELCKMGT.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFD.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDbincnt.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDfrqerrarb.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDgrycnt.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDplsgen.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDshcnt.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsicr.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsmplcnt.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsync.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/Actel/DirectCore/CORERFD/2.0.100/rtl/vlog/core/CORERFDsyncen.v
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_0/PF_XCVR_0.v

HDL source files for Synopsys SynplifyPro Synthesis tool:
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_0/I_XCVR/PF_XCVR_0_I_XCVR_PF_XCVR.v

Stimulus files for all Simulation tools:
    C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/AC468_DFE/Libero_Project/component/work/PF_XCVR_0/I_XCVR/PF_XCVR_0_I_XCVR_PF_XCVR_sim.v

