set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\acmtable.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructnvm_bb.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\iram512x9_rtl.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructram.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\debugblk.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\instructions.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram128x8_polarfire.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256x16_rtl.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256x8_rtl.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ram256xdwidth_ecc_g5.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\ramblocks.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst_0\rtl\vlog\core\coreabc.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\CoreABC_Inst\CoreABC_Inst.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\Flag_for_RXPLL_lock.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PF_INIT_MONITOR.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\INIT_MONITOR\INIT_MONITOR.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CCC_50\PF_CCC_50_0\PF_CCC_50_PF_CCC_50_0_PF_CCC.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CCC_50\PF_CCC_50.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0_0\PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_OSC_160\PF_OSC_160_0\PF_OSC_160_PF_OSC_160_0_PF_OSC.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_OSC_160\PF_OSC_160.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_TX_PLL_0\PF_TX_PLL_0_0\PF_TX_PLL_0_PF_TX_PLL_0_0_PF_TX_PLL.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_TX_PLL_0\PF_TX_PLL_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELCKMGT\2.0.100\rtl\vlog\core\CORELCKMGT.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDbincnt.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsmplcnt.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDfrqerrarb.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDgrycnt.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDplsgen.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDshcnt.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsyncen.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsync.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFDsicr.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORERFD\2.0.100\rtl\vlog\core\CORERFD.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_0\I_XCVR\PF_XCVR_0_I_XCVR_PF_XCVR.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\SgCore\PF_XCVR_APBLINK_V\1.0.102\hdl\PF_XCVR_APBLINK_V.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode0.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode1.v}
 add_include_path  {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTRmode2.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\Actel\DirectCore\CORELANEMSTR\2.0.100\rtl\vlog\core\CORELANEMSTR.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_0\PF_XCVR_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_DRI\PF_XCVR_DRI_0\PF_XCVR_DRI_PF_XCVR_DRI_0_PF_DRI.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_DRI\PF_XCVR_DRI.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_REF_CLK_0\PF_XCVR_REF_CLK_0_0\PF_XCVR_REF_CLK_0_PF_XCVR_REF_CLK_0_0_PF_XCVR_REF_CLK.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\PF_XCVR_REF_CLK_0\PF_XCVR_REF_CLK_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\prbs_asic_chk.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\PRBS_chk.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\prbs_asic_gen.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\hdl\PRBS_gen.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_rx\reset_syn_rx_0\core\corereset_pf.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_rx\reset_syn_rx.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_tx\reset_syn_tx_0\core\corereset_pf.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_syn_tx\reset_syn_tx.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\reset_logic\reset_logic.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\component\work\top\top.v}
set_top_level {top}
map_netlist
read_sdc {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\constraint\top_derived_constraints.sdc}
check_constraints {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\constraint\synthesis_sdc_errors.log}
write_fdc {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\AC468_DFE\Libero_Project\designer\top\synthesis.fdc}
