//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Jan  7 09:24:25 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

//////////////////////////////////////////////////////////////////////
// Component Description (Tcl) 
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CoreABC_Inst to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CoreABC_Inst
create_and_configure_core -core_vlnv {Actel:DirectCore:COREABC:3.8.102} -component_name {CoreABC_Inst} -params {\
"ABCCODE: $Wait_For_DFE_Trigger
IOREAD
JUMP IFNOT ZERO $DFE_Enable
JUMP $Wait_For_DFE_Trigger


$DFE_Enable


IOWRT 0x002 
APBREAD 0 0x1068
APBWRT DAT 0 0x1068 0x405


IOWRT 0x022
APBWRT DAT 0 0x10E0 0x00060E00

  
APBWRT DAT 0 0x10D8 0x00800010


APBWRT DAT 0 0x10DC 0x00000
APBWRT DAT 0 0x10DC 0x40000
APBWRT DAT 0 0x10DC 0x00000

 
$WaitCalibrate
APBREAD 0 0x1100
CMP 0x3FFFFFF
JUMP IFNOT ZERO $WaitCalibrate


$Calibrate_Done


IOWRT 0x002
APBWRT DAT 0 0x1068 0x404
IOWRT 0x003

$Wait_In_Loop
JUMP $Wait_In_Loop


HALT  "  \
"ACT_CALIBRATIONDATA:true"  \
"APB_AWIDTH:13"  \
"APB_DWIDTH:32"  \
"APB_SDEPTH:2"  \
"CODEHEXDUMP:"  \
"CODEHEXDUMP2:"  \
"DEBUG:true"  \
"EN_ACM:false"  \
"EN_ADD:true"  \
"EN_ALURAM:false"  \
"EN_AND:true"  \
"EN_CALL:true"  \
"EN_DATAM:2"  \
"EN_INC:true"  \
"EN_INDIRECT:false"  \
"EN_INT:0"  \
"EN_IOREAD:true"  \
"EN_IOWRT:true"  \
"EN_MULT:0"  \
"EN_OR:true"  \
"EN_PUSH:true"  \
"EN_RAM:true"  \
"EN_RAM_ECC:false"  \
"EN_SHL:true"  \
"EN_SHR:true"  \
"EN_XOR:true"  \
"ICWIDTH:5"  \
"IFWIDTH:0"  \
"IIWIDTH:1"  \
"IMEM_APB_ACCESS:0"  \
"INITWIDTH:11"  \
"INSMODE:0"  \
"IOWIDTH:10"  \
"ISRADDR:1"  \
"MAX_NVMDWIDTH:32"  \
"STWIDTH:4"  \
"TESTMODE:0"  \
"UNIQ_STRING:CoreABC_Inst_CoreABC_Inst_0"  \
"UNIQ_STRING_LENGTH:27"  \
"VERILOGCODE:"  \
"VERILOGVARS:"  \
"VHDLCODE:"  \
"VHDLVARS:"  \
"ZRWIDTH:0"   }
# Exporting Component Description of CoreABC_Inst to TCL done
*/

// CoreABC_Inst
module CoreABC_Inst(
    // Inputs
    IO_IN,
    NSYSRESET,
    PCLK,
    PRDATA_M,
    PREADY_M,
    PSLVERR_M,
    // Outputs
    IO_OUT,
    PADDR_M,
    PENABLE_M,
    PRESETN,
    PSEL_M,
    PWDATA_M,
    PWRITE_M
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  [0:0]  IO_IN;
input         NSYSRESET;
input         PCLK;
input  [31:0] PRDATA_M;
input         PREADY_M;
input         PSLVERR_M;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [9:0]  IO_OUT;
output [19:0] PADDR_M;
output        PENABLE_M;
output        PRESETN;
output        PSEL_M;
output [31:0] PWDATA_M;
output        PWRITE_M;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [19:0] APB3master_0_PADDR;
wire          APB3master_0_PENABLE;
wire   [31:0] PRDATA_M;
wire          PREADY_M;
wire          APB3master_0_PSELx;
wire          PSLVERR_M;
wire   [31:0] APB3master_0_PWDATA;
wire          APB3master_0_PWRITE;
wire   [0:0]  IO_IN;
wire   [9:0]  IO_OUT_0;
wire          NSYSRESET;
wire          PCLK;
wire          PRESETN_net_0;
wire          PRESETN_net_1;
wire   [19:0] APB3master_0_PADDR_net_0;
wire          APB3master_0_PSELx_net_0;
wire          APB3master_0_PENABLE_net_0;
wire          APB3master_0_PWRITE_net_0;
wire   [31:0] APB3master_0_PWDATA_net_0;
wire   [9:0]  IO_OUT_0_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire   [10:0] INITADDR_const_net_0;
wire   [8:0]  INITDATA_const_net_0;
wire          GND_net;
wire          VCC_net;
wire   [12:0] PADDR_S_const_net_0;
wire   [31:0] PWDATA_S_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign INITADDR_const_net_0 = 11'h000;
assign INITDATA_const_net_0 = 9'h000;
assign GND_net              = 1'b0;
assign VCC_net              = 1'b1;
assign PADDR_S_const_net_0  = 13'h0000;
assign PWDATA_S_const_net_0 = 32'h00000000;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign PRESETN_net_1              = PRESETN_net_0;
assign PRESETN                    = PRESETN_net_1;
assign APB3master_0_PADDR_net_0   = APB3master_0_PADDR;
assign PADDR_M[19:0]              = APB3master_0_PADDR_net_0;
assign APB3master_0_PSELx_net_0   = APB3master_0_PSELx;
assign PSEL_M                     = APB3master_0_PSELx_net_0;
assign APB3master_0_PENABLE_net_0 = APB3master_0_PENABLE;
assign PENABLE_M                  = APB3master_0_PENABLE_net_0;
assign APB3master_0_PWRITE_net_0  = APB3master_0_PWRITE;
assign PWRITE_M                   = APB3master_0_PWRITE_net_0;
assign APB3master_0_PWDATA_net_0  = APB3master_0_PWDATA;
assign PWDATA_M[31:0]             = APB3master_0_PWDATA_net_0;
assign IO_OUT_0_net_0             = IO_OUT_0;
assign IO_OUT[9:0]                = IO_OUT_0_net_0;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CoreABC_Inst_CoreABC_Inst_0_COREABC   -   Actel:DirectCore:COREABC:3.8.102
CoreABC_Inst_CoreABC_Inst_0_COREABC #( 
        .ACT_CALIBRATIONDATA ( 1 ),
        .APB_AWIDTH          ( 13 ),
        .APB_DWIDTH          ( 32 ),
        .APB_SDEPTH          ( 2 ),
        .DEBUG               ( 1 ),
        .EN_ACM              ( 0 ),
        .EN_ADD              ( 1 ),
        .EN_ALURAM           ( 0 ),
        .EN_AND              ( 1 ),
        .EN_CALL             ( 1 ),
        .EN_DATAM            ( 2 ),
        .EN_INC              ( 1 ),
        .EN_INDIRECT         ( 0 ),
        .EN_INT              ( 0 ),
        .EN_IOREAD           ( 1 ),
        .EN_IOWRT            ( 1 ),
        .EN_MULT             ( 0 ),
        .EN_OR               ( 1 ),
        .EN_PUSH             ( 1 ),
        .EN_RAM              ( 1 ),
        .EN_RAM_ECC          ( 0 ),
        .EN_SHL              ( 1 ),
        .EN_SHR              ( 1 ),
        .EN_XOR              ( 1 ),
        .FAMILY              ( 26 ),
        .ICWIDTH             ( 5 ),
        .IFWIDTH             ( 0 ),
        .IIWIDTH             ( 1 ),
        .IMEM_APB_ACCESS     ( 0 ),
        .INITWIDTH           ( 11 ),
        .INSMODE             ( 0 ),
        .IOWIDTH             ( 10 ),
        .ISRADDR             ( 1 ),
        .MAX_NVMDWIDTH       ( 32 ),
        .STWIDTH             ( 4 ),
        .TESTMODE            ( 0 ),
        .UNIQ_STRING_LENGTH  ( 27 ),
        .ZRWIDTH             ( 0 ) )
CoreABC_Inst_0(
        // Inputs
        .INITADDR   ( INITADDR_const_net_0 ), // tied to 11'h000 from definition
        .INITDATA   ( INITDATA_const_net_0 ), // tied to 9'h000 from definition
        .INITDATVAL ( GND_net ), // tied to 1'b0 from definition
        .INITDONE   ( VCC_net ), // tied to 1'b1 from definition
        .INTREQ     ( GND_net ), // tied to 1'b0 from definition
        .IO_IN      ( IO_IN ),
        .NSYSRESET  ( NSYSRESET ),
        .PCLK       ( PCLK ),
        .PRDATA_M   ( PRDATA_M ),
        .PREADY_M   ( PREADY_M ),
        .PSLVERR_M  ( PSLVERR_M ),
        .PADDR_S    ( PADDR_S_const_net_0 ), // tied to 13'h0000 from definition
        .PSEL_S     ( GND_net ), // tied to 1'b0 from definition
        .PENABLE_S  ( GND_net ), // tied to 1'b0 from definition
        .PWRITE_S   ( GND_net ), // tied to 1'b0 from definition
        .PWDATA_S   ( PWDATA_S_const_net_0 ), // tied to 32'h00000000 from definition
        // Outputs
        .INTACT     (  ),
        .IO_OUT     ( IO_OUT_0 ),
        .PRESETN    ( PRESETN_net_0 ),
        .PADDR_M    ( APB3master_0_PADDR ),
        .PENABLE_M  ( APB3master_0_PENABLE ),
        .PSEL_M     ( APB3master_0_PSELx ),
        .PWDATA_M   ( APB3master_0_PWDATA ),
        .PWRITE_M   ( APB3master_0_PWRITE ),
        .PRDATA_S   (  ),
        .PREADY_S   (  ),
        .PSLVERR_S  (  ) 
        );


endmodule
