# Exporting core CoreABC_Inst to TCL
# Exporting Create design command for core CoreABC_Inst
create_and_configure_core -core_vlnv Actel:DirectCore:COREABC:$COREABCver -component_name {CoreABC_Inst} -params {\
"ABCCODE: $Wait_For_DFE_Trigger
IOREAD
JUMP IFNOT ZERO $DFE_Enable
JUMP $Wait_For_DFE_Trigger


$DFE_Enable


IOWRT 0x002 
APBREAD 0 0x1068
APBWRT DAT 0 0x1068 0x405


IOWRT 0x022
APBWRT DAT 0 0x10E0 0x00060E00

  
APBWRT DAT 0 0x10D8 0x00800010


APBWRT DAT 0 0x10DC 0x00000
APBWRT DAT 0 0x10DC 0x40000
APBWRT DAT 0 0x10DC 0x00000

 
$WaitCalibrate
APBREAD 0 0x1100
CMP 0x3FFFFFF
JUMP IFNOT ZERO $WaitCalibrate


$Calibrate_Done


IOWRT 0x002
APBWRT DAT 0 0x1068 0x404
IOWRT 0x003

$Wait_In_Loop
JUMP $Wait_In_Loop


HALT  "  \
"ACT_CALIBRATIONDATA:true"  \
"APB_AWIDTH:13"  \
"APB_DWIDTH:32"  \
"APB_SDEPTH:2"  \
"CODEHEXDUMP:"  \
"CODEHEXDUMP2:"  \
"DEBUG:true"  \
"EN_ACM:false"  \
"EN_ADD:true"  \
"EN_ALURAM:false"  \
"EN_AND:true"  \
"EN_CALL:true"  \
"EN_DATAM:2"  \
"EN_INC:true"  \
"EN_INDIRECT:false"  \
"EN_INT:0"  \
"EN_IOREAD:true"  \
"EN_IOWRT:true"  \
"EN_MULT:0"  \
"EN_OR:true"  \
"EN_PUSH:true"  \
"EN_RAM:true"  \
"EN_SHL:true"  \
"EN_SHR:true"  \
"EN_XOR:true"  \
"ICWIDTH:5"  \
"IFWIDTH:0"  \
"IIWIDTH:1"  \
"IMEM_APB_ACCESS:0"  \
"INITWIDTH:11"  \
"INSMODE:0"  \
"IOWIDTH:10"  \
"ISRADDR:1"  \
"MAX_NVMDWIDTH:32"  \
"STWIDTH:4"  \
"TESTMODE:0"  \
"UNIQ_STRING:CoreABC_Inst_CoreABC_Inst_0"  \
"UNIQ_STRING_LENGTH:27"  \
"VERILOGCODE:"  \
"VERILOGVARS:"  \
"VHDLCODE:"  \
"VHDLVARS:"  \
"ZRWIDTH:0"   }
# Exporting core CoreABC_Inst to TCL done
