# Import source files
import_files -hdl_source {./src/src_hdl/Flag_for_RXPLL_lock.v}
import_files -hdl_source {./src/src_hdl/prbs_asic_chk.v}
import_files -hdl_source {./src/src_hdl/prbs_asic_gen.v}
import_files -hdl_source {./src/src_hdl/PRBS_chk.v}
import_files -hdl_source {./src/src_hdl/PRBS_gen.v}



build_design_hierarchy 

# Create, configure and generate core components
source ./src/src_components/CoreABC_Inst.tcl
source ./src/src_components/INIT_MONITOR.tcl
source ./src/src_components/PF_CCC_50.tcl
source ./src/src_components/PF_CLK_DIV_C0.tcl
source ./src/src_components/PF_OSC_160.tcl
source ./src/src_components/PF_TX_PLL_0.tcl
source ./src/src_components/PF_XCVR_0.tcl
source ./src/src_components/PF_XCVR_DRI.tcl
source ./src/src_components/PF_XCVR_REF_CLK_0.tcl
source ./src/src_components/reset_syn_rx.tcl
source ./src/src_components/reset_syn_tx.tcl






# Generate SmartDesign Components

source ./src/src_components/reset_logic.tcl
build_design_hierarchy 
source ./src/src_components/top.tcl
# Set top level module
build_design_hierarchy 
set_root -module {top::work} 

save_project
puts "Design generated successfully\n"
