`timescale 1 ns/100 ps
// ********************************************************************/
// Copyright 2019 Microsemi Corporation.  All rights reserved.
// IP Engineering
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// File:  ram256xdwidth_ecc_g5.v
//
// Description: G5 RAM blocks with ECC support enabled
//
//
// SVN Revision Information:
// SVN $Revision: 22329 $
// SVN $Date: 2014-04-10 15:08:25 +0100 (Thu, 10 Apr 2014) $
//
// Notes:
//
// *********************************************************************/
module CoreABC_Inst_CoreABC_Inst_0_RAM256XDWIDTH_ECC (
       WD,
       RD,
       WADDR,
       RADDR,
       WEN,
       WCLK,
       RCLK,
       SB_CORRECT,
       DB_DETECT
    );

    parameter DWIDTH = 8;

    input  [DWIDTH-1:0] WD;
    output [DWIDTH-1:0] RD;
    input  [7:0] WADDR;
    input  [7:0] RADDR;
    input  WEN;
    input  WCLK;
    input  RCLK;
    output SB_CORRECT;
    output DB_DETECT;

    wire ACCESS_BUSY, VCC, GND, ADLIB_VCC;
    wire GND_power_net1;
    wire VCC_power_net1;

    assign GND = GND_power_net1;
    assign VCC = VCC_power_net1;
    assign ADLIB_VCC = VCC_power_net1;
    
    GND GND_power_inst1 (
        .Y(GND_power_net1)
    );

    VCC VCC_power_inst1 (
        .Y(VCC_power_net1)
    );

    generate 
        if (DWIDTH == 8)
        begin : U_RAM256X8
            RAM1K20 RAM1K20_R0C0 (
                .A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19}), 
                .B_DOUT({nc20, nc21, nc22, nc23, nc24, nc25, nc26, nc27, nc28, nc29, nc30, nc31, RD[7:0]}), 
                .DB_DETECT(DB_DETECT), 
                .SB_CORRECT(SB_CORRECT), 
                .ACCESS_BUSY(ACCESS_BUSY), 
                .A_ADDR({GND, RADDR[7:0], GND, GND, GND, GND, GND}), 
                .A_BLK_EN({VCC, VCC, VCC}), 
                .A_CLK(RCLK), 
                .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
                .A_REN(VCC), 
                .A_WEN({VCC, VCC}), 
                .A_DOUT_EN(VCC), 
                .A_DOUT_ARST_N(VCC), 
                .A_DOUT_SRST_N(VCC), 
                .B_ADDR({GND, WADDR[7:0], GND, GND, GND, GND, GND}), 
                .B_BLK_EN({WEN, VCC, VCC}), 
                .B_CLK(WCLK), 
                .B_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, nc32, nc33, nc34, WD[7:0]}), 
                .B_REN(VCC), 
                .B_WEN({VCC, VCC}), 
                .B_DOUT_EN(VCC), 
                .B_DOUT_ARST_N(VCC), 
                .B_DOUT_SRST_N(VCC), 
                .ECC_EN(VCC), 
                .BUSY_FB(GND), 
                .A_WIDTH({VCC, GND, VCC}), 
                .A_WMODE({GND, GND}), 
                .A_BYPASS(VCC), 
                .B_WIDTH({VCC, GND, VCC}), 
                .B_WMODE({GND, GND}), 
                .B_BYPASS(VCC), 
                .ECC_BYPASS(VCC)
            );
        end
    endgenerate

    generate 
        if (DWIDTH == 16)
        begin : U_RAM256X16
            RAM1K20 RAM1K20_R0C0 (
                .A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, nc12, nc13, nc14, nc15, nc16, nc17, nc18, nc19}), 
                .B_DOUT({nc20, nc21, nc22, nc23, RD[15:0]}), 
                .DB_DETECT(DB_DETECT), 
                .SB_CORRECT(SB_CORRECT), 
                .ACCESS_BUSY(ACCESS_BUSY), 
                .A_ADDR({GND, RADDR[7:0], GND, GND, GND, GND, GND}), 
                .A_BLK_EN({VCC, VCC, VCC}), 
                .A_CLK(RCLK), 
                .A_DIN({GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND, GND}), 
                .A_REN(VCC), 
                .A_WEN({VCC, VCC}), 
                .A_DOUT_EN(VCC), 
                .A_DOUT_ARST_N(VCC), 
                .A_DOUT_SRST_N(VCC), 
                .B_ADDR({GND, WADDR[7:0], GND, GND, GND, GND, GND}), 
                .B_BLK_EN({WEN, VCC, VCC}), 
                .B_CLK(WCLK), 
                .B_DIN({GND, GND, GND, nc24, WD[15:0]}), 
                .B_REN(VCC), 
                .B_WEN({VCC, VCC}), 
                .B_DOUT_EN(VCC), 
                .B_DOUT_ARST_N(VCC), 
                .B_DOUT_SRST_N(VCC), 
                .ECC_EN(VCC), 
                .BUSY_FB(GND), 
                .A_WIDTH({VCC, GND, VCC}), 
                .A_WMODE({GND, GND}), 
                .A_BYPASS(VCC), 
                .B_WIDTH({VCC, GND, VCC}), 
                .B_WMODE({GND, GND}), 
                .B_BYPASS(VCC), 
                .ECC_BYPASS(VCC)
            );
        end
    endgenerate

    generate 
        if (DWIDTH == 32)
        begin : U_RAM256X32
            RAM1K20 RAM1K20_R0C0 (
                .A_DOUT({nc0, nc1, nc2, nc3, nc4, RD[31:17]}), 
                .B_DOUT({nc5, nc6, nc7, RD[16:0]}), 
                .DB_DETECT(DB_DETECT), 
                .SB_CORRECT(SB_CORRECT), 
                .ACCESS_BUSY(ACCESS_BUSY), 
                .A_ADDR({GND, RADDR[7:0], GND, GND, GND, GND, GND}), 
                .A_BLK_EN({VCC, VCC, VCC}), 
                .A_CLK(RCLK), 
                .A_DIN({GND, GND, GND, GND, GND, WD[31:17]}), 
                .A_REN(VCC), 
                .A_WEN({VCC, VCC}), 
                .A_DOUT_EN(VCC), 
                .A_DOUT_ARST_N(VCC), 
                .A_DOUT_SRST_N(VCC), 
                .B_ADDR({GND, WADDR[7:0], GND, GND, GND, GND, GND}), 
                .B_BLK_EN({WEN, VCC, VCC}), 
                .B_CLK(WCLK), 
                .B_DIN({GND, GND, GND, WD[16:0]}), 
                .B_REN(VCC), 
                .B_WEN({VCC, VCC}), 
                .B_DOUT_EN(VCC), 
                .B_DOUT_ARST_N(VCC), 
                .B_DOUT_SRST_N(VCC), 
                .ECC_EN(VCC), 
                .BUSY_FB(GND), 
                .A_WIDTH({VCC, GND, VCC}), 
                .A_WMODE({GND, GND}), 
                .A_BYPASS(VCC), 
                .B_WIDTH({VCC, GND, VCC}), 
                .B_WMODE({GND, GND}), 
                .B_BYPASS(VCC), 
                .ECC_BYPASS(VCC)
            );
        end
    endgenerate

endmodule

