# Creating SmartDesign reset_logic
set sd_name {reset_logic}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {tx_clk} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {tx_clk_stable} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {INIT_DONE} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_clk} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {rx_val} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {prbs_gen_rst_n} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {prbs_chk_rst_n} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BANK_y_VDDI_STATUS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {FPGA_POR_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PLL_POWERDOWN_B} -port_direction {OUT}


# Add reset_syn_rx_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_syn_rx} -instance_name {reset_syn_rx_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_rx_0:PLL_LOCK} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_rx_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_rx_0:FF_US_RESTORE} -value {GND}



# Add reset_syn_tx_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_syn_tx} -instance_name {reset_syn_tx_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_tx_0:PLL_LOCK} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_tx_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {reset_syn_tx_0:FF_US_RESTORE} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {reset_syn_tx_0:PLL_POWERDOWN_B}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_syn_rx_0:BANK_x_VDDI_STATUS" "reset_syn_rx_0:BANK_y_VDDI_STATUS" "reset_syn_tx_0:BANK_y_VDDI_STATUS" "reset_syn_tx_0:BANK_x_VDDI_STATUS" "BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"FPGA_POR_N" "reset_syn_rx_0:FPGA_POR_N" "reset_syn_tx_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_DONE" "reset_syn_rx_0:INIT_DONE" "reset_syn_tx_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PLL_POWERDOWN_B" "reset_syn_rx_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"prbs_chk_rst_n" "reset_syn_rx_0:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"prbs_gen_rst_n" "reset_syn_tx_0:FABRIC_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rx_clk" "reset_syn_rx_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rx_val" "reset_syn_rx_0:EXT_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"tx_clk" "reset_syn_tx_0:CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"tx_clk_stable" "reset_syn_tx_0:EXT_RST_N" }



# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign reset_logic
generate_component -component_name ${sd_name}
