# Creating SmartDesign top
set sd_name {top}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_CALIBRATING} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {DFE_CAL_DONE} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {lock} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {error_out} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SWITCH} -port_direction {IN}


# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add CoreABC_Inst_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreABC_Inst} -instance_name {CoreABC_Inst_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreABC_Inst_0:IO_OUT} -pin_slices {[0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreABC_Inst_0:IO_OUT} -pin_slices {[9:1]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PADDR_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PSEL_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PENABLE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PWRITE_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PRDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PWDATA_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PREADY_M}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {CoreABC_Inst_0:APB3master} -pin_names {CoreABC_Inst_0:PSLVERR_M}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreABC_Inst_0:PRESETN}



# Add Flag_for_RXPLL_lock_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {Flag_for_RXPLL_lock} -hdl_file {hdl\Flag_for_RXPLL_lock.v} -instance_name {Flag_for_RXPLL_lock_0}



# Add INIT_MONITOR_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {INIT_MONITOR} -instance_name {INIT_MONITOR_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:SRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {INIT_MONITOR_0:AUTOCALIB_DONE}



# Add PF_CCC_50_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_50} -instance_name {PF_CCC_50_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_CCC_50_0:PLL_LOCK_0}



# Add PF_CLK_DIV_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CLK_DIV_C0} -instance_name {PF_CLK_DIV_C0_0}



# Add PF_OSC_160_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_160} -instance_name {PF_OSC_160_0}



# Add PF_TX_PLL_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_0} -instance_name {PF_TX_PLL_0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_0_0:PLL_LOCK}



# Add PF_XCVR_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_0} -instance_name {PF_XCVR_0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_SLIP} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_0_0:LANE0_LOS} -value {GND}



# Add PF_XCVR_DRI_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_DRI} -instance_name {PF_XCVR_DRI_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_XCVR_DRI_0:PADDR} -pin_slices {[19:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_XCVR_DRI_0:PADDR} -pin_slices {[28:20]}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PADDR}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PSEL}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PENABLE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PWRITE}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PRDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PWDATA}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PREADY}
sd_show_bif_pins -sd_name ${sd_name} -bif_pin_name {PF_XCVR_DRI_0:APBS} -pin_names {PF_XCVR_DRI_0:PSLVERR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_DRI_0:PINTERRUPT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_DRI_0:PTIMEOUT}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_DRI_0:BUSERROR}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_DRI_0:PSTRB} -value {VCC}



# Add PF_XCVR_REF_CLK_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_0} -instance_name {PF_XCVR_REF_CLK_0_0}



# Add PRBS_chk_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {PRBS_chk} -hdl_file {hdl\PRBS_chk.v} -instance_name {PRBS_chk_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PRBS_chk_0:clr_err_counter} -value {GND}



# Add PRBS_gen_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {PRBS_gen} -hdl_file {hdl\PRBS_gen.v} -instance_name {PRBS_gen_0}



# Add reset_logic_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {reset_logic} -instance_name {reset_logic_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CoreABC_Inst_0:NSYSRESET" "PF_XCVR_DRI_0:PRESETN" "Flag_for_RXPLL_lock_0:reset_n_i" "PF_XCVR_0_0:LANE0_CALIB_REQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PENABLE_M" "PF_XCVR_DRI_0:PENABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PSEL_M" "PF_XCVR_DRI_0:PSEL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PWRITE_M" "PF_XCVR_DRI_0:PWRITE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:IO_OUT[0]" "DFE_CAL_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"error_out" "PRBS_chk_0:error_out" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:IO_IN" "Flag_for_RXPLL_lock_0:flag_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR_0:BANK_6_VDDI_STATUS" "reset_logic_0:BANK_y_VDDI_STATUS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR_0:DEVICE_INIT_DONE" "AND2_0:B" "reset_logic_0:INIT_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR_0:FABRIC_POR_N" "reset_logic_0:FPGA_POR_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"INIT_MONITOR_0:XCVR_INIT_DONE" "PF_XCVR_0_0:LANE0_PCS_ARST_N" "PF_XCVR_0_0:LANE0_PMA_ARST_N" "PF_XCVR_0_0:CTRL_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_CALIBRATING" "LANE0_CALIBRATING" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RXD_N" "LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RXD_P" "LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TXD_N" "LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TXD_P" "LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"lock" "PRBS_chk_0:lock" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PCLK" "PF_CCC_50_0:OUT0_FABCLK_0" "PF_XCVR_DRI_0:PCLK" "Flag_for_RXPLL_lock_0:clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CLK_DIV_C0_0:CLK_OUT" "PF_XCVR_0_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_50_0:REF_CLK_0" "PF_CLK_DIV_C0_0:CLK_IN" "PF_OSC_160_0:RCOSC_160MHZ_GL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_CLK_R" "reset_logic_0:rx_clk" "PRBS_chk_0:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Flag_for_RXPLL_lock_0:rx_idle_i" "PF_XCVR_0_0:LANE0_RX_IDLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Flag_for_RXPLL_lock_0:rx_ready_i" "PF_XCVR_0_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_VAL" "reset_logic_0:rx_val" "PRBS_chk_0:rx_val" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_R" "reset_logic_0:tx_clk" "PRBS_gen_0:clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_CLK_STABLE" "reset_logic_0:tx_clk_stable" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PREADY_M" "PF_XCVR_DRI_0:PREADY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PSLVERR_M" "PF_XCVR_DRI_0:PSLVERR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_0_0:REF_CLK" "PF_XCVR_0_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_N" "PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"REF_CLK_PAD_P" "PF_XCVR_REF_CLK_0_0:REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_50_0:PLL_POWERDOWN_N_0" "reset_logic_0:PLL_POWERDOWN_B" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_logic_0:prbs_chk_rst_n" "PRBS_chk_0:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_logic_0:prbs_gen_rst_n" "PRBS_gen_0:reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SWITCH" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:IO_OUT[9:1]" "PF_XCVR_DRI_0:PADDR[28:20]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PADDR_M" "PF_XCVR_DRI_0:PADDR[19:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PWDATA_M" "PF_XCVR_DRI_0:PWDATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_RX_DATA" "PRBS_chk_0:data_in" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreABC_Inst_0:PRDATA_M" "PF_XCVR_DRI_0:PRDATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_TX_DATA" "PRBS_gen_0:data_out" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:CLKS_FROM_TXPLL_0" "PF_TX_PLL_0_0:CLKS_TO_XCVR" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_0_0:LANE0_DRI_SLAVE" "PF_XCVR_DRI_0:Q2_LANE0_DRI" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign top
generate_component -component_name ${sd_name}
