"PF_CCC_50_0/PF_CCC_50_0/pll_inst_0/OUT0",20,"PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0","PF_CCC_50_0/PF_CCC_50_0/pll_inst_0:OUT0"
"PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD/Y_DIV",25,"PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV","PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:Y_DIV"
"PF_OSC_160_0/PF_OSC_160_0/I_OSC_160/CLK",6.25,"PF_OSC_160_0/PF_OSC_160_0/I_OSC_160:CLK","PF_OSC_160_0/PF_OSC_160_0/I_OSC_160:CLK"
"PF_XCVR_0_0/I_XCVR/LANE0/RX_CLK_R",3.879,"PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R","PF_XCVR_0_0/I_XCVR/LANE0:RX_CLK_R"
"PF_XCVR_0_0/I_XCVR/LANE0/TX_CLK_R",3.879,"PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R","PF_XCVR_0_0/I_XCVR/LANE0:TX_CLK_R"
"REF_CLK_PAD_P",8,"REF_CLK_PAD_P","REF_CLK_PAD_P"
