`timescale 1 ns / 100 ps
// ********************************************************************/
// Copyright 2012 Actel Corporation.  All rights reserved.
// IP Engineering
//
// ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
// ACCORDANCE WITH THE ACTEL LICENSE AGREEMENT AND MUST BE APPROVED
// IN ADVANCE IN WRITING.
//
// File:  ram128x8_smartfusion2.v
//
// Description: Simple APB Bus Controller
//              Low Level RAM Model (SmartFusion2 Family)
//
//
// SVN Revision Information:
// SVN $Revision: 22329 $
// SVN $Date: 2014-04-10 15:08:25 +0100 (Thu, 10 Apr 2014) $
//
// Notes:
//
// *********************************************************************/
module CoreABC_Inst_CoreABC_Inst_0_RAM128X8(
       WD,
       RD,
       WADDR,
       RADDR,
       WEN,
       WCLK,
       RCLK,
       RESETN
    );
input  [7:0] WD;
input RESETN;
output [7:0] RD;
input  [6:0] WADDR;
input  [6:0] RADDR;
input  WEN;
input  WCLK;
input  RCLK;
    
    RAM1K20 RAM1K20_R0C0 (
	.A_DOUT({nc0, nc1, nc2, nc3, nc4, nc5, nc6, nc7, nc8, nc9, nc10, nc11, RD[7:0]}), 
	.B_DOUT(/*NC*/), 
	.DB_DETECT(/*NC*/), 
	.SB_CORRECT(/*NC*/), 
	.ACCESS_BUSY(/*NC*/), 
	.A_ADDR({4'b0, RADDR[6:0], 3'b0}), 
	.A_BLK_EN(3'b111), 
	.A_CLK(RCLK), 
	.A_DIN(20'b0), 
	.A_REN(1'b1), 
	.A_WEN(2'b0),
	.A_DOUT_EN(1'b0), 
	.A_DOUT_ARST_N(1'b1), 
	.A_DOUT_SRST_N(1'b1), 
	.B_ADDR({4'b0, WADDR[6:0], 3'b0}), 
	.B_BLK_EN({WEN, 1'b1, 1'b1}), 
    .B_CLK(WCLK), 
	.B_DIN({12'b0, WD[7:0]}), 
	.B_REN(1'b1), 
	.B_WEN({1'b0, 1'b1}), 
	.B_DOUT_EN(1'b1), 
	.B_DOUT_ARST_N(1'b0), 
	.B_DOUT_SRST_N(1'b1), 
	.ECC_EN(1'b0), 
	.BUSY_FB(1'b0), 
	.A_WIDTH(3'b011), 
	.A_WMODE(2'b0), 
	.A_BYPASS(1'b1), 
	.B_WIDTH(3'b011), 
	.B_WMODE({2'b0}), 
	.B_BYPASS(1'b1), 
	.ECC_BYPASS(1'b0));
    
endmodule
