//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Thu Jan  7 09:25:02 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    LANE0_RXD_N,
    LANE0_RXD_P,
    REF_CLK_PAD_N,
    REF_CLK_PAD_P,
    SWITCH,
    // Outputs
    DFE_CAL_DONE,
    LANE0_CALIBRATING,
    LANE0_TXD_N,
    LANE0_TXD_P,
    error_out,
    lock
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input  LANE0_RXD_N;
input  LANE0_RXD_P;
input  REF_CLK_PAD_N;
input  REF_CLK_PAD_P;
input  SWITCH;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output DFE_CAL_DONE;
output LANE0_CALIBRATING;
output LANE0_TXD_N;
output LANE0_TXD_P;
output error_out;
output lock;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire          AND2_0_Y;
wire   [9:1]  CoreABC_Inst_0_IO_OUT9to1;
wire   [19:0] CoreABC_Inst_0_PADDR_M;
wire          CoreABC_Inst_0_PENABLE_M;
wire          CoreABC_Inst_0_PSEL_M;
wire   [31:0] CoreABC_Inst_0_PWDATA_M;
wire          CoreABC_Inst_0_PWRITE_M;
wire   [0:0]  DFE_CAL_DONE_net_0;
wire          error_out_net_0;
wire          Flag_for_RXPLL_lock_0_flag_o;
wire          INIT_MONITOR_0_BANK_6_VDDI_STATUS;
wire          INIT_MONITOR_0_DEVICE_INIT_DONE;
wire          INIT_MONITOR_0_FABRIC_POR_N;
wire          INIT_MONITOR_0_XCVR_INIT_DONE;
wire          LANE0_CALIBRATING_net_0;
wire          LANE0_RXD_N;
wire          LANE0_RXD_P;
wire          LANE0_TXD_N_net_0;
wire          LANE0_TXD_P_net_0;
wire          lock_net_0;
wire          PF_CCC_50_0_OUT0_FABCLK_0;
wire          PF_CLK_DIV_C0_0_CLK_OUT;
wire          PF_OSC_160_0_RCOSC_160MHZ_GL;
wire          PF_TX_PLL_0_0_CLKS_TO_XCVR_BIT_CLK;
wire          PF_TX_PLL_0_0_CLKS_TO_XCVR_LOCK;
wire          PF_TX_PLL_0_0_CLKS_TO_XCVR_REF_CLK_TO_LANE;
wire          PF_XCVR_0_0_LANE0_RX_CLK_R;
wire   [39:0] PF_XCVR_0_0_LANE0_RX_DATA;
wire          PF_XCVR_0_0_LANE0_RX_IDLE;
wire          PF_XCVR_0_0_LANE0_RX_READY;
wire          PF_XCVR_0_0_LANE0_RX_VAL;
wire          PF_XCVR_0_0_LANE0_TX_CLK_R;
wire          PF_XCVR_0_0_LANE0_TX_CLK_STABLE;
wire   [31:0] PF_XCVR_DRI_0_PRDATA;
wire          PF_XCVR_DRI_0_PREADY;
wire          PF_XCVR_DRI_0_PSLVERR;
wire          PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_ARST_N;
wire          PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CLK;
wire   [10:0] PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CTRL;
wire          PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_INTERRUPT;
wire   [32:0] PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_RDATA;
wire   [32:0] PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_WDATA;
wire          PF_XCVR_REF_CLK_0_0_REF_CLK;
wire   [39:0] PRBS_gen_0_data_out;
wire          REF_CLK_PAD_N;
wire          REF_CLK_PAD_P;
wire          reset_logic_0_PLL_POWERDOWN_B;
wire          reset_logic_0_prbs_chk_rst_n;
wire          reset_logic_0_prbs_gen_rst_n;
wire          SWITCH;
wire          LANE0_TXD_P_net_1;
wire          LANE0_TXD_N_net_1;
wire          LANE0_CALIBRATING_net_1;
wire          DFE_CAL_DONE_net_1;
wire          lock_net_1;
wire          error_out_net_1;
wire   [28:0] PADDR_net_0;
wire   [9:0]  IO_OUT_net_0;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
wire   [3:0]  PSTRB_const_net_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net           = 1'b0;
assign PSTRB_const_net_0 = 4'hF;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign LANE0_TXD_P_net_1       = LANE0_TXD_P_net_0;
assign LANE0_TXD_P             = LANE0_TXD_P_net_1;
assign LANE0_TXD_N_net_1       = LANE0_TXD_N_net_0;
assign LANE0_TXD_N             = LANE0_TXD_N_net_1;
assign LANE0_CALIBRATING_net_1 = LANE0_CALIBRATING_net_0;
assign LANE0_CALIBRATING       = LANE0_CALIBRATING_net_1;
assign DFE_CAL_DONE_net_1      = DFE_CAL_DONE_net_0[0];
assign DFE_CAL_DONE            = DFE_CAL_DONE_net_1;
assign lock_net_1              = lock_net_0;
assign lock                    = lock_net_1;
assign error_out_net_1         = error_out_net_0;
assign error_out               = error_out_net_1;
//--------------------------------------------------------------------
// Slices assignments
//--------------------------------------------------------------------
assign CoreABC_Inst_0_IO_OUT9to1 = IO_OUT_net_0[9:1];
assign DFE_CAL_DONE_net_0[0]     = IO_OUT_net_0[0:0];
//--------------------------------------------------------------------
// Concatenation assignments
//--------------------------------------------------------------------
assign PADDR_net_0 = { CoreABC_Inst_0_IO_OUT9to1 , CoreABC_Inst_0_PADDR_M };
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------AND2
AND2 AND2_0(
        // Inputs
        .A ( SWITCH ),
        .B ( INIT_MONITOR_0_DEVICE_INIT_DONE ),
        // Outputs
        .Y ( AND2_0_Y ) 
        );

//--------CoreABC_Inst
CoreABC_Inst CoreABC_Inst_0(
        // Inputs
        .IO_IN     ( Flag_for_RXPLL_lock_0_flag_o ),
        .NSYSRESET ( AND2_0_Y ),
        .PCLK      ( PF_CCC_50_0_OUT0_FABCLK_0 ),
        .PREADY_M  ( PF_XCVR_DRI_0_PREADY ),
        .PSLVERR_M ( PF_XCVR_DRI_0_PSLVERR ),
        .PRDATA_M  ( PF_XCVR_DRI_0_PRDATA ),
        // Outputs
        .PRESETN   (  ),
        .PADDR_M   ( CoreABC_Inst_0_PADDR_M ),
        .PSEL_M    ( CoreABC_Inst_0_PSEL_M ),
        .PENABLE_M ( CoreABC_Inst_0_PENABLE_M ),
        .PWRITE_M  ( CoreABC_Inst_0_PWRITE_M ),
        .PWDATA_M  ( CoreABC_Inst_0_PWDATA_M ),
        .IO_OUT    ( IO_OUT_net_0 ) 
        );

//--------Flag_for_RXPLL_lock
Flag_for_RXPLL_lock Flag_for_RXPLL_lock_0(
        // Inputs
        .clk_i      ( PF_CCC_50_0_OUT0_FABCLK_0 ),
        .reset_n_i  ( AND2_0_Y ),
        .rx_idle_i  ( PF_XCVR_0_0_LANE0_RX_IDLE ),
        .rx_ready_i ( PF_XCVR_0_0_LANE0_RX_READY ),
        // Outputs
        .flag_o     ( Flag_for_RXPLL_lock_0_flag_o ) 
        );

//--------INIT_MONITOR
INIT_MONITOR INIT_MONITOR_0(
        // Outputs
        .FABRIC_POR_N               ( INIT_MONITOR_0_FABRIC_POR_N ),
        .PCIE_INIT_DONE             (  ),
        .USRAM_INIT_DONE            (  ),
        .SRAM_INIT_DONE             (  ),
        .DEVICE_INIT_DONE           ( INIT_MONITOR_0_DEVICE_INIT_DONE ),
        .XCVR_INIT_DONE             ( INIT_MONITOR_0_XCVR_INIT_DONE ),
        .USRAM_INIT_FROM_SNVM_DONE  (  ),
        .USRAM_INIT_FROM_UPROM_DONE (  ),
        .USRAM_INIT_FROM_SPI_DONE   (  ),
        .SRAM_INIT_FROM_SNVM_DONE   (  ),
        .SRAM_INIT_FROM_UPROM_DONE  (  ),
        .SRAM_INIT_FROM_SPI_DONE    (  ),
        .AUTOCALIB_DONE             (  ),
        .BANK_6_VDDI_STATUS         ( INIT_MONITOR_0_BANK_6_VDDI_STATUS ) 
        );

//--------PF_CCC_50
PF_CCC_50 PF_CCC_50_0(
        // Inputs
        .REF_CLK_0         ( PF_OSC_160_0_RCOSC_160MHZ_GL ),
        .PLL_POWERDOWN_N_0 ( reset_logic_0_PLL_POWERDOWN_B ),
        // Outputs
        .OUT0_FABCLK_0     ( PF_CCC_50_0_OUT0_FABCLK_0 ),
        .PLL_LOCK_0        (  ) 
        );

//--------PF_CLK_DIV_C0
PF_CLK_DIV_C0 PF_CLK_DIV_C0_0(
        // Inputs
        .CLK_IN  ( PF_OSC_160_0_RCOSC_160MHZ_GL ),
        // Outputs
        .CLK_OUT ( PF_CLK_DIV_C0_0_CLK_OUT ) 
        );

//--------PF_OSC_160
PF_OSC_160 PF_OSC_160_0(
        // Outputs
        .RCOSC_160MHZ_GL ( PF_OSC_160_0_RCOSC_160MHZ_GL ) 
        );

//--------PF_TX_PLL_0
PF_TX_PLL_0 PF_TX_PLL_0_0(
        // Inputs
        .REF_CLK         ( PF_XCVR_REF_CLK_0_0_REF_CLK ),
        // Outputs
        .PLL_LOCK        (  ),
        .LOCK            ( PF_TX_PLL_0_0_CLKS_TO_XCVR_LOCK ),
        .BIT_CLK         ( PF_TX_PLL_0_0_CLKS_TO_XCVR_BIT_CLK ),
        .REF_CLK_TO_LANE ( PF_TX_PLL_0_0_CLKS_TO_XCVR_REF_CLK_TO_LANE ) 
        );

//--------PF_XCVR_0
PF_XCVR_0 PF_XCVR_0_0(
        // Inputs
        .LANE0_RXD_P          ( LANE0_RXD_P ),
        .LANE0_RXD_N          ( LANE0_RXD_N ),
        .LANE0_TX_DATA        ( PRBS_gen_0_data_out ),
        .LANE0_CDR_REF_CLK_0  ( PF_XCVR_REF_CLK_0_0_REF_CLK ),
        .LANE0_RX_SLIP        ( GND_net ),
        .LANE0_PCS_ARST_N     ( INIT_MONITOR_0_XCVR_INIT_DONE ),
        .LANE0_PMA_ARST_N     ( INIT_MONITOR_0_XCVR_INIT_DONE ),
        .LANE0_DRI_CLK        ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CLK ),
        .LANE0_DRI_WDATA      ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_WDATA ),
        .LANE0_DRI_ARST_N     ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_ARST_N ),
        .LANE0_DRI_CTRL       ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CTRL ),
        .TX_PLL_LOCK_0        ( PF_TX_PLL_0_0_CLKS_TO_XCVR_LOCK ),
        .TX_BIT_CLK_0         ( PF_TX_PLL_0_0_CLKS_TO_XCVR_BIT_CLK ),
        .TX_PLL_REF_CLK_0     ( PF_TX_PLL_0_0_CLKS_TO_XCVR_REF_CLK_TO_LANE ),
        .CTRL_CLK             ( PF_CLK_DIV_C0_0_CLK_OUT ),
        .CTRL_ARST_N          ( INIT_MONITOR_0_XCVR_INIT_DONE ),
        .LANE0_LOS            ( GND_net ),
        .LANE0_CALIB_REQ      ( AND2_0_Y ),
        // Outputs
        .LANE0_TXD_P          ( LANE0_TXD_P_net_0 ),
        .LANE0_TXD_N          ( LANE0_TXD_N_net_0 ),
        .LANE0_RX_DATA        ( PF_XCVR_0_0_LANE0_RX_DATA ),
        .LANE0_TX_CLK_R       ( PF_XCVR_0_0_LANE0_TX_CLK_R ),
        .LANE0_RX_CLK_R       ( PF_XCVR_0_0_LANE0_RX_CLK_R ),
        .LANE0_RX_IDLE        ( PF_XCVR_0_0_LANE0_RX_IDLE ),
        .LANE0_TX_CLK_STABLE  ( PF_XCVR_0_0_LANE0_TX_CLK_STABLE ),
        .LANE0_RX_BYPASS_DATA (  ),
        .LANE0_DRI_RDATA      ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_RDATA ),
        .LANE0_DRI_INTERRUPT  ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_INTERRUPT ),
        .LANE0_CALIBRATING    ( LANE0_CALIBRATING_net_0 ),
        .LANE0_RX_READY       ( PF_XCVR_0_0_LANE0_RX_READY ),
        .LANE0_RX_VAL         ( PF_XCVR_0_0_LANE0_RX_VAL ) 
        );

//--------PF_XCVR_DRI
PF_XCVR_DRI PF_XCVR_DRI_0(
        // Inputs
        .PCLK                   ( PF_CCC_50_0_OUT0_FABCLK_0 ),
        .PSTRB                  ( PSTRB_const_net_0 ),
        .PRESETN                ( AND2_0_Y ),
        .PSEL                   ( CoreABC_Inst_0_PSEL_M ),
        .PENABLE                ( CoreABC_Inst_0_PENABLE_M ),
        .PWRITE                 ( CoreABC_Inst_0_PWRITE_M ),
        .PADDR                  ( PADDR_net_0 ),
        .PWDATA                 ( CoreABC_Inst_0_PWDATA_M ),
        .Q2_LANE0_DRI_RDATA     ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_RDATA ),
        .Q2_LANE0_DRI_INTERRUPT ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_INTERRUPT ),
        // Outputs
        .PINTERRUPT             (  ),
        .PTIMEOUT               (  ),
        .BUSERROR               (  ),
        .PRDATA                 ( PF_XCVR_DRI_0_PRDATA ),
        .PREADY                 ( PF_XCVR_DRI_0_PREADY ),
        .PSLVERR                ( PF_XCVR_DRI_0_PSLVERR ),
        .DRI_CLK                ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CLK ),
        .DRI_WDATA              ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_WDATA ),
        .DRI_ARST_N             ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_ARST_N ),
        .Q2_LANE0_DRI_CTRL      ( PF_XCVR_DRI_0_Q2_LANE0_DRI_DRI_CTRL ) 
        );

//--------PF_XCVR_REF_CLK_0
PF_XCVR_REF_CLK_0 PF_XCVR_REF_CLK_0_0(
        // Inputs
        .REF_CLK_PAD_P ( REF_CLK_PAD_P ),
        .REF_CLK_PAD_N ( REF_CLK_PAD_N ),
        // Outputs
        .REF_CLK       ( PF_XCVR_REF_CLK_0_0_REF_CLK ) 
        );

//--------PRBS_chk
PRBS_chk PRBS_chk_0(
        // Inputs
        .reset           ( reset_logic_0_prbs_chk_rst_n ),
        .clk             ( PF_XCVR_0_0_LANE0_RX_CLK_R ),
        .data_in         ( PF_XCVR_0_0_LANE0_RX_DATA ),
        .rx_val          ( PF_XCVR_0_0_LANE0_RX_VAL ),
        .clr_err_counter ( GND_net ),
        // Outputs
        .rx_val_o        (  ),
        .error_out       ( error_out_net_0 ),
        .lock            ( lock_net_0 ) 
        );

//--------PRBS_gen
PRBS_gen PRBS_gen_0(
        // Inputs
        .reset    ( reset_logic_0_prbs_gen_rst_n ),
        .clk      ( PF_XCVR_0_0_LANE0_TX_CLK_R ),
        // Outputs
        .data_out ( PRBS_gen_0_data_out ) 
        );

//--------reset_logic
reset_logic reset_logic_0(
        // Inputs
        .tx_clk             ( PF_XCVR_0_0_LANE0_TX_CLK_R ),
        .tx_clk_stable      ( PF_XCVR_0_0_LANE0_TX_CLK_STABLE ),
        .INIT_DONE          ( INIT_MONITOR_0_DEVICE_INIT_DONE ),
        .rx_clk             ( PF_XCVR_0_0_LANE0_RX_CLK_R ),
        .rx_val             ( PF_XCVR_0_0_LANE0_RX_VAL ),
        .BANK_y_VDDI_STATUS ( INIT_MONITOR_0_BANK_6_VDDI_STATUS ),
        .FPGA_POR_N         ( INIT_MONITOR_0_FABRIC_POR_N ),
        // Outputs
        .prbs_gen_rst_n     ( reset_logic_0_prbs_gen_rst_n ),
        .prbs_chk_rst_n     ( reset_logic_0_prbs_chk_rst_n ),
        .PLL_POWERDOWN_B    ( reset_logic_0_PLL_POWERDOWN_B ) 
        );


endmodule
