//-------------------------------------------------------------------
//                                                                 
//  Microsemi Corporation Proprietary and Confidential
//  Copyright 2017 Microsemi Corporation. All rights reserved.
//                                                                  
//  ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN 
//  ACCORDANCE WITH THE MICROSEMI LICENSE AGREEMENT AND MUST BE APPROVED 
//  IN ADVANCE IN WRITING.
//
//-------------------------------------------------------------------
// Title        : Flag_for_RXPLL_lock.v
// Created      : February-2018
// Description  : This module receives RX_IDLE and RX_READY signals from
// transceiver interface and performs edge detection for logical AND operation 
// of (!rx_idle && rx_ready). After edge detection, flag is asserted to
// CoreABC interface as input. 
//
// Revision     : NA
// Hierarchy    :
//                fpga_top
//                  -- Flag_for_RXPLL_lock.v              <-- This module
//
// Target device: <Family:PolarFire> <Die:MPF300TS_ES> <Pkg:FCG1152>
//-------------------------------------------------------------------

module Flag_for_RXPLL_lock
( 
	input  clk_i, //input clock
	input  reset_n_i, //input reset 
        input  rx_idle_i, //RX_IDLE signal input from transceiver
        input  rx_ready_i,	//RX_READY signal input from transceiver
        output flag_o //flag output to trigger DFE calibration 
);

wire ready_inv_rxidle_i;
reg flag_s;

assign ready_inv_rxidle_i = (~rx_idle_i & rx_ready_i);

//flag assertion when valid RX_IDLE and RX_READY signals are received from
//transceiver
 
always@(posedge clk_i,negedge reset_n_i)
begin
 if(reset_n_i==1'b0)
  flag_s <= 1'b0;
 else
  begin
   if(ready_inv_rxidle_i==1'b1)
     flag_s <= 1'b1; 
   else
     flag_s <= flag_s;      
  end
end
assign flag_o = flag_s;

endmodule

